Xilinx ML401, ML402, ML403 User Manual
ML401/ML402/ML403
www.BDTIC.com/XILINX
Evaluation Platform
User Guide
UG080 (v2.5) May 24, 2006
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Revision History
The following table shows the revision history for this document.
Date Version Revision
09/24/04 1.0 Initial Xilinx release.
10/20/04 1.0.1 Minor edits to text and figures.
02/17/05 1.1 Minor edits:
• Figure 1and Figure 4: Corrected the regulator number for the 6A SWIFT part that goes
to 1.2V. Removed digital supply reference.
• Table 6: Corrected the GPIO LED 3 (DS6) FPGA pin number.
02/28/05 2.0 Renamed title from ML401 Evaluation Platform user guide to ML40x Evaluation Platform
user guide.
Expanded document from ML401-specific to include ML401, ML402, and ML403
platforms.
Minor edits to text and figures.
ML401/ML402/ML403 Evaluation Platform www.xilinx.com UG080 (v2.5) May 24, 2006
Date Version Revision
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10/25/05 2.1 Renamed title from ML40x Evaluation Platform user guide to ML401/ML402/ML403
Evaluation Platform user guide.
Technical edits:
• Features section: Expanded VGA output bullet items.
• 15. VGA Output section: Added Table 13 for the Video DAC connections.
Minor edits to text for clarity.
11/15/05 2.2 Clarified ZBT synchronous RAM size in Features section.
01/13/06 2.3
05/07/06 2.4 Updated
05/24/06 2.5 Updated
Minor edits:
• Deleted “P/N 0402337” (obsolete) from document’s identification.
• Deleted power cord reference from Power supply bullet in Package Contents section.
• Typographical corrections.
USB interface chip criteria in Features section.
USB interface chip criteria in Features section.
Updated 18. ZBT Synchronous SRAM section.
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Table of Contents
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Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ML401/ML402/ML403 Evaluation Platform
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Virtex-4 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Differential Clock Input And Output With SMA Connectors . . . . . . . . . . . . . . . . . 16
4. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. LCD Brightness and Contrast Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. DIP Switches (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. User and Error LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. User Push Buttons (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9. CPU Reset Button (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10. Expansion Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. Stereo AC97 Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12. RS-232 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13. 16-Character x 2-Line LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
14. IIC Bus with 4-Kb EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15. VGA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16. PS/2 Mouse and Keyboard Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
17. System ACE and CompactFlash Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18. ZBT Synchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
19. Linear Flash Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
20. Xilinx XC95144XL CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
21. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
22. USB Controller with Host and Peripheral Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
23. Xilinx XCF32P Platform Flash Configuration Storage Device . . . . . . . . . . . . . . . . 28
24. JTAG Configuration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
25. Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
26. AC Adapter and Input Power Switch/Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
27. Power Indicator LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
28. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
29. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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31. Configuration Address and Mode DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
32. Encryption Key Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
33. Configuration Source Selector Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JTAG (Parallel Cable IV Cable and System ACE Controller) . . . . . . . . . . . . . . . . . . . . 31
Platform Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Linear Flash + CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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About This Guide
www.BDTIC.com/XILINX
The ML401/ML402/ML403 evaluation platforms enable designers to investigate and
experiment with features of the Virtex™-4 family of FPGAs. This user guide describes
features and operation of the ML401, ML402, and ML403 (ML40x) evaluation platforms.
Guide Contents
This manual contains the following chapter: “ML401/ML402/ML403 Evaluation
Platform.”
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature/index.htm.
Preface
Conventions
Typographical
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
Courier bold
Helvetica bold
program files that the system
displays
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcuts Ctrl+C
speed grade: - 100
ngdbuild design_name
File → Open
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Italic font
Square brackets [ ]
Convention Meaning or Use Example
Variables in a syntax statement
for which you must supply
values
References to other manuals
Emphasis in text
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild design_name
See the Development System
Reference Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
ngdbuild [option_name]
design_name
R
Braces { }
Vertical bar |
Vertical ellipsis
.
.
.
Horizontal ellipsis . . .
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Red text
A list of items from which you
must choose one or more
Separates items in a list of
choices
Repetitive material that has
been omitted
Repetitive material that has
been omitted
Cross-reference link to a
location in the current
document
Cross-reference link to a
location in another document
lowpwr ={on|off}
lowpwr ={on|off}
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
allow block block_name loc1
loc2 ... locn;
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
See Figure 2-5 in the Virtex-II
Handbook.
Blue, underlined text
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Hyperlink to a website (URL)
Go to http://www.xilinx.com
for the latest speed files.
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Introduction
The ML401/ML402/ML403 evaluation platform enables designers to investigate and
experiment with features of the Virtex™-4 family of FPGAs. This user guide describes
features and operation of the ML401, ML402, and ML403 (ML40x) evaluation platforms.
Features
• Virtex-4 FPGA:
♦ ML401: XC4VLX25-FF668-10
♦ ML402: XC4VSX35-FF668-10
♦ ML403: XC4VFX12-FF668-10
• 64-MB DDR SDRAM, 32-bit interface running up to 266-MHz data rate
• One differential clock input pair and differential clock output pair with SMA
connectors
• One 100-MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator
socket
• General purpose DIP switches (ML401/ML402 platform), LEDs, and push buttons
• Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs,
14 spare I/Os shared with buttons and LEDs, power, JTAG chain expansion
capability, and IIC bus expansion
• Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, and
microphone-in (mono) jacks
• RS-232 serial port
• 16-character x 2-line LCD display
• One 4-Kb IIC EEPROM
• VGA output:
♦ ML401: 50 MHz / 24-bit video DAC
♦ ML402: 140 MHz / 24-bit video DAC
♦ ML403: 140 MHz / 15-bit video DAC
• PS/2 mouse and keyboard connectors
• System ACE™ CompactFlash configuration controller with Type I/II CompactFlash
connector
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Package Contents
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• ZBT synchronous SRAM
♦ ML401/ML402: 9 Mb on 32-bit data bus with four parity bits
♦ ML403: 8 Mb on 32-bit data bus with no parity bits
• Intel StrataFlash (or compatible) linear flash chips (8 MB)
• 10/100/1000 tri-speed Ethernet PHY transceiver
• USB interface chip (Cypress CY7C67300) with host and peripheral ports
• Xilinx XC95144XL CPLD to allow linear flash chips to be used for FPGA configuration
• Xilinx XCF32P Platform Flash configuration storage device
• JTAG configuration port for use with Parallel Cable III or Parallel Cable IV cable
• Onboard power supplies for all necessary voltages
• 5V @ 3A AC adapter
• Power indicator LED
• Xilinx Virtex-4 ML40x evaluation platform
• System ACE CompactFlash card
• Power supply
• Carrying case with anti-static foam
• Printed documentation
Additional Information
For current information about your ML40x evaluation platform, visit the corresponding
Web page:
• ML401: http://www.xilinx.com/ml401
• ML402: http://www.xilinx.com/ml402
• ML403: http://www.xilinx.com/ml403
The information includes:
• Current version of this user guide in PDF format
• Example design files for demonstration of Virtex-4 features and technology
• Demonstration hardware and software configuration files for the System ACE
controller, Platform Flash configuration storage device, CPLD, and linear flash chips
• MicroBlaze™ and PowerPC™ 405 (ML403) EDK reference design files
• Full schematics in PDF format and ViewDraw schematic format
• PC board layout in Pads PCB format
• Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware
Gerber file viewers available on the internet for viewing and printing these files)
• Additional documentation, errata, frequently asked questions, and the latest news
For information about the Virtex-4 family of FPGA devices, including product highlights,
data sheets, user guides, and application notes, see the Virtex-4 website at
http://www.xilinx.com/virtex4
and application notes from the component manufacturers.
. Additional information is available from the data sheets
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