LogiCORE IP AXI
Bridge for PCI Express
v2.4
Product Guide
Vivado Design Suite
PG055 June 4, 2014
Table of Contents
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IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bridge Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parameter Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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PG055 June 4, 2014
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AXI Transactions for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transaction Ordering for PCIe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Malformed TLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Abnormal Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Root Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Simulation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Implementation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 6: Test Bench
Appendix A: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transceiver Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
AXI Bridge for PCI Express v2.4 www.xilinx.com 3
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IP Facts
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Introduction
The Xilinx® LogiCORE™ IP AXI Root Port/
Endpoint (RP/EP) Bridge for PCI Express® core
is an interface between the AXI4 and PCI
Express. Definitions and references are
provided in this document for all of the
functional modules, registers, and interfaces
that are implemented in the AXI Bridge for PCI
Express core. Definitions are also provided for
the hardware implementation and software
interfaces to the AXI Bridge for PCI Express core
in supported FPGA devices.
Features
• Zynq®-7000, Kintex®-7, Virtex®-7, and
Artix®-7 FPGA Integrated Blocks for PCI
Express
• Maximum Payload Size (MPS) up to 256 bytes
• Multiple Vector Messaged Signaled Interrupts
(MSIs)
•Legacy interrupt support
• Memory-mapped AXI4 access to PCIe® space
• PCIe access to memory-mapped AXI4 space
• Tracks and manages Transaction Layer Packets
(TLPs) completion processing
• Detects and indicates error conditions with
interrupts
• Optimal AXI4 pipeline support for enhanced
performance
• Compliant with Advanced RISC Machine
(ARM®) Advanced Microcontroller Bus
Architecture 4 (AMBA®) AXI4 specification
• Supports up to three PCIe 32-bit or 64-bit
PCIe Base Address Registers (BARs) as
Endpoint
• Supports a single PCIe 32-bit or 64-bit BAR as
Root Port
LogiCORE IP Facts Table
Core Specifics
Supported
Device
(1)
Family
Supported
User Interfaces
Resources See Tab l e 2 - 2
Zynq-7000, 7 Series
AXI4
Provided with Core
Design Files VHDL and Verilog
Example
Design
Tes t B en c h Verilog
Constraints
File
Simulation
Model
Supported
S/W Driver
(2)
Tested Design Flows
Design Entry
Simulation
Synthesis Vivado Synthesis
Xilinx Design Tools: Release Notes Guide
For supported simulators, see the
Standalone and Linux
(3)
Vivado® Design Suite
Vivado IP integrator
Verilog
XDC
Not Provided
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog. See also Table 2-1, page 11.
2. Standalone driver details can be found in the SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux
OS and driver support information is available from
wiki.xilinx.com
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
4. Except for XC7VX485T, Virtex 7 devices are not supported.
.
.
(1)
AXI Bridge for PCI Express v2.4 www.xilinx.com 4
PG055 June 4, 2014 Product Specification
Overview
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The AXI Bridge for PCI Express® core is designed for the Vivado® IP integrator in the
Vivado Design Suite. The AXI Bridge for PCI Express core provides an interface between an
AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI
Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4
embedded system to the PCI Express system. The AXI Bridge for PCI Express core translates
the AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets and
translates PCIe memory read and write request TLP packets to AXI4 interface commands.
The architecture of the AXI Bridge for PCI Express is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Chapter 1
AXI Bridge for PCI Express v2.4 www.xilinx.com 5
PG055 June 4, 2014
Figure 1-1: High-Level AXI Bridge for PCI Express Architecture
Chapter 1: Overview
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Feature Summary
The AXI Bridge for PCI Express core is an interface between the AXI4 and PCI Express. It
contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced
Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a
register block and two functional half bridges, referred to as the Slave Bridge and Master
Bridge. The Slave Bridge connects to the AXI4 Interconnect as a slave device to handle any
issued AXI4 master read or write requests. The Master Bridge connects to the AXI4
Interconnect as a master to process the PCIe generated read or write TLPs. The core uses a
set of interrupts to detect and flag error conditions.
The AXI Bridge for PCI Express core supports both Root Port and Endpoint configurations.
• When configured as an Endpoint, the AXI Bridge for PCI Express core supports up to
three 32-bit or 64-bit PCIe Base Address Registers (BARs).
• When configured as a Root Port, the core supports a single 32-bit or 64-bit PCIe BAR.
The AXI Bridge for PCI Express core is compliant with the PCI Express Base Specification v2.0
[Ref 5] and with the AMBA® AXI4 specification [Ref 4].
Unsupported Features
The following features are not supported in the AXI Bridge for PCI Express core.
• Tandem PROM and Tandem PCIe
• Advanced Error Reporting (AER)
Limitations
Reference Clock for PCIe Frequency Value
The refclk input used by the serial transceiver for PCIe must be 100 MHz, 125 MHz, and
MHz for 7 series and Zynq®-7000 device configurations. The C_REF_CLK_FREQ
250
parameter is used to set this value, as defined in
Tab le 2-4, page 15.
AXI Bridge for PCI Express v2.4 www.xilinx.com 6
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Chapter 1: Overview
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Licensing and Ordering Information
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
For more information, visit the AXI Bridge for PCI Express product page.
Xilinx End User License.
AXI Bridge for PCI Express v2.4 www.xilinx.com 7
PG055 June 4, 2014
Product Specification
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Figure 2-1 shows the architecture of the AXI Bridge for PCI Express® core.
X-Ref Target - Figure 2-1
Chapter 2
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PG055 June 4, 2014
Figure 2-1: AXI Bridge for PCI Express Architecture
The Register block contains registers used in the AXI Bridge for PCI Express core for
dynamically mapping the AXI4 memory mapped (MM) address range provided using the
AXIBAR parameters to an address for PCIe range.
The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI
master device (such as a processor). The Slave Bridge provides a way to translate addresses
that are mapped within the AXI4 memory mapped address domain to the domain addresses
for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the
write address and qualifiers are captured and write data is queued in a first in first out
(FIFO). These are then converted into one or more MemWr TLPs, depending on the
Chapter 2: Product Specification
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configured Max Payload Size setting, which are passed to the Integrated Block for PCI
Express.
A second remote AXI master initiated write request write address and qualifiers can then be
captured and the associated write data queued, pending the completion of the previous
write TLP transfer to the core. The resulting AXI Slave Bridge write pipeline is two-deep.
When a remote AXI master initiates a read transaction to the Slave Bridge, the read address
and qualifiers are captured and a MemRd request TLP is passed to the core and a
completion timeout timer is started. Completions received through the core are correlated
with pending read requests and read data is returned to the AXI master. The Slave bridge is
capable of handling up to eight memory mapped AXI4 read requests with pending
completions.
The Master Bridge processes both PCIe MemWr and MemRd request TLPs received from the
integrated block for PCI Express and provides a means to translate addresses that are
mapped within the address for PCIe domain to the memory mapped AXI4 address domain.
Each PCIe MemWr request TLP header is used to create an address and qualifiers for the
memory mapped AXI4 bus and the associated write data is passed to the addressed
memor y mapped AXI4 Slave. The Master Bridge can support up to four active PCIe MemWr
request TLPs.
Each PCIe MemRd request TLP header is used to create an address and qualifiers for the
memory-mapped AXI4 bus. Read data is collected from the addressed memory mapped
AXI4 Slave and used to generate completion TLPs which are then passed to the integrated
block for PCI Express. The Master bridge can handle up to four read requests with pending
completions for improved AXI4 pipelining performance.
The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the
Requester/Completer interfaces to the AXI bridge and the Register block. The Register
block contains the status, control, interrupt registers, and the AXI4-Lite interface.
Standards
The AXI Bridge for PCIe core is compliant with the ARM® AMBA® AXI4 Protocol
Specification
[Ref 4] and the PCI Express Base Specification v2.0 [Ref 5].
AXI Bridge for PCI Express v2.4 www.xilinx.com 9
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Performance
AXI4-Lite
MicroBlaze
Controller
AXI INTC
AXI GPIO
AXI UARTLite
AXI4
Memory
Controller
MDM
MicroBlaze
Domain
AXI4
Block RAM
Controller
D_LMB
I_LMB
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AXI Block Ram
(DC)
AXI PCIe
Memory
(DP)
LEDs
RS232
AXI CDMA
MemoryMap
Interconnect
(AXI4)
Control
Interface
Subset
Interconnect
(AXI4-Lite)
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Figure 2-2 shows a configuration diagram for a target FPGA.
X-Ref Target - Figure 2-2
Chapter 2: Product Specification
AXI Bridge for PCI Express v2.4 www.xilinx.com 10
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Figure 2-2: FPGA System Configuration Diagram
The target FPGA is filled with logic to drive the lookup table (LUT) and block RAM utilization
to approximately 70% and the I/O utilization to approximately 80%.
Maximum Frequencies
The maximum frequency for the AXI clock is 125 MHz for 7 series FPGAs.
Line Rate Support for PCIe Gen1/Gen2
The link speed, number of lanes supported, and support of line rate for PCIe are defined in
Tab le 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock
frequency, the AXI data width, the number of lanes, and Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s)
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link speed.
Table 2-1: Line Rate for PCIe Support for Gen1/Gen2
Chapter 2: Product Specification
C_FAMILY C_X_AXI_DATA_WIDTH
64
7 series,
Zynq®-7000
128
Notes:
1. x8 Gen2 configuration is not supported. Artix-7 does not support x8 Gen1.
PCIe Link
Speed
Gen 1
Gen 2 x1, 2
Gen 1,
Gen 2
C_NO_OF_LANES
x1, 2, 4, 8
x1 62.5 MHz 62.5 MHz 62.5 MHz
x2, 4
(1)
Resource Utilization
Tab le 2-2 illustrates a subset of IP core conf igurations and the device utilization estimates.
Variation in tools and optimization settings can result in variance of these reported
numbers.
Tab le 2-2 shows the resource utilization for the AXI Bridge for PCIe core for different
configurations on the Virtex-7 XC7V2000T device. These numbers were generated in the
Vivado® Design Suite. Resource Utilization numbers for other devices can be generated by
implementing the provided example design and checking for the resources used by only
the core in the resource utilization report.
AXI_ACLK
_OUT
125 MHz 125 MHz 125 MHz
125 MHz 250 MHz 125 MHz
Userclk1 Userclk2
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Table 2-2: Resource Utilization Summary
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Configuration Slice Registers Slice LUTs
Chapter 2: Product Specification
Endpoint x1 Gen1
Endpoint x2 Gen1
Endpoint x4 Gen1
Endpoint x8 Gen1
Endpoint x1 Gen2
Endpoint x2 Gen2
Endpoint x4 Gen2
Root Port x1 Gen1
Root Port x2 Gen1
Root Port x4 Gen1
Root Port x8 Gen1
Root Port x1 Gen2
Root Port x2 Gen2
Root Port x4 Gen2
Port Descriptions
8678 13054
8963 13300
9558 13666
11912 17355
8620 14041
8897 14362
10629 16477
10703 15909
10836 15537
11431 15924
13805 20128
10674 16734
11062 17137
12563 19325
The interface signals for the AXI Bridge for PCI Express are described in Tab le 2-3.
Table 2-3: Top-Level Interface Signals
Signal Name I/O Description
Global Signals
refclk I PCIe Reference Clock
axi_aresetn I Global reset signal for AXI Interfaces
axi_aclk_out O PCIe derived clock output for axi_aclk
axi_ctl_aclk_out O PCIe derived clock output for axi_ctl_aclk
mmcm_lock O axi_aclk_out from the axi_enhanced_pcie block is stable
interrupt_out O Interrupt signal
AXI Slave Interface
s_axi_awid[c_s_axi_id_width-1:0] I Slave write address ID
s_axi_awaddr[c_s_axi_addr_width-1:0] I Slave address write
s_axi_awregion[3:0] I Slave write region decode
s_axi_awlen[7:0] I Slave write burst length
s_axi_awsize[2:0] I Slave write burst size
AXI Bridge for PCI Express v2.4 www.xilinx.com 12
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Table 2-3: Top-Level Interface Signals (Cont’d)
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Signal Name I/O Description
s_axi_awburst[1:0] I Slave write burst type
s_axi_awvalid I Slave address write valid
s_axi_awready O Slave address write ready
s_axi_wdata[c_s_axi_data_width-1:0] I Slave write data
s_axi_wstrb[c_s_axi_data_width/8-1:0] I Slave write strobe
s_axi_wlast I Slave write last
s_axi_wvalid I Slave write valid
s_axi_wready O Slave write ready
s_axi_bid[c_s_axi_id_width-1:0] O Slave response ID
s_axi_bresp[1:0] O Slave write response
s_axi_bvalid O Slave write response valid
s_axi_bready I Slave response ready
s_axi_arid[c_s_axi_id_width-1:0] I Slave read address ID
Chapter 2: Product Specification
s_axi_araddr[c_s_axi_addr_width-1:0] I Slave read address
s_axi_arregion[3:0] I Slave read region decode
s_axi_arlen[7:0] I Slave read burst length
s_axi_arsize[2:0] I Slave read burst size
s_axi_arburst[1:0] I Slave read burst type
s_axi_arvalid I Slave read address valid
s_axi_arready O Slave read address ready
s_axi_rid[c_s_axi_id_width-1:0] O Slave read ID tag
s_axi_rdata[c_s_axi_data_width-1:0] O Slave read data
s_axi_rresp[1:0] O Slave read response
s_axi_rlast O Slave read last
s_axi_rvalid O Slave read valid
s_axi_rready I Slave read ready
AXI Master Interface
m_axi_awaddr[c_m_axi_addr_width-1:0] O Master address write
m_axi_awlen[7:0] O Master write burst length
m_axi_awsize[2:0] O Master write burst size
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m_axi_awburst[1:0] O Master write burst type
m_axi_awprot[2:0] O Master write protection type
m_axi_awvalid O Master write address valid
m_axi_awready I Master write address ready
m_axi_wdata[c_m_axi_data_width-1:0] O Master write data
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Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
m_axi_wstrb[c_m_axi_data_width/8-1:0] O Master write strobe
m_axi_wlast O Master write last
m_axi_wvalid O Master write valid
m_axi_wready I Master write ready
m_axi_bresp[1:0] I Master write response
m_axi_bvalid I Master write response valid
m_axi_bready O Master response ready
m_axi_araddr[c_m_axi_addr_width-1:0] O Master read address
m_axi_arlen[7:0] O Master read burst length
m_axi_arsize[2:0] O Master read burst size
m_axi_arburst[1:0] O Master read burst type
m_axi_arprot[2:0] O Master read protection type
m_axi_arvalid O Master read address valid
m_axi_arready I Master read address ready
m_axi_rdata[c_m_axi_data_width-1:0] I Master read data
m_axi_rresp[1:0] I Master read response
m_axi_rlast I Master read last
m_axi_rvalid I Master read valid
m_axi_rready O Master read ready
AXI4-Lite Control Interface
s_axi_ctl_awaddr[31:0] I Slave write address
s_axi_ctl_awvalid I Slave write address valid
s_axi_ctl_awready O Slave write address ready
s_axi_ctl_wdata[31:0] I Slave write data
s_ax_ctl_wstrb[3:0] I Slave write strobe
s_axi_ctl_wvalid I Slave write valid
s_axi_ctl_wready O Slave write ready
s_axi_ctl_bresp[1:0] O Slave write response
s_axi_ctl_bvalid O Slave write response valid
s_axi_ctl_bready I Slave response ready
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s_axi_ctl_araddr[31:0] I Slave read address
s_axi_ctl_arvalid I Slave read address valid
s_axi_ctl_arready O Slave read address ready
s_axi_ctl_rdata[31:0] O Slave read data
s_axi_ctl_rresp[1:0] O Slave read response
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Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
s_axi_ctl_rvalid O Slave read valid
s_axi_ctl_rready I Slave read ready
MSI Signals
Legacy interrupt input (see c_interrupt_pin) when
intx_msi_request I
intx_msi_grant O
msi_enable O Indicates when MSI is enabled.
msi_enable = 0.
Initiates a MSI write request when msi_enable = 1.
Intx_msi_request is asserted for one clock period.
Indicates legacy interrupt/MSI grant signal. The
intx_msi_grant signal is asserted for one clock period
when the interrupt is accepted by the PCIe core.
msi_vector_num [4:0] I
msi_vector_width [2:0] O
Indicates MSI vector to send when writing a MSI write
request.
Indicates the size of the MSI field (the number of MSI
vectors allocated to the device).
PCIe Interface
pci_exp_rxp[c_no_of_lanes-1: 0] I PCIe RX serial interface
pci_exp_rxn[c_no_of_lanes-1: 0] I PCIe RX serial interface
pci_exp_txp[c_no_of_lanes-1: 0] O PCIe TX serial interface
pci_exp_txn[c_no_of_lanes-1:0] O PCIe TX serial interface
Bridge Parameters
Because many features in the AXI Bridge for PCI Express core design can be parameterized,
you are able to uniquely tailor the implementation of the core using only the resources
required for the desired functionality. This approach also achieves the best possible
performance with the lowest resource usage.
The parameters defined for the AXI Bridge for PCI Express are shown in Tab le 2-4.
Table 2-4: To p- L ev el P a ra m et e rs
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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C_PCIE_BLK_LOCN
Bridge Parameters
PCIe integrated
block location
within FPGA
0: X0Y0
1: X0Y1
2: X0Y2
3: X1Y0
4: X1Y1
0 String
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
NONE
KC705_REVA
C_XLNX_REF_BOARD Target FPGA Board
KC705_REVB
KC705_REVC
VC707
NONE String
G1 C_FAMILY Target FPGA Family
Configures the AXI
G2 C_INCLUDE_RC
G3 C_COMP_TIMEOUT
G4
G5
C_INCLUDE_
BAROFFSET_REG
C_SUPPORTS_
NARROW_BURST
bridge for PCIe to be
a Root Port or an
Endpoint
Selects the Slave
Bridge completion
timeout counter
value
Include the registers
for high-order bits
to be substituted in
translation in Slave
Bridge
Instantiates internal
logic to support
narrow burst
transfers. Only
enable when AXI
master bridge
generates narrow
burst traffic.
kintex7, virtex7, artix7,
zynq
0: Endpoint
1: Root Port (applies only
series, and
for 7
Zynq-7000 devices)
0: 50 µs
1: 50 ms
0: Exclude
1: Include
0: Not supported
1: Supported
String
0 Integer
0 Integer
0 Integer
0 Integer
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G6 C_AXIBAR_NUM
G7 C_AXIBAR_0
G8
G9 C_AXIBAR_AS_0
C_AXIBAR_
HIGHADDR_0
Number of AXI
address apertures
that can be accessed
AXI BAR_0 aperture
low address
AXI BAR_0 aperture
high address
AXI BAR_0 address
size
1-6;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
4: BAR_0 through BAR_3
enabled
5: BAR_0 through BAR_4
enabled
6: BAR_0 through BAR_5
enabled
Valid AXI address
Valid AXI address
0: 32 bit
1: 64 bit
(1)(3)(4)
(1)(3)(4)
6 Integer
0xFFFF_FFFF
0x0000_0000
0 Integer
std_logic_
vector
std_logic_
vector
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
G10 C_AXIBAR2PCIEBAR_0
G11 C_AXIBAR_1
G12
C_AXIBAR_
HIGHADDR_1
G13 C_AXIBAR_AS_1
G14 C_AXIBAR2PCIEBAR_1
G15 C_AXIBAR_2
G16
C_AXIBAR_
HIGHADDR_2
G17 C_AXIBAR_AS_2
G18 C_AXIBAR2PCIEBAR_2
PCIe BAR to which
AXI BAR_0 is
mapped
AXI BAR_1 aperture
low address
AXI BAR_1 aperture
high address
AXI BAR_1 address
size
PCIe BAR to which
AXI BAR_1 is
mapped
AXI BAR_2 aperture
low address
AXI BAR_2 aperture
high address
AXI BAR_2 address
size
PCIe BAR to which
AXI BAR_2 is
mapped
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
(2)
(2)
(2)
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
G19 C_AXIBAR_3
G20
C_AXIBAR_
HIGHADDR_3
G21 C_AXIBAR_AS_3
G22 C_AXIBAR2PCIEBAR_3
G23 C_AXIBAR_4
G24
C_AXIBAR_
HIGHADDR_4
G25 C_AXIBAR_AS_4
G26 C_AXIBAR2PCIEBAR_4
G27 C_AXIBAR_5
AXI BAR_3 aperture
low address
AXI BAR_3 aperture
high address
AXI BAR_3 address
size
PCIe BAR to which
AXI BAR_3 is
mapped
AXI BAR_4 aperture
low address
AXI BAR_4 aperture
high address
AXI BAR_4 address
size
PCIe BAR to which
AXI BAR_4 is
mapped
AXI BAR_5 aperture
low address
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
(1)(3)(4)
(2)
(2)
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
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PG055 June 4, 2014
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
G28
G29 C_AXIBAR_AS_5
G30 C_AXIBAR2PCIEBAR_5
G31 C_PCIEBAR_NUM
G32 C_PCIEBAR_AS
C_AXIBAR_
HIGHADDR_5
AXI BAR_5 aperture
high address
AXI BAR_5 address
size
PCIe BAR to which
AXI BAR_5 is
mapped
Number of address
for PCIe apertures
that can be accessed
Configures PCIEBAR
aperture width to be
32 bits wide or 64
bits wide
Valid AXI address
0: 32 bit
1: 64 bit
Valid address for PCIe
1-3;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
0: Generates three 32-bit
PCIEBAR address
apertures.
32-bit BAR example:
PCIEBAR_0 is 32 bits
PCIEBAR_1 is 32 bits
PCIEBAR_2 is 32 bits
1: Generates three 64 bit
PCIEBAR address
apertures.
64-bit BAR example:
PCIEBAR_0 and PCIEBAR_1
concatenate to comprise
64-bit PCIEBAR_0.
(1)(3)(4)
(2)
0x0000_0000
0 Integer
0xFFFF_FFFF
3 Integer
1 Integer
std_logic_
vector
std_logic_
vector
G33 C_PCIEBAR_LEN_0
G34 C_PCIEBAR2AXIBAR_0
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PG055 June 4, 2014
Power of 2 in the
size of bytes of PCIE
BAR_0 space
AXIBAR to which
PCIE BAR_0 is
mapped
PCIEBAR_2 and PCIEBAR_3
concatenate to comprise
64-bit PCIEBAR_1.
PCIEBAR_4 and PCIEBAR_5
concatenate to comprise
64-bit PCIEBAR_2
13-31 16 Integer
Valid AXI address 0x0000_0000
std_logic_
vector
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
Defines the AXIBAR
C_PCIEBAR2AXIBAR_0
_SEC
G35 C_PCIEBAR_LEN_1
memory space (PCIe
BAR_0) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE
BAR_1 space
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
13-31 16 Integer
0 Integer
G36 C_PCIEBAR2AXIBAR_1
C_PCIEBAR2AXIBAR_1
_SEC
G37 C_PCIEBAR_LEN_2
G38 C_PCIEBAR2AXIBAR_2
C_PCIEBAR2AXIBAR_2
_SEC
AXIBAR to which
PCIE BAR_1 is
mapped
Defines the AXIBAR
memory space (PCIe
BAR_1) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE
BAR_2 space
AXIBAR to which
PCIE BAR_2 is
mapped
Defines the AXIBAR
memory space (PCIe
BAR_2) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
AXI4-Lite Parameters
Device base address
Valid AXI address 0x0000_0000
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
13-31 16 Integer
Valid AXI address 0x0000_0000
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
0 Integer
0 Integer
std_logic_
vector
std_logic_
vector
G39 C_BASEADDR
G40 C_HIGHADDR Device high address Valid AXI address 0x0000_0000
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PG055 June 4, 2014
Note: When
configured as an
RP, the minimum
alignment
granularity must be
256 MB. Bit [27:0]
are used for Bus
Number, Device
Number, Function
number.
Valid AXI address 0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
AXI4-Lite port
C_S_AXI_CTL_
PROTOCOL
G41 C_NO_OF_LANES
connection
definition to AXI
Interconnect in the
Vivado IP integrator.
Core for PCIe Configuration Parameters
Number of PCIe
Lanes
AXI4LITE AXI4LITE String
1, 2, 4, 8: 7 series FPGAs 1 Integer
G42 C_DEVICE_ID Device ID 16-bit vector 0x0000
G43 C_VENDOR_ID Vendor I D 16-bit vector 0x0000
G44 C_CLASS_CODE Class Code 24-bit vector 0x00_0000
G45 C_REV_ID Rev ID 8-bit vector 0x00
G46 C_SUBSYSTEM_ID Subsystem ID 16-bit vector 0x0000
G47
C_SUBSYSTEM_
VENDOR_ID
C_PCIE_USE_MODE
Subsystem Vendor
ID
Specifies PCIe use
mode for underlying
serial transceiver
wrapper usage/
configuration
(specific only to 7
series).
This parameter
ignored for
Zynq-7000 devices
(set to 3.0).
16-bit vector 0x0000
See Tab le 2-6.
1.0: For Kintex-7 325T IES
(initial ES) silicon
1.1: For Virtex-7 485T IES
(initial ES) silicon
3.0: For GES (general ES)
silicon
1.0 String
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
G48
G49 C_REF_CLK_FREQ
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C_PCIE_CAP_SLOT_
IMPLEMENTED
PCIE Capabilities
Register Slot
Implemented
REFCLK input
Frequency
0: Not add-in card slot
1: Downstream port is
connected to add-in card
slot
(valid only for Root
Complex)
0: 100 MHz
1: 125 MHz
2: 250 MHz - 7 series
FPGAs only
0 Integer
0 Integer
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
Specifies the size of
the MSI request
vector for selecting
the number of
requested message
values.
Memory Mapped AXI4 Parameters
AXI Master Bus Data
width
0-5 0 Integer
64: 7 series FPGAs only
128: 7 series FPGAs only
64 Integer
G50
C_NUM_MSI_REQ
C_M_AXI_DATA_
WIDTH
G51
G52 C_S_AXI_ID_WIDTH
G53
G54
G55
G56 C_INTERRUPT_PIN
G57
C_M_AXI_ADDR_
WIDTH
C_S_AXI_DATA_
WIDTH
C_S_AXI_ADDR_
WIDTH
C_M_AXI_PROTOCOL
C_S_AXI_PROTOCOL
C_MAX_LINK_
SPEED
NUM_WRITE_
OUTSTANDING
AXI Master Bus
Address width
AXI Slave Bus ID
width
AXI Slave Bus Data
width
AXI Slave Bus
Address width
Protocol definition
for M_AXI (Master
Bridge) port on AXI
Interconnect in the
Vivado IP integrator.
Protocol definition
for S_AXI (Slave
Bridge) port on AXI
Interconnect in the
Vivado IP integrator.
Maximum PCIe link
speed supported
Legacy INTX pin
support/select
AXI4 Interconnect Parameters
AXI Interconnect
Slave Port Write
Pipeline Depth
32 32 Integer
4 4 Integer
64: 7 series FPGAs only
128: 7 series FPGAs only
32 32 Integer
AXI4 AXI4 String
AXI4 AXI4 String
0: 2.5 GT/s - 7 series
1: 5.0 GT/s - 7 series
0: No INTX support
(setting for Root Port)
1: INTA selected (only
allowable when core in
Endpoint configuration)
1: Only one active AXI
AWADDR can be accepted
in the AXI slave bridge for
PCIe
2: Maximum of two active
AXI AWADDR values can
be stored in AXI slave
bridge for PCIe
64 Integer
0 Integer
0 Integer
2 Integer
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Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
1: Only one active AXI
ARADDR can be accepted
in AXI slave bridge PCIe.
2, 4, 8: Size of pipeline for
active AXI ARADDR values
to be stored in AXI slave
bridge PCIe
A value of 8 is not allowed
for 128-bit core (Gen2 7
series) configurations. The
maximum setting of this
parameter value is 4.
1, 2, 4: Number of actively
issued AXI AWADDR
values on the AXI
Interconnect to the target
slave device(s).
8 Integer
4 Integer
G58
G59
NUM_READ_
OUTSTANDING
NUM_WRITE_
OUTSTANDING
AXI Interconnect
Slave Port Read
Pipeline Depth
AXI4 Master Interconnect Parameters
AXI Interconnect
Master Bridge write
address issue depth
G60
Notes:
1. This is a 32-bit address.
2. The width of this should match the address size (C_AXIBAR_AS) for this BAR.
3. The range specified must comprise a complete, contiguous power of two range, such that the range = 2
significant bits of the Base Address are zero. The address value is a 32-bit AXI address.
4. The difference between C_AXIBAR_n and C_AXIBAR_HIGHADDR_n must be less than or equal to 0x7FFF_FFFF and greater
than or equal to 0x0000_1FFF.
5. It is recommended that you do not edit these default values on the AXI bridge for PCIe IP unless you need to reduce the
resource utilization. Doing so impacts the AXI bridge performance.
NUM_READ_
OUTSTANDING
AXI Interconnect
Master Bridge read
address issue depth
1, 2, 4: Number of actively
issued AXI ARADDR values
on the AXI Interconnect to
the target slave device(s).
4 Integer
n
and the n least
Parameter Dependencies
Tab le 2-5 lists the parameter dependencies.
Table 2-5: Parameter Dependencies
Generic Parameter Affects Depends Description
G1 C_FAMILY
G2 C_INCLUDE_RC G1 Meaningful only if G1 = Kintex-7.
G3 C_COMP_TIMEOUT
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PG055 June 4, 2014
Bridge Parameters
G2, G41,
G49, G55
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Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
G10,
G14,
G4 C_INCLUDE_BAROFFSET_REG
G5
G6 C_AXIBAR_NUM
G7 C_AXIBAR_0 G8 G6, G8
G8 C_AXIBAR_HIGHADDR_0 G7 G6, G7
G9 C_AXIBAR_AS_0 G6
G10 C_AXIBAR2PCIEBAR_0 G4, G6 Meaningful when G4 = 1.
C_SUPPORTS_NARROW_
BURST
G18,
G22,
G26, G30
G4, G7 -
G30
G6
If G4 = 0, then G10, G14, G18, G22,
G26 and G30 have no meaning. The
number of registers included is set
by G6.
If G6 = 1, then G7 - G10 are enabled.
If G6 = 2, then G7 - G14 are enabled.
If G6 = 3, then G7 - G18 are enabled.
If G6 = 4, then G7 - G22 are enabled.
If G6 = 5, then G7 - G26 are enabled.
If G6 = 6, then G7 - G30 are enabled.
G7 and G8 define the range in AXI
memory space that is responded to
by this device (AXIBAR)
G7 and G8 define the range in AXI
memory space that is responded to
by this device (AXIBAR)
G11 and G12 define the range in
G11 C_AXIBAR_1 G12 G12
G12 C_AXIBAR_HIGHADDR_1 G11 G6, G11
G13 C_AXIBAR_AS_1 G6
G14 C_AXIBAR2PCIEBAR_1 G4, G6 Meaningful when G4 = 1.
G15 C_AXIBAR_2 G16 G16
G16 C_AXIBAR_HIGHADDR_2 G15 G6, G15
G17 C_AXIBAR_AS_2 G6
G18 C_AXIBAR2PCIEBAR_2 G4, G6 Meaningful when G4 = 1.
G19 C_AXIBAR_3 G20 G20
G20 C_AXIBAR_HIGHADDR_3 G19 G6, G19
AXI-memory space that is responded
to by this device (AXIBAR)
G11 and G12 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G15 and G16 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G15 and G16 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G19 and G20 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G19 and G20 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
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Chapter 2: Product Specification
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Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
G21 C_AXIBAR_AS_3 G6
G22 C_AXIBAR2PCIEBAR_3 G4, G6 Meaningful when G4 = 1.
G23 and G24 define the range in
G23 C_AXIBAR_4 G24 G24
G24 C_AXIBAR_HIGHADDR_4 G23 G6, G23
G25 C_AXIBAR_AS_4 G6
G26 C_AXIBAR2PCIEBAR_4 G4, G6 Meaningful if G4 = 1.
G27 C_AXIBAR_5 G28 G28
G28 C_AXIBAR_HIGHADDR_5 G27 G6, G27
AXI-memory space that is responded
to by this device (AXIBAR)
G23 and G24 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G29 C_AXIBAR_AS_5 G6
G30 C_AXIBAR2PCIEBAR_5 G4, G6 Meaningful if G4 = 1.
If G31 = 1, then G32, G33 are
enabled.
G31 C_PCIEBAR_NUM G33-G38
G32 C_PCIEBAR_AS
G33 C_PCIEBAR_LEN_0 G34 G31
G34 C_PCIEBAR2AXIBAR_0 G31, G33
G35 C_PCIEBAR_LEN_1 G36 G31
G36 C_PCIEBAR2AXIBAR_1 G31, G35
G37 C_PCIEBAR_LEN_2 G38 G31
G38 C_PCIEBAR2AXIBAR_2 G31, G37
If G31 = 2, then G32 - G36 are
enabled.
If G31 = 3, then G32 - G38 are
enabled
Only the high-order bits above the
length defined by G33 are
meaningful.
Only the high-order bits above the
length defined by G35 are
meaningful.
Only the high-order bits above the
length defined by G37 are
meaningful.
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PG055 June 4, 2014
Chapter 2: Product Specification
Parameter Setting Result
G1 = Kintex-7 &
G50 = G53 = 64
G41 = 1, 2, or 4 (Gen1),
or G41 = 1 or 2 (Gen2)
G1 = Kintex-7 &
G50 = G53 = 128
G41 = 1, 2, 4, or 8
(Gen1) or 1, 2, or 4
(Gen2)
Send Feedback
Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
Core for PCIe Configuration Parameters
G41 C_NO_OF_LANES
G42 C_DEVICE_ID
G43 C_VENDOR_ID
G44 C_CLASS_CODE
G45 C_REV_ID
G46 C_SUBSYSTEM_ID
G47 C_SUBSYSTEM_VENDOR_ID
G48
G49 C_REF_CLK_FREQ G1
C_PCIE_CAP_SLOT_
IMPLEMENTED
G1, G50,
G53
G2 If G2 = 0, G48 is not meaningful
Memory-Mapped AXI4 Bus Parameters
G50 C_M_AXI_DATA_WIDTH G53
G51 C_M_AXI_ADDR_WIDTH G54 G54 G51 must be equal to G54
G52 C_S_AXI_ID_WIDTH
G1, G41,
G53
G50 must be equal to G53
G53 C_S_AXI_DATA_WIDTH G50
G54 C_S_AXI_ADDR_WIDTH G51 G51 G54 must be equal to G51
G55 C_MAX_LINK_SPEED G1
G56 C_INTERRUPT_PIN
Tab le 2-6 summarizes the relationship between the IP design parameters, C_FAMILY and
C_PCIE_USE_MODE. The C_PCIE_USE_MODE is used to specify the 7 series (and derivative
FPGA technology) serial transceiver wrappers to use based on the silicon version. Initial
Engineering Silicon (IES) as well as General Engineering Silicon (GES) must be specified.
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G1, G41,
G50
G53 must be equal to G50
Table 2-6: Silicon Version Specification
Send Feedback
C_FAMILY C_PCIE_USE_MODE
Chapter 2: Product Specification
Kintex-7
Virtex-7
Artix-7
Zynq Not applicable. (set internally = 3.0)
1.1 = for Kintex-7 325T IES (initial silicon)
3.0 = for GES (general silicon)
1.1 = for Virtex-7 485T IES (initial silicon)
3.0 = for GES and Production (general silicon and Production silicon)
1.0 = for IES (initial silicon) as well as GES and Production (General silicon and Production
silicon) to use latest serial transceiver wrappers (only allowable value)
Memory Map
The memory map shown in Ta ble 2-7 shows the address mapping for the AXI Bridge for PCI
Express core. These registers are described in more detail in the following section. All
registers are accessed through the AXI4-Lite Control Interface and are offset from
C_BASEADDR. During a reset, all registers return to default values.
Table 2-7: Register Memory Map
Accessibility Offset Contents Location
RO - EP, R/W - RC 0x000 - 0x124 PCIe Configuration Space Header
Part of integrated PCIe
configuration space.
RO 0x128
RO 0x12C VSEC Header
RO 0x130 Bridge Info
RO - EP, R/W - RC 0x134 Bridge Status and Control
R/W 0x138 Interrupt Decode
R/W 0x13C Interrupt Mask
RO - EP, R/W - RC 0x140 Bus Location
RO 0x144 Physical-Side Interface (PHY) Status/Control
RO - EP, R/W - RC 0x148 Root Port Status/Control
RO - EP, R/W - RC 0x14C Root Port MSI Base 1
RO - EP, R/W - RC 0x150 Root Port MSI Base 2
RO - EP, R/W - RC 0x154 Root Port Error FIFO Read
RO - EP, R/W - RC 0x158 Root Port Interrupt FIFO Read 1
RO - EP, R/W - RC 0x15C Root Port Interrupt FIFO Read 2
RO 0x160 - 0x1FF Reserved (zeros returned on read)
RO 0x200 VSEC Capability 2
Vendor-Specific Enhanced Capability (VSEC)
Capability
VSEC of integrated PCIe
configuration space.
AXI bridge defined
memory-mapped
register space.
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Chapter 2: Product Specification
Send Feedback
Table 2-7: Register Memory Map (Cont’d)
Accessibility Offset Contents Location
RO 0x204 VSEC Header 2
R/W 0x208 - 0x234
RO 0x238 - 0xFFF Reserved (zeros returned on read)
AXI Base Address Translation Configuration
Registers
PCIe Configuration Space Header
The PCIe Configuration Space Header is a memory aperture for accessing the core for PCIe
configuration space. For 7 series devices, this area is read-only when configured as an
Endpoint. Writes are permitted for some registers when a 7 series device is configured as a
Root Port. Special access modes can be enabled using the PHY Status/Control register. All
reserved or undefined memory-mapped addresses must return zero and writes have no
effect.
VSEC Capability Register (Offset 0x128)
The VSEC Capability register (described in Tabl e 2-8) allows the memory space of the core
to appear as though it is a part of the underlying core configuration space. The VSEC is
inserted immediately following the last enhanced capability structure in the underlying
block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19 of v2.0)
[Ref 5].
AXI bridge defined
memory-mapped
space.
Table 2-8: VSEC Capability Register
Bits Name
15:0 VSEC Capability ID RO 0x000B
19:16 Capability Version RO 0x1 Version of this capability structure. Hardcoded to 0x1.
31:20
Next Capability
Offset
Core
Access
RO 0x200 Offset to next capability. Hardcoded to 0x0200.
Reset Value Description
PCI-SIG® defined ID identifying this Enhanced
Capability as a Vendor-Specific capability. Hardcoded to
0x000B.
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VSEC Header Register (Offset 0x12C)
Send Feedback
The VSEC Header register (described in Tab le 2-9) provides a unique (within a given vendor)
identifier for the layout and contents of the VSEC structure, as well as its revision and
length.
Table 2-9: VSEC Header Register
Chapter 2: Product Specification
Bits Name
15:0 VSEC ID RO 0x0001
19:16 VSEC REV RO 0 Version of this capability structure. Hardcoded to 0h.
31:20 VSEC Length RO 0x038
Core
Access
Reset Value Description
ID value uniquely identifying the nature and format of
this VSEC structure.
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hardcoded to
0x038 (56 decimal).
Bridge Info Register (Offset 0x130)
The Bridge Info register (described in Ta bl e 2-10) provides general configuration
information about the AXI4-Stream Bridge. Information in this register is static and does
not change during operation.
Table 2-10: Bridge Info Register
Bits Name
0 Gen 2 C apa bl e RO 0
1 Root Port Present RO 0
Core
Access
Reset
Val u e
Description
If set, indicates the link is Gen2 capable. Underlying integrated
block and Link partner support PCIe Gen2 speed.
Indicates the underlying integrated block is a Root Port when
this bit is set.
If set, Root Port registers are present in this interface.
2
15:3 Reserved RO 0 Reserved
18:16 ECAM Size RO 0
31:19 Reser ved RO 0 Reserved
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Up Config
Capable
RO
Indicates the underlying integrated block is upconfig capable
when this bit is set.
Size of Enhanced Configuration Access Mechanism (ECAM) Bus
Number field, in number of bits. If ECAM window is present,
value is between 1 and 8. If not present, value is 0. Total address
bits dedicated to ECAM window is 20+(ECAM Size).
The size of the ECAM is determined by the parameter settings
of C_BASEADDR and C_HIGHADDR.
Bridge Status and Control Register (Offset 0x134)
Send Feedback
The Bridge Status and Control register (described in Tab le 2-11) provides information about
the current state of the AXI4-Stream Bridge. It also provides control over how reads and
writes to the Core Configuration Access aperture are handled.
Table 2-11: Bridge Status and Control Register
Chapter 2: Product Specification
Bits Name
0 ECAM Busy RO 0
7:1 Reserved RO 0 Reser ved
8
15:9 Reserved RO 0 Reser ved
16 RW1C as RW RW 0
17 RO as RW RW 0
31:18 Reser ved RO 0 Reserved
Global
Disable
Core
Access
RW 0
Reset
Value
Indicates an ECAM access is in progress (waiting for
completion).
When set, disables interrupt line from being asserted. Does not
prevent bits in Interrupt Decode register from being set.
When set, allows writing to core registers which are normally
RW1C.
When set, allows writing to certain registers which are normally
RO.
(Only supported for Kintex-7 FPGA cores.)
Interrupt Decode Register (Offset 0x138)
The Interrupt Decode register (described in Tab le 2-12) provides a single location where the
host processor interrupt service routine can determine what is causing the interrupt to be
asserted and how to clear the interrupt. Writing a 1'b1 to any bit of the Interrupt Decode
register clears that bit except for the Correctable, Non-Fatal, and Fatal bits.
Description
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Follow this sequence to clear the Correctable, Non-Fatal, and Fatal bits:
1. Clear the Root Port Error FIFO (0x154) by performing first a read, followed by write-back
of the same register.
2. Write to the Interrupt Decode Register (0x138) with ‘1’ to the appropriate error bit to
clear it.
IMPORTANT: An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert
unless the corresponding bit in the Interrupt Mask register is also set.
Table 2-12: Interrupt Decode Register
Send Feedback
Chapter 2: Product Specification
Bits Name
0 Link Down RW1C 0
1 ECRC Error RW1C 0
2 Streaming Error RW1C 0
3 Hot Reset RW1C 0 Indicates a Hot Reset was detected.
4 Reser ved RO 0 Reserved
7:5
8 Cfg Timeout RW1C 0
9 Correctable RW1C 0
10 Non-Fatal RW1C 0
Cfg Completion
Status
Core
Access
RW1C 0 Indicates config completion status.
Reset
Value
Description
Indicates that Link-Up on the PCI Express link was lost. Not
asserted unless link-up had previously been seen.
Indicates Received packet failed ECRC check.
(Only applicable to Kintex-7 FPGA cores.)
Indicates a gap was encountered in a streamed packet on the TX
interface (RW, RR, or CC).
Indicates timeout on an ECAM access.
(Only applicable to Root Port cores.)
Indicates a correctable error message was received.
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates a non-fatal error message was received.
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates a fatal error message was received.
11 Fatal RW1C 0
15:12 Reser ved RO 0 Reser ved
16
17
19:18 Reser ved RO 0 Reser ved
20
21
22
23 Slave Error Poison RW1C 0 Indicates the EP bit was set in a completion TLP.
INTx Interrupt
Received
MSI Interrupt
Received
Slave
Unsupported
Request
Slave Unexpected
Completion
Slave Completion
Timeout
RW1C 0
RW1C 0
RW1C 0
RW1C 0
RW1C 0
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates an INTx interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
Indicates an MSI(x) interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
Indicates that a completion TLP was received with a status of
0b001 - Unsupported Request.
Indicates that a completion TLP was received that was
unexpected.
Indicates that the expected completion TLP(s) for a read request
for PCIe was not returned within the time period selected by the
C_COMP_TIMEOUT parameter.
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