LogiCORE IP AXI
Bridge for PCI Express
v2.4
Product Guide
Vivado Design Suite
PG055 June 4, 2014
Table of Contents
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IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bridge Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parameter Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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PG055 June 4, 2014
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AXI Transactions for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transaction Ordering for PCIe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Malformed TLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Abnormal Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Root Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Simulation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Implementation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 6: Test Bench
Appendix A: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transceiver Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
AXI Bridge for PCI Express v2.4 www.xilinx.com 3
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IP Facts
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Introduction
The Xilinx® LogiCORE™ IP AXI Root Port/
Endpoint (RP/EP) Bridge for PCI Express® core
is an interface between the AXI4 and PCI
Express. Definitions and references are
provided in this document for all of the
functional modules, registers, and interfaces
that are implemented in the AXI Bridge for PCI
Express core. Definitions are also provided for
the hardware implementation and software
interfaces to the AXI Bridge for PCI Express core
in supported FPGA devices.
Features
• Zynq®-7000, Kintex®-7, Virtex®-7, and
Artix®-7 FPGA Integrated Blocks for PCI
Express
• Maximum Payload Size (MPS) up to 256 bytes
• Multiple Vector Messaged Signaled Interrupts
(MSIs)
•Legacy interrupt support
• Memory-mapped AXI4 access to PCIe® space
• PCIe access to memory-mapped AXI4 space
• Tracks and manages Transaction Layer Packets
(TLPs) completion processing
• Detects and indicates error conditions with
interrupts
• Optimal AXI4 pipeline support for enhanced
performance
• Compliant with Advanced RISC Machine
(ARM®) Advanced Microcontroller Bus
Architecture 4 (AMBA®) AXI4 specification
• Supports up to three PCIe 32-bit or 64-bit
PCIe Base Address Registers (BARs) as
Endpoint
• Supports a single PCIe 32-bit or 64-bit BAR as
Root Port
LogiCORE IP Facts Table
Core Specifics
Supported
Device
(1)
Family
Supported
User Interfaces
Resources See Tab l e 2 - 2
Zynq-7000, 7 Series
AXI4
Provided with Core
Design Files VHDL and Verilog
Example
Design
Tes t B en c h Verilog
Constraints
File
Simulation
Model
Supported
S/W Driver
(2)
Tested Design Flows
Design Entry
Simulation
Synthesis Vivado Synthesis
Xilinx Design Tools: Release Notes Guide
For supported simulators, see the
Standalone and Linux
(3)
Vivado® Design Suite
Vivado IP integrator
Verilog
XDC
Not Provided
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog. See also Table 2-1, page 11.
2. Standalone driver details can be found in the SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux
OS and driver support information is available from
wiki.xilinx.com
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
4. Except for XC7VX485T, Virtex 7 devices are not supported.
.
.
(1)
AXI Bridge for PCI Express v2.4 www.xilinx.com 4
PG055 June 4, 2014 Product Specification
Overview
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The AXI Bridge for PCI Express® core is designed for the Vivado® IP integrator in the
Vivado Design Suite. The AXI Bridge for PCI Express core provides an interface between an
AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI
Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4
embedded system to the PCI Express system. The AXI Bridge for PCI Express core translates
the AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets and
translates PCIe memory read and write request TLP packets to AXI4 interface commands.
The architecture of the AXI Bridge for PCI Express is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Chapter 1
AXI Bridge for PCI Express v2.4 www.xilinx.com 5
PG055 June 4, 2014
Figure 1-1: High-Level AXI Bridge for PCI Express Architecture
Chapter 1: Overview
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Feature Summary
The AXI Bridge for PCI Express core is an interface between the AXI4 and PCI Express. It
contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced
Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a
register block and two functional half bridges, referred to as the Slave Bridge and Master
Bridge. The Slave Bridge connects to the AXI4 Interconnect as a slave device to handle any
issued AXI4 master read or write requests. The Master Bridge connects to the AXI4
Interconnect as a master to process the PCIe generated read or write TLPs. The core uses a
set of interrupts to detect and flag error conditions.
The AXI Bridge for PCI Express core supports both Root Port and Endpoint configurations.
• When configured as an Endpoint, the AXI Bridge for PCI Express core supports up to
three 32-bit or 64-bit PCIe Base Address Registers (BARs).
• When configured as a Root Port, the core supports a single 32-bit or 64-bit PCIe BAR.
The AXI Bridge for PCI Express core is compliant with the PCI Express Base Specification v2.0
[Ref 5] and with the AMBA® AXI4 specification [Ref 4].
Unsupported Features
The following features are not supported in the AXI Bridge for PCI Express core.
• Tandem PROM and Tandem PCIe
• Advanced Error Reporting (AER)
Limitations
Reference Clock for PCIe Frequency Value
The refclk input used by the serial transceiver for PCIe must be 100 MHz, 125 MHz, and
MHz for 7 series and Zynq®-7000 device configurations. The C_REF_CLK_FREQ
250
parameter is used to set this value, as defined in
Tab le 2-4, page 15.
AXI Bridge for PCI Express v2.4 www.xilinx.com 6
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Chapter 1: Overview
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Licensing and Ordering Information
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
For more information, visit the AXI Bridge for PCI Express product page.
Xilinx End User License.
AXI Bridge for PCI Express v2.4 www.xilinx.com 7
PG055 June 4, 2014
Product Specification
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Figure 2-1 shows the architecture of the AXI Bridge for PCI Express® core.
X-Ref Target - Figure 2-1
Chapter 2
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PG055 June 4, 2014
Figure 2-1: AXI Bridge for PCI Express Architecture
The Register block contains registers used in the AXI Bridge for PCI Express core for
dynamically mapping the AXI4 memory mapped (MM) address range provided using the
AXIBAR parameters to an address for PCIe range.
The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI
master device (such as a processor). The Slave Bridge provides a way to translate addresses
that are mapped within the AXI4 memory mapped address domain to the domain addresses
for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the
write address and qualifiers are captured and write data is queued in a first in first out
(FIFO). These are then converted into one or more MemWr TLPs, depending on the
Chapter 2: Product Specification
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configured Max Payload Size setting, which are passed to the Integrated Block for PCI
Express.
A second remote AXI master initiated write request write address and qualifiers can then be
captured and the associated write data queued, pending the completion of the previous
write TLP transfer to the core. The resulting AXI Slave Bridge write pipeline is two-deep.
When a remote AXI master initiates a read transaction to the Slave Bridge, the read address
and qualifiers are captured and a MemRd request TLP is passed to the core and a
completion timeout timer is started. Completions received through the core are correlated
with pending read requests and read data is returned to the AXI master. The Slave bridge is
capable of handling up to eight memory mapped AXI4 read requests with pending
completions.
The Master Bridge processes both PCIe MemWr and MemRd request TLPs received from the
integrated block for PCI Express and provides a means to translate addresses that are
mapped within the address for PCIe domain to the memory mapped AXI4 address domain.
Each PCIe MemWr request TLP header is used to create an address and qualifiers for the
memory mapped AXI4 bus and the associated write data is passed to the addressed
memor y mapped AXI4 Slave. The Master Bridge can support up to four active PCIe MemWr
request TLPs.
Each PCIe MemRd request TLP header is used to create an address and qualifiers for the
memory-mapped AXI4 bus. Read data is collected from the addressed memory mapped
AXI4 Slave and used to generate completion TLPs which are then passed to the integrated
block for PCI Express. The Master bridge can handle up to four read requests with pending
completions for improved AXI4 pipelining performance.
The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the
Requester/Completer interfaces to the AXI bridge and the Register block. The Register
block contains the status, control, interrupt registers, and the AXI4-Lite interface.
Standards
The AXI Bridge for PCIe core is compliant with the ARM® AMBA® AXI4 Protocol
Specification
[Ref 4] and the PCI Express Base Specification v2.0 [Ref 5].
AXI Bridge for PCI Express v2.4 www.xilinx.com 9
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Performance
AXI4-Lite
MicroBlaze
Controller
AXI INTC
AXI GPIO
AXI UARTLite
AXI4
Memory
Controller
MDM
MicroBlaze
Domain
AXI4
Block RAM
Controller
D_LMB
I_LMB
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AXI Block Ram
(DC)
AXI PCIe
Memory
(DP)
LEDs
RS232
AXI CDMA
MemoryMap
Interconnect
(AXI4)
Control
Interface
Subset
Interconnect
(AXI4-Lite)
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Figure 2-2 shows a configuration diagram for a target FPGA.
X-Ref Target - Figure 2-2
Chapter 2: Product Specification
AXI Bridge for PCI Express v2.4 www.xilinx.com 10
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Figure 2-2: FPGA System Configuration Diagram
The target FPGA is filled with logic to drive the lookup table (LUT) and block RAM utilization
to approximately 70% and the I/O utilization to approximately 80%.
Maximum Frequencies
The maximum frequency for the AXI clock is 125 MHz for 7 series FPGAs.
Line Rate Support for PCIe Gen1/Gen2
The link speed, number of lanes supported, and support of line rate for PCIe are defined in
Tab le 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock
frequency, the AXI data width, the number of lanes, and Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s)
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link speed.
Table 2-1: Line Rate for PCIe Support for Gen1/Gen2
Chapter 2: Product Specification
C_FAMILY C_X_AXI_DATA_WIDTH
64
7 series,
Zynq®-7000
128
Notes:
1. x8 Gen2 configuration is not supported. Artix-7 does not support x8 Gen1.
PCIe Link
Speed
Gen 1
Gen 2 x1, 2
Gen 1,
Gen 2
C_NO_OF_LANES
x1, 2, 4, 8
x1 62.5 MHz 62.5 MHz 62.5 MHz
x2, 4
(1)
Resource Utilization
Tab le 2-2 illustrates a subset of IP core conf igurations and the device utilization estimates.
Variation in tools and optimization settings can result in variance of these reported
numbers.
Tab le 2-2 shows the resource utilization for the AXI Bridge for PCIe core for different
configurations on the Virtex-7 XC7V2000T device. These numbers were generated in the
Vivado® Design Suite. Resource Utilization numbers for other devices can be generated by
implementing the provided example design and checking for the resources used by only
the core in the resource utilization report.
AXI_ACLK
_OUT
125 MHz 125 MHz 125 MHz
125 MHz 250 MHz 125 MHz
Userclk1 Userclk2
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Table 2-2: Resource Utilization Summary
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Configuration Slice Registers Slice LUTs
Chapter 2: Product Specification
Endpoint x1 Gen1
Endpoint x2 Gen1
Endpoint x4 Gen1
Endpoint x8 Gen1
Endpoint x1 Gen2
Endpoint x2 Gen2
Endpoint x4 Gen2
Root Port x1 Gen1
Root Port x2 Gen1
Root Port x4 Gen1
Root Port x8 Gen1
Root Port x1 Gen2
Root Port x2 Gen2
Root Port x4 Gen2
Port Descriptions
8678 13054
8963 13300
9558 13666
11912 17355
8620 14041
8897 14362
10629 16477
10703 15909
10836 15537
11431 15924
13805 20128
10674 16734
11062 17137
12563 19325
The interface signals for the AXI Bridge for PCI Express are described in Tab le 2-3.
Table 2-3: Top-Level Interface Signals
Signal Name I/O Description
Global Signals
refclk I PCIe Reference Clock
axi_aresetn I Global reset signal for AXI Interfaces
axi_aclk_out O PCIe derived clock output for axi_aclk
axi_ctl_aclk_out O PCIe derived clock output for axi_ctl_aclk
mmcm_lock O axi_aclk_out from the axi_enhanced_pcie block is stable
interrupt_out O Interrupt signal
AXI Slave Interface
s_axi_awid[c_s_axi_id_width-1:0] I Slave write address ID
s_axi_awaddr[c_s_axi_addr_width-1:0] I Slave address write
s_axi_awregion[3:0] I Slave write region decode
s_axi_awlen[7:0] I Slave write burst length
s_axi_awsize[2:0] I Slave write burst size
AXI Bridge for PCI Express v2.4 www.xilinx.com 12
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Table 2-3: Top-Level Interface Signals (Cont’d)
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Signal Name I/O Description
s_axi_awburst[1:0] I Slave write burst type
s_axi_awvalid I Slave address write valid
s_axi_awready O Slave address write ready
s_axi_wdata[c_s_axi_data_width-1:0] I Slave write data
s_axi_wstrb[c_s_axi_data_width/8-1:0] I Slave write strobe
s_axi_wlast I Slave write last
s_axi_wvalid I Slave write valid
s_axi_wready O Slave write ready
s_axi_bid[c_s_axi_id_width-1:0] O Slave response ID
s_axi_bresp[1:0] O Slave write response
s_axi_bvalid O Slave write response valid
s_axi_bready I Slave response ready
s_axi_arid[c_s_axi_id_width-1:0] I Slave read address ID
Chapter 2: Product Specification
s_axi_araddr[c_s_axi_addr_width-1:0] I Slave read address
s_axi_arregion[3:0] I Slave read region decode
s_axi_arlen[7:0] I Slave read burst length
s_axi_arsize[2:0] I Slave read burst size
s_axi_arburst[1:0] I Slave read burst type
s_axi_arvalid I Slave read address valid
s_axi_arready O Slave read address ready
s_axi_rid[c_s_axi_id_width-1:0] O Slave read ID tag
s_axi_rdata[c_s_axi_data_width-1:0] O Slave read data
s_axi_rresp[1:0] O Slave read response
s_axi_rlast O Slave read last
s_axi_rvalid O Slave read valid
s_axi_rready I Slave read ready
AXI Master Interface
m_axi_awaddr[c_m_axi_addr_width-1:0] O Master address write
m_axi_awlen[7:0] O Master write burst length
m_axi_awsize[2:0] O Master write burst size
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m_axi_awburst[1:0] O Master write burst type
m_axi_awprot[2:0] O Master write protection type
m_axi_awvalid O Master write address valid
m_axi_awready I Master write address ready
m_axi_wdata[c_m_axi_data_width-1:0] O Master write data
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Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
m_axi_wstrb[c_m_axi_data_width/8-1:0] O Master write strobe
m_axi_wlast O Master write last
m_axi_wvalid O Master write valid
m_axi_wready I Master write ready
m_axi_bresp[1:0] I Master write response
m_axi_bvalid I Master write response valid
m_axi_bready O Master response ready
m_axi_araddr[c_m_axi_addr_width-1:0] O Master read address
m_axi_arlen[7:0] O Master read burst length
m_axi_arsize[2:0] O Master read burst size
m_axi_arburst[1:0] O Master read burst type
m_axi_arprot[2:0] O Master read protection type
m_axi_arvalid O Master read address valid
m_axi_arready I Master read address ready
m_axi_rdata[c_m_axi_data_width-1:0] I Master read data
m_axi_rresp[1:0] I Master read response
m_axi_rlast I Master read last
m_axi_rvalid I Master read valid
m_axi_rready O Master read ready
AXI4-Lite Control Interface
s_axi_ctl_awaddr[31:0] I Slave write address
s_axi_ctl_awvalid I Slave write address valid
s_axi_ctl_awready O Slave write address ready
s_axi_ctl_wdata[31:0] I Slave write data
s_ax_ctl_wstrb[3:0] I Slave write strobe
s_axi_ctl_wvalid I Slave write valid
s_axi_ctl_wready O Slave write ready
s_axi_ctl_bresp[1:0] O Slave write response
s_axi_ctl_bvalid O Slave write response valid
s_axi_ctl_bready I Slave response ready
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s_axi_ctl_araddr[31:0] I Slave read address
s_axi_ctl_arvalid I Slave read address valid
s_axi_ctl_arready O Slave read address ready
s_axi_ctl_rdata[31:0] O Slave read data
s_axi_ctl_rresp[1:0] O Slave read response
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Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
s_axi_ctl_rvalid O Slave read valid
s_axi_ctl_rready I Slave read ready
MSI Signals
Legacy interrupt input (see c_interrupt_pin) when
intx_msi_request I
intx_msi_grant O
msi_enable O Indicates when MSI is enabled.
msi_enable = 0.
Initiates a MSI write request when msi_enable = 1.
Intx_msi_request is asserted for one clock period.
Indicates legacy interrupt/MSI grant signal. The
intx_msi_grant signal is asserted for one clock period
when the interrupt is accepted by the PCIe core.
msi_vector_num [4:0] I
msi_vector_width [2:0] O
Indicates MSI vector to send when writing a MSI write
request.
Indicates the size of the MSI field (the number of MSI
vectors allocated to the device).
PCIe Interface
pci_exp_rxp[c_no_of_lanes-1: 0] I PCIe RX serial interface
pci_exp_rxn[c_no_of_lanes-1: 0] I PCIe RX serial interface
pci_exp_txp[c_no_of_lanes-1: 0] O PCIe TX serial interface
pci_exp_txn[c_no_of_lanes-1:0] O PCIe TX serial interface
Bridge Parameters
Because many features in the AXI Bridge for PCI Express core design can be parameterized,
you are able to uniquely tailor the implementation of the core using only the resources
required for the desired functionality. This approach also achieves the best possible
performance with the lowest resource usage.
The parameters defined for the AXI Bridge for PCI Express are shown in Tab le 2-4.
Table 2-4: To p- L ev el P a ra m et e rs
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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C_PCIE_BLK_LOCN
Bridge Parameters
PCIe integrated
block location
within FPGA
0: X0Y0
1: X0Y1
2: X0Y2
3: X1Y0
4: X1Y1
0 String
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
NONE
KC705_REVA
C_XLNX_REF_BOARD Target FPGA Board
KC705_REVB
KC705_REVC
VC707
NONE String
G1 C_FAMILY Target FPGA Family
Configures the AXI
G2 C_INCLUDE_RC
G3 C_COMP_TIMEOUT
G4
G5
C_INCLUDE_
BAROFFSET_REG
C_SUPPORTS_
NARROW_BURST
bridge for PCIe to be
a Root Port or an
Endpoint
Selects the Slave
Bridge completion
timeout counter
value
Include the registers
for high-order bits
to be substituted in
translation in Slave
Bridge
Instantiates internal
logic to support
narrow burst
transfers. Only
enable when AXI
master bridge
generates narrow
burst traffic.
kintex7, virtex7, artix7,
zynq
0: Endpoint
1: Root Port (applies only
series, and
for 7
Zynq-7000 devices)
0: 50 µs
1: 50 ms
0: Exclude
1: Include
0: Not supported
1: Supported
String
0 Integer
0 Integer
0 Integer
0 Integer
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G6 C_AXIBAR_NUM
G7 C_AXIBAR_0
G8
G9 C_AXIBAR_AS_0
C_AXIBAR_
HIGHADDR_0
Number of AXI
address apertures
that can be accessed
AXI BAR_0 aperture
low address
AXI BAR_0 aperture
high address
AXI BAR_0 address
size
1-6;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
4: BAR_0 through BAR_3
enabled
5: BAR_0 through BAR_4
enabled
6: BAR_0 through BAR_5
enabled
Valid AXI address
Valid AXI address
0: 32 bit
1: 64 bit
(1)(3)(4)
(1)(3)(4)
6 Integer
0xFFFF_FFFF
0x0000_0000
0 Integer
std_logic_
vector
std_logic_
vector
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
G10 C_AXIBAR2PCIEBAR_0
G11 C_AXIBAR_1
G12
C_AXIBAR_
HIGHADDR_1
G13 C_AXIBAR_AS_1
G14 C_AXIBAR2PCIEBAR_1
G15 C_AXIBAR_2
G16
C_AXIBAR_
HIGHADDR_2
G17 C_AXIBAR_AS_2
G18 C_AXIBAR2PCIEBAR_2
PCIe BAR to which
AXI BAR_0 is
mapped
AXI BAR_1 aperture
low address
AXI BAR_1 aperture
high address
AXI BAR_1 address
size
PCIe BAR to which
AXI BAR_1 is
mapped
AXI BAR_2 aperture
low address
AXI BAR_2 aperture
high address
AXI BAR_2 address
size
PCIe BAR to which
AXI BAR_2 is
mapped
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
(2)
(2)
(2)
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
G19 C_AXIBAR_3
G20
C_AXIBAR_
HIGHADDR_3
G21 C_AXIBAR_AS_3
G22 C_AXIBAR2PCIEBAR_3
G23 C_AXIBAR_4
G24
C_AXIBAR_
HIGHADDR_4
G25 C_AXIBAR_AS_4
G26 C_AXIBAR2PCIEBAR_4
G27 C_AXIBAR_5
AXI BAR_3 aperture
low address
AXI BAR_3 aperture
high address
AXI BAR_3 address
size
PCIe BAR to which
AXI BAR_3 is
mapped
AXI BAR_4 aperture
low address
AXI BAR_4 aperture
high address
AXI BAR_4 address
size
PCIe BAR to which
AXI BAR_4 is
mapped
AXI BAR_5 aperture
low address
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
Valid AXI address
(1)(3)(4)
(1)(3)(4)
0: 32 bit
1: 64 bit
Valid address for PCIe
Valid AXI address
(1)(3)(4)
(2)
(2)
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0 Integer
0xFFFF_FFFF
0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
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PG055 June 4, 2014
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
G28
G29 C_AXIBAR_AS_5
G30 C_AXIBAR2PCIEBAR_5
G31 C_PCIEBAR_NUM
G32 C_PCIEBAR_AS
C_AXIBAR_
HIGHADDR_5
AXI BAR_5 aperture
high address
AXI BAR_5 address
size
PCIe BAR to which
AXI BAR_5 is
mapped
Number of address
for PCIe apertures
that can be accessed
Configures PCIEBAR
aperture width to be
32 bits wide or 64
bits wide
Valid AXI address
0: 32 bit
1: 64 bit
Valid address for PCIe
1-3;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
0: Generates three 32-bit
PCIEBAR address
apertures.
32-bit BAR example:
PCIEBAR_0 is 32 bits
PCIEBAR_1 is 32 bits
PCIEBAR_2 is 32 bits
1: Generates three 64 bit
PCIEBAR address
apertures.
64-bit BAR example:
PCIEBAR_0 and PCIEBAR_1
concatenate to comprise
64-bit PCIEBAR_0.
(1)(3)(4)
(2)
0x0000_0000
0 Integer
0xFFFF_FFFF
3 Integer
1 Integer
std_logic_
vector
std_logic_
vector
G33 C_PCIEBAR_LEN_0
G34 C_PCIEBAR2AXIBAR_0
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PG055 June 4, 2014
Power of 2 in the
size of bytes of PCIE
BAR_0 space
AXIBAR to which
PCIE BAR_0 is
mapped
PCIEBAR_2 and PCIEBAR_3
concatenate to comprise
64-bit PCIEBAR_1.
PCIEBAR_4 and PCIEBAR_5
concatenate to comprise
64-bit PCIEBAR_2
13-31 16 Integer
Valid AXI address 0x0000_0000
std_logic_
vector
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
Defines the AXIBAR
C_PCIEBAR2AXIBAR_0
_SEC
G35 C_PCIEBAR_LEN_1
memory space (PCIe
BAR_0) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE
BAR_1 space
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
13-31 16 Integer
0 Integer
G36 C_PCIEBAR2AXIBAR_1
C_PCIEBAR2AXIBAR_1
_SEC
G37 C_PCIEBAR_LEN_2
G38 C_PCIEBAR2AXIBAR_2
C_PCIEBAR2AXIBAR_2
_SEC
AXIBAR to which
PCIE BAR_1 is
mapped
Defines the AXIBAR
memory space (PCIe
BAR_1) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
Power of 2 in the
size of bytes of PCIE
BAR_2 space
AXIBAR to which
PCIE BAR_2 is
mapped
Defines the AXIBAR
memory space (PCIe
BAR_2) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
AXI4-Lite Parameters
Device base address
Valid AXI address 0x0000_0000
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
13-31 16 Integer
Valid AXI address 0x0000_0000
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
0 Integer
0 Integer
std_logic_
vector
std_logic_
vector
G39 C_BASEADDR
G40 C_HIGHADDR Device high address Valid AXI address 0x0000_0000
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PG055 June 4, 2014
Note: When
configured as an
RP, the minimum
alignment
granularity must be
256 MB. Bit [27:0]
are used for Bus
Number, Device
Number, Function
number.
Valid AXI address 0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
AXI4-Lite port
C_S_AXI_CTL_
PROTOCOL
G41 C_NO_OF_LANES
connection
definition to AXI
Interconnect in the
Vivado IP integrator.
Core for PCIe Configuration Parameters
Number of PCIe
Lanes
AXI4LITE AXI4LITE String
1, 2, 4, 8: 7 series FPGAs 1 Integer
G42 C_DEVICE_ID Device ID 16-bit vector 0x0000
G43 C_VENDOR_ID Vendor I D 16-bit vector 0x0000
G44 C_CLASS_CODE Class Code 24-bit vector 0x00_0000
G45 C_REV_ID Rev ID 8-bit vector 0x00
G46 C_SUBSYSTEM_ID Subsystem ID 16-bit vector 0x0000
G47
C_SUBSYSTEM_
VENDOR_ID
C_PCIE_USE_MODE
Subsystem Vendor
ID
Specifies PCIe use
mode for underlying
serial transceiver
wrapper usage/
configuration
(specific only to 7
series).
This parameter
ignored for
Zynq-7000 devices
(set to 3.0).
16-bit vector 0x0000
See Tab le 2-6.
1.0: For Kintex-7 325T IES
(initial ES) silicon
1.1: For Virtex-7 485T IES
(initial ES) silicon
3.0: For GES (general ES)
silicon
1.0 String
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
std_logic_
vector
G48
G49 C_REF_CLK_FREQ
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C_PCIE_CAP_SLOT_
IMPLEMENTED
PCIE Capabilities
Register Slot
Implemented
REFCLK input
Frequency
0: Not add-in card slot
1: Downstream port is
connected to add-in card
slot
(valid only for Root
Complex)
0: 100 MHz
1: 125 MHz
2: 250 MHz - 7 series
FPGAs only
0 Integer
0 Integer
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
Specifies the size of
the MSI request
vector for selecting
the number of
requested message
values.
Memory Mapped AXI4 Parameters
AXI Master Bus Data
width
0-5 0 Integer
64: 7 series FPGAs only
128: 7 series FPGAs only
64 Integer
G50
C_NUM_MSI_REQ
C_M_AXI_DATA_
WIDTH
G51
G52 C_S_AXI_ID_WIDTH
G53
G54
G55
G56 C_INTERRUPT_PIN
G57
C_M_AXI_ADDR_
WIDTH
C_S_AXI_DATA_
WIDTH
C_S_AXI_ADDR_
WIDTH
C_M_AXI_PROTOCOL
C_S_AXI_PROTOCOL
C_MAX_LINK_
SPEED
NUM_WRITE_
OUTSTANDING
AXI Master Bus
Address width
AXI Slave Bus ID
width
AXI Slave Bus Data
width
AXI Slave Bus
Address width
Protocol definition
for M_AXI (Master
Bridge) port on AXI
Interconnect in the
Vivado IP integrator.
Protocol definition
for S_AXI (Slave
Bridge) port on AXI
Interconnect in the
Vivado IP integrator.
Maximum PCIe link
speed supported
Legacy INTX pin
support/select
AXI4 Interconnect Parameters
AXI Interconnect
Slave Port Write
Pipeline Depth
32 32 Integer
4 4 Integer
64: 7 series FPGAs only
128: 7 series FPGAs only
32 32 Integer
AXI4 AXI4 String
AXI4 AXI4 String
0: 2.5 GT/s - 7 series
1: 5.0 GT/s - 7 series
0: No INTX support
(setting for Root Port)
1: INTA selected (only
allowable when core in
Endpoint configuration)
1: Only one active AXI
AWADDR can be accepted
in the AXI slave bridge for
PCIe
2: Maximum of two active
AXI AWADDR values can
be stored in AXI slave
bridge for PCIe
64 Integer
0 Integer
0 Integer
2 Integer
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Chapter 2: Product Specification
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Table 2-4: Top -L e ve l Pa r am e te r s (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
1: Only one active AXI
ARADDR can be accepted
in AXI slave bridge PCIe.
2, 4, 8: Size of pipeline for
active AXI ARADDR values
to be stored in AXI slave
bridge PCIe
A value of 8 is not allowed
for 128-bit core (Gen2 7
series) configurations. The
maximum setting of this
parameter value is 4.
1, 2, 4: Number of actively
issued AXI AWADDR
values on the AXI
Interconnect to the target
slave device(s).
8 Integer
4 Integer
G58
G59
NUM_READ_
OUTSTANDING
NUM_WRITE_
OUTSTANDING
AXI Interconnect
Slave Port Read
Pipeline Depth
AXI4 Master Interconnect Parameters
AXI Interconnect
Master Bridge write
address issue depth
G60
Notes:
1. This is a 32-bit address.
2. The width of this should match the address size (C_AXIBAR_AS) for this BAR.
3. The range specified must comprise a complete, contiguous power of two range, such that the range = 2
significant bits of the Base Address are zero. The address value is a 32-bit AXI address.
4. The difference between C_AXIBAR_n and C_AXIBAR_HIGHADDR_n must be less than or equal to 0x7FFF_FFFF and greater
than or equal to 0x0000_1FFF.
5. It is recommended that you do not edit these default values on the AXI bridge for PCIe IP unless you need to reduce the
resource utilization. Doing so impacts the AXI bridge performance.
NUM_READ_
OUTSTANDING
AXI Interconnect
Master Bridge read
address issue depth
1, 2, 4: Number of actively
issued AXI ARADDR values
on the AXI Interconnect to
the target slave device(s).
4 Integer
n
and the n least
Parameter Dependencies
Tab le 2-5 lists the parameter dependencies.
Table 2-5: Parameter Dependencies
Generic Parameter Affects Depends Description
G1 C_FAMILY
G2 C_INCLUDE_RC G1 Meaningful only if G1 = Kintex-7.
G3 C_COMP_TIMEOUT
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PG055 June 4, 2014
Bridge Parameters
G2, G41,
G49, G55
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Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
G10,
G14,
G4 C_INCLUDE_BAROFFSET_REG
G5
G6 C_AXIBAR_NUM
G7 C_AXIBAR_0 G8 G6, G8
G8 C_AXIBAR_HIGHADDR_0 G7 G6, G7
G9 C_AXIBAR_AS_0 G6
G10 C_AXIBAR2PCIEBAR_0 G4, G6 Meaningful when G4 = 1.
C_SUPPORTS_NARROW_
BURST
G18,
G22,
G26, G30
G4, G7 -
G30
G6
If G4 = 0, then G10, G14, G18, G22,
G26 and G30 have no meaning. The
number of registers included is set
by G6.
If G6 = 1, then G7 - G10 are enabled.
If G6 = 2, then G7 - G14 are enabled.
If G6 = 3, then G7 - G18 are enabled.
If G6 = 4, then G7 - G22 are enabled.
If G6 = 5, then G7 - G26 are enabled.
If G6 = 6, then G7 - G30 are enabled.
G7 and G8 define the range in AXI
memory space that is responded to
by this device (AXIBAR)
G7 and G8 define the range in AXI
memory space that is responded to
by this device (AXIBAR)
G11 and G12 define the range in
G11 C_AXIBAR_1 G12 G12
G12 C_AXIBAR_HIGHADDR_1 G11 G6, G11
G13 C_AXIBAR_AS_1 G6
G14 C_AXIBAR2PCIEBAR_1 G4, G6 Meaningful when G4 = 1.
G15 C_AXIBAR_2 G16 G16
G16 C_AXIBAR_HIGHADDR_2 G15 G6, G15
G17 C_AXIBAR_AS_2 G6
G18 C_AXIBAR2PCIEBAR_2 G4, G6 Meaningful when G4 = 1.
G19 C_AXIBAR_3 G20 G20
G20 C_AXIBAR_HIGHADDR_3 G19 G6, G19
AXI-memory space that is responded
to by this device (AXIBAR)
G11 and G12 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G15 and G16 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G15 and G16 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G19 and G20 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G19 and G20 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
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Chapter 2: Product Specification
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Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
G21 C_AXIBAR_AS_3 G6
G22 C_AXIBAR2PCIEBAR_3 G4, G6 Meaningful when G4 = 1.
G23 and G24 define the range in
G23 C_AXIBAR_4 G24 G24
G24 C_AXIBAR_HIGHADDR_4 G23 G6, G23
G25 C_AXIBAR_AS_4 G6
G26 C_AXIBAR2PCIEBAR_4 G4, G6 Meaningful if G4 = 1.
G27 C_AXIBAR_5 G28 G28
G28 C_AXIBAR_HIGHADDR_5 G27 G6, G27
AXI-memory space that is responded
to by this device (AXIBAR)
G23 and G24 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G29 C_AXIBAR_AS_5 G6
G30 C_AXIBAR2PCIEBAR_5 G4, G6 Meaningful if G4 = 1.
If G31 = 1, then G32, G33 are
enabled.
G31 C_PCIEBAR_NUM G33-G38
G32 C_PCIEBAR_AS
G33 C_PCIEBAR_LEN_0 G34 G31
G34 C_PCIEBAR2AXIBAR_0 G31, G33
G35 C_PCIEBAR_LEN_1 G36 G31
G36 C_PCIEBAR2AXIBAR_1 G31, G35
G37 C_PCIEBAR_LEN_2 G38 G31
G38 C_PCIEBAR2AXIBAR_2 G31, G37
If G31 = 2, then G32 - G36 are
enabled.
If G31 = 3, then G32 - G38 are
enabled
Only the high-order bits above the
length defined by G33 are
meaningful.
Only the high-order bits above the
length defined by G35 are
meaningful.
Only the high-order bits above the
length defined by G37 are
meaningful.
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PG055 June 4, 2014
Chapter 2: Product Specification
Parameter Setting Result
G1 = Kintex-7 &
G50 = G53 = 64
G41 = 1, 2, or 4 (Gen1),
or G41 = 1 or 2 (Gen2)
G1 = Kintex-7 &
G50 = G53 = 128
G41 = 1, 2, 4, or 8
(Gen1) or 1, 2, or 4
(Gen2)
Send Feedback
Table 2-5: Parameter Dependencies (Cont’d)
Generic Parameter Affects Depends Description
Core for PCIe Configuration Parameters
G41 C_NO_OF_LANES
G42 C_DEVICE_ID
G43 C_VENDOR_ID
G44 C_CLASS_CODE
G45 C_REV_ID
G46 C_SUBSYSTEM_ID
G47 C_SUBSYSTEM_VENDOR_ID
G48
G49 C_REF_CLK_FREQ G1
C_PCIE_CAP_SLOT_
IMPLEMENTED
G1, G50,
G53
G2 If G2 = 0, G48 is not meaningful
Memory-Mapped AXI4 Bus Parameters
G50 C_M_AXI_DATA_WIDTH G53
G51 C_M_AXI_ADDR_WIDTH G54 G54 G51 must be equal to G54
G52 C_S_AXI_ID_WIDTH
G1, G41,
G53
G50 must be equal to G53
G53 C_S_AXI_DATA_WIDTH G50
G54 C_S_AXI_ADDR_WIDTH G51 G51 G54 must be equal to G51
G55 C_MAX_LINK_SPEED G1
G56 C_INTERRUPT_PIN
Tab le 2-6 summarizes the relationship between the IP design parameters, C_FAMILY and
C_PCIE_USE_MODE. The C_PCIE_USE_MODE is used to specify the 7 series (and derivative
FPGA technology) serial transceiver wrappers to use based on the silicon version. Initial
Engineering Silicon (IES) as well as General Engineering Silicon (GES) must be specified.
AXI Bridge for PCI Express v2.4 www.xilinx.com 25
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G1, G41,
G50
G53 must be equal to G50
Table 2-6: Silicon Version Specification
Send Feedback
C_FAMILY C_PCIE_USE_MODE
Chapter 2: Product Specification
Kintex-7
Virtex-7
Artix-7
Zynq Not applicable. (set internally = 3.0)
1.1 = for Kintex-7 325T IES (initial silicon)
3.0 = for GES (general silicon)
1.1 = for Virtex-7 485T IES (initial silicon)
3.0 = for GES and Production (general silicon and Production silicon)
1.0 = for IES (initial silicon) as well as GES and Production (General silicon and Production
silicon) to use latest serial transceiver wrappers (only allowable value)
Memory Map
The memory map shown in Ta ble 2-7 shows the address mapping for the AXI Bridge for PCI
Express core. These registers are described in more detail in the following section. All
registers are accessed through the AXI4-Lite Control Interface and are offset from
C_BASEADDR. During a reset, all registers return to default values.
Table 2-7: Register Memory Map
Accessibility Offset Contents Location
RO - EP, R/W - RC 0x000 - 0x124 PCIe Configuration Space Header
Part of integrated PCIe
configuration space.
RO 0x128
RO 0x12C VSEC Header
RO 0x130 Bridge Info
RO - EP, R/W - RC 0x134 Bridge Status and Control
R/W 0x138 Interrupt Decode
R/W 0x13C Interrupt Mask
RO - EP, R/W - RC 0x140 Bus Location
RO 0x144 Physical-Side Interface (PHY) Status/Control
RO - EP, R/W - RC 0x148 Root Port Status/Control
RO - EP, R/W - RC 0x14C Root Port MSI Base 1
RO - EP, R/W - RC 0x150 Root Port MSI Base 2
RO - EP, R/W - RC 0x154 Root Port Error FIFO Read
RO - EP, R/W - RC 0x158 Root Port Interrupt FIFO Read 1
RO - EP, R/W - RC 0x15C Root Port Interrupt FIFO Read 2
RO 0x160 - 0x1FF Reserved (zeros returned on read)
RO 0x200 VSEC Capability 2
Vendor-Specific Enhanced Capability (VSEC)
Capability
VSEC of integrated PCIe
configuration space.
AXI bridge defined
memory-mapped
register space.
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Chapter 2: Product Specification
Send Feedback
Table 2-7: Register Memory Map (Cont’d)
Accessibility Offset Contents Location
RO 0x204 VSEC Header 2
R/W 0x208 - 0x234
RO 0x238 - 0xFFF Reserved (zeros returned on read)
AXI Base Address Translation Configuration
Registers
PCIe Configuration Space Header
The PCIe Configuration Space Header is a memory aperture for accessing the core for PCIe
configuration space. For 7 series devices, this area is read-only when configured as an
Endpoint. Writes are permitted for some registers when a 7 series device is configured as a
Root Port. Special access modes can be enabled using the PHY Status/Control register. All
reserved or undefined memory-mapped addresses must return zero and writes have no
effect.
VSEC Capability Register (Offset 0x128)
The VSEC Capability register (described in Tabl e 2-8) allows the memory space of the core
to appear as though it is a part of the underlying core configuration space. The VSEC is
inserted immediately following the last enhanced capability structure in the underlying
block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19 of v2.0)
[Ref 5].
AXI bridge defined
memory-mapped
space.
Table 2-8: VSEC Capability Register
Bits Name
15:0 VSEC Capability ID RO 0x000B
19:16 Capability Version RO 0x1 Version of this capability structure. Hardcoded to 0x1.
31:20
Next Capability
Offset
Core
Access
RO 0x200 Offset to next capability. Hardcoded to 0x0200.
Reset Value Description
PCI-SIG® defined ID identifying this Enhanced
Capability as a Vendor-Specific capability. Hardcoded to
0x000B.
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VSEC Header Register (Offset 0x12C)
Send Feedback
The VSEC Header register (described in Tab le 2-9) provides a unique (within a given vendor)
identifier for the layout and contents of the VSEC structure, as well as its revision and
length.
Table 2-9: VSEC Header Register
Chapter 2: Product Specification
Bits Name
15:0 VSEC ID RO 0x0001
19:16 VSEC REV RO 0 Version of this capability structure. Hardcoded to 0h.
31:20 VSEC Length RO 0x038
Core
Access
Reset Value Description
ID value uniquely identifying the nature and format of
this VSEC structure.
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hardcoded to
0x038 (56 decimal).
Bridge Info Register (Offset 0x130)
The Bridge Info register (described in Ta bl e 2-10) provides general configuration
information about the AXI4-Stream Bridge. Information in this register is static and does
not change during operation.
Table 2-10: Bridge Info Register
Bits Name
0 Gen 2 C apa bl e RO 0
1 Root Port Present RO 0
Core
Access
Reset
Val u e
Description
If set, indicates the link is Gen2 capable. Underlying integrated
block and Link partner support PCIe Gen2 speed.
Indicates the underlying integrated block is a Root Port when
this bit is set.
If set, Root Port registers are present in this interface.
2
15:3 Reserved RO 0 Reserved
18:16 ECAM Size RO 0
31:19 Reser ved RO 0 Reserved
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Up Config
Capable
RO
Indicates the underlying integrated block is upconfig capable
when this bit is set.
Size of Enhanced Configuration Access Mechanism (ECAM) Bus
Number field, in number of bits. If ECAM window is present,
value is between 1 and 8. If not present, value is 0. Total address
bits dedicated to ECAM window is 20+(ECAM Size).
The size of the ECAM is determined by the parameter settings
of C_BASEADDR and C_HIGHADDR.
Bridge Status and Control Register (Offset 0x134)
Send Feedback
The Bridge Status and Control register (described in Tab le 2-11) provides information about
the current state of the AXI4-Stream Bridge. It also provides control over how reads and
writes to the Core Configuration Access aperture are handled.
Table 2-11: Bridge Status and Control Register
Chapter 2: Product Specification
Bits Name
0 ECAM Busy RO 0
7:1 Reserved RO 0 Reser ved
8
15:9 Reserved RO 0 Reser ved
16 RW1C as RW RW 0
17 RO as RW RW 0
31:18 Reser ved RO 0 Reserved
Global
Disable
Core
Access
RW 0
Reset
Value
Indicates an ECAM access is in progress (waiting for
completion).
When set, disables interrupt line from being asserted. Does not
prevent bits in Interrupt Decode register from being set.
When set, allows writing to core registers which are normally
RW1C.
When set, allows writing to certain registers which are normally
RO.
(Only supported for Kintex-7 FPGA cores.)
Interrupt Decode Register (Offset 0x138)
The Interrupt Decode register (described in Tab le 2-12) provides a single location where the
host processor interrupt service routine can determine what is causing the interrupt to be
asserted and how to clear the interrupt. Writing a 1'b1 to any bit of the Interrupt Decode
register clears that bit except for the Correctable, Non-Fatal, and Fatal bits.
Description
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Follow this sequence to clear the Correctable, Non-Fatal, and Fatal bits:
1. Clear the Root Port Error FIFO (0x154) by performing first a read, followed by write-back
of the same register.
2. Write to the Interrupt Decode Register (0x138) with ‘1’ to the appropriate error bit to
clear it.
IMPORTANT: An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert
unless the corresponding bit in the Interrupt Mask register is also set.
Table 2-12: Interrupt Decode Register
Send Feedback
Chapter 2: Product Specification
Bits Name
0 Link Down RW1C 0
1 ECRC Error RW1C 0
2 Streaming Error RW1C 0
3 Hot Reset RW1C 0 Indicates a Hot Reset was detected.
4 Reser ved RO 0 Reserved
7:5
8 Cfg Timeout RW1C 0
9 Correctable RW1C 0
10 Non-Fatal RW1C 0
Cfg Completion
Status
Core
Access
RW1C 0 Indicates config completion status.
Reset
Value
Description
Indicates that Link-Up on the PCI Express link was lost. Not
asserted unless link-up had previously been seen.
Indicates Received packet failed ECRC check.
(Only applicable to Kintex-7 FPGA cores.)
Indicates a gap was encountered in a streamed packet on the TX
interface (RW, RR, or CC).
Indicates timeout on an ECAM access.
(Only applicable to Root Port cores.)
Indicates a correctable error message was received.
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates a non-fatal error message was received.
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates a fatal error message was received.
11 Fatal RW1C 0
15:12 Reser ved RO 0 Reser ved
16
17
19:18 Reser ved RO 0 Reser ved
20
21
22
23 Slave Error Poison RW1C 0 Indicates the EP bit was set in a completion TLP.
INTx Interrupt
Received
MSI Interrupt
Received
Slave
Unsupported
Request
Slave Unexpected
Completion
Slave Completion
Timeout
RW1C 0
RW1C 0
RW1C 0
RW1C 0
RW1C 0
Requester ID of error message should be read from the Root Port
FIFO.
(Only applicable to Root Port cores.)
Indicates an INTx interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
Indicates an MSI(x) interrupt was received.
Interrupt details should be read from the Root Port FIFO.
(Only applicable to Root Port cores.)
Indicates that a completion TLP was received with a status of
0b001 - Unsupported Request.
Indicates that a completion TLP was received that was
unexpected.
Indicates that the expected completion TLP(s) for a read request
for PCIe was not returned within the time period selected by the
C_COMP_TIMEOUT parameter.
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Table 2-12: Interrupt Decode Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name
24
25 Slave Illegal Burst RW1C 0
26 Master DECERR RW1C 0 Indicates a Decoder Error (DECERR) response was received.
27 Master SLVERR RW1C 0 Indicates a Slave Error (SLVERR) response was received.
28
31:29 Reser ved RO 0 Reser ved
Slave Completer
Abort
Master Error
Poison
Core
Access
RW1C 0
RW1C 0 Indicates an EP bit was set in a MemWR TLP for PCIe.
Reset
Value
Description
Indicates that a completion TLP was received with a status of
0b100 - Completer Abort.
Indicates that a burst type other than INCR was requested by the
AXI master.
Interrupt Mask Register (Offset 0x13C)
The Interrupt Mask register controls whether each individual interrupt source can cause the
interrupt line to be asserted. A one in any location allows the interrupt source to assert the
interrupt line. The Interrupt Mask register initializes to all zeros. Therefore, by default no
interrupt is generated for any event.
and values.
Tab le 2-13 describes the Interrupt Mask register bits
Table 2-13: Interrupt Mask Register
Bits Name
0 Link Down RW 0 Enables interrupts for Link Down events when bit is set.
1 ECRC Error RW 0
2 Streaming Error RW 0 Enables interrupts for Streaming Error events when bit is set.
3 Hot Reset RW 0
4 Reser ved RO 0 Reser ved
7:5
8 Cfg Timeout RO 0
9 Correctable RO 0
10 Non-Fatal RO 0
11 Fatal RO 0
Cfg Completion
Status
Core
Access
RW 0
Reset
Value
Description
Enables interrupts for ECRC Error events when bit is set.
(Only writable for EP configurations, otherwise = ‘0’)
Enables interrupts for Hot Reset events when bit is set.
(Only writable for EP configurations, otherwise = ‘0’)
Enables interrupts for config completion status.
(Only writable for Root Port Configurations, otherwise = ‘0’)
Enables interrupts for Config (Cfg) Timeout events when bit is
set.
(Only writable for Root Port Configurations, otherwise = ‘0’)
Enables interrupts for Correctable Error events when bit is set.
(Only writable for Root Port Configurations, otherwise = ‘0’)
Enables interrupts for Non-Fatal Error events when bit is set.
(Only writable for Root Port Configurations, otherwise = ‘0’)
Enables interrupts for Fatal Error events when bit is set.
(Only writable for Root Port Configurations, otherwise = ‘0’)
15:12 Reser ved RO 0 Reserved
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Table 2-13: Interrupt Mask Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name
16
17
19:18 Reser ved RO 0 Reserved
20
21
22
23 Slave Error Poison RW 0 Enables the Slave Error Poison interrupt when bit is set.
24
25 Slave Illegal Burst RW 0 Enables the Slave Illegal Burst interrupt when bit is set.
26 Master DECERR RW 0 Enables the Master DECERR interrupt when bit is set.
27 Master SLVERR RW 0 Enables the Master SLVERR interrupt when bit is set.
INTx Interrupt
Received
MSI Interrupt
Received
Slave
Unsupported
Request
Slave Unexpected
Completion
Slave Completion
Timeout
Slave Completer
Abort
Core
Access
RO 0
RO 0
RW 0
RW 0
RW 0 Enables the Slave Completion Timeout interrupt when bit is set.
RW 0 Enables the Slave Completer Abort interrupt when bit is set.
Reset
Value
Description
Enables interrupts for INTx Interrupt events when bit is set.
(Only writable for Root Port Configurations, otherwise =0)
Enables interrupts for MSI Interrupt events when bit is set.
(Only writable for Root Port Configurations, otherwise =0)
Enables the Slave Unsupported Request interrupt when bit is
set.
Enables the Slave Unexpected Completion interrupt when bit is
set.
28
31:29 Reser ved RO 0 Reserved
Master Error
Poison
RW 0 Enables the Master Error Poison interrupt when bit is set.
Bus Location Register (Offset 0x140)
The Bus Location register reports the Bus, Device, and Function number, and the Port
number for the PCIe port (
Table 2-14: Bus Location Register
Bits Name
2:0 Function Number RO 0 Function number of the port for PCIe. Hard-wired to 0.
7:3 Device Number RO 0
15:8 Bus Number RO 0
23:16 Port Number RW 0 Sets the Port number field of the Link Capabilities register.
31:24 Reser ved RO 0 Reserved
Core
Access
Tab le 2-14).
Reset
Value
Device number of port for PCIe. For Endpoint, this register is RO
and is set by the Root Port.
Bus number of port for PCIe. For Endpoint, this register is RO and
is set by the external Root Port.
Description
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PHY Status/Control Register (Offset 0x144)
Send Feedback
The PHY Status/Control register (described in Tab le 2-15) provides the status of the current
PHY state, as well as control of speed and rate switching for Gen2-capable cores.
Table 2-15: PHY Status/Control Register
Chapter 2: Product Specification
Bits Name
0 Link Rate RO 0 Reports the current link rate. 0b = 2.5 GT/s, 1b = 5.0 GT/s.
2:1 Link Width RO 0
8:3 LTSSM State RO 0
10:9 Lane Reversal RO 0
11 Link Up RO 0
15:12 Reser ved RO 0 Reser ved
17:16
Directed Link
Width
Core
Access
RW 0
Reset
Valu e
Description
Reports the current link width. 00b = x1, 01b = x2, 10b = x4, 11b
= x8.
Reports the current Link Training and Status State Machine
(LTSSM) state. Encoding is specific to the underlying integrated
block.
Reports the current lane reversal mode.
•00b: No reversal
• 01b: Lanes 1:0 reversed
• 10b: Lanes 3:0 reversed
• 11b: Lanes 7:0 reversed
Reports the current PHY Link-up state.
•1b: Link up
•0b: Link down
Link up indicates the core has achieved link up status, meaning
the LTSSM is in the L0 state and the core can send/receive data
packets.
Specifies completer link width for a directed link change
operation. Only acted on when Directed Link Change specifies a
width change.
•00b: x1
•01b: x2
•10b: x4
•11b: x8
18
19
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Directed Link
Speed
Directed Link
Autonomous
RW 0
RW 0
Specifies completer link speed for a directed link change
operation. Only acted on when Directed Link Change specifies a
speed change.
• 0b: 2.5 GT/s
• 1b: 5.0 GT/s
Specifies link reliability or autonomous for directed link change
operation.
• 0b: Link reliability
• 1b: Autonomous
Table 2-15: PHY Status/Control Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name
21:20
31:22 Reser ved RO 0 Reser ved
Directed Link
Change
Core
Access
RW 0
Reset
Valu e
Directs LTSSM to initiate a link width and/or speed change.
•00b: No change
• 01b: Force link width
• 10b: Force link speed
• 11b: Force link width and speed
Root Port Status/Control Register (Offset 0x148)
The Root Port Status/Control register provides access to Root Port specific status and
control. This register is only implemented for Root Port cores. For non-Root Port cores,
reads return 0 and writes are ignored (described in
Table 2-16: Root Port Status/Control Register
Bits Name
0 Bridge Enable RW 0
Core
Access
Reset
Valu e
When set, allows the reads and writes to the AXIBARs to be
presented on the PCIe bus. Root Port software needs to write 1
to this bit when enumeration is done. AXI Enhanced PCIe Bridge
clears this location when link up to link down transition occurs.
Default is set to 0.
Description
Tab le 2-16).
Description
15:1 Reserved RO 0 Reserved.
16
17
18
19
27:20
31:28 Reser ved RO 0 Reser ved.
Error FIFO Not
Empty
Error FIFO
Overflow
Interrupt FIFO Not
Empty
Interrupt FIFO
Overflow
Completion
Timeout
RO 0 Indicates that the Root Port Error FIFO has data to read.
RW1C 0
RO 0 Indicates that the Root Port Interrupt FIFO has data to read.
RW1C 0
RW 0 Sets the timeout counter size for Completion Timeouts.
Indicates that the Root Port Error FIFO overflowed and an error
message was dropped. Writing a 1 clears the overflow status.
Indicates that the Root Port Interrupt FIFO overflowed and an
interrupt message was dropped. Writing a 1 clears the overflow
status
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Root Port MSI Base Register 1 (Offset 0x14C)
Send Feedback
The Root Port MSI Base register contains the upper 32-bits of the 64-bit MSI address
(described in
For EP configurations, read returns zero.
Table 2-17: Root Port MSI Base Register 1
Tab le 2-17).
Chapter 2: Product Specification
Bits Name
31:0 MSI Base RW 0
Core
Access
Reset
Valu e
Description
4Kb-aligned address for MSI interrupts. In case of 32-bit MSI,
it returns 0 but captures the upper 32-bits of the MSI address in
case of 64-bit MSI.
Root Port MSI Base Register 2 (Offset 0x150)
The Root Port MSI Base register 2 (described in Ta bl e 2-18) sets the address window in Root
Port cores used for MSI interrupts. MemWr TLPs to addresses in this range are interpreted
as MSI interrupts. MSI TLPS are interpreted based on the address programmed in this
register. The window is always 4 Kb, beginning at the address indicated in this register. For
EP configurations, a read returns zero. However, the AXI Bridge for PCI Express core does
not support MSI-X and multiple vector address, only single MSI is supported.
Table 2-18: Root Port MSI Base Register 2
Bits Name
11:0 Reserved RO 0 Reserved
31:12 MSI Base RW 0 4 Kb-aligned address for MSI interrupts.
Core
Access
Reset
Valu e
Description
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Root Port Error FIFO Read Register (Offset 0x154)
Reads from this location return queued error (Correctable/Non-fatal/Fatal) messages. Data
from each read follows the format shown in
zero.
Reads are non-destructive. Removing the message from the FIFO requires a write. The write
value is ignored.
Tab le 2-19. For EP configurations, read returns
Table 2-19: Root Port Error FIFO Read Register
Send Feedback
Chapter 2: Product Specification
Bits Name
15:0 Requester ID RWC 0 Requester ID belonging to the requester of the error message.
17:16 Error Type RWC 0
18 Error Valid RWC 0
31:19 Reser ved RO 0 Reser ved
Core
Access
Reset
Valu e
Description
Indicates the type of the error.
00b: Correctable
01b: Non-Fatal
10b: Fatal
11b: Reserved
Indicates whether read succeeded.
1b: Success
0b: No message to read
Root Port Interrupt FIFO Read Register 1 (Offset 0x158)
Reads from this location return queued interrup t messages . Data f rom ea ch read follows th e
format shown in
Root Port Interrupt FIFO Read 2 register. The interrupt-handling flow should be to read this
register first, immediately followed by the Root Port Interrupt FIFO Read 2 register. For
non-Root Port cores, reads return zero.
Tab le 2-20. For MSI interrupts, the message payload is presented in the
Note: Reads are non-destructive. Removing the message from the FIFO requires a write to either
this register or the Root Port Interrupt FIFO Read 2 register. The write value is ignored.
Table 2-20: Root Port Interrupt FIFO Read Register 1
Bits Name
15:0 Requester ID RWC 0 Requester ID belonging to the requester of the error message.
26:16 MSI Address RWC 0
28:27 Interrupt Line RWC 0
29 Interrupt Assert RWC 0
30 MSI Interrupt RWC 0
31 Interrupt Valid RWC 0
Core
Access
Reset
Valu e
Description
For MSI interrupts, contains address bits 12:2 from the TLP
address field.
Indicates interrupt line used.
00b: INTA
01b: INTB
10b: INTC
11b: INTD
For MSI, this field is set to 00b and should be ignored.
Indicates assert or deassert for INTx.
1b: Assert
0b: Deassert
For MSI, this field is set to 0b and should be ignored.
Indicates whether interrupt is MSI or INTx.
1b = MSI, 0b = INTx.
Indicates whether read succeeded.
1b: Success
0b: No interrupt to read
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Root Port Interrupt FIFO Read Register 2 (Offset 0x15C)
Send Feedback
Reads from this location return queued interrup t messages . Data f rom ea ch read follows th e
format shown in
register, while the header information is presented in the Root Port Interrupt FIFO Read 1
register. The interrupt-handling flow should be to read the Root Port Interrupt FIFO Read 1
register first, immediately followed by this register. For non-Root Port cores, reads return 0.
For INTx interrupts, reads return zero.
Note: Reads are non-destructive. Removing the message from the FIFO requires a write to either
this register or the Root Port Interrupt FIFO Read 1 register (write value is ignored).
Table 2-21: Root Port Interrupt FIFO Read Register 2
Tab le 2-21. For MSI interrupts, the message payload is presented in this
Chapter 2: Product Specification
Bits Name
15:0 Message Data RWC 0 Payload for MSI messages.
31:16 Reser ved RO 0 Reser ved
Core
Access
Reset
Valu e
Description
VSEC Capability Register 2 (Offset 0x200)
The VSEC capability register (described in Tab le 2-22) allows the memory space for the core
to appea r as thoug h it is a pa rt of the underlying integrated block PCIe configuration space.
The VSEC is inserted immediately following the last enhanced capability structure in the
underlying block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19
of v2.0)
This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 2-22: VSEC Capability Register 2
Bits Name
15:0 VSEC Capability ID RO 0x000B
19:16 Capability Version RO 0x1 Version of this capability structure. Hardcoded to 0x1.
[Ref 5].
Core
Access
Reset
Value
Description
PCI-SIG defined ID identifying this Enhanced Capability as a
Vendor-Specific capability. Hardcoded to 0x000B.
31:20
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Next Capability
Offset
RO 0x000 Offset to next capability.
VSEC Header Register 2 (Offset 0x204)
The VSEC Header Register 2 (described in Tab le 2-23) provides a unique (within a given
vendor) identifier for the layout and contents of the VSEC structure, as well as its revision
and length.
This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 2-23: VSEC Header Register 2
Send Feedback
Chapter 2: Product Specification
Bits Name
15:0 VSEC ID RO 0x0002
19:16 VSEC REV RO 0x0 Version of this capability structure. Hardcoded to 0x0.
31:20 VSEC Length RO 0x038
Core
Access
Reset Value Description
ID value uniquely identifying the nature and format of
this VSEC structure.
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hardcoded to
0x038 (56 decimal).
AXI Base Address Translation Configuration Registers (Offset 0x208 - 0x234)
The AXI Base Address Translation Configuration Registers and their offsets are shown in
Tab le 2-24 and the register bits are described in Tab le 2-25. This set of registers can be used
in two configurations based on the top-level parameter C_AXIBAR_AS_n. When the BAR is
set to a 32-bit address space, then the translation vector should be placed into the
AXIBAR2PCIEBAR_nL register where n is the BAR number. When the BAR is set to a 64-bit
address space, then the most significant 32 bits are written into the AXIBAR2PCIEBAR_nU
and the least significant 32 bits are written into AXIBAR2PCIEBAR_nL. These registers are
only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 2-24: AXI Base Address Translation Configuration Registers
Offset Bits Register Mnemonic
0x208 31-0
0x20C 31-0
0x210 31-0
0x214 31-0
0x218 31-0
0x21C 31-0
0x220 31-0
0x224 31-0
0x228 31-0
0x22C 31-0
0x230 31-0
0x234 31-0
AXIBAR2PCIEBAR_0U
AXIBAR2PCIEBAR_0L
AXIBAR2PCIEBAR_1U
AXIBAR2PCIEBAR_1L
AXIBAR2PCIEBAR_2U
AXIBAR2PCIEBAR_2L
AXIBAR2PCIEBAR_3U
AXIBAR2PCIEBAR_3L
AXIBAR2PCIEBAR_4U
AXIBAR2PCIEBAR_4L
AXIBAR2PCIEBAR_5U
AXIBAR2PCIEBAR_5L
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Table 2-25: AXI Base Address Translation Configuration Register Bit Definitions
Bits Name
31-0
31-0
31-0
31-0
31-0
Lower
Address
Upper
Address
Lower
Address
Upper
Address
Lower
Address
Core
Access
R/W C_AXIBAR2PCIEBAR_0(31 to 0)
if (C_AXIBAR2PCIEBAR_0 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_0(63 to
R/W
R/W C_AXIBAR2PCIEBAR_1(31 to 0)
R/W
R/W C_AXIBAR2PCIEBAR_2(31 to 0)
32)
if (C_AXIBAR2PCIEBAR_0 = 32 bits), then
reset value = 0x00000000
if (C_AXIBAR2PCIEBAR_1 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_1(63 to
32)
if (C_AXIBAR2PCIEBAR_1 = 32 bits), then
reset value = 0x00000000
Reset Value Description
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
To create the address for PCIe– this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
31-0
31-0
31-0
31-0
Upper
Address
Lower
Address
Upper
Address
Lower
Address
if (C_AXIBAR2PCIEBAR_2 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_2(63 to
R/W
R/W C_AXIBAR2PCIEBAR_3(31 to 0)
R/W
R/W C_AXIBAR2PCIEBAR_4(31 to 0)
32)
if (C_AXIBAR2PCIEBAR_2 = 32 bits), then
reset value = 0x00000000
if (C_AXIBAR2PCIEBAR_3 = 64 bits) then
reset value = C_AXIBAR2PCIEBAR_3(63 to
32)
if (C_AXIBAR2PCIEBAR_3 = 32 bits) then
reset value = 0x00000000
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
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Table 2-25: AXI Base Address Translation Configuration Register Bit Definitions (Cont’d)
Bits Name
31-0
31-0
31-0
Upper
Address
Lower
Address
Upper
Address
Enhanced Configuration Access
When the AXI Bridge for PCI Express core is configured as a Root Port, configuration traffic
is generated by using the PCI Express Enhanced Configuration Access Mechanism (ECAM).
ECAM functionality is available only when the core is configured as a Root Port. Reads and
writes to a certain memory aperture are translated to configuration reads and writes, as
specified in the PCI Express Base Specification (v1.1 and v2.1), §7.2.2
Core
Access
if (C_AXIBAR2PCIEBAR_4 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_4(63 to
R/W
R/W C_AXIBAR2PCIEBAR_5(31 to 0)
R/W
32)
if (C_AXIBAR2PCIEBAR_4 = 32 bits), then
reset value = 0x00000000
if (C_AXIBAR2PCIEBAR_5 = 64 bits), then
reset value = C_AXIBAR2PCIEBAR_5(63 to
32)
if (C_AXIBAR2PCIEBAR_5 = 32 bits), then
reset value = 0x00000000
Reset Value Description
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the least significant
32 bits of the AXI address.
To create the address for PCIe–this is the
value substituted for the most significant
32 bits of the AXI address.
[Ref 5].
Depending on the core configuration, the ECAM memory aperture is 221–228 (byte)
addresses. The address breakdown is defined in
memory map base address and extends to 2
Tab le 2-26. The ECAM window begins at
(20+ECAM_SIZE)
- 1. ECAM_SIZE is calculated from
the C_BASEADDR and C_HIGHADDR parameters. The number N of low-order bits of the two
parameters that do not match, specifies the 2**n byte address range of the ECAM space. If
C_INCLUDE_RC = 0, then ECAM_SIZE = 0.
When an ECAM access is attempted to the primary bus number, which defaults as bus 0
from reset, then access to the type 1 PCI™ Configuration Header of the integrated block in
the Enhanced Interface for PCIe is performed. When an ECAM access is attempted to the
secondary bus number, then type 0 configuration transactions are generated. When an
ECAM access is attempted to a bus number that is in the range defined by the secondary
bus number and subordinate bus number (not including the secondary bus number), then
type 1 configuration transactions are generated. The primary, secondary, and subordinate
bus numbers are written by Root Port software to the type 1 PCI Configuration Header of
the Enhanced Interface for PCIe in the beginning of the enumeration procedure.
When an ECAM access is attempted to a bus number that is out of the bus_number and
subordinate bus number, the bridge does not generate a configuration request and signal
SLVERR response on the AXI4-Lite bus. When the AXI Bridge for PCIe is configured for EP
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(C_INCLUDE_RC = 0), the underlying Integrated Block configuration space and the core
memory map are available at the beginning of the memory space. The memory space looks
like a simple PCI Express configuration space. When the AXI Bridge for PCIe is configured
for RC (C_INCLUDE_RC = 1), the same is true, but it also looks like an ECAM access to
primary bus, Device 0, Function 0.
When the AXI Bridge for PCI Express core is configured as a Root Port, the reads and writes
of the local ECAM are Bus 0. Because the FPGA only has a single Integrated Block for PCIe
core, all local ECAM operations to Bus 0 return the ECAM data for Device 0, Function 0.
Configuration write accesses across the PCI Express bus are non-posted writes and block
the AXI4-Lite interface while they are in progress. Because of this, system software is not
able to service an interrupt if one were to occur. However, interrupts due to abnormal
terminations of configuration transactions can generate interrupts. ECAM read transactions
block subsequent Requester read TLPs until the configuration read completions packet is
returned to allow unique identification of the completion packet.
Table 2-26: ECAM Addressing
Bits Name Description
1:0 Byte Address
7:2 Register Number Register within the conf iguration space to access.
11:8
14:12 Function Number Function Number to completer.
19:15 Device Number Device Number to completer.
(20+n-1):20 Bus Number
Extended Register
Number
Ignored for this implementation. The S_AXI_CTL_WSTRB[3:0] signals
define byte enables for ECAM accesses.
Along with Register Number, allows access to PCI Express Extended
Configuration Space.
Bus Number, 1 <= n <= 8. n is the number of bits available for Bus
Number as derived from core parameters C_INCLUDE_RC,
C_BASEADDR, and C_HIGHADDR.
Unsupported Memory Space
Advanced Error Reporting (AER) is not supported in the AXI Bridge for PCI Express core. The
AER register space is not accessible in the AXI Bridge for PCI Express memory mapped
space.
AXI Bridge for PCI Express v2.4 www.xilinx.com 41
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Designing with the Core
!8)
0#)E
)0
AXI?ACLK
AXI?CTL?ACLK
AXI?ACLK?OUT
AXI?CTL?ACLK?OUT
MMCM?LOCK
REFCLK
0#)E2EFERENCE#LOCK
Send Feedback
This chapter includes guidelines and additional information to make designing with the
core easier.
General Design Guidelines
The Xilinx® Vivado® Design Suite has been optimized to provide a starting point for
designing with the AXI Bridge for PCI Express® core.
Clocking
Chapter 3
Figure 3-1 shows the clocking diagram for the core. The main memory mapped AXI4 bus
clock axi_aclk is driven by axi_aclk_out.
X-Ref Target - Figure 3-1
Figure 3-1: Clocking Diagram
IMPORTANT: axi_aclk_out and axi_ctl_aclk_out are connected to axi_aclk and
axi_ctl_aclk, respectively, and they do not need to be connected in the design.
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Chapter 3: Designing with the Core
!8)
0#)E
)0
MMCM?LOCK
0%234N
PROC?SYS?RESET
)0
$#-?,/#+%$
!UX?2ESET?)N
)NTERCONNECT?ARESETN
!8)!2%3%4N
AXI?ARESETN
8
Send Feedback
The refclk input must be provided at the frequency selected by the value of
c_ref_clk_freq. This clock is used to generate the two output clocks and is also the
clock used to drive the AXI4 bus.
The AXI4-Lite interconnect clock axi_ctl_aclk is driven by axi_ctl_aclk_out. The
axi_ctl_aclk_out clock is rising edge aligned and an integer division of the
axi_aclk_out clock.
The output clock frequency is 62.5 Mhz for x1 gen1 64-bit AXI interface, and 125 Mhz for
the remaining configurations.
Resets
The AXI Bridge for PCI Express core is designed to be used with the Processing System Reset
module for generation of the axi_areset input. When using the Vivado IP integrator to
build a system, it is best to connect the perstn pin of the host connector for PCIe to the
Aux_Reset_In port of the Processing System Reset module. The bridge does not use
perstn directly. Also, the mmcm_lock output must be connected to the dcm_locked
input of the Processing System Reset module to make sure that axi_aresetn is held
active for 16 clocks after mmcm_lock becomes active. See
Figure 3-2.
Note: Be sure to set the correct polarity on the aux_reset_in signal of the proc_sys_reset ip
block. when
PARAMETER C_AUX_RESET_HIGH = 0
X-Ref Target - Figure 3-2
PERSTN is active-Low, set the parameter as follows:
Figure 3-2: System Reset Connection
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Chapter 3: Designing with the Core
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Shared Logic
This new feature allows you to share common blocks across multiple instantiations. It
minimizes the amount of required HDL modifications. You can use your own system-level
clocking or reset circuit
(for example, swapping a BUFG for a BUFH)
'common/shared logic' from one core among all instantiated cores. This is
for Endpoint mode, and not Root Port mode
In the Vivado Design Suite, the shared logic options are available in the Shared Logic page
when customizing the core.
There are four types of logic sharing:
• Shared Clocking
• Shared GT_COMMON
• Shared GT_COMMON and Clocking
. You can modify some of these blocks due to system requirements
. You can instantiate multiple cores and share
only applicable
.
• Internal Shared GT_COMMON and Clocking
Shared Clocking
To use the share clocking feature, select Include Shared Logic (Clocking) in example
design option in the in the Shared Logic tab (
When this feature is selected, the mixed-mode clock manager (MMCM) instance is removed
from the pipe wrappers and is moved into the support wrapper of the example design. It
also brings out additional ports to the top level to enable sharing of the clocks.
You also have the option to modify and use the unused outputs of the MMCM.
Figure 3-3).
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X-Ref Target - Figure 3-3
Send Feedback
Chapter 3: Designing with the Core
Figure 3-3: Shared Clocking
The MMCM generates the following clocks for PCIe solution wrapper:
• clk_125mhz - 125 MHz clock.
• clk_250mhz - 250 MHz clock.
• userclk - 62.5 MHz / 125 MHz / 250 MHz clock, depending on selected PCIe core lane
width, link speed, and AXI interface width.
• userclk2 – 250 MHz / 500 MHz clock, depending on selected PCIe core link speed.
• oobclk – 50 MHz clock.
The other cores/logic present in the user design can use any of the MMCM outputs listed
above.
The MMCM instantiated in the PCIe example design has two unconnected outputs:
clkout5, and clkout6. You can use those outputs to generate other desired clock
frequencies by selecting the appropriate CLKOUT5_DIVIDE and CLKOUT6_DIVIDE
parameters for MMCM.
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TIP: Sharing the MMCM between PCIe and other cores in your design saves FPGA resources and eases
output clock path routing.
Limitations
• Reference clock input to MMCM is restricted to 100 MHz in most use cases.
There is an option for selecting a reference clock of 125MHz or 250MHz, which is
°
not a common use case.
• The MMCM reset is tied to a static value in the top module. The MMCM can be reset as
required by the system design. Note that MMCM reset can be asserted only after
reference clock is recovered and is stable. Also, MMCM reset is indirectly tied to the
PCIe core reset and asserting MMCM reset will reset the PCIe core.
•The userclk1 and userclk2 outputs are selected based on the PCIe Lane Width,
Link Speed, and AXI width selections (for details, see Customizing the Core in
Chapter 4). Sharing cores must comply with these requirements.
Shared GT_COMMON
A quad phase-locked loop (QPLL) in GT_COMMON can serve a quad of GT_CHANNEL
instances. If the PCIe core is configured as X1 or X2 and is using a QPLL, the remaining
GT_CHANNEL instances can be used by other cores by sharing the same QPLL and
GT_COMMON.
To share GT_COMMON instances, select Include Shared Logic (Transceiver
GT_COMMON) in example design option in the Shared Logic tab(
When this feature is selected, the GT_COMMON instance is removed from the pipe
wrappers and is moved into the support wrapper of the example design. It also brings out
additional ports to the top level to enable sharing of the GT_COMMON.
Shared logic feature for GT_COMMON helps save FPGA resources and also eases dedicated
clock routing within the single GT Quad.
Shared GT_COMMON Use Cases with GTX and GTP
Table 3-1: Shared GT_COMMON Use Cases
GT – PCIe max Link
Speed
Device – PCIe Max Link Speed Shared GT_COMMON
Figure 3-4).
AXI Bridge for PCI Express v2.4 www.xilinx.com 46
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GTX Kintex7, Virtex7 (485T) – PCIe Gen2 PCIe Pipe Wrappers instantiate
GT_COMMON . Shared IP uses QPLL because
PCIe uses CPLL inside GT_CHANNEL
GTP Artix7 – PCIe Gen2 GTP_COMMON has 2 QPLLs. PCIe Pipe
Wrappers use only one QPLL. The remaining
one can be used by shared IP core.
Chapter 3: Designing with the Core
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Limitations
• The reset logic in the pipe wrapper resets the QPLL when the PCIe Block performs a
rate change. When sharing is enabled, the core/logic which is sharing the QPLL must be
able to handle and recover from this reset.
• The settings of the GT_COMMON should not be changed as they are optimized for the
PCIe core.
X-Ref Target - Figure 3-4
AXI Bridge for PCI Express v2.4 www.xilinx.com 47
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Figure 3-4: Shared GT_COMMON
Shared GT_COMMON and Clocking
You can share both GT_COMMON and Clocking instances when you select Include Shared
Logic (Clocking) in example design and Include Shared Logic (Transceiver
GT_COMMON) in example design in the Shared Logic page (see
Figure 3-5).
X-Ref Target - Figure 3-5
Send Feedback
Chapter 3: Designing with the Core
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Figure 3-5: Shared GT_COMMON and Clocking
Internal Shared GT_COMMON and Clocking
This feature allows sharing of GT_COMMON and Clocks while these modules are still
internal to the core (not brought up to the support wrapper). It can be enabled when you
select Include Shared Logic in Core in the Shared Logic page (see
Figure 3-6).
X-Ref Target - Figure 3-6
Send Feedback
Chapter 3: Designing with the Core
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Figure 3-6: Internal Shared Logic
Clocking Interface
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Tab le 3-2 defines the clocking interface signals.
Table 3-2: Clocking Interface Signals
Name Direction Description
Chapter 3: Designing with the Core
pipe_pclk_in Input
pipe_rxusrclk_in Input Provides a clock for the internal RX PCS datapath.
pipe_rxoutclk_in Input Recommended clock output to the FPGA logic.
pipe_dclk_in Input Dynamic reconfiguration clock.
pipe_userclk1_in Input Optional user clock.
pipe_userclk2_in Input Optional user clock.
pipe_mmcm_lock_in Input Indicates if the MMCM is locked onto the source CLK.
pipe_txoutclk_out Output Recommended clock output to the FPGA logic.
pipe_rxoutclk_out Output Recommended clock output to the FPGA logic.
pipe_pclk_sel_out Output Parallel clock select.
pipe_gen3_out Output Indicates the PCI Express operating speed.
pipe_mmcm_rst_n
Parallel clock used to synchronize data transfers across the
parallel interface of the GTX transceiver.
MMCM reset port. This port could be used by the upper layer to
reset MMCM if error recovery is required. If the system detects
the deassertion of MMCM lock, Xilinx recommends that you
reset the MMCM. The recommended approach is to reset the
MMCM after the MMCM input clock recovers (if MMCM reset
occurs before the input reference clock recovers, the MMCM
might never relock). After MMCM is reset, wait for MMCM to
lock and then reset the PIPE Wrapper as normally done.
Currently this port is tied High.
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The Clocking architecture is described in detail in the Use Model chapter of the 7 Series
FPGAs GTX/GTH Transceivers User Guide (UG476)
[Ref 3].
AXI Transactions for PCIe
Tab le 3-3 and Tabl e 3-4 are the translation tables for AXI4-Stream and memory-mapped
transactions.
Table 3-3: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs
AXI4 Memory-Mapped Transaction AXI4-Stream PCIe TLPs
INCR Burst Read of 32-bit address AXIBAR MemRd 32 (3DW)
INCR Burst Write to 32-bit address AXIBAR MemWr 32 (3DW)
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Table 3-3: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs (Cont’d)
AXI4 Memory-Mapped Transaction AXI4-Stream PCIe TLPs
INCR Burst Read of 32-bit address AXIBAR MemRd 64 (4DW)
INCR Burst Write to 32-bit address AXIBAR MemWr 64 (4DW)
Table 3-4: AXI4-Stream PCIe TLPs to AXI4 Memory Mapped Transactions
AXI4-Stream PCIe TLPs AXI4 Memory-Mapped Transaction
MemRd 32 (3DW) of PCIEBAR INCR Burst Read with 32-bit address
MemWr 32 (3DW) to PCIEBAR INCR Burst Write with 32-bit address
MemRd 64 (4DW) of PCIEBAR INCR Burst Read with 32-bit address
MemWr 64 (4DW) to PCIEBAR INCR Burst Write with 32-bit address
Transaction Ordering for PCIe
The AXI Bridge for PCI Express core conforms to strict PCIe transaction ordering rules. See
the PCIe v2.1 Specification
implemented in the AXI Bridge for PCI Express core to enforce the PCIe transaction ordering
rules on the highly-parallel AXI bus of the bridge. The rules are enforced without regard to
the Relaxed Ordering attribute bit within the TLP header:
•The bresp to the remote (requesting) AXI4 master device for a write to a remote PCIe
device is not issued until the MemWr TLP transmission is guaranteed to be sent on the
PCIe link before any subsequent TX-transfers.
• A remote AXI master read of a remote PCIe device is not permitted to pass any previous
or simultaneous AXI master writes to a remote PCIe device that occurs previously or at
the same time. Timing is based off the AXI arvalid signal timing relative to the AXI
awvalid. Any AXI write transaction in which awvalid was asserted before or at the
same time as the arvalid for a read from pcie is asserted causes the MemRd TLP(s) to
be held until the pipelined or simultaneous MemWr TLP(s) have been sent.
• A remote PCIe device read of a remote AXI slave is not permitted to pass any previous
remote PCIe device writes to a remote AXI slave received by the AXI Bridge for PCI
Express core. The AXI read address phase is held until the previous AXI write
transactions have completed and bresp has been received for the AXI write
transactions.
[Ref 5] for the complete rule set. The following behaviors are
AXI Bridge for PCI Express v2.4 www.xilinx.com 51
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• Read completion data received from a remote PCIe device are not permitted to pass
any remote PCIe device writes to a remote AXI slave received by the AXI Bridge for PCI
Express core prior to the read completion data. The bresp for the AXI write(s) must be
received before the completion data is presented on the AXI read data channel.
• Read data from a remote AXI slave is not permitted to pass any remote AXI master
writes to a remote PCIe device initiated on the AXI bus prior to or simultaneously with
Chapter 3: Designing with the Core
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the read data being returned on the AXI bus. Timing is based off the AXI awvalid
signal timing relative to the AXI rvalid assertion. Any AXI write transaction in which
awvalid was asserted before or simultaneously with the rvalid being asserted up to
and including the last data beat, causes the Completion TLP(s) to be held until the
pipelined or simultaneous MemWr TLP(s) have been sent.
IMPORTANT: The transaction ordering rules for PCIe might have an impact on data throughput in
heavy bidirectional traffic.
Address Translation
The address space for PCIe is different than AXI address space. To access one address space
from another address space requires an address translation process. On the AXI side, the
bridge supports mapping to PCIe on up to six 32-bit or 64-bit AXI base address registers
(BARs). The generics used to configure the BARs follow.
C_AXIBAR_NUM, C_AXIBAR_n, C_AXIBAR_HIGHADDR_n, C_AXIBAR2PCIEBAR_n and
C_AXIBAR_AS_n,
where n represents an AXIBAR number from 0 to 5. The bridge for PCIe supports
mapping on up to three 64-bit BARs for PCIe. The generics used to configure the BARs
are:
C_PCIEBAR_NUM, C_PCIE2AXIBAR_n and C_PCIEBAR_LEN_n,
where n represents a particular BAR number for PCIe from 0 to 2.
Note:
parameter is set to one, the AXIBAR2PCIEBAR_n translation vectors can be changed by using the
software.
Four examples follow:
• Example 1 (32-bit PCIe Address Mapping) demonstrates how to set up four 32-bit AXI
• Example 2 (64-bit PCIe Address Mapping) demonstrates how to set up three 64-bit AXI
• Example 3 demonstrates how to set up two 64-bit PCIe BARs and translate the address
The C_INCLUDE_BAROFFSET_REG generic allows for dynamic address translation. When this
BARs and translate the AXI address to an address for PCIe.
BARs and translate the AXI address to an address for PCIe.
for PCIe to an AXI address.
AXI Bridge for PCI Express v2.4 www.xilinx.com 52
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• Example 4 demonstrates how set up a combination of two 32-bit AXI BARs and two 64
bit AXI BARs, and translate the AXI address to an address for PCIe.
Chapter 3: Designing with the Core
X
X&&&&
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8
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Send Feedback
Example 1 (32-bit PCIe Address Mapping)
This example shows the generic settings to set up four independent 32-bit AXI BARs and
address translation of AXI addresses to a remote address space for PCIe. This setting of AXI
BARs does not depend on the BARs for PCIe within the AXI Bridge for PCI Express core.
In this example, where C_AXIBAR_NUM=4, the following assignments for each range are
made:
C_AXIBAR_AS_0=0
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 do not matter as the lower 16-bits hold the
actual lower 16-bits of the PCIe address)
C_AXIBAR_AS_1=0
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0xFEDC0XXX (Bits 12-0 do not matter as the lower 13-bits hold the
actual lower 13-bits of the PCIe address)
C_AXIBAR_AS_2=0
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 do not care)
• Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields
X-Ref Target - Figure 3-7
• Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields
• Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields
0x56710ABC on the bus for PCIe.
Figure 3-7: AXI to PCIe Address Translation
0xFEDC1123 on the bus for PCIe.
0x41FEDCBA on the bus for PCIe.
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Example 2 (64-bit PCIe Address Mapping)
This example shows the generic settings to set up to three independent 64-bit AXI BARs
and address translation of AXI addresses to a remote address space for PCIe. This setting of
AXI BARs does not depend on the BARs for PCIe within the Bridge.
In this example, where C_AXIBAR_NUM=3, the following assignments for each range are
made:
C_AXIBAR_AS_0=1
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x500000005671XXXX (Bits 15-0 do not matter)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x60000000FEDC0XXX (Bits 12-0 do not matter)
C_AXIBAR_AS_2=1
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x7000000040XXXXXX (Bits 24-0 do not matter)
• Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields
0x5000000056710ABC on the bus for PCIe.
• Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields
0x60000000FEDC1123 on the bus for PCIe.
• Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields
0x7000000041FEDCBA on the bus for PCIe.
Example 3
This example shows the generic settings to set up two independent BARs for PCIe and
address translation of addresses for PCIe to a remote AXI address space. This setting of
BARs for PCIe does not depend on the AXI BARs within the bridge.
In this example, where C_PCIEBAR_NUM=2, the following range assignments are made:
BAR 0 is set to 0x20000000_ABCD8000 by the Root Port
C_PCIEBAR_LEN_0=15
C_PCIEBAR2AXIBAR_0=0x1234_0XXX (Bits 14-0 do not matter)
BAR 1 is set to 0xA000000012000000 by Root Port
C_PCIEBAR_LEN_1=25
C_PCIEBAR2AXIBAR_1=0xFEXXXXXX (Bits 24-0 do not matter)
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• Accessing the Bridge PCIEBAR_0 with address 0x20000000_ABCDFFF4 on the bus for
PCIe yields 0x1234_7FF4 on the AXI bus.
Chapter 3: Designing with the Core
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X-Ref Target - Figure 3-8
Figure 3-8: PCIe to AXI Translation
• Accessing Bridge PCIEBAR_1 with address 0xA00000001235FEDC on the bus for PCIe
yields 0xFE35FEDC on the AXI bus.
Example 4
This example shows the generic settings to set up a combination of two independent 32-bit
AXI BARs and two independent 64-bit BARs and address translation of AXI addresses to a
remote address space for PCIe. This setting of AXI BARs does not depend on the BARs for
PCIe within the Bridge.
In this example, where C_AXIBAR_NUM=4, the following assignments for each range are
made:
C_AXIBAR_AS_0=0
C_AXIBAR_0=0x12340000
C_AXI_HIGHADDR_0=0x1234FFFF
C_AXIBAR2PCIEBAR_0=0x5671XXXX (Bits 15-0 do not matter)
C_AXIBAR_AS_1=1
C_AXIBAR_1=0xABCDE000
C_AXI_HIGHADDR_1=0xABCDFFFF
C_AXIBAR2PCIEBAR_1=0x50000000FEDC0XXX (Bits 12-0 do not matter)
C_AXIBAR_AS_2=0
C_AXIBAR_2=0xFE000000
C_AXI_HIGHADDR_2=0xFFFFFFFF
C_AXIBAR2PCIEBAR_2=0x40XXXXXX (Bits 24-0 do not matter)
C_AXIBAR_AS_3=1
C_AXIBAR_3=0x00000000
C_AXI_HIGHADDR_3=0x0000007F
C_AXIBAR2PCIEBAR_3=0x600000008765438X (Bits 6-0 do not matter)
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• Accessing the Bridge AXIBAR_0 with address 0x12340ABC on the AXI bus yields
0x56710ABC on the bus for PCIe.
• Accessing the Bridge AXIBAR_1 with address 0xABCDF123 on the AXI bus yields
0x50000000FEDC1123 on the bus for PCIe.
• Accessing the Bridge AXIBAR_2 with address 0xFFFEDCBA on the AXI bus yields
0x41FEDCBA on the bus for PCIe.
• Accessing the AXI M S PCIe Bridge AXIBAR_3 with address 0x00000071 on the AXI bus
yields 0x60000000876543F1 on the bus for PCIe.
Addressing Checks
When setting the following parameters for PCIe address mapping, C_PCIE2AXIBAR_n and
C_PCIEBAR_LEN_n, be sure these are set to allow for the 32-bit addressing space on the AXI
system. For example, the following setting is illegal and results in an invalid AXI address.
C_PCIE2AXIBAR_0 = 0xFFFF_0000
C_PCIEBAR_LEN_0 = 23
Also, check for a larger value on C_PCIEBAR_LEN_n compared to the value assigned to
parameter, C_PCIE2AXIBAR_n. For example, the following parameter settings.
C_PCIE2AXIBAR_0 = 0xFFFF_E000
C_PCIEBAR_LEN_0 = 20
To keep the AXIBAR upper address bits as 0xFFFF_E000 (to reference bits [31:13]), the
C_PCIEBAR_LEN_0 parameter must be set to 13.
Interrupts
This section describes the interrupt pins which include Local, MSI and Legacy Interrupts.
Local Interrupts
The interrupt_out pin can be configured to send interrupts based on the settings of the
Interrupt Mask register. The interrupt_out pin signals interrupts to devices attached to
the memory mapped AXI4 side of the Bridge. The MSI interrupt defined in the Interrupt
Mask & Interrupt Decode registers is used to indicate the receipt of a Message Signaled
Interrupt only when the bridge is operating in Root Port mode (C_INCLUDE_RC=1).
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MSI Interrupt
When the msi_enable output pin indicates that the bridge has Endpoint MSI functionality
enabled (msi_enable = ‘1’), the intx_msi_request input pin is defined as MSI_Request
and can be used to trigger a Message Signaled Interrupt through a special MemWr TLP to
an external Root Port for PCIe on the PCIe side of the Bridge. The intx_msi_request
input pin is positive-edge detected and synchronous to axi_aclk_out. The address and
data contained in this MemWr TLP are determined by an external Root Port for PCIe
configuration of registers within the integrated block for PCI Express. The
intx_msi_request pin input is valid only when the bridge is operating in Endpoint mode
(C_INCLUDE_RC=0).
Additional MSI capability now supports multiple vectors on the Endpoint configuration of
the AXI Bridge for PCI Express core. Using the handshaking described here, an additional
input value specifies the vector number to send with the MSI MemWr TLP upstream to the
Root Port. This is specified on the input signal, msi_vector_num. This signal is (4:0), and
represents up to (32), the allowable MSI messages that can be sent from the Endpoint (and
what is enabled after configuration).
The bridge ignores any bits set on the msi_vector_num input signal, if they are not
allocated in the Message Control Register.
The Endpoint requests the number of message as specified in the design parameter (of the
AXI Bridge for PCI Express), C_NUM_MSI_REQ. Following specification requirements, this
parameter can be set up to 5. C_NUM_MSI_REQ represents the number of MSI vectors
requested. For example, C_NUM_MSI_REQ = 5 represents a request of 2
5
= 32 MSI vectors.
This parameter value, C_NUM_MSI_REQ is assigned to the Message Control Register field,
Multiple Message Capable, bits (3:1).
After configuration, the number of allocated MSI vectors is specified in the design output
port, msi_vector_width. This signal with width, (2:0), can only be values up to 5 (101),
representing 32 allocated MSI vectors for the Endpoint. Output values of 6 and 7; 110 and
111 are reserved. The msi_vector_width output signal is a direct correlation from the
value in the Multiple Message Enable field bits (6:4) of the Message Control Register as
shown in
Tab le 3-5.
Table 3-5: MSI Vectors Enabled in Message Control Register
Value Number of Messages Requested Output Signal, MSI_Vector_Width (2:0)
“000” 1 000
“001” 2 001
“010” 4 010
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“011” 8 011
“100” 16 100
“101” 32 101
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Table 3-5: MSI Vectors Enabled in Message Control Register (Cont’d)
Value Number of Messages Requested Output Signal, MSI_Vector_Width (2:0)
110 Reserved N/A
111 Reserved N/A
Additional IP is required in the Endpoint PCIe system to create the prioritization scheme for
the MSI vectors on the PCIe interface.
Legacy Interrupts
The bridge supports legacy interrupts for PCI if selected by the C_INTERRUPT_PIN
parameter. (Can only be set to 1 when C_INCLUDE_RC = 0.) A value of 1 selects INTA, as
defined in
output pin indicates that the bridge has endpoint MSI functionality disabled
(MSI_enable = ‘0’), the intx_msi_request pin is defined as intx. When the intx pin
goes High, an assert INTA message is sent. When the INTX pin goes Low, a deassert INTA
message is sent. These messages are defined in the PCI 2.1 specification. The
intx_msi_request pin input is valid only when the bridge is operating in Endpoint mode
(C_INCLUDE_RC=0).
Tab le 2-4. If a legacy interrupt for PCI support is selected and the msi_enable
Malformed TLP
The integrated block for PCI Express detects a malformed TLP. For the IP configured as an
Endpoint core, a malformed TLP results in a fatal error message being sent upstream if error
reporting is enabled in the Device Control Register.
For the IP configured as a Root Port, when a malformed TLP is received from the Endpoint,
this can fall under one of several types of violations as per the PCIe specification. For
example, if a Received TLP has the Error Poison bit set, this is discarded by the MM/S master
bridge, and the MEP (Master Error Poison) bit is set in the Interrupt Decode register.
Abnormal Conditions
This section describes how the Slave side (Ta bl e 3-6) and Master side (Ta bl e 3-7) of the AXI
Bridge for PCI Express core handle abnormal conditions.
Slave Bridge Abnormal Conditions
Slave Bridge abnormal conditions are classified as: Illegal Burst Type and Completion TLP
Errors. The following sections describe the manner in which the Bridge handles these errors.
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Illegal Burst Type
The Slave Bridge monitors AXI read and write burst type inputs to ensure that only the INCR
(incrementing burst) type is requested. Any other value on these inputs is treated as an
error condition and the Slave Illegal Burst (SIB) interrupt is asserted. In the case of a read
request, the Bridge asserts SLVERR for all data beats and arbitrary data is placed on the
s_axi_rdata bus. In the case of a write request, the Bridge asserts SLVERR for the write
response and all write data is discarded.
Completion TLP Errors
Any request to the bus for PCIe (except for posted Memory write) requires a completion TLP
to complete the associated AXI request. The Slave side of the Bridge checks the received
completion TLPs for errors and checks for completion TLPs that are never returned
(Completion Timeout). Each of the completion TLP error types are discussed in the
subsequent sections.
Unexpected Completion
When the Slave Bridge receives a completion TLP, it matches the header RequesterID and
Tag to the outstanding RequesterID and Tag. A match failure indicates the TLP is an
Unexpected Completion which results in the completion TLP being discarded and a Slave
Unexpected Completion (SUC) interrupt strobe being asserted. Normal operation then
continues.
Unsupported Request
A device for PCIe might not be capable of satisfying a specific read request. For example,
the read request targets an unsupported address for PCIe causing the completer to return
a completion TLP with a completion status of 0b001 - Unsupported Request. The completer
can also return a completion TLP with a completion status that is reserved according to the
2.1 PCIe Specification, which must be treated as an unsupported request status. When the
slave bridge receives an unsupported request response, the Slave Unsupported Request
(SUR) interrupt is asserted and the SLVERR response is asserted with arbitrary data on the
memory mapped AXI4 bus.
Completion Timeout
A Completion Timeout occurs when a completion (Cpl) or completion with data (CplD) TLP
is not returned after an AXI to PCIe read request. Completions must complete within the
C_COMP_TIMEOUT parameter selected value from the time the MemRd for PCIe request is
issued. When a completion timeout occurs, a Slave Completion Timeout (SCT) interrupt is
asserted and the SLVERR response is asserted with arbitrary data on the memory mapped
AXI4 bus.
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Poison Bit Received on Completion Packet
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An Error Poison occurs when the completion TLP EP bit is set, indicating that there is
poisoned data in the payload. When the slave bridge detects the poisoned packet, the Slave
Error Poison (SEP) interrupt is asserted and the SLVERR response is asserted with arbitrary
data on the memory mapped AXI4 bus.
Completer Abort
A Completer Abort occurs when the completion TLP completion status is 0b100 Completer Abort. This indicates that the completer has encountered a state in which it was
unable to complete the transaction. When the slave bridge receives a completer abort
response, the Slave Completer Abort (SCA) interrupt is asserted and the SLVERR response is
asserted with arbitrary data on the memory mapped AXI4 bus.
Table 3-6: Slave Bridge Response to Abnormal Conditions
Transfer Type Abnormal Condition Bridge Response
Chapter 3: Designing with the Core
Read Illegal burst type
Write Illegal burst type
Read Unexpected completion
Read
Read Completion timeout
Read Poison bit in completion
Read
Unsupported Request status
returned
Completer Abort (CA) status
returned
Master Bridge Abnormal Conditions
The following sections describe the manner in which the Master Bridge handles abnormal
conditions.
SIB interrupt is asserted.
SLVERR response given with arbitrary read data.
SIB interrupt is asserted.
Write data is discarded.
SLVERR response given.
SUC interrupt is asserted.
Completion is discarded.
SUR interrupt is asserted.
SLVERR response given with arbitrary read data.
SCT interrupt is asserted.
SLVERR response given with arbitrary read data.
Completion data is discarded.
SEP interrupt is asserted.
SLVERR response given with arbitrary read data.
SCA interrupt is asserted.
SLVERR response given with arbitrary read data.
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AXI DECERR Response
When the Master Bridge receives a DECERR response from the AXI bus, the request is
discarded and the Master DECERR (MDE) interrupt is asserted. If the request was
non-posted, a completion packet with the Completion Status = Unsupported Request (UR)
is returned on the bus for PCIe.
AXI SLVERR Response
When the Master Bridge receives a SLVERR response from the addressed AXI slave, the
request is discarded and the Master SLVERR (MSE) interrupt is asserted. If the request was
non-posted, a completion packet with the Completion Status = Completer Abort (CA) is
returned on the bus for PCIe.
Max Payload Size for PCIe, Max Read Request Size or 4K Page Violated
It is the responsibility of the requester to ensure that the outbound request adhere to the
Max Payload Size, Max Read Request Size, and 4 Kb Page Violation rules. If the master
bridge receives a request that violates one of these rules, the bridge processes the invalid
request as a valid request, which can return a completion that violates one of these
conditions or can result in the loss of data. The Master Bridge does not return a malformed
TLP completion to signal this violation.
Completion Packets
When the MAX_READ_REQUEST_SIZE is greater than the MAX_PAYLOAD_SIZE, a read
request for PCIe can ask for more data than the Master Bridge can insert into a single
completion packet. When this situation occurs, multiple completion packets are generated
up to MAX_PAYLOAD_SIZE, with the Read Completion Boundary (RCB) observed.
Poison Bit
When the poison bit is set in a transaction layer packet (TLP) header, the payload following
the header is corrupt. When the Master Bridge receives a memory request TLP with the
poison bit set, it discards the TLP and asserts the Master Error Poison (MEP) interrupt
strobe.
Zero Length Requests
When the Master Bridge receives a read request with the Length = 0x1, FirstBE = 0x00, and
LastBE = 0x00, it responds by sending a completion with Status = Successful Completion.
When the Master Bridge receives a write request with the Length = 0x1, FirstBE = 0x00, and
LastBE = 0x00 there is no effect.
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Table 3-7: Master Bridge Response to Abnormal Conditions
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Transfer Type Abnormal Condition Bridge Response
Chapter 3: Designing with the Core
Read DECERR response
Write DECERR response MDE interrupt strobe asserted
Read SLVERR response
Write SLVERR response MSE interrupt strobe asserted
Write Poison bit set in request
Read DECERR response
Write DECERR response MDE interrupt strobe asserted
MDE interrupt strobe asserted
Completion returned with Unsupported Request status
MSE interrupt strobe asserted
Completion returned with Completer Abort status
MEP interrupt strobe asserted
Data is discarded
MDE interrupt strobe asserted
Completion returned with Unsupported Request status
Link Down Behavior
The normal operation of the AXI Bridge for PCI Express core is dependent on the integrated
block for PCIe establishing and maintaining the point-to-point link with an external device
for PCIe. If the link has been lost, it must be re-established to return to normal operation.
When a Hot Reset is received by the AXI Bridge for PCI Express core, the link goes down and
the PCI Configuration Space must be reconfigured.
Initiated AXI4 write transactions that have not yet completed on the AXI4 bus when the link
goes down have a SLVERR response given and the write data is discarded. Initiated AXI4
read transactions that have not yet completed on the AXI4 bus when the link goes down
have a SLVERR response given, with arbitrary read data returned.
Any MemWr TLPs for PCIe that have been received, but the associated AXI4 write
transaction has not started when the link goes down, are discarded. If the associated AXI4
write transaction is in the process of being transferred, it completes as normal. Any MemRd
TLPs for PCIe that have been received, but have not returned completion TLPs by the time
the link goes down, complete on the AXI4 bus, but do not return completion TLPs on the
PCIe bus.
Root Port
When configured to support Root Port functionality, the AXI Bridge for PCI Express core
fully supports Root Port operation as supported by the underlying block. There are a few
details that need special consideration. The following subsections contain information and
design considerations about Root Port support.
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Power Limit Message TLP
The AXI Bridge for PCI Express core automatically sends a Power Limit Message TLP when
the Master Enable bit of the Command Register is set. The software must set the Requester
ID register before setting the Master Enable bit to ensure that the desired Requester ID is
used in the Message TLP.
Root Port Configuration Read
When an ECAM access is performed to the primary bus number, self-configuration of the
integrated block for PCIe is performed. A PCIe configuration transaction is not performed
and is not presented on the link. When an ECAM access is performed to the bus number
that is equal to the secondary bus value in the Enhanced PCIe type 1 configuration header,
then type 0 configuration transactions are generated.
When an ECAM access is attempted to a bus number that is in the range defined by the
secondary bus number and subordinate bus number range (not including secondary bus
number), then type 1 configuration transactions are generated. The primary, secondary and
subordinate bus numbers are written and updated by Root Port software to the type 1 PCI
Configuration Header of the AXI Bridge for PCI Express core in the enumeration procedure.
When an ECAM access is attempted to a bus number that is out of the range defined by the
secondary bus_number and subordinate bus number, the bridge does not generate a
configuration request and signal a SLVERR response on the AXI4-Lite bus.
When a Unsupported Request (UR) response is received for a configuration read request, all
ones are returned on the AXI4-Lite bus to signify that a device does not exist at the
requested device address. It is the responsibility of the software to ensure configuration
write requests are not performed to device addresses that do not exist. However, the AXI
Bridge for PCI Express core asserts SLVERR response on the AXI4-Lite bus when a
configuration write request is performed on device addresses that do not exist or a UR
response is received.
If a configuration transaction is attempted to a device number other than zero, the AXI
Bridge for PCI Express core asserts SLVERR on the AXI4-Lite bus. PCIe transactions are
generated for only the device number of zero.
Unsupported Request to Upstream Traffic
To receive upstream traffic from a connected device, the Root Ports PCIe BAR_0 must be
configured. If BAR_0 is not configured, the Root Port responds to requests with a
Completion returned with Unsupported Request status.
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Configuration Transaction Timeout
Configuration transactions are non-posted transactions. The AXI Bridge for PCI Express core
has a timer for timeout termination of configuration transactions that have not completed
on the PCIe link. SLVERR is returned when a configuration timeout occurs. Timeout of
configuration transactions are flagged by an interrupt as well.
Abnormal Configuration Transaction Termination Responses
Responses on AXI4-Lite to abnormal terminations to configuration transactions are shown
in
Tab le 3-8.
Table 3-8: Responses of AXI Bridge for PCI Express to Abnormal Configuration Terminations
Transfer Type Abnormal Condition Bridge Response
Config Read or Write
Config Read or Write Valid bus number and completion timeout occurs SLVERR response is asserted
Config Read or Write Device number not zero SLVERR response is asserted
Config Read or Write Completion timeout SLVERR response is asserted
Config Write
Bus number not in the range of primary bus
number through subordinate bus number
Bus number in the range of secondary bus number
through subordinate bus number and UR is
returned.
SLVERR response is asserted
SLVERR response is asserted
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Design Flow Steps
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This chapter describes customizing and generating the core, constraining the core, and the
simulation, synthesis and implementation steps that are specific to this IP core. More
detailed information about the standard design flows in the Vivado® IP Integrator can be
found in the following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 12]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 8]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 10]
Chapter 4
Customizing and Generating the Core
This section includes information about using the Vivado Design Suite to customize and
generate the core.
Note: If you are customizing and generating the core in the Vivado IP Integrator, see the Vivado
Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 12] for detailed
information. IP Integrator might auto-compute certain configuration values when validating or
generating the design. To check whether the values do change, see the description of the parameter
in this chapter. To view the parameter value you can run the validate_bd_design command in
the Tcl Console.
You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:
1. Select the IP from the IP catalog.
2. Double-click the selected IP, or select the Customize IP command from the toolbar or
right-click menu.
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Chapter 4: Design Flow Steps
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For further details, see:
• “Working with IP” and “Customizing IP for the Design” in the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 9].
• “Working with the Vivado IDE” section in the Vivado Design Suite User Guide: Getting
Started (UG910) [Ref 8].
Note:
This layout might vary from the current version.
Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).
Customizing the Core
The AXI Bridge for PCI Express core customization parameters are described in the
following sections.
Basic Parameter Settings
The initial customization screen shown in Figure 4-1 is used to define the basic parameters
for the core, including the component name, reference clock frequency, and silicon type.
X-Ref Target - Figure 4-1
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Figure 4-1: Basic Parameter Settings
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Component Name
Base name of the output f iles generated for the core. The name must begin with a letter
and can be composed of these characters: a to z, 0 to 9, and “_.”
PCIe Device / Port Type
Indicates the PCI Express logical device type.
Reference Clock Frequency
Selects the frequency of the reference clock provided on sys_clk .
Slot Clock Configuration
Enables the Slot Clock Configuration bit in the Link Status register. Selecting this option
means the link is synchronously clocked. See
clocking options.
Clocking, page 42 for more information on
Silicon Type
Selects the silicon type.
PCIe Link Configuration
The PCIe Link Config page is shown in Figure 4-2.
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X-Ref Target - Figure 4-2
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Chapter 4: Design Flow Steps
Figure 4-2: PCIe Link Configuration
Number of Lanes
The AXI Bridge for PCI Express® core requires the selection of the initial lane width.
Tab le 4-1 defines the available widths and associated generated core. Wider lane width
cores can train down to smaller lane widths if attached to a smaller lane-width device.
Table 4-1: Lane Width and Product Generated
Lane Width Product Generated
x1 1-Lane
x2 2-Lane
x4 4-Lane
x8 8-Lane
Link Speed
The AXI Bridge for PCI Express core allows the selection of Maximum Link Speed supported
by the device.
Higher link speed cores are capable of training to a lower link speed if connected to a lower
link speed capable device.
Tab le 4-2 defines the lane widths and link speeds supported by the device.
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Table 4-2: Lane Width and Link Speed
Lane Width Link Speed
x1 2.5 Gb/s, 5 Gb/s
x2 2.5 Gb/s, 5 Gb/s
x4 2.5 Gb/s, 5 Gb/s
x8 2.5 Gb/s, 5 Gb/s
PCIe Block Location
The AXI Bridge for PCI Express core allows the selection of the PCI Express Hard Block within
Xilinx FPGAs.
PCIe ID Settings
The Identity Settings pages are shown in Figure 4-3. These settings customize the IP initial
values and device class code.
X-Ref Target - Figure 4-3
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Figure 4-3: PCIe ID Settings
ID Initial Values
• Vendor ID: Identifies the manufacturer of the device or application. Valid identifiers
are assigned by the PCI™ Special Interest Group to guarantee that each identifier is
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unique. The default value, 10EEh, is the Vendor ID for Xilinx. Enter your vendor
identification number here. FFFFh is reserved.
• Device ID: A unique identifier for the application; the default value, which depends on
the configuration selected, is 70<link speed><link width>h. This field can be any value;
change this value for the application.
• Revision ID: Indicates the revision of the device or application; an extension of the
Device ID. The default value is 00h; enter values appropriate for the application.
• Subsystem Vendor ID: Further qualifies the manufacturer of the device or application.
Enter a Subsystem Vendor ID here; the default value is 10EEh. Typically, this value is the
same as Vendor ID. Setting the value to 0000h can cause compliance testing issues.
• Subsystem ID: Further qualifies the manufacturer of the device or application. This
value is typically the same as the Device ID; the default value depends on the lane
width and link speed selected. Setting the value to 0000h can cause compliance testing
issues.
Class Code
The Class Code identifies the general function of a device, and is divided into three
byte-size fields. The Vivado IDE allows you to either enter the 24-bit value manually
(default) by either selecting the Enter Class Code Manually checkbox or using the Class
Code lookup assistant to populate the field. De-select the checkbox to enable the Class
Code assistant.
• Base Class: Broadly identifies the type of function performed by the device.
• Sub-Class: More specifically identifies the device function.
• Interface: Defines a specific register-level programming interface, if any, allowing
device-independent software to interface with the device.
Class code encoding can be found in the PCI-SIG® specifications [Ref 5].
Class Code Look-up Assistant
The Class Code Look-up Assistant provides the Base Class, Sub-Class and Interface values
for a selected general function of a device. This Look-up Assistant tool only displays the
three values for a selected function. You must enter the values in Class Code for these
values to be translated into device settings.
Base Address Registers
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The Base Address Registers (BARs) screens shown in Figure 4-4 set the base address register
space for the Endpoint configuration. Each BAR (0 through 5) configures the BAR Aperture
Size and Control attributes of the Physical Function, as described in
Tab le 4-3, page 72.
X-Ref Target - Figure 4-4
Send Feedback
Chapter 4: Design Flow Steps
Figure 4-4: PCIe Base Address Register
Base Address Register Overview
The AXI Bridge for PCI Express core in Endpoint configuration supports up to three 32-bit
BARs or three 64-bit BARs. The AXI Memory Mapped to PCI Express® in Root Port
configuration supports one 32-bit BARs or one 64-bit BAR.
You should edit this parameter with the proper value for AXI-PCIe BAR Translation.
BARs can be one of two sizes. The selection applies to all BARs.
• 32-bit BARs: The address space can be as small as 16 bytes or as large as 2 gigabytes.
Used for Memory to I/O.
• 64-bit BARs: The address space can be as small as 128 bytes or as large as 8 exabytes.
Used for Memory only.
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Chapter 4: Design Flow Steps
Send Feedback
All BAR registers share these options:
• Checkbox: Click the checkbox to enable the BAR; deselect the checkbox to disable the
BAR.
• Type: BARs can be Memory apertures only.
Memory: Memory BARs can be either 64-bit or 32-bit. Prefetch is enabled for
°
64-bit and not enabled for 32-bit. When a BAR is set as 64 bits, it uses the next BAR
for the extended address space, making it inaccessible.
• Size: The available Size range depends on the PCIe® Device/Port Type and the Type of
BAR selected. Tab l e 4 - 3 lists the available BAR size ranges.
Table 4-3: BAR Size Ranges for Device Configuration
PCIe Device/Port Type BAR Type BAR Size Range
PCI Express Endpoint 32-bit Memory 128 Bytes - 2 Gigabytes
64-bit Memory 128 Bytes - 8 Exabytes
• Value: The value assigned to the BAR based on the current selections.
For more information about managing the Base Address Register settings, see Managing
Base Address Register Settings.
Managing Base Address Register Settings
Memory indicates that the address space is defined as memory aperture. The base address
register only responds to commands that access the specified address space. Generally,
memory spaces less than 4 KB in size should be avoided.
Disabling Unused Resources
For best results, disable unused base address registers to conserve system resources. A base
address register is disabled by deselecting unused BARs in the Vivado IDE.
PCIe Miscellaneous
The PCIe Misc screen is shown in Figure 4-5.
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X-Ref Target - Figure 4-5
Send Feedback
Chapter 4: Design Flow Steps
Figure 4-5: PCIe Miscellaneous
Interrupt Pin
Indicates the usage of Legacy interrupts.The AXI Bridge for PCI Express core implements
INTA only.
MSI Vectors Requested
Indicates the number of MSI vectors requested by the core.
Completion Timeout Configuration
Indicates the completion timeout value for incoming completions due to outstanding
memory read requests.
Dynamic Slave Bridge Address Translation
Enables the address translation vectors within the AXI Bridge for PCI Express bridge logic to
be changed dynamically through the AXI Lite interface.
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Chapter 4: Design Flow Steps
Send Feedback
AXI Base Address Registers
The AXI Base Address Registers (BARs) screen shown in Figure 4-6 sets the AXI base address
registers and the translation between AXI Memory space and PCI Express Memory space.
Each BAR has a Base Address, High Address, and translation field which can be configured
through the Vivado IDE.
X-Ref Target - Figure 4-6
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Figure 4-6: AXI Base Address Registers
Number of BARs
Indicates the number of AXI BARs enabled.The BARs are enabled sequentially.
64-bit Enable
Indicates if the AXI Base Address Register is 64-bit addressable. Selecting a 64-bit BAR
consumes the subsequent BAR.
Aperture Base Address
Sets the base address for the address range associated to the BAR. You should edit this
parameter to fit design requirements.
Chapter 4: Design Flow Steps
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Aperture High Address
Sets the upper address threshold for the address range associated to the BAR. You should
edit this parameter to fit design requirements.
AXI to PCIe Translation
Configures the translation mapping between AXI and PCI Express address space. You
should edit this parameter to fit design requirements.
SRIOV BARs can be one of two sizes:
• 32-bit BARs: The address space can be as small as 16 bytes or as large as 2 gigabytes.
Used for Memory to I/O.
• 64-bit BARs: The address space can be as small as 128 bytes or as large as 8 exabytes.
Used for Memory only.
AXI System
The AXI System screen shown in Figure 4-7 sets the AXI Addressing and AXI Interconnect
parameters.
X-Ref Target - Figure 4-7
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Figure 4-7: AXI System Settings
Chapter 4: Design Flow Steps
Send Feedback
BASEADDR
Sets the AXI Base Address for the device. You should edit this parameter to fit design
requirements.
HIGHADDR
Sets the AXI High Address threshold for the device. You should edit this parameter to fit
design requirements.
S AXI ID WIDTH
Sets the ID width for the AXI Slave Interface.
Note: Multiple IDs are not supported for AXI Master Interface. Therefore, all signals concerned with
ID are not available at AXI Master Interface.
S AXI ADDR WIDTH
AXI supports 32-bit addressing so this field is always set to 32.
S AXI DATA WIDTH
Sets the data bus width for the AXI Slave interface. This can be 64-bit or 128-bit based on
your requirements. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum
performance.
M AXI ADDR WIDTH
AXI supports 32-bit addressing so this field is always set to 32.
M AXI DATA WIDTH
Sets the data bus width for the AXI Master interface. This can be 64-bit or 128-bit based on
your requirement. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum
performance.
S AXI SUPPORTS NARROW BURST
Configures the IP to accept narrow burst transactions. When not enabled, the IP is
optimized accordingly.
Shared Logic
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Enables you to share common blocks across multiple instantiations by selecting one or
more of the options on this page. For a details description of the shared logic feature, see
Shared Logic in Chapter 3.
Chapter 4: Design Flow Steps
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Output Generation
For details, see “Generating IP Output Products” in the Vivado Design Suite User Guide:
Designing with IP (UG896)
For information regarding the example design, see Example Design Output Structure in
Chapter 5.
[Ref 9].
Constraining the Core
Required Constraints
The AXI Bridge for PCI Express® core requires a clock period constraint for the REFCLK
input that agrees with the C_REF_CLK_FREQ parameter setting. In addition, pin-placement
(LOC) constraints are needed that are board/part/package specific.
See Placement Constraints for more details on the constraint paths for FPGA architectures.
Additional information on clocking can be found in the Xilinx Solution Center for PCI
Express (see
Solution Centers, page 88).
System Integration
A typical embedded system including the AXI Bridge for PCI Express core is shown in
Figure 2-2, page 10. Some additional components to this sys tem in the V ivado IP integrator
can include the need to connect the MicroBlaze™ processor or Zynq® device ARM®
processor peripheral to communicate with PCI Express™ (in addition to the AXI4-Lite
register port on the PCIe bridge). A helper core is available to achieve this functionality and
bridges transactions from the AXI4-Lite MicroBlaze processor peripheral ports (DP and IP)
to the AXI4 Interconnect (connected to the AXI Bridge for PCI Express). The
axi2axi_connector IP core
The AXI Bridge for PCI Express core can be configured with each port connection for an AXI
Vivado IP integrator system topology. When instantiating the core, ensure the following bus
interface tags are defined.
BUS_INTERFACE M_AXI
BUS_INTERFACE S_AXI
BUS_INTERFACE S_AXI_CTL
[Ref 6] provides this support.
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PCIe Clock Integration
The PCIe differential clock input in the system might need to use a differential input buffer
(that is instantiated separately) from the AXI Bridge for the PCIe core. The Vivado IP
integrator automatically inserts the appropriate clock buffer.
Chapter 4: Design Flow Steps
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Placement Constraints
The AXI Bridge for PCI Express core provides a Xilinx design constraint (XDC) file for all
supported PCIe, Part, and Package permutations. You can find the generated XDC file in the
Sources tab of the Vivado IDE after generating the IP in the Customize IP dialog box.
For design platforms, it might be necessary to manually place and constrain the underlying
blocks of the AXI Bridge for the PCIe core. The modules to assign a LOC constraint include:
• the embedded integrated block for PCIe itself
• the GTX transceivers (for each channel)
• the PCIe differential clock input (if utilized)
The following subsection describes example constraints for the 7 series architecture.
Constraints for Virtex-7 and Kintex-7 FPGAs
This section highlights the LOC constraints to be specified in the XDC file for the AXI Bridge
for PCI Express core for 7 series FPGA design implementations.
For placement/path information on the integrated block for PCIe itself, the following
constraint can be utilized:
set_property LOC PCIE_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
pcie_top_i/pcie_7x_i/pcie_block_i}]
For placement/path information of the GTX transceivers, the following constraint can be
utilized:
set_property LOC GTXE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/
gtx_channel.gtxe2_channel_i}]
For placement/path constraints of the input PCIe differential clock source (using the
example provided in
set_property LOC IBUFDS_GTE2_X*Y* [get_cells {*/PCIe_Diff_Clk_I/
USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I}]
System Integration), the following can be utilized:
Constraints for Artix-7 FPGAs
Special consideration must be given to Artix®-7 device implementations. The same IP block
constraint can be used as described previously (see
FPGAs, page 78). However, the PCIe serial transceiver wrapper instance is different in the IP.
Use the following LOC constraint for the GTP transceivers in Artix-7 devices.
Constraints for Virtex-7 and Kintex-7
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Chapter 4: Design Flow Steps
Send Feedback
set_property LOC GTPE2_CHANNEL_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/
gtp_channel.gtpe2_channel_i}]
Also for Artix-7 devices, the GTP_COMMON must be constrained to a location. The
following LOC constraint can be utilized.
set_property LOC GTPE2_COMMON_X*Y* [get_cells {U0/comp_axi_enhanced_pcie/
comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_inst/
gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.qpll_wrapper_i/
gtp_common.gtpe2_common_i}]
Clock Frequencies
The AXI Memory Mapped to PCI Express Bridge supports reference clock frequencies of
100 MHz and 250 MHz and is configurable within the Vivado IDE.
Simulation
• For comprehensive information about Vivado simulation components, as well as
information about using supported third party tools, see the Vivado Design Suite User
Guide: Logic Simulation (UG900) [Ref 10].
• For information regarding simulating the example design, see Simulation Design
Overview in Chapter 5.
Synthesis and Implementation
• For details about synthesis and implementation, see “Synthesizing IP” and
“Implementing IP” in the Vivado Design Suite User Guide: Designing with IP (UG896)
[Ref 9].
• For information regarding implementing the example design, see Implementation
Design Overview in Chapter 5.
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Example Design
Send Feedback
This chapter contains information about the example design provided in the Vivado®
Design Suite.
Overview
The example simulation design for the Endpoint configuration of the AXI-PCIe block
consists of two discrete parts:
• The Root Port Model, a test bench that generates, consumes, and checks PCI Express
bus traffic.
• An AXI BRAM Controller.
Chapter 5
Simulation Design Overview
For the simulation design, transactions are sent from the Root Port Model to the AXI Bridge
for PCI Express core configured as an Endpoint and processed inside the AXI BRAM
controller design.
Figure 5-1 illustrates the simulation design provided with the AXI Bridge for PCI Express
core.
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X-Ref Target - Figure 5-1
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Send Feedback
Chapter 5: Example Design
Figure 5-1: Example Design Block Diagram
Note: The example design supports Verilog as the target language.
Customizing and Generating the Example Design
In Customize IP dialog box, make the following selections for the example design.
1. In the PCIE:Basics page, the example design supports only an Endpoint (EP) device.
2. The PCIE:ID defaults are supported.
3. The PCIE:BARS defaults are supported.
4. The PCIE:Misc page defaults are supported.
5. In the AXI:BARS page, default values are assigned to the Base Address, High Address,
and AXI to PCIe Translation values.
6. The AXI:System page default values are supported:
Note:
Design. This opens a separate example design. Simulate the core by following the steps in the next
section.
After customizing the core, right-click the component name, and select Open IP Example
Simulating the Example Design
The example design can be run in any configuration using:
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• Vivado Simulator
•Cadence IES Simulator
• Mentor Graphics Questa® SIM
•VCS Simulator
Chapter 5: Example Design
Send Feedback
Vivado Simulator
By defaults, the simulator is set to Vivado simulator. To run a simulation, click Run
Behavioral Simulation in the Flow Navigator.
Cadence IES
For a Cadence IES simulation, the following steps are required:
1. Run the following command in Vivado Tcl console of the example project to create an
IES environment:
export_simulation -lib_map_path /proj/xbuilds/2013.3_daily_latest/clibs/ius/
12.20.016/lin64/lib/ -simulator ies -directory ncsim
2. Go to ncsim directory on the terminal, and run the ./board_sim_ies.sh command.
Mentor Graphics Questa SIM
For a Questa SIM simulation, the following steps are required:
1. In the Vivado IDE, change the simulation settings as follows:
Tar get s im u lat or : QuestaSim/ModelSim
°
2. On the Simulator tab, select Run Simulation > Run behavioral simulation.
VCS Simulator
For a VCS simulation, the following steps are required:
1. In the Vivado Tcl console, enter set_param
ips.useProjectLanguageSubcoreFileDiscovery "true"
2. In the Vivado Sources Tab, select AXI_BRAM_CTRL IP > Reset Output Products >
Generate Output Products.
3. Run the following command in Vivado Tcl console of the example project to create a VCS
environment:
export_simulation -lib_map_path /proj/xbuilds/2014.1_daily_latest/clibs/vcs/
H-2013.06-3/lin64/lib/ -simulator vcs_mx -force -directory vcs_mx
4. Go to the vcs_mx directory on the terminal, and run the ./board_sim_vcs_mx.sh
command.
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IMPORTANT: Simulation is not supported for configurations with the Silicon Revision option set to IES.
Only implementation is supported.
Chapter 5: Example Design
Send Feedback
Implementation Design Overview
For implementation design, the AXI-BRAM controller can be used as a scratch pad memory
to write and read to Block RAM locations.
Example Design Elements
The core wrapper includes:
• An example Verilog HDL or VHDL wrapper (instantiates the cores and example design).
• A customizable demonstration test bench to simulate the example design.
Example Design Output Structure
Figure 5-2 provides the output structure of the example design.
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X-Ref Target - Figure 5-2
Send Feedback
Chapter 5: Example Design
Figure 5-2: Example Design Output Structure
Tab le 5-1 provides a descriptions of the contents of the example design directories.
Table 5-1: Example Design Structure
Directory Description
project_1/axi_pcie_0_example Contains all example design files.
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/imports/
example_design/
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/ip/axi_pcie_0
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/ip/
axi_bram_ctrl_0
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sim_1/imports/
simulation/dsport
Contains the top module for the
example design,
xilinx_axi_pcie_ep.v.
Contains the XDC file based on device
selected, all design files and subcores
used in axi_pcie, and the top modules for
simulation and synthesis.
Contains block RAM controller files used
in example design.
Contains all RP files, cgator and PIO files.
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Chapter 5: Example Design
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Directory Description
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sim_1/imports/
simulation/functional
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/constrs_1/imports/
example_design
Contains the test bench file.
Contains the example design XDC file.
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Test Be n ch
Send Feedback
For information about the test bench for the example design, see Chapter 5, Example
Design.
Chapter 6
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Migrating and Upgrading
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This appendix contains information about migrating a design from ISE® Design Suite to the
Vivado
customers upgrading in the Vivado Design Suite, important details (where applicable)
about any port changes and other impact to user logic are included.
Migrating to the Vivado Design Suite
For information on migrating to the Vivado Design Suite, see ISE to Vivado Design Suite
Migration Methodology Guide (UG911)
®
Design Suite, and for upgrading to a more recent version of the IP core. For
[Ref 7].
Appendix A
Upgrading in the Vivado Design Suite
This section provides information about any changes to the user logic or port designations
that take place when you upgrade to a more current version of this core in the Vivado
Design Suite.
Parameter Changes
No parameter changes.
Port Changes
No port changes.
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Debugging
Send Feedback
This appendix provides information for using the resources available on the Xilinx®
Support website, debug tools, and other step-by-step processes for debugging designs
that use the AXI Bridge for PCI Express core.
Finding Help on Xilinx.com
To help in the design and debug process when using the AXI Bridge for PCI Express core, the
Xilinx Support web page (www.xilinx.com/support) contains key resources such as product
documentation, release notes, answer records, information about known issues, and links
for opening a Technical Support WebCase.
Appendix B
Documentation
This product puide is the main document associated with the AXI Bridge for PCI Express
core. This guide, along with documentation related to all products that aid in the design
proces s, can be fo und on the X il inx Suppo rt w eb page (
the Xilinx Documentation Navigator.
You can download the Xilinx Documentation Navigator from the Design Tools tab on the
Downloads page (
features available, see the online help after installation.
www.xilinx.com/download). For more information about this tool and the
www.xilinx.com/support) or by using
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
The PCI Express Solution Center is located at Xilinx Solution Center for PCI Express.
Extensive debugging collateral is available in AR: 56802.
Answer Records
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Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Appendix B: Debugging
Send Feedback
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.
Answer Records for this core are listed below, and can be located by using the Search
Support box on the main
proper keywords, such as:
• the product name
• tool messages
• summary of the issue encountered
A filter search is available after results are returned to further target the results.
Xilinx support web page. To maximize your search results, use
Master Answer Record for the AXI Bridge for PCI Express
AR: 54646
Contacting Technical Support
Xilinx provides technical support at www.xilinx.com/support for this LogiCORE™ IP product
when used as described in the product documentation. Xilinx cannot guarantee timing,
functionality, or support of product if implemented in devices that are not defined in the
documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support:
1. Navigate to www.xilinx.com/support.
2. Open a WebCase by selecting the WebCase
When opening a WebCase, include:
• Target FPGA including package and speed grade.
• All applicable Xilinx Design Tools and simulator software versions.
• Additional files based on the specific issue might also be required. See the relevant
sections in this debug guide for guidelines about which files to include with the
WebCase.
Note:
support options.
Access to WebCase is not available in all cases. Log in to the WebCase tool to see your specific
link located under Support Quick Links.
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Appendix B: Debugging
Send Feedback
Debug Tools
There are many tools available to address AXI Bridge for PCI Express design issues. It is
important to know which tools are useful for debugging various situations.
Vivado Lab Tool
Vivado® lab tools inserts logic analyzer (ILA) and virtual I/O (VIO) cores directly into your
design. Vivado lab tools also allow you to set trigger conditions to capture application and
integrated block port signals in hardware. Captured signals can then be analyzed. This
feature in the Vivado IDE is used for logic debugging and validation of a design running in
Xilinx devices.
The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores,
including:
• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)
See Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 11].
Reference Boards
Various Xilinx development boards support the AXI Bridge for PCI Express core. These
boards can be used to prototype designs and establish that the core can communicate with
the system.
• 7 series evaluation boards
KC705
°
VC707
°
ZC706
°
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Appendix B: Debugging
Send Feedback
Third-Party Tools
This section describes third-party software tools that can be useful in debugging.
LSPCI (Linux)
LSPCI is available on Linux platforms and allows you to view the PCI Express device
configuration space. LSPCI is usually found in the /sbin directory. LSPCI displays a list of
devices on the PCI buses in the system. See the LSPCI manual for all command options.
Some useful commands for debugging include:
• lspci -x -d [<vendor>]:[<device>]
This displays the first 64 bytes of configuration space in hexadecimal form for the device
with vendor and device ID specified (omit the -d option to display information for all
devices). The default Vendor/Device ID for Xilinx cores is 10EE:6012. Here is a sample of
a read of the configuration space of a Xilinx device:
> lspci -x -d 10EE:6012
81:00.0 Memory controller: Xilinx Corporation: Unknown device 6012
00: ee 10 12 60 07 00 10 00 00 00 80 05 10 00 00 00
10: 00 00 80 fa 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ee 10 6f 50
30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00
Included in this section of the configuration space are the Device ID, Vendor ID, Class
Code, Status and Command, and Base Address Registers.
• lspci -xxxx -d [<vendor>]:[<device>]
This displays the extended configuration space of the device. It can be useful to read the
extended configuration space on the root and look for the Advanced Error Reporting
(AER) registers. These registers provide more information on why the device has flagged
an error (for example, it might show that a correctable error was issued because of a
replay timer timeout).
• lspci -k
Shows kernel drivers handling each device and kernel modules capable of handling it
(works with kernel 2.6 or later).
PCItree (Windows)
PCItree can be downloaded at www.pcitree.de and allows you to view the PCI Express device
configuration space and perform one DWORD memory writes and reads to the aperture.
The configuration space is displayed by default in the lower right corner when the device is
selected, as shown in
Figure B-1.
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X-Ref Target - Figure B-1
Send Feedback
Appendix B: Debugging
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Figure B-1: PCItree with Read of Configuration Space
HWDIRECT (Windows)
HWDIRECT can be purchased at www.eprotek.com and allows you to view the PCI Express
device configuration space as well as the extended configuration space (including the AER
registers on the root).
X-Ref Target - Figure B-2
Send Feedback
Appendix B: Debugging
Figure B-2: HWDIRECT with Read of Configuration Space
PCI-SIG Software Suites
PCI-SIG® software suites such as PCIE-CV can be used to test compliance with the
specification. This software can be downloaded at
www.pcisig.com.
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Send Feedback
Appendix B: Debugging
Simulation Debug
The simulation debug flow for Mentor Graphics Questa® SIM is illustrated in Figure B-3. A
similar approach can be used with other simulators.
Figure B-3: Questa SIM Simulation Debug Flow
AXI Bridge for PCI Express v2.4 www.xilinx.com 94
PG055 June 4, 2014
Appendix B: Debugging
Send Feedback
Hardware Debug
Hardware issues can range from device recognition issues to problems seen after hours of
testing. This section provides debug flow diagrams for some of the most common issues.
Endpoints that are shaded gray indicate that more information is found in sections after
Figure B-4.
AXI Bridge for PCI Express v2.4 www.xilinx.com 95
PG055 June 4, 2014
X-Ref Target - Figure B-4
Design Fails in Hardware
Does a soft reset fix the problem?
(user_lnk_up = 1)
No
Is user_reset deasserted?
(user_reset = 0)
No
Is user_lnk_up asserted?
(user_lnk_up = 1)
To eliminate FPGA configuration
as a root cause, perform a soft
restart of the system. Performing a
soft reset on the system will keep
power applied and forces
re-enumeration of the device.
One reason user_reset stays
asserted other than the system
reset being asserted is due to a
faulty clock. This might keep the
PLL from locking which holds
user_reset asserted.
Yes
See “Link is Training Debug” section.
Yes
Yes
See "FPGA Configuration Time
Debug" section.
Is it a multi-lane link?
Multi-lane links are susceptible to
crosstalk and noise when all lanes
are switching during training.
A quick test for this is forcing one
lane operation. This can be done
by using an interposer or adapter
to isolate the upper lanes or use
a tape such as Scotch tape and
tape off the upper lanes on the
connector. If it is an embedded
board, remove the AC capacitors if
possible to isolate the lanes.
Yes
Force x1 Operation
Does user_lnk_up = 1 when using
as x1 only?
There are potentially issues
with the board layout causing
interference when all lanes are
switching. See board debug
suggestions.
Yes
No
No
No
Do you have a link analyzer?
Use the link analyzer to monitor the training
sequence and to determine the point of failure.
Have the analyzer trigger on the first TS1 that it
recognizes and then compare the output to the
LTSSM state machine sequences outlined in
Chapter 4 of the PCI Express Base Specification.
Yes
The Vivado lab tools can be used to
determine the point of failure.
Using probes, an LED, Vivado lab
tools or some other method,
determine ifuser_lnk_up is asserted.
Whenuser_lnk_up is High, it
indicates the core has achieved link
up meaning the LTSSM is in L0
state and the data link layer is in the
DL_Active state.
See "Clock Debug" section.
Send Feedback
Appendix B: Debugging
AXI Bridge for PCI Express v2.4 www.xilinx.com 96
PG055 June 4, 2014
Figure B-4: Design Fails in Hardware Debug Flow Diagram
Appendix B: Debugging
Send Feedback
FPGA Configuration Time Debug
Device initialization and configuration issues can be caused by not having the FPGA
configured fast enough to enter link training and be recognized by the system. Section 6.6
of PCI Express Base Specification, rev. 2.1
FPGA Configuration Time:
• A component must enter the LTSSM Detect state within 20 ms of the end of the
Fundamental reset.
• A system must guarantee that all components intended to be software visible at boot
time are ready to receive Configuration Requests within 100 ms of the end of
Conventional Reset at the Root Complex.
These statements basically mean the FPGA must be configured within a certain finite time,
and not meeting these requirements could cause problems with link training and device
recognition.
Configuration can be accomplished using an onboard PROM or dynamically using JTAG.
When using JTAG to configure the device, configuration typically occurs after the Chipset
has enumerated each peripheral. After configuring the FPGA, a soft reset is required to
restart enumeration and configuration of the device. A soft reset on a Windows-based PC is
performed by going to Start > Shut Down and then selecting Restart.
[Ref 5] states two rules that might be impacted by
To eliminate FPGA configuration as a root cause, you should perform a soft restart of the
system. Performing a soft reset on the system keeps power applied and forces
re-enumeration of the device. If the device links up and is recognized after a soft reset is
performed, the FPGA configuration is most likely the issue. Most typical systems use ATX
power supplies which provide some margin on this 100 ms window as the power supply is
normally valid before the 100 ms window starts.
Link is Training Debug
Figure B-5 shows the flowchart for link trained debug.
AXI Bridge for PCI Express v2.4 www.xilinx.com 97
PG055 June 4, 2014
X-Ref Target - Figure B-5
,INKIS4RAINING
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8
Send Feedback
Appendix B: Debugging
AXI Bridge for PCI Express v2.4 www.xilinx.com 98
PG055 June 4, 2014
Figure B-5: Link Trained Debug Flow Diagram
FPGA Configuration Time Debug
Device initialization and configuration issues can be caused by not having the FPGA
configured fast enough to enter link training and be recognized by the system. Section 6.6
Appendix B: Debugging
Send Feedback
of PCI Express Base Specification, rev. 2.1 [Ref 5] states two rules that might be impacted by
FPGA Configuration Time:
• A component must enter the LTSSM Detect state within 20 ms of the end of the
Fundamental reset.
• A system must guarantee that all components intended to be software visible at boot
time are ready to receive Configuration Requests within 100 ms of the end of
Conventional Reset at the Root Complex.
These statements basically mean the FPGA must be configured within a certain finite time,
and not meeting these requirements could cause problems with link training and device
recognition.
Configuration can be accomplished using an onboard PROM or dynamically using JTAG.
When using JTAG to configure the device, configuration typically occurs after the Chipset
has enumerated each peripheral. After configuring the FPGA, a soft reset is required to
restart enumeration and configuration of the device. A soft reset on a Windows based PC is
performed by going to Start > Shut Down and then selecting Restart.
To eliminate FPGA configuration as a root cause, you should perform a soft restart of the
system. Performing a soft reset on the system keeps power applied and forces
re-enumeration of the device. If the device links up and is recognized after a soft reset is
performed, then FPGA configuration is most likely the issue. Most typical systems use ATX
power supplies which provides some margin on this 100
normally valid before the 100 ms window starts.
ms window as the power supply is
Clock Debug
One reason to not deassert the user_reset_out signal is that the FPGA PLL (MMCM) and
Transceiver PLL have not locked to the incoming clock. To verify lock, monitor the
transceiver RXPLLLKDET output and the MMCM LOCK output. If the PLLs do not lock as
expected, it is necessary to ensure the incoming reference clock meets the requirements in
7
Series FPGAs GTX/GTH Transceivers User Guide [Ref 3]. The REFCLK signal should be routed
to the dedicated reference clock input pins on the serial transceiver, and the design should
instantiate the IBUFDS_GTE2 primitive in the design. See the 7
Transceivers User Guide for more information on PCB layout requirements, including
reference clock requirements.
Reference clock jitter can potentially close both the TX and RX eyes, depending on the
frequency content of the phase jitter. Therefore, maintain as clean a reference clock as
possible. Reduce crosstalk on REFCLK by isolating the clock signal from nearby high-speed
traces. Maintain a separation of at least 25
Special Interest Group website provides other tools for ensuring the reference clocks are
compliant to the requirements of the PCI Express Specification:
specifications/pciexpress/compliance/compliance_library.
mils from the nearest aggressor signals. The PCI
Series FPGAs GTX/GTH
www.pcisig.com/
AXI Bridge for PCI Express v2.4 www.xilinx.com 99
PG055 June 4, 2014
Appendix B: Debugging
Send Feedback
Debugging PCI Configuration Space Parameters
Often, a user application fails to be recognized by the system, but the Xilinx PIO Example
design works. In these cases, the user application is often using a PCI configuration space
setting that is interfering with the system systems ability to recognize and allocate
resources to the card.
The Xilinx solutions for PCI Express handle all configuration transactions internally and
generate the correct responses to incoming configuration requests. Chipsets have limits to
the amount of system resources they can allocate and the core must be configured to
adhere to these limitations.
The resources requested by the Endpoint are identified by the BAR settings within the
Endpoint configuration space. You should verify that the resources requested in each BAR
can be allocated by the chipset. I/O BARs are especially limited so configuring a large I/O
BAR typically prevents the chipset from configuring the device. Generate a core that
implements a small amount of memory (approximately 2
cause.
KB) to identify if this is the root
The Class Code setting selected in the Vivado IDE can also affect configuration. The Class
Code informs the Chipset as to what type of device the Endpoint is. Chipsets might expect
a certain type of device to be plugged into the PCI Express slot and configuration might fail
if it reads an unexpected Class Code. The BIOS could be configurable to work around this
issue.
Using a link analyzer, it is possible to monitor the link traffic and possibly determine when
during the enumeration and configuration process problems occur.
Using a Link Analyzer to Debug Device Recognition Issues
In cases where the link is up (user_lnk_up = 1), but the device is not recognized by the
system, a link analyzer can help solve the issue. It is likely the FPGA is not responding
properly to some type of access. The link view can be used to analyze the traffic and see if
anything looks out of place.
To focus on the issue, it might be necessary to try different triggers. Here are some trigger
examples:
• Trigger on the first INIT_FC1 and/or UPDATE_FC in either direction. This allows the
analyzer to begin capture after link up.
AXI Bridge for PCI Express v2.4 www.xilinx.com 100
PG055 June 4, 2014
• The first TLP normally transmitted to an Endpoint is the Set Slot Power Limit Message.
This usually occurs before Configuration traffic begins. This might be a good trigger
point.
• Trigger on Configuration TLPs.
• Trigger on Memory Read or Memory Write TLPs.
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