Xilinx 1600E, MIcroblaze Development Spartan-3E 1600E User Manual

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MicroBlaze Development

Kit Spartan-3E 1600E

Edition User Guide

UG257 (v1.1) December 5, 2007

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2002-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

6/23/06

1.0

Initial release.

 

 

 

12/5/07

1.1

Updated Figures 15-8, 15-9, and 15-10 to comply with UCF I/O location constraints.

 

 

 

MicroBlaze Development Kit Spartan-3E 1600E Edition User Guidewww.xilinx.com

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Table of Contents

Preface: About This Guide

Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: Introduction and Overview

Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Spartan-3E FPGA Features and Embedded Processing Functions . . . . . . . . . . . . . . . . . 9 Learning Xilinx FPGA, CPLD, and ISE Development Software Basics . . . . . . . . . . . . . 9 Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Key Components and Features

Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 2: Switches, Buttons, and Knob

Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Rotary Push-Button Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Discrete LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 3: Clock Sources

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SMA Clock Input or Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 4: FPGA Configuration Options

Configuration Mode Jumpers

PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DONE Pin LED

Programming the FPGA, CPLD, or Platform Flash PROM via USB . . . . . . . . . . . 27 Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Programming via iMPACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Programming Platform Flash PROM via USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 5: Character LCD Screen

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Character LCD Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interaction with Intel StrataFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Disabling the Unused LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 6: VGA Display Port

Signal Timing for a 60 Hz, 640x480 VGA Display

VGA Signal Timing

UCF Location Constraints

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 7: RS-232 Serial Ports

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 8: PS/2 Mouse/Keyboard Port

Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Chapter 9: Digital to Analog Converter (DAC)

SPI Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 70 SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Chapter 10: Analog Capture Circuit

Digital Outputs from Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Programmable Pre-Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Programmable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . 81

Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Chapter 11: Intel StrataFlash Parallel NOR Flash PROM

StrataFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Chapter 12: SPI Serial Flash

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Setting the FPGA Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Additional Design Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Other SPI Flash Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 13: DDR SDRAM

DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Chapter 14: 10/100 Ethernet Physical Layer Interface

Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Chapter 15: Expansion Connectors

Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Connector Pinout and FPGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Mating Receptacle Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Chapter 16: XC2C64A CoolRunner-II CPLD

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Chapter 17: DS2432 1-Wire SHA-1 EEPROM

UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Appendix A: Schematics

FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header . . . . 134

RS-232 Ports, VGA Port, and PS/2 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

FPGA I/O Banks 0 and 1, Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 FPGA I/O Banks 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM . . . 154 Buttons, Switches, Rotary Encoder, and Character LCD . . . . . . . . . . . . . . . . . . . . . 156 DDR SDRAM Series Termination and FX2 Connector Differential Termination 158

Appendix B: Example User Constraints File (UCF)

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Preface

About This Guide

This user guide provides basic information on the MicroBlaze Development Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference designs, including VHDL or Verilog source code, please visit the following web link.

xSpartan™-3E Starter Kit Board Reference Page http://www.xilinx.com/sp3e1600e

Acknowledgements

Xilinx wishes to thank the following companies for their support of the MicroBlaze Development Kit board:

x Intel Corporation for the 128 Mbit StrataFlash memory

xLinear Technology for the SPI-compatible A/D and D/A converters, the programmable pre-amplifier, and the power regulators for the non-FPGA components

x Micron Technology, Inc. for the 32M x 16 DDR SDRAM x SMSC for the 10/100 Ethernet PHY

x STMicroelectronics for the 16M x 1 SPI serial Flash PROM

xTexas Instruments Incorporated for the three-rail TPS75003 regulator supplying most of the FPGA supply voltages

xXilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM and their support for the embedded USB programmer

x Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD

Guide Contents

This manual contains the following chapters:

xChapter 1, “Introduction and Overview,” provides an overview of the key features of the MicroBlaze Development Kit board.

xChapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs present on the MicroBlaze Development Kit board.

xChapter 3, “Clock Sources,” describes the various clock sources available on the MicroBlaze Development Kit board.

xChapter 4, “FPGA Configuration Options,” describes the configuration options for the FPGA on the MicroBlaze Development Kit board.

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xChapter 5, “Character LCD Screen,” describes the functionality of the character LCD screen.

x Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.

x Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.

xChapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2 mouse and keyboard port.

xChapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the DAC.

xChapter 10, “Analog Capture Circuit,” describes the functionality of the A/D converter with a programmable gain pre-amplifier.

xChapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality of the StrataFlash PROM.

xChapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash memory.

x Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.

xChapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of the 10/100Base-T Ethernet physical layer interface.

xChapter 15, “Expansion Connectors,” describes the various connectors available on the MicroBlaze Development Kit board.

xChapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in FPGA configuration when using Master Serial and BPI mode.

xChapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration bitstreams.

xAppendix A, “Schematics,” lists the schematics for the MicroBlaze Development Kit board.

xAppendix B, “Example User Constraints File (UCF),” provides example code from a UCF.

Additional Resources

To find addtional resources for the MicroBlaze Processor or the Xilinx Embedded development tools, see the Xilinx website at:

http://www.Xilinx.com/Microblaze or http://www.Xilinx.com/EDK To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

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Chapter 1

Introduction and Overview

Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E Edition. You will find it useful in developing your Spartan-3E FPGA application.

Choose the Starter Kit Board for Your Needs

Depending on specific requirements, choose the Xilinx development board that best suits your needs.

Spartan-3E FPGA Features and Embedded Processing Functions

The MicroBlaze Development Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features:

x Spartan-3E specific features

i Parallel NOR Flash configuration

iMultiBoot FPGA configuration from Parallel NOR Flash PROM

iSPI serial Flash configuration

xEmbedded development

iMicroBlaze 32-bit embedded RISC processor

i PicoBlaze™ 8-bit embedded controller i DDR memory interfaces

i 10-100 Ethernet i UART

Learning Xilinx FPGA, CPLD, and ISE Development Software Basics

The MicroBlaze Development Kit board is more advanced and complex compared to other Spartan development boards.

Advanced Spartan-3 Generation Development Boards

The MicroBlaze Development Kit board demonstrates the basic capabilities of the MicroBlaze embedded processor and the Xilinx Embedded Development Kit (EDK). For more advanced development on a board with additional peripherals and FPGA logic, consider the V4 FX12 Board:

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xhttp://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO- ML403-EDK-ISE

Also consider the capable boards offered by Xilinx partners: x http://www.xilinx.com/products/devboards/index.htm

Key Components and Features

The key features of the MicroBlaze Development Kit board are: x Xilinx XC3S1600E Spartan-3E FPGA

i Up to 250

i user-I/O pins

i320-pin FBGA package

iOver 33,000 logic cells

xTwo Xilinx 4 Mbit Platform Flash configuration PROM

xXilinx 64-macrocell XC2C64A CoolRunner CPLD

x64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz

x16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)

iFPGA configuration storage

iMicroBlaze code storage/shadowing

x16 Mbits of SPI serial Flash (STMicro)

iFPGA configuration storage

i MicroBlaze code shadowing

x2 x 16 LCD display screen

x PS/2 mouse or keyboard port x VGA display port

x 10/100 Ethernet PHY (requires Ethernet MAC in FPGA) x Two 9-pin RS-232 ports (DTEand DCE-style)

x On-board USB-based FPGA/CPLD download/debug interface x 50 MHz and 66 MHz clock oscillators

x SHA-1 1-wire serial EEPROM for bitstream copy protection x Hirose FX2 expansion connector with 40-user I/O

x Three Digilent 6-pin expansion connectors

x Four-output, SPI-based Digital-to-Analog Converter (DAC)

xTwo-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier

x ChipScope™ SoftTouch debugging port x Rotary-encoder with push-button shaft x Eight discrete LEDs

x Four slide switches

x Four push-button switches x SMA clock input

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Design Trade-Offs

x 8-pin DIP socket for auxiliary clock oscillator

Design Trade-Offs

A few system-level design trade-offs were required in order to provide the MicroBlaze Development Kit board with the most functionality.

Configuration Methods Galore!

A typical FPGA application uses a single non-volatile memory to store configuration images. To demonstrate new Spartan-3E capabilities, the MicroBlaze Development Kit board has three different configuration memory sources that all need to function well together. The extra configuration functions make the starter kit board more complex than typical Spartan-3E applications.

The starter kit board also includes an on-board USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable. This USB port is for programming only and can not be used as an independent USB interface.

Voltages for all Applications

The MicroBlaze Development Kit board showcases a triple-output regulator developed by Texas Instruments, the TPS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This regulator is sufficient for most stand-alone FPGA applications. However, the starter kit board includes DDR SDRAM, which requires its own high-current supply. Similarly, the USB-based JTAG download solution requires a separate 1.8V supply.

Related Resources

xXilinx MicroBlaze Soft Processor http://www.xilinx.com/microblaze

xXilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze

xXilinx Embedded Development Kit http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm

xXilinx software tutorials http://www.xilinx.com/support/techsup/tutorials/

xTexas Instruments TPS75003 http://focus.ti.com/docs/prod/folders/print/tps75003.html

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Chapter 2

Switches, Buttons, and Knob

Slide Switches

Locations and Labels

The MicroBlaze Development Kit board has four slide switches, as shown in Figure 2-1. The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.

Spartan-3E

Development Board

SW3

 

SW0

 

Figure 2-1: Four Slide Switches

HIGH

LOW

UG257_02_01_061306

Operation

When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

UCF Location Constraints

Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin assignment and the I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition.

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NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;

NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

UG257_02_060206

Figure 2-2: UCF Constraints for Slide Switches

Push-Button Switches

Locations and Labels

The MicroBlaze Development Kit board has four momentary-contact push-button switches, shown in Figure 2-3. The push buttons are located in the lower left corner of the board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins that connect to the push buttons appear in parentheses in Figure 2-3 and the associated UCF appears in Figure 2-5.

 

Rotary Push Button Switch

 

ROT_A:(K18) requires an internal pull-up

BTN_NORTH (V4)

ROT_B:(G18) requires an internal pull-up

ROT_Center:(V16) requires an internal pull-down

 

 

Spartan-3E

 

Development Board

BTN_WEST (D18)

BTN_SOUTH (K17)

BTN_EAST (H13)

Notes:

 

1. All BTN_* push-button inputs require an internal pull-down resistor.

 

2. BTN_SOUTH is also used as a soft reset in some FPGA applications

UG257_02_03_061306

Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch

Operation

Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4. Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.

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Rotary Push-Button Switch

3.3V

Push Button

FPGA I/O Pin

 

 

 

 

 

 

 

 

 

BTN_* Signal

UG227_02_04_060206

Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA

Input Pin

In some applications, the BTN_SOUTH push-button switch is also a soft reset that selectively resets functions within the FPGA.

UCF Location Constraints

Figure 2-5 provides the UCF constraints for the four push-button switches, including the I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.

NET "BTN_EAST" NET "BTN_NORTH" NET "BTN_SOUTH" NET "BTN_WEST"

LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;

UG257_02_05_060206

Figure 2-5: UCF Constraints for Push-Button Switches

Rotary Push-Button Switch

Locations and Labels

The rotary push-button switch is located in the center of the four individual push-button switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.

Operation

The rotary push-button switch integrates two different functions. The switch shaft rotates and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a push-button switch.

Push-Button Switch

Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to 3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to generate a logic Low. Figure 2-9 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.

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Rotary / Push Button

FPGA I/O Pin 3.3V

ROT_CENTER Signal

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Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input

Pin

Rotary Shaft Encoder

In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2-7. Depending on which way the shaft is rotated, one of the switches opens before the other. Likewise, as the rotation continues, one switch closes before the other. However, when the shaft is stationary, also called the detent position, both switches are closed.

A pull-up resistor in each input pin

 

 

 

 

 

 

 

 

 

generates a ‘1’ for an open switch.

 

FPGA

 

 

 

See the UCF file for details on

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vcco

specifying the pull-up resistor.

 

 

 

 

 

 

 

 

 

A=‘0’

Vcco

Rotary Shaft

Encoder

B=‘1’

GND

 

UG257_02_07_060206

 

Figure 2-7: Basic example of rotary shaft encoder circuitry

Closing a switch connects it to ground, generating a logic Low. When the switch is open, a pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints in Figure 2-9 describe how to define the pull-up resistor.

The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction! See the Rotary Encoder Interface reference design in“Related Resources” for an example.

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Discrete LEDs

A

B

Rising edge on ‘A’

 

 

Switch opening chatter on ‘A’

when ‘B’ is Low indicates

 

 

 

 

injects false “clicks” to the RIGHT

 

RIGHT (clockwise) rotation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rotating RIGHT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Detent

Switch closing chatter on ‘B’ injects false “clicks” to the LEFT (’B’ rising edge when ‘A’ is Low)

Detent

UG257_02_08_060206

Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter

UCF Location Constraints

Figure 2-9 provides the UCF constraints for the four push-button switches, including the I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each input.

NET "ROT_A"

LOC = "K18" | IOSTANDARD = LVTTL | PULLUP

;

NET "ROT_B"

LOC = "G18"

|

IOSTANDARD = LVTTL | PULLUP

;

NET "ROT_CENTER" LOC = "V16"

|

IOSTANDARD = LVTTL | PULLDOWN ;

UG257_03_060206

Figure 2-9: UCF Constraints for Rotary Push-Button Switch

Discrete LEDs

Locations and Labels

The MicroBlaze Development Kit board has eight individual surface-mount LEDs located above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED.

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Spartan-3E

Development Board

LED7

 

LED0

 

UG257_02_10_061306

Figure 2-10: Eight Discrete LEDs

Operation

Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390: current limiting resistor. To light an individual LED, drive the associated FPGA control signal High.

UCF Location Constraints

Figure 2-11 provides the UCF constraints for the four push-button switches, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.

NET "LED<7>" LOC = "A8" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<6>" LOC = "G9" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<5>" LOC = "A7" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<4>" LOC = "D13"

| IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "LED<3>" LOC = "E6" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8

;

NET "LED<2>" LOC = "D6" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8

;

NET "LED<1>" LOC = "C3" |

IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8

;

NET "LED<0>" LOC = "D4” |

IOSTANDARD = SSTL2_I ;

 

UG257_02_11_062106

Figure 2-11: UCF Constraints for Eight Discrete LEDs

Related Resources

xRotary Encoder Interface for Spartan-3E Starter Kit (Reference Design) http://www.xilinx.com/s3estarter http://www.xilinx.com/sp3e1600E

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Chapter 3

Clock Sources

Overview

As shown in Figure 3-1, the MicroBlaze Development Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo.

x The board includes an on-board 50 MHz clock oscillator.

x The user clock socket is populated with a 66 MHz oscillator

xClocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector.

x Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket

.

8-Pin DIP Oscillator Socket CLK_AUX:[B8]

Bank 0, Oscillator Voltage (Controlled by Jumper JP9)

Spartan-3E

Development Board

On-Board 50 MHz Oscillator

 

CLK_50MHz:[C9]

 

SMA Connector

UG257_03_01_061306

 

Figure 3-1: Available Clock Inputs

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Clock Connections

Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM.

Table 3-1: Clock Inputs and Associated Global Buffers and DCMs

Clock Input

FPGA Pin

Global Buffer

Associated DCM

 

 

 

 

CLK_50MHZ

C9

GCLK10

DCM_X0Y1

 

 

 

 

CLK_AUX

B8

GCLK8

DCM_X0Y1

 

 

 

 

CLK_SMA

A10

GCLK7

DCM_X1Y1

 

 

 

 

Voltage Control

The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9. Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when jumper JP9 is set for 2.5V.

50 MHz On-Board Oscillator

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator is accurate to ±2500 Hz or ±50 ppm.

Auxiliary Clock Oscillator Socket

The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this socket if the FPGA application requires a frequency other than 50 MHz. This socket is populated with a 66 MHz oscillator. This clock input is used for some of the reference designs provided with the board. Alternatively, use the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.

SMA Clock Input or Output Connector

To provide a clock from an external source, connect the input clock signal to the SMA connector. The FPGA can also generate a single-ended clock output or other high-speed signal on the SMA clock connector for an external device.

UCF Constraints

The clock input sources require two different types of constraints. The location constraints define the I/O pin assignments and I/O standards. The period constraints define the clock period—and consequently the clock frequency—and the duty cycle of the incoming clock signal.

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Related Resources

Location

Figure 3-2 provides the UCF constraints for the three clock input sources, including the I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.

NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;

NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;

NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;

UG257_03_02_061306

Figure 3-2: UCF Location Constraints for Clock Sources

Clock Period Constraints

The Xilinx ISE development software uses timing-driven logic placement and routing. Set the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3 for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to 60%.

# Define clock period for 50 MHz oscillator NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;

UG257_03_03_060206

Figure 3-3: UCF Clock PERIOD Constraint

Related Resources

xEpson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator) http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/ prog_oscillators/go/Resources/TestC2/SG8002JF

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Chapter 4

FPGA Configuration Options

The MicroBlaze Development Kit board supports a variety of FPGA configuration options:

xDownload FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. SPI serial Flash and StrataFlash programming are performed separately.

xProgram the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode.

xProgram the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode.

xProgram the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI Down configuration modes. Further, an FPGA application can dynamically load two different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the Spartan-3E data sheet (DS312) for additional details on the MultiBoot feature.

Figure 4-1 indicates the position of the USB download/programming interface and the onboard non-volatile memories that potentially store FPGA configuration images. Figure 4-2 provides additional details on configuration options.

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16 Mbit ST Micro SPI Serial Flash

Configuration Options

PROG_B button, Platform

Uses Peripheral Interface (SPI) Mode

Flash PROM, mode pins

 

 

 

 

 

 

 

 

USB-based Download

128 Mbit Intel StrataFlash

Parallel NOR Flash Memory

and Debug Port

Byte Peripheral Interface (BPI) mode

Uses standard USB cable

UG257_04_01_061306

 

Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options

 

 

 

Configuration Mode Jumper Settings (Header J30)

Spartan-3E

DONE Pin LED

Lights up when FPGA successfully configured

Development Board

 

 

 

 

 

 

 

 

 

4 Mbit Xilinx Platform Flash PROM

Configuration storage for Master Serial mode (one XC04S on front and one on the back of the board”

64 Macrocell Xilinx XC2C64A CoolRunner CPLD Controller upper address lines in BPI mode and Platform Flash chip select (User programmable)

 

PROG_B Push Button Switch

 

 

Press and release to restart configuration

UG257_04_02_061306

 

Figure 4-2: Detailed Configuration Options

 

 

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Configuration Mode Jumpers

The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed.

The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process.

The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.

The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is userprogrammable.

Configuration Mode Jumpers

As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual jumpers to select the FPGA’s configuration mode and associated configuration memory source.

Table 4-1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings

(Header J30 in Figure 4-2)

Configuration

Mode Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode

M2:M1:M0

FPGA Configuration Image Source

Jumper Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master Serial

000

Platform Flash PROM

M0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPI

001

SPI Serial Flash PROM starting at

M0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(see

 

address 0

M1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chapter 12,

 

 

M2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“SPI Serial

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J30

 

Flash”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BPI Up

010

StrataFlash parallel Flash PROM,

M0

 

 

 

 

 

 

 

 

 

 

(see

 

starting at address 0 and

 

 

 

 

 

 

 

 

M1

 

 

 

 

 

 

 

 

 

 

incrementing through address

 

 

 

 

 

 

 

 

Chapter 11,

 

 

 

 

 

 

 

M2

 

 

 

 

 

 

 

 

 

 

“Intel

 

space. The CPLD controls address

 

 

 

 

 

 

 

 

lines A[24:20] during BPI

 

 

 

 

 

 

 

 

 

 

 

 

 

StrataFlash

 

 

 

 

 

 

J30

 

configuration.

 

 

 

 

 

Parallel NOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROM”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 4-1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings

(Header J30 in Figure 4-2)

Configuration

Mode Pins

 

 

 

 

 

 

 

 

Mode

M2:M1:M0

FPGA Configuration Image Source

Jumper Settings

 

 

 

 

 

 

 

 

 

 

BPI Down

011

StrataFlash parallel Flash PROM,

M0

 

 

 

 

 

(see

 

starting at address 0x1FF_FFFF and

 

 

 

 

 

 

M1

 

 

 

 

 

 

decrementing through address

 

 

 

 

 

Chapter 11,

 

 

 

 

 

 

 

M2

 

 

 

 

 

 

“Intel

 

space. The CPLD controls address

 

 

 

 

 

 

 

lines A[24:20] during BPI

 

 

 

 

 

 

 

StrataFlash

 

 

 

J30

 

configuration.

 

 

Parallel NOR

 

 

 

 

 

 

 

 

Flash

 

 

 

 

 

 

 

 

 

PROM”)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG

101

Downloaded from host via USB-

M0

 

 

 

 

 

 

 

JTAG port

 

 

 

 

 

 

M1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J30

 

 

 

 

 

 

 

 

 

 

PROG Push Button

The PROG push button, shown in Figure 4-2, page 24, forces the FPGA to reconfigure from the selected configuration memory source. Press and release this button to restart the FPGA configuration process at any time.

DONE Pin LED

The DONE pin LED, shown in Figure 4-2, page 24, lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

Programming the FPGA, CPLD, or Platform Flash PROM via USB

As shown in Figure 4-1, page 24, the MicroBlaze Development Kit board includes embedded USB-based programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the parallel or serial Flash PROMs is not presently supported.

Connecting the USB Cable

The kit includes a standard USB Type A/Type B cable, similar to the one shown in

Figure 4-3. The actual cable color might vary from the picture.

USB Type B Connector

Connects to USB connector on Starter Kit

USB Type A Connector

Connects to USB connector on computer

UG257_04_03_061206

Figure 4-3: Standard USB Type A/Type B Cable

The wider and narrower Type A connector fits the USB connector at the back of the computer.

After installing the Xilinx software, connect the square Type B connector to the MicroBlaze Development Kit board, as shown in Figure 4-4. The USB connector is on the left side of the board, immediately next to the Ethernet connector. When the board is powered on, the Windows operating system should recognize and install the associated driver software.

UG257_04_04_061206

Figure 4-4: Connect the USB Type B Connector to the MicroBlaze Development Kit

Board Connector

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When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating a good connection.

Programming via iMPACT

After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable.

To begin programming, connect the USB cable to the starter kit board and apply power to the board. Then, double-click Configure Device (iMPACT) from within Project Navigator, as shown in Figure 4-5.

UG257_04_05_061206

Figure 4-5: Double-Click to Invoke iMPACT

If the board is connected properly, the iMPACT programming software automatically recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it. Right-click the FPGA and select Assign New Configuration File. Select the desired FPGA configuration file and click OK.

UG257_04_06_0612

Figure 4-6: Right-Click to Assign a Configuration File to the Spartan-3E FPGA

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in Figure 4-7. This message can be safely ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.

UG257 04-07 06906

Figure 4-7: iMPACT Issues a Warning if the StartUp Clock Was Not CCLK

To start programming the FPGA, right-click the FPGA and select Program. The iMPACT software reports status during programming process. Direct programming to the FPGA takes a few seconds to less than a minute, depending on the speed of the PC’s USB port and the iMPACT settings.

UG257_04_08_061206

Figure 4-8: Right-Click to Program the Spartan-3E FPGA

When the FPGA successfully programs, the iMPACT software indicates success, as shown in Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED (see Figure 4-2) lights up.

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UG257_09_061206

Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High

Programming Platform Flash PROM via USB

The on-board USB-JTAG circuitry also programs the two Xilinx XCF04S serial Platform Flash PROM. The steps provided in this section describe how to set up the PROM file and how to download it to the board to ultimately program the FPGA.

Generating the FPGA Configuration Bitstream File

Before generating the PROM file, create the FPGA bitstream file. The FPGA provides an output clock, CCLK, when loading itself from an external PROM. The FPGA’s internal CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz CCLK frequency.

Right-click Generator Programming File in the Processes pane, as shown in Figure 4-10. Left-click Properties.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

UG257_04_10_061206

Figure 4-10: Set Properties for Bitstream Generator

Click Configuration Options as shown in Figure 4-11. Using the Configuration Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately

25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished.

UG257_04_11_061206

Figure 4-11: Set CCLK Configuration Rate under Configuration Options

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To regenerate the programming file, double-click Generate Programming File, as shown in Figure 4-12.

UG257_04_12_022706

Figure 4-12: Double-Click Generate Programming File

Generating the PROM File

After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 4-13.

UG257_04_13_061206

Figure 4-13: Double-Click Generate PROM, ACE, or JTAG File

After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

UG257_04_14_061206

Figure 4-14: Double-Click PROM File Formatter

Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name. Click Next > when finished.

UG257_04_15_061206

Figure 4-15: Choose the PROM Target Type, the, Data Format, and File Location

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The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s from the drop list, as shown in Figure 4-16. Click Add, then click Next >.

UG257_4-16_061206

Figure 4-16: Choose the XCF04S Platform Flash PROM

The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.

UG257_4-17_061206

Figure 4-17: Click Finish after Entering PROM Formatter Settings

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.

UG257_4-18_060906

Figure 4-18: Enter FPGA Configuration Bitstream File(s)

When PROM formatting is complete, the iMPACT software presents the present settings by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA bitstream stored in an XCF04S Platform Flash PROM.

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UG257_4-19_061206

Figure 4-19: PROM Formatting Completed

To generate the actual PROM file, click Operations Æ Generate File as shown in Figure 4-20.

UG257_4-20_061206

Figure 4-20: Click Operations Æ Generate File to Create the Formatted PROM File

The iMPACT software indicates that the PROM file was successfully created, as shown in Figure 4-21.

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

UG257 4 21 061206

Figure 4-21: PROM File Formatter Succeeded

Programming the Platform Flash PROM

To program the formatted PROM file into the Platform Flash PROM via the on-board USBJTAG circuitry, follow the steps outlined in this subsection.

Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on the Boundary Scan tab.

UG257_04_22_061206

Figure 4-22: Switch to Boundary Scan Mode

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Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File. Select a previously generated PROM format file and click OK.

UG257_4-23_060106

Figure 4-23: Assign the PROM File to the XCF04S Platform Flash PROM

To start programming the PROM, right-click the PROM icon and then click Program..

UG257_4-24_061

Figure 4-24: Program the XCF04S Platform Flash PROM

The programming software again prompts for the PROM type to be programmed. Select xcf04s and click OK, as shown in Figure 4-25.

 

UG257_04_25_061206

 

Figure 4-25: Select XCF04S Platform Flash PROM

 

 

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Programming the FPGA, CPLD, or Platform Flash PROM via USB

Before programming, choose the programming options available in Figure 4-26. Checking the Erase Before Programming option erases the Platform Flash PROM completely before programming, ensuring that no previous data lingers. The Verify option checks that the PROM was correctly programmed and matches the downloaded configuration bitstream. Both these options are recommended even though they increase overall programming time.

The Load FPGA option immediately forces the FPGA to reconfigure after programming the Platform Flash PROM. The FPGA’s configuration mode pins must be set for Master Serial mode, as defined in Table 4-1, page 25. Click OK when finished.

UG257_04_26_061206

Figure 4-26: PROM Programming Options

The iMPACT software indicates if programming was successful or not. If programming was successful and the Load FPGA option was left unchecked, push the PROG_B pushbutton switch shown in Figure 4-2, page 24 to force the FPGA to reconfigure from the newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE LED, also shown in Figure 4-2, lights up.

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Chapter 5

Character LCD Screen

Overview

The Spartan-3E MicroBlaze Development Kit board has been designed with a 16 pin female header connector. The Spartan-3E MicroBlaze Development board is shipped with a 2x16 LCD display attached, but any standard LCD display can be attached to this connector.

The Spartan-3E MicroBlaze Development Kit board prominently features a 2-line by 16character liquid crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface or 8 bit data interface in shown Figure 5-1.

Spartan-3E

 

 

LCD

FPGA

PSWT

 

Header (J13)

 

 

1

 

GND

 

 

 

2

 

LCD_RW

 

(L17)

 

3

LCD_D / i

 

(L18)

 

4

LCD_RET

 

(E3)

 

5

LCD_E

 

(M18)

 

6

SF_D8

 

(R15)

 

7

SF_D9

 

 

 

(R16)

 

8

SF_D10

 

 

 

(P17)

 

9

SF_D11

 

(M15)

 

10

SF_D12

 

(M16)

 

11

SF_D13

 

(P6)

 

12

SF_D14

 

(R8)

 

13

SF_D15

 

(T8)

 

14

LCD_CS1

 

(P3)

 

15

LCD_CS2

 

(P4)

 

16

 

 

 

 

 

Intel StrataFlash

 

 

1

D[15:8]

 

SF_CEO

CE0

 

 

 

 

 

UG257_05_01_062106

Figure 5-1: Character LCD Interface

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Once mastered, the LCD is a practical way to display a variety of information using standard ASCII and custom characters. However, these displays are not fast. Scrolling the display at half-second intervals tests the practical limit for clarity. Compared with the

50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently controls display timing plus the actual content of the display.

Character LCD Interface Signals

Table 5-1 shows the interface character LCD interface signals.

Table 5-1: Character LCD Interface

Signal Name

FPGA Pin

 

Function

 

 

 

 

SF_D<15>

T8

Data bit DB7

 

 

 

 

 

SF_D<14>

R8

Data bit DB6

 

 

 

 

 

SF_D<13>

P6

Data bit DB5

 

 

 

 

 

SF_D<12>

M16

Data bit DB4

Shared with StrataFlash pins

 

 

 

SF_D<11>

M15

Data bit DB3

SF_D<15:8>

 

 

 

 

 

SF_D<10>

P17

Data bit DB2

 

 

 

 

 

SF_D<9>

R16

Data bit DB1

 

 

 

 

 

SF_D<8>

R15

Data bit DB0

 

 

 

 

 

LCD_E

M18

Read/Write Enable Pulse

 

 

0: Disabled

 

 

 

1: Read/Write operation enabled

 

 

 

 

LCD_RS

L18

Register Select

 

 

 

0: Instruction register during write operations. Busy

 

 

Flash during read operations

 

 

1: Data for read or write operations

 

 

 

 

LCD_RW

L17

Read/Write Control

 

 

 

0: WRITE, LCD accepts data

 

 

1: READ, LCD presents data

 

 

 

 

LCD_RET

E3

 

 

 

 

 

 

LCD_CS1

P3

 

 

 

 

 

 

LCD_CS2

P4

 

 

 

 

 

 

Voltage Compatibility

The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements.

The 390: series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a writeonly peripheral and never read from from the display.

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Interaction with Intel StrataFlash

Interaction with Intel StrataFlash

As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the application usage in the design. When the StrataFlash memory is disabled (SF_CE0 = High), then the FPGA application has full read/write access to the LCD. Conversely, when LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full read/write access to the StrataFlash memory

Table 5-2: LCD/StrataFlash Control Interaction

SF_CE0

SF_BYTE

LCD_RW

Operation

 

 

 

 

1

X

X

StrataFlash disabled. Full read/write access to LCD.

 

 

 

 

X

X

0

LCD write access only. Full access to StrataFlash.

 

 

 

 

X

0

X

StrataFlash in byte-wide (x8) mode. Upper address lines

 

 

 

are not used. Full access to both LCD and StrataFlash.

 

 

 

 

Notes:

1. ‘X’ indicates a don’t care, can be either 0 or 1.

If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA application has full simultaneous read/write access to both the LCD and the StrataFlash memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data lines.

UCF Location Constraints

Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin assignment and the I/O standard used.

# ==== Character LCD (LCD) ====

NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_DI" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ;

NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ;

NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;

# LCD data connections are shared with StrataFlash connections SF_D<15:8> NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

UG257_05_02_061306

Figure 5-2: UCF Location Constraints for the Character LCD

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LCD Controller

The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices.

x Samsung S6A0069X or KS0066U x Hitachi HD44780

x SMOS SED1278

Memory Map

The controller has three internal memory regions, each with a specific purpose. The display must be initialized before accessing any of these memory regions.

DD RAM

The Display Data RAM (DD RAM) stores the character code to be displayed on the screen. Most applications interact primarily with DD RAM. The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG ROM character set or in the user-defined CG RAM character set.

Figure 5-3shows the default address for the 32 character locations on the display. The upper line of characters is stored between addresses 0x00 and 0x0F. The second line of characters is stored between addresses 0x40 and 0x4F.

 

 

 

 

Character Display Addresses

 

 

 

 

Undisplayed

 

 

 

 

 

 

 

 

Addresses

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

. . . 27

2

40

41

42

43

44

45

46

47

48

49

4A

4B

 

4C

4D

4E

4F

50

. . . 67

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

. . . 40

 

1 2 3 4 5 6 7 8 9 10

11

12

 

13

14

15

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG257_05_03_061206

Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting)

Physically, there are 80 total character locations in DD RAM with 40 characters available per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations can also store characters that can only displayed using controller’s display shifting functions.

The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM. Write DD RAM data using the Write Data to CG RAM or DD RAM command, and read DD RAM using the Read Data from CG RAM or DD RAM command.

The DD RAM address counter either remains constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command.

CG ROM

The Character Generator ROM (CG ROM) contains the font bitmap for each of the predefined characters that the LCD screen can display, shown in Figure 5-4. The character code stored in DD RAM for each character location subsequently references a position with the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101”

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LCD Controller

binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the character ‘S’ appears on the screen.

English/Roman characters are stored in CG ROM at their equivalent ASCII code address.

DB7

DB6

DB5

DB4

Lower Data Nibble

DB0

DB1

DB2

DB3

Figure 5-4:

Upper Data Nibble

UG257_05_04_061206

LCD Character Set

The character ROM contains the ASCII English character set and Japanese kana characters.

The controller also provides for eight custom character bitmaps, stored in CG RAM. These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location.

CG RAM

The Character Generator RAM (CG RAM) provides space to create eight custom character bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in Figure 5-5.

The Set CG RAM Address command initializes the address counter before reading or writing to CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM command, and read CG RAM using the Read Data from CG RAM or DD RAM command.

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The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command.

Figure 5-5 provides an example, creating a special checkerboard character. The custom character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03. To write the custom character, the CG RAM address is first initialized using the Set CG RAM Address command. The upper three address bits point to the custom character location. The lower three address bits point to the row address for the character bitmap. The Write Data to CG RAM or DD RAM command is used to write each character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the lower five data bits are used; the upper three data bits are don’t care positions. The eighth row of bitmap data is usually left as all zeros to accommodate the cursor.

 

 

 

 

 

 

Upper Nibble

Lower Nibble

 

 

 

 

 

 

Write Data to CG RAM or DD RAM

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Character

 

Row

 

Don’t Care

Character Bitmap

Addresses

Addresses

 

 

 

 

 

 

 

 

0

1

1

0

0

0

0

 

0

 

0

0

1

1

0

0

1

 

0

 

0

 

0

1

1

0

1

0

0

 

0

 

0

0

1

1

0

1

1

 

0

 

0

 

0

1

1

1

0

0

0

 

0

 

0

0

1

1

1

0

1

 

0

 

0

 

0

1

1

1

1

0

0

 

0

 

0

0

1

1

1

1

1

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

UG257_05_05_061406

Figure 5-5: Example Custom Checkerboard Character with Character Code 0x03

Command Set

Table 5-3 summarizes the available LCD controller commands and bit definitions. Because the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles. The upper nibble is transferred first, followed by the lower nibble.

Table 5-3: LCD Character Display Command Set

 

 

 

LCD RS

LCD RW

 

Upper Nibble

 

 

Lower Nibble

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DB7

 

DB6

DB5

 

DB4

DB3

 

DB2

DB1

 

DB0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clear Display

 

0

0

0

 

0

0

 

0

0

 

0

0

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Return Cursor Home

 

0

0

0

 

0

0

 

0

0

 

0

1

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Entry Mode Set

 

0

0

0

 

0

0

 

0

0

 

1

I/D

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Display On/Off

 

0

0

0

 

0

0

 

0

1

 

D

C

 

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cursor and Display Shift

 

0

0

0

 

0

0

 

1

S/C

 

R/L

-

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function Set

 

0

0

0

 

0

1

 

0

1

 

0

-

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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LCD Controller

Table 5-3: LCD Character Display Command Set (Continued)

 

LCD RS

LCD RW

 

Upper Nibble

 

 

Lower Nibble

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

DB7

 

DB6

DB5

 

DB4

DB3

 

DB2

DB1

 

DB0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set CG RAM Address

0

0

0

 

1

A5

 

A4

A3

 

A2

A1

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set DD RAM Address

0

0

1

 

A6

A5

 

A4

A3

 

A2

A1

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Busy Flag and

0

1

BF

 

A6

A5

 

A4

A3

 

A2

A1

 

A0

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Data to CG RAM or

1

0

D7

 

D6

D5

 

D4

D3

 

D2

D1

 

D0

DD RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Data from CG RAM

1

1

D7

 

D6

D5

 

D4

D3

 

D2

D1

 

D0

or DD RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disabled

If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.

Clear Display

Clear the display and return the cursor to the home position, the top-left corner.

This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode Set command.

Execution Time: 82 Ps – 1.64 ms

Return Cursor Home

Return the cursor to the home position, the top-left corner. DD RAM contents are unaffected. Also returns the display being shifted to the original position, shown in Figure 5-3.

The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its original status if it was shifted. The cursor or blink move to the top-left character location.

Execution Time: 40 Ps – 1.6 ms

Entry Mode Set

Sets the cursor move direction and specifies whether or not to shift the display.

These operations are performed during data reads and writes.

Execution Time: 40 Ps

Bit DB1: (I/D) Increment/Decrement

0 Auto-decrement address counter. Cursor/blink moves to left.

1 Auto-increment address counter. Cursor/blink moves to right.

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This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command. The cursor or blink position moves accordingly.

Bit DB0: (S) Shift

0Shifting disabled

1During a DD RAM write operation, shift the entire display value in the direction controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant and the display moves.

Display On/Off

Display is turned on or off, controlling all characters, cursor and cursor position character (underscore) blink.

Execution Time: 40 Ps

Bit DB2: (D) Display On/Off

0 No characters displayed. However, data stored in DD RAM is retained

1 Display characters stored in DD RAM

Bit DB1: (C) Cursor On/Off

The cursor uses the five dots on the bottom line of the character. The cursor appears as a line under the displayed character.

0No cursor

1Display cursor

Bit DB0: (B) Cursor Blink On/Off

0No cursor blinking

1Cursor blinks on and off approximately every half second

Cursor and Display Shift

Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor position or display to the right or left without writing or reading display data.

This function positions the cursor in order to modify an individual character, or to scroll the display window left or right to reveal additional data stored in the DD RAM, beyond the 16th character on a line. The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line. The first and second line displays shift at the same time.

When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line.

Execution Time: 40 Ps

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