Xilinx 1000BASE-X User Manual

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LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

User Guide

UG155 March 24, 2008

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Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.

THE SPECIFICATION IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRDPARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICATION, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE SPECIFICATION, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE SPECIFICATION. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE SPECIFICATION TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Specification is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Specification in such High-Risk Applications is fully at your risk.

© 2004-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

Doc

Revision

Version

 

 

 

 

 

09/30/04

1.0

Initial Xilinx release.

 

 

 

04/28/05

2.0

Updated to Xilinx tools 7.1i SP2, support for Virtex-4 Rocket IO.

 

 

 

01/18/06

3.0

Updated to Xilinx tools 8.1i SP1 for 7.0 release, added new chapter for dynamic switching.

 

 

 

07/13/06

4.0

Updated to core version 7.1; Xilinx tools 8.2i.

 

 

 

10/23/06

5.0

Updated to core version 8.0, support for Virtex-5 LXT and Spartan-3A families.

 

 

 

02/15/07

6.0

Updated to core version 8.1, Xilinx tools 9.1i.

 

 

 

08/08/07

7.0

Updated to core version 9.0, Xilinx tools 9.2i.

 

 

 

03/24/08

8.0

Updated to core version 9.1, Xilinx tools 10.1.

 

 

 

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Table of Contents

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Preface: About This Guide

Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 1: Introduction

About the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Designs Using RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Related Xilinx Ethernet Products and Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Ethernet 1000BASE-X PCS/PMA or SGMII Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 2: Core Architecture

System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver . . . . . . . 23

Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface . . . . . . . . . . . . . . . 25

Core Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Client Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Physical Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 3: Generating and Customizing the Core

GUI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Select Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SGMII/Dynamic Standard Switching Elastic Buffer Options . . . . . . . . . . . . . . . . . . . . 41

RocketIO Tile Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Parameter Values in the XCO File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 4: Designing with the Core

Design Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Generate the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Examine the Example Design Provided with the Core . . . . . . . . . . . . . . . . . . . . . . . . . 50

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Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core

in Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 5: Using the Client-side GMII Data Path

Designing with the Client-side GMII for the 1000BASE-X Standard. . . . . . . . . . . . 53

GMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 GMII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 status_vector[4:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Using the Virtex-II Pro RocketIO Transceiver CRC Functionality . . . . . . . . . . . . . . . . 57

Designing with Client-side GMII for the SGMII Standard. . . . . . . . . . . . . . . . . . . . . . 59

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 GMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 GMII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Using the GMII as an Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Implementing External GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 GMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 6: The Ten-Bit Interface

Ten-Bit-Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Receiver Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clock Sharing across Multiple Cores with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 7: 1000BASE-X with RocketIO Transceivers

RocketIO Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Clock Sharing Across Multiple Cores with RocketIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

Receiver Elastic Buffer Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Selecting the Buffer Implementation from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 The Requirement for the FPGA Fabric Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . 96 The RocketIO Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

RocketIO Logic using the RocketIO Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 RocketIO Logic with the Fabric Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Virtex-4 Devices for SGMII or Dynamic Standards Switching . . . . . . . . . . . . . . . . . . 101 Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching . . . . . . . 103 Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching . . . . . . . . . . . . . . 105

Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer . . . . . . . . . 107

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Chapter 9: Configuration and Status

MDIO Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

MDIO Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 MDIO Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 MDIO Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Connecting the MDIO to an Internally Integrated STA . . . . . . . . . . . . . . . . . . . . . . . . 118 Connecting the MDIO to an External STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

1000BASE-X Standard Using the Optional Auto-Negotiation . . . . . . . . . . . . . . . . . . 119 1000BASE-X Standard Without the Optional Auto-Negotiation . . . . . . . . . . . . . . . . 129 SGMII Standard Using the Optional Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . 135 SGMII Standard without the Optional Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . 145 Both 1000BASE-X and SGMII Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Optional Configuration Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Chapter 10: Auto-Negotiation

Overview of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

1000BASE-X Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Setting the Configurable Link Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

1000BASE-X Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Simulating Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Using the Auto-Negotiation Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards

Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Operation of the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Selecting the Power-On / Reset Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Switching the Standard Using MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Auto-Negotiation State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Setting the Auto-Negotiation Link Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Chapter 12: Constraining the Core

Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Device, Package, and Speedgrade Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 I/O Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . 161 Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Virtex-4 RocketIO MGTs for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . . . . . 164 Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints 166 Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . 166 Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . 167

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Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Ten-Bit Interface Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Constraints When Implementing an External GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Understanding Timing Reports for Setup/Hold Timing . . . . . . . . . . . . . . . . . . . . . . 176

Chapter 13: Interfacing to Other Cores

Integrating with the 1-Gigabit Ethernet MAC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI . . . . . . . . 179 Integration of the 1-Gigabit Ethernet MAC Using a RocketIO Transceiver . . . . . . . 181 Integration of the 1-Gigabit Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Integrating with the Tri-Mode Ethernet MAC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Integration of the Tri-Mode Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Integration of the Tri-Mode Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality using RocketIO Transceivers . . . . . . . . . . 188

Chapter 14: Special Design Considerations

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Startup Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Core with the TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Core with RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Chapter 15: Implementing the Design

Pre-implementation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Using the Simulation Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XST - VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XST - Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Generating the Xilinx Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Placing and Routing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Generating a Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Post-Implementation Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Generating a Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Using the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Other Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Appendix A: Core Verification, Compliance, and Interoperability

Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

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Appendix B: Core Latency

Core Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Latency for 1000BASE-X PCS with TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver . . . . . . . . . . 208 Latency for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Appendix C: Calculating the DCM Fixed Phase Shift Value

Requirement for DCM Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Finding the Ideal Phase Shift Value for Your System. . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Appendix D: 1000BASE-X State Machines

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Start of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

The Even Transmission Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Reception of the Even Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

The Odd Transmission Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Reception of the Odd Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Preamble Shrinkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

End of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

The Even Transmission case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Reception of the Even Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

The Odd Transmission Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Reception of the Odd Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Appendix E: Rx Elastic Buffer Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Rx Elastic Buffers: Depths and Maximum Frame Sizes . . . . . . . . . . . . . . . . . . . . . . . . . 219

RocketIO Rx Elastic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SGMII Fabric Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TBI Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Maximum Frame Sizes for Sustained Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . 226

Jumbo Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Appendix F: Debugging Guide

General Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Problems with the MDIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Problems with Data Reception or Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Problems with Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Problems in Obtaining a Link (Auto-Negotiation Disabled) . . . . . . . . . . . . . . . . . . . 228

Problems with a High Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Symptoms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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Schedule of Figures

Chapter 2: Core Architecture

Figure 2-1: Functional Block Diagram Using RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 2-2: Functional Block Diagram with a Ten-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 2-3: Component Pinout Using RocketIO Transceiver

with PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2-4: Component Pinout Using RocketIO Transceiver

without PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 2-5: Component Pinout Using the Ten-Bit Interface

with PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 2-6: Component Pinout Using Ten-Bit Interface

without PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 2-7: Component Pinout with the Dynamic Switching Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 3: Generating and Customizing the Core

Figure 3-1: Core Customization Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 3-2: 1000BASE-X Standard Options Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 3-3: SGMII/Dynamic Standard Switching Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 3-4: RocketIO Tile Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 4: Designing with the Core

Figure 4-1: 1000BASE-X Standard Using a RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 4-2: Example Design 1000BASE-X Standard Using TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 4-3: Example Design Performing the SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 4-4: Example Design Performing the SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Chapter 5: Using the Client-side GMII Data Path

Figure 5-1: GMII Normal Frame Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 5-2: GMII Error Propagation Within a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 5-3: GMII Normal Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 5-4: GMII Normal Frame Reception with Carrier Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 5-5: GMII Frame Reception with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 5-6: False Carrier Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 5-7: status_vector[4:2] timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 5-8: GMII Frame Transmission with RocketIO Transceiver CRC Logic Enabled . . . . . . . . 58 Figure 5-9: GMII Frame Reception with the RocketIO Transceiver CRC Logic Enabled . . . . . . . . 58

Figure 5-10: GMII Frame Transmission at 1 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 5-11: GMII Data Transmission at 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 5-12: GMII Frame Reception at 1 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 5-13: GMII Data Reception at 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 5-14: GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 5-15: External GMII Transmitter Logic for Spartan-3, Spartan-3E and

Spartan-3A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 5-16: External GMII Transmitter Logic for Virtex-4 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 5-17: External GMII Transmitter Logic for Virtex-5 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 5-18: External GMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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Chapter 6: The Ten-Bit Interface

Figure 6-1: Ten-Bit Interface Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 6-2: Ten-Bit-Interface Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices. . . . . . . . . . . . . 72 Figure 6-4: Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design) . . . . . . . . . . . . . . 73 Figure 6-5: Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices . . . . . . . . . . . . . . . . . . . 74 Figure 6-6: Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design) . . . . . . . . . . . . . . 75 Figure 6-7: Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . . 76 Figure 6-8: Clock Management, Multiple Core Instances with Ten-Bit Interface . . . . . . . . . . . . . . . 77

Chapter 7: 1000BASE-X with RocketIO Transceivers

Figure 7-1: 1000BASE-X Connection to a Virtex-II Pro MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 7-3: 1000BASE-X Connection to Virtex-5 GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 7-4: 1000BASE-X Connection to Virtex-5 GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 7-5: Clock Management: Two Core Instances, Virtex-II Pro

MGTs for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X . . . . . . . . . . . . . 89 Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

Figure 8-1: SGMII Implementation using Separate Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 8-2: SGMII Implementation using Shared Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver. . . . . . . . . . . . . . . . . . . . . . 100

Figure 8-4: SGMII Connection to a Virtex-4 MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 8-5: SGMII Connection to a Virtex-5 RocketIO GTP Transceiver . . . . . . . . . . . . . . . . . . . . . 104 Figure 8-6: SGMII Connection to a Virtex-5 RocketIO GTX Transceiver . . . . . . . . . . . . . . . . . . . . . 106 Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 8-8: Clock Management with Multiple Core Instances with Virtex-4 MGTs for SGMII . 110 Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 GTP

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 GTX

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Chapter 9: Configuration and Status

Figure 9-1: A Typical MDIO-managed System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 9-2: MDIO Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 9-3: MDIO Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 9-4: Creating an External MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 9-5: Dynamic Switching (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Chapter 10: Auto-Negotiation

 

Figure 10-1: 1000BASE-X Auto-Negotiation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

153

Figure 10-2: SGMII Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards

Figure 11-1: Typical Application for Dynamic Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

157

Chapter 12: Constraining the Core

Figure 12-1: Local Clock Place and Route for Top MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 12-2: Input TBI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 12-3: Input GMII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 12-4: Timing Report Setup/Hold Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Chapter 13: Interfacing to Other Cores

Figure 13-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI . . . . . . . . 180 Figure 13-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-II Pro MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 13-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-4 MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 13-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-5 GTP Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 13-5: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-5 GTX Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 13-6: Tri-Speed Ethernet MAC Extended to use an SGMII with TBI . . . . . . . . . . . . . . . . . . 187 Figure 13-7: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-II Pro . . . . . . . . . . . . 189 Figure 13-8: Tri-Speed Ethernet MAC Extended to Use an SGMII in Virtex-4 . . . . . . . . . . . . . . . . 191 Figure 13-9: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT. . . . . . . . 193 Figure 13-10: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 FXT . . . . . . . . . . . 195

Chapter 14: Special Design Considerations

Figure 14-1: Loopback Implementation Using the TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 14-2: Loopback Implementation When Using the Core with RocketIO Transceivers . . . . 199

Appendix D: 1000BASE-X State Machines

Figure D-1: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 212 Figure D-2: 1000BASE-X Reception State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . 213 Figure D-3: 1000BASE-X Transmit State Machine Operation (Odd Case) . . . . . . . . . . . . . . . . . . . . 214 Figure D-4: 1000BASE-X Reception State Machine Operation (Odd Case). . . . . . . . . . . . . . . . . . . . 214 Figure D-5: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 215 Figure D-6: 1000BASE-X Reception State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . 216 Figure D-7: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 217 Figure D-8: 1000BASE-X Reception State Machine Operation (Odd Case). . . . . . . . . . . . . . . . . . . . 217

Appendix E: Rx Elastic Buffer Specifications

Figure E-1: Elastic Buffer Sizes for all RocketIO Transceiver Families . . . . . . . . . . . . . . . . . . . . . . . 220 Figure E-2: Elastic Buffer Size for all RocketIO families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure E-3: TBI Elastic Buffer Size for All Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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Schedule of Tables

Chapter 2: Core Architecture

Table 2-1: GMII Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 2-2: Other Common Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 2-3: Optional MDIO Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 2-4: Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 2-5: Optional Auto-Negotiation Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . 35

Table 2-6: Optional Dynamic Standard Switching Signals . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 2-7: Optional RocketIO Transceiver Interface Pinout . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 2-8: Optional TBI Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3: Generating and Customizing the Core

Table 3-1: XCO File Values and Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 4: Designing with the Core

 

Table 4-1: Degree of Difficulty for Various Implementations . . . . . . . . . . . . . . . . . . . . .

. 51

Chapter 9: Configuration and Status

 

Table 9-1: Abbreviations and Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

116

Table 9-2: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . .

119

Table 9-3: Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

Table 9-4: Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

122

Table 9-5: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

124

Table 9-6: Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . .

124

Table 9-7: Auto-Negotiation Link Partner Ability Base Register (Register 5) . . . . . . . .

125

Table 9-8: Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . .

126

Table 9-9: Auto-Negotiation Next Page Transmit (Register 7). . . . . . . . . . . . . . . . . . . . . .

127

Table 9-10: Auto-Negotiation Next Page Receive (Register 8) . . . . . . . . . . . . . . . . . . . . . .

128

Table 9-11: Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

128

Table 9-12: Vendor Specific Register: Auto-Negotiation Interrupt

 

Control Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

129

Table 9-13: MDIO Registers for 1000BASE-X without Auto-Negotiation. . . . . . . . . . . .

130

Table 9-14: Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

130

Table 9-15: Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

132

Table 9-16: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

133

Table 9-17: Extended Status (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

134

Table 9-18: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . .

135

Table 9-19: SGMII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

136

Table 9-20: SGMII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

137

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Table 9-21: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 139

Table 9-23: SGMII Auto-Negotiation Link Partner Ability Base (Register 5) . . . . . . . . 140

Table 9-24: SGMII Auto-Negotiation Expansion (Register 6) . . . . . . . . . . . . . . . . . . . . . . 141

Table 9-25: SGMII Auto-Negotiation Next Page Transmit (Register 7). . . . . . . . . . . . . . 141

Table 9-26: SGMII Auto-Negotiation Next Page Receive (Register 8) . . . . . . . . . . . . . . . 142

Table 9-27: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 9-28: SGMII Auto-Negotiation Interrupt Control (Register 16) . . . . . . . . . . . . . . . 144

Table 9-29: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . 145

Table 9-30: SGMII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 9-31: SGMII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 9-32: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 9-33: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 149

Table 9-34: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 9-35: Vendor-specific Register: Standard Selection Register (Register 17) . . . . . 151

Table 9-36: Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 12: Constraining the Core

Table 12-1: Input TBI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 12-2: Input GMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Appendix D: 1000BASE-X State Machines

Table D-1: Defined Ordered Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

211

Appendix E: Rx Elastic Buffer Specifications

Table E-1: Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers

(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table E-2: Maximum Frame Sizes: Fabric Rx Elastic Buffers

(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table E-3: Maximum Frame Size: (Sustained Frame Reception)

Capabilities of the Rx Elastic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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Preface

About This Guide

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

Guide Contents

This guide contains the following information.

Preface, “About This Guide” introduces the organization and purpose of this guide and defines the conventions used in this document.

Chapter 1, “Introduction” describes the core and related information, including recommended design experience, additional documentation resources, technical support, and submitting feedback to Xilinx.

Chapter 2, “Core Architecture” provides an overview of the core including all interfaces and major functional blocks.

Chapter 3, “Generating and Customizing the Core” describes the Graphical User Interface (GUI) options used to generate and customize the core.

Chapter 4, “Designing with the Core” provides general guidelines for creating designs with the core.

Chapter 5, “Using the Client-side GMII Data Path” provides general guidelines for creating designs using client side GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core.

Chapter 6, “The Ten-Bit Interface” provides general design guidelines when using the Ten-Bit Interface (TBI) as the Physical Side of the core.

Chapter 7, “1000BASE-X with RocketIO Transceivers” provides general design guidelines when using the 1000BASE-X standard with the RocketIO™ transceiver as the physical side of the core.

Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers” provides general design guidelines when using either the SGMII standard, or the Dynamic Switching option (between 1000BASE-X and SGMII standards). These options always use a RocketIO as the physical interface.

Chapter 9, “Configuration and Status” provides general guidelines for configuring and monitoring the core, including a detailed description of the management registers present in the core.

Chapter 10, “Auto-Negotiation” provides guidelines for Auto-Negotiation function of the core.

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Preface: About This Guide

Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards” provides general guidelines for using the core to perform dynamic standards switching between 1000BASE-X and SGMII.

Chapter 12, “Constraining the Core” defines the constraint requirements of the core.

Chapter 13, “Interfacing to Other Cores” describes additional design considerations associated with implementing the core with the 1-Gigabit Ethernet MAC and TriMode Ethernet MAC cores.

Chapter 14, “Special Design Considerations” describes additional design considerations associated with implementing the core.

Chapter 15, “Implementing the Design”describes how to simulate and implement your design containing the core.

Appendix A, “Core Verification, Compliance, and Interoperability” describes how the core was verified.

Appendix B, “Core Latency” defines the latency of the core.

Appendix C, “Calculating the DCM Fixed Phase Shift Value” instructs the user about how to calculate the system timing requirements when using DCMs with the core.

Appendix D, “1000BASE-X State Machines” serves as a reference for the basic operation of the 1000BASE-X IEEE 802.3 clause 36 transmitter and receiver state machines.

Appendix E, “Rx Elastic Buffer Specifications” describes the depth of the Rx Elastic Buffers which are available with the core. The size of the buffer is related to the maximum frame size which the core can accommodate.

Appendix F, “Debugging Guide” provides information for debugging the core within a system.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document.

Convention

Meaning or Use

Example

 

 

 

 

Messages, prompts, and

 

Courier font

program files that the system

speed grade: - 100

 

displays

 

 

 

 

Courier bold

Literal commands you enter in

ngdbuild design_name

 

a syntactical statement

 

 

 

 

 

References to other manuals

See the User Guide for details.

Italic font

 

 

 

If a wire is drawn so that it

 

 

 

Emphasis in text

overlaps the pin of a symbol,

 

 

the two nets are not connected.

 

 

 

Dark Shading

Items that are not supported

This feature is not supported

or reserved

 

 

 

 

 

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Convention

Meaning or Use

Example

 

 

 

 

An optional entry or

 

Square brackets [ ]

parameter. However, in bus

ngdbuild [option_name]

specifications, such as

design_name

 

 

bus[7:0], they are required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

must choose one or more

 

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

choices

 

 

 

 

 

Vertical ellipsis

 

IOB #1: Name = QOUT’

Repetitive material that has

IOB #2: Name = CLKIN’

.

.

.

been omitted

.

.

 

 

.

 

 

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

been omitted

loc1 loc2 ... locn;

 

 

 

 

The prefix ‘0x’ or the suffix ‘h

A read of address

 

0x00112975 returned

 

indicate hexadecimal notation

Notations

45524943h.

 

 

 

A ‘_n’ means the signal is

usr_teof_n is active low.

 

active low

 

 

 

 

 

Online Document

The following conventions are used in this document.

Convention

Meaning or Use

Example

 

 

 

 

Cross-reference link to a

See the section “Additional

 

Resources” for details.

Blue text

location in the current

See “Title Formats” in

 

document

 

Chapter 1 for details.

 

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to www.xilinx.com for the

latest speed files.

 

 

 

 

 

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Chapter 1

Introduction

The Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully verified solution that supports Verilog HDL and VHDL. In addition, the example design provided with the core supports both Verilog and VHDL.

This chapter introduces the Ethernet 1000BASE-X PCS/PMA or SGMII core and provides related information, including recommended design experience, additional resources, technical support, and methods for submitting feedback to Xilinx.

About the Core

The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the Ethernet 100BASE-X PCS/PMA product page. For information about system requirements and licensing options, see Chapter 2, “Licensing the Core,” in the Getting Started Guide.

Designs Using RocketIO Transceivers

RocketIO transceivers are defined by device family in the following way:

For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)

For Virtex-5 LXT and SXT devices, RocketIO GTP transceivers; Virtex-5 FXT devices, RocketIO GTX transceivers

Recommended Design Experience

Although the Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high-performance, pipelined FPGA designs using Xilinx implementation software and User Constraint Files (UCF) is recommended.

Contact your local Xilinx representative for a closer review and estimation for your specific requirements.

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Chapter 1: Introduction

Additional Core Resources

For detailed information and updates about the Ethernet 1000BASE-X PCS/PMA or

SGMII core, see the following documents, located on the Xilinx Ethernet 100BASE-X

PCS/PMA product page.

Ethernet 1000BASE-X PCS/PMA or SGMII Data Sheet

Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide

After generating the core, the following documents are available in the document directory:

Ethernet 1000BASE-X PCS/PMA or SGMII Release Notes

Ethernet 1000BASE-X PCS/PMA or SGMII User Guide

Related Xilinx Ethernet Products and Services

For information about all Xilinx Ethernet solutions, see www.xilinx.com/products/design_resources/conn_central/protocols/gigabit_ethernet. htm.

Specifications

IEEE 802.3

Serial-GMII Specification (CISCO SYSTEMS, ENG-46158)

Technical Support

To obtain technical support specific to the Ethernet 1000BASE-X PCS/PMA or SGMII core, visit www.support.xilinx.com/. Questions are routed to a team of engineers with expertise using the Ethernet 1000BASE-X PCS/PMA or SGMII core.

Xilinx provides technical support for use of this product as described in the Ethernet 1000BASE-X PCS/PMA or SGMII User Guide and the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the Ethernet 1000BASE-X PCS/PMA or SGMII core and the documentation supplied with the core.

Ethernet 1000BASE-X PCS/PMA or SGMII Core

For comments or suggestions about the core, please submit a WebCase from www.support.xilinx.com/. Be sure to include the following information:

Product name

Core version number

Explanation of your comments

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Document

For comments or suggestions about this document, please submit a WebCase from www.support.xilinx.com/. Be sure to include the following information:

Document title

Document number

Page number(s) to which your comments refer

Explanation of your comments

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Chapter 2

Core Architecture

This chapter describes the architecture of the Ethernet 1000BASE-X PCS/PMA or SGMII core, including all interfaces and major functional blocks.

System Overview

Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver

The Ethernet 1000BASE-X PCS/PMA or SGMII core provides the functionality to implement the 1000BASE-X PCS and PMA sub-layers or used to provide a GMII to SGMII bridge when used with a RocketIO transceiver. RocketIO transceivers are defined in the following way:

For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)

For Virtex-5 LXT and SXT FPGAs, RocketIO GTP transceivers; Virtex-5 FXT FPGA, RocketIO GTX transceiver

The core interfaces to a RocketIO transceiver, providing some of the PCS layer functionality such as 8B/10B encoding/decoding, the PMA SERDES, and clock recovery. Figure 2-1 illustrates the remaining PCS sublayer functionality, and also shows the major functional blocks of the core.

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Chapter 2: Core Architecture

 

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core

 

 

 

 

PCS Transmit Engine

 

 

 

GMII

GMII Block

Optional

RocketIO I/F Block

RocketIO Transeiver

To PMD

to MAC

Auto-Negotiation

Sublayer

 

 

 

 

 

 

 

PCS Receive Engine

 

 

 

 

 

and Synchronization

 

 

 

MDIO

 

Optional PCS

 

 

 

 

Management

 

 

 

Interface

 

 

 

 

 

 

 

 

Figure 2-1: Functional Block Diagram Using RocketIO Transceiver

GMII Block

A client-side GMII is provided with the core, which can be used as an internal interface for connection to an embedded Media Access Controller (MAC) or other custom logic. Alternatively, the GMII may be routed to device IOBs to provide an external (off chip) GMII.

PCS Transmit Engine

The PCS transmit engine converts the GMII data octets into a sequence of ordered sets by implementing the state diagrams of IEEE 802.3 (figures 36-5 and 36-6). See Appendix D, “1000BASE-X State Machines.”

PCS Receive Engine and Synchronization

The synchronization process implements the state diagram of IEEE 802.3 (figure 36-9). The PCS receive engine converts the sequence of ordered sets to GMII data octets by implementing the state diagrams of IEEE 802.3 (figures 36-7a and 36-7b). See Appendix D, “1000BASE-X State Machines.”

Optional Auto-Negotiation Block

IEEE 802.3 clause 37 describes the 1000BASE-X Auto-Negotiation function that allows a device to advertise the modes of operation that it supports to a device at the remote end of a link segment (link partner), and to detect corresponding operational modes that the link partner may be advertising.

Auto-Negotiation is controlled and monitored through the PCS Management Registers. See Chapter 10, “Auto-Negotiation.”

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System Overview

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Optional PCS Management Registers

Configuration and status of the core, including access to and from the optional AutoNegotiation function, uses the 1000BASE-X PCS Management Registers defined in IEEE 802.3 clause 37. These registers are accessed through the serial Management Data Input/Output Interface (MDIO), defined in IEEE 802.3 clause 22, as if it were an externally connected PHY.

The PCS Management Registers may be omitted from the core when the core is performing the 1000BASE-X standard. In this situation, configuration and status of the core is made possible with the use of an alternative configuration vector and a status signal.

When the core is performing the SGMII standard, the PCS Management Registers become mandatory and information in the registers takes on a different interpretation. For more information, see “Management Registers” in Chapter 9.

RocketIO Interface Block

The RocketIO Interface Block enables the core to connect to a Virtex-II Pro, Virtex-4, or Virtex-5 FPGA RocketIO transceiver.

Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface

The Ethernet 1000BASE-X PCS/PMA or SGMII core, when used with the Ten-Bit Interface (TBI), allows you to implement only the 1000BASE-X PCS sublayer.

 

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core

 

 

 

 

PCS Transmit Engine

8B/10B

 

 

 

 

 

Encoder

 

 

 

GMII

BlockGMII

Optional

 

BlockTBI

IOBs

TBI

 

 

 

 

to MAC

 

 

 

 

 

Atuo-negotiation

 

 

 

to PMA

 

 

 

 

 

 

 

 

 

 

 

 

Sublayer

 

 

PCS Receive Engine

8B/10B

RX

 

 

 

 

Elastic

 

 

 

 

and Synchronization

Decoder

 

 

 

 

Buffer

 

 

 

 

 

 

 

 

MDIO

Optional PCS

 

 

 

 

 

Management

 

 

 

 

 

Interface

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2-2:

Functional Block Diagram with a Ten-Bit Interface

 

The optional TBI can be used in place of the RocketIO transceiver to provide a parallel interface for connection to an external PMA SERDES device. In this implementation, additional logic blocks are required to replace some of the RocketIO transceiver functionality. These are shown in the surrounded by the dotted line box in Figure 2-2 and are described in the following sections. The other blocks are described previously in this document.

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Chapter 2: Core Architecture

8B/10B Encoder

8B10B encoding, as defined in IEEE 802.3 (Tables 36-1a to 36-1e and Table 36-2), is implemented in a block SelectRAM™, configured as ROM, and used as a large look-up table.

8B/10B Decoder

8B10B decoding, as defined in IEEE 802.3 (Table 36-1a to 36-1e and Table 36-2), is implemented in a block SelectRAM, configured as ROM, and used as a large look-up table.

Receiver Elastic Buffer

The Receiver Elastic Buffer enables the 10-bit parallel TBI data, received from the PMA sublayer synchronously to the TBI receiver clocks, to be transferred onto the cores internal 125 MHz clock domain. It is an asynchronous FIFO implemented in internal RAM. The Receiver Elastic Buffer attempts to maintain a constant occupancy by inserting or removing Idle sequences as necessary. This causes no corruption to the frames of data.

TBI Block

The core provides a TBI interface that should be routed to device IOBs to provide an offchip TBI.

Core Interfaces

All ports of the core are internal connections in FPGA fabric. An HDL example design (delivered with the core) connects the core, where appropriate, to a RocketIO transceiver, and/or add IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII and TBI. IOBs are added to the remaining unconnected ports to take the example design through the Xilinx implementation software.

All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores). This example design is provided in both VHDL and Verilog. For more information, see the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide.

Figure 2-3 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a RocketIO transceiver with the optional PCS Management Registers. The signals shown in the Auto-Negotiation box included only when the core includes the Auto-Negotiation

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functionality. For more information, see Chapter 3, “Generating and Customizing the Core.”

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset gtx_clk

Auto_Negotiation

an_interrupt link_timer_value[8:0]

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2 dcm_locked

rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata enablealign

signal_detect

status_vector[4:0]

Figure 2-3: Component Pinout Using RocketIO Transceiver with PCS Management Registers

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Chapter 2: Core Architecture

Figure 2-4 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using a RocketIO transceiver without the optional PCS Management Registers

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO Replacement

configuration_vector[3:0]

reset gtx_clk

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2 dcm_locked

rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata enablealign

signal_detect

status_vector[4:0]

Figure 2-4: Component Pinout Using RocketIO Transceiver without PCS Management Registers

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Figure 2-5 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when using the TBI with optional PCS Management Registers. The signals shown in the AutoNegotiation box are included only when the core includes the Auto-Negotiation functionality (see Chapter 3, “Generating and Customizing the Core”).

).

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset gtx_clk

Auto_Negotiation

an_interrupt link_timer_value[8:0]

Ten-Bit Interface (TBI)

tx_code_group[9:0]

loc_ref

ewrap en_cdet

rx_code_group0[9:0] rx_code_group1[9:0] pma_rx_clk0 pma_rx_clk1

signal_detect

status_vector[4:0]

Figure 2-5: Component Pinout Using the Ten-Bit Interface with PCS Management Registers

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Chapter 2: Core Architecture

Figure 2-6 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when using a TBI without the optional PCS Management Registers.

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO Replacement

configuration_vector[3:0]

reset gtx_clk

Ten-Bit Interface (TBI)

tx_code_group[9:0]

loc_ref

ewrap en_cdet

rx_code_group0[9:0] rx_code_group1[9:0] pma_rx_clk0 pma_rx_clk1

signal_detect

status_vector[4:0]

Figure 2-6: Component Pinout Using Ten-Bit Interface without PCS Management Registers

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Figure 2-7 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using the optional dynamic switching logic (between 1000BASE-X and SGMII standards). This mode is shown used with a RocketIO transceiver interface. For more information, see Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards.”

GMII gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

MDIO

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset gtx_clk

Auto_Negotiation an_interrupt

link_timer_basex[8:0] link_timer_sgmii[8:0] basex_or_sgmii

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2 dcm_locked

rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata enablealign

signal_detect

status_vector[4:0]

Figure 2-7: Component Pinout with the Dynamic Switching Logic

Client Side Interface

GMII Pinout

Table 2-1 describes the GMII-side interface signals of the core common to all parameterizations of the core. These are typically attached to an Ethernet MAC, either offchip or internally integrated. The HDL example design delivered with the core connects these signals to IOBs to provide a place-and-route example.

For more information, see “Designing with the Client-side GMII for the 1000BASE-X

Standard” in Chapter 5.

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Chapter 2: Core Architecture

Table 2-1: GMII Interface Signal Pinout

Signal

Direction

Description

 

 

 

gmii_txd[7:0]1

Input

GMII Transmit data from MAC.

gmii_tx_en1

Input

GMII Transmit control signal from MAC.

gmii_tx_er1

Input

GMII Transmit control signal from MAC.

gmii_rxd[7:0]2

Output

GMII Received data to MAC.

gmii_rx_dv2

Output

GMII Received control signal to MAC.

gmii_rx_er2

Output

GMII Received control signal to MAC.

gmii_isolate2

Output

IOB Tri-state control for GMII Isolation. Only of use

 

 

when implementing an External GMII as illustrated by

 

 

the example design HDL.

 

 

 

1.When the Transmitter Elastic Buffer is present these signals are synchronous to gmii_tx_clk. When the Transmitter Elastic Buffer is omitted, see Note 2.

2.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; gtx_clk when the core is used with TBI.

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Common Signal Pinout

Table 2-2 describes the remaining signals common to all parameterizations of the core.

Table 2-2: Other Common Signals

Signal

Direction

Description

 

 

 

reset

Input

Asynchronous reset for the entire core. Active High. Clock

 

 

domain is not applicable.

 

 

 

signal_detect

Input

Signal direct from PMD sublayer indicating the presence

 

 

of light detected at the optical receiver. If set to ’1,’

 

 

indicates that the optical receiver has detected light. If set

 

 

to ’0,’ this indicates the absence of light.

 

 

If unused this signal should be set to ’1’to enable correct

 

 

operation the core. Clock domain is not applicable.

 

 

 

status_vector[4:0]1

Output

Bit[0]: Link Status

 

 

Indicates the status of the link.

 

 

• When high, the link is valid: synchronization of the link

 

 

has been obtained and Auto-Negotiation (if present and

 

 

enabled) has successfully completed.

 

 

• When low, a valid link has not been established. Either

 

 

link synchronization has failed or Auto-Negotiation (if

 

 

present and enabled) has failed to complete.

 

 

• When auto-negotiation is enabled this signal is identical

 

 

to Status Register Bit 1.2: Link Status.

 

 

• When auto-negotiation is disabled this signal is identical

 

 

to status_vector Bit[1].

 

 

Bit[1]: Link Synchronization

 

 

Indicates the state of the synchronization state machine

 

 

(IEEE802.3 figure 36-9) which is based on the reception of

 

 

valid 8B10B code groups. This signal is similar to Bit[0]

 

 

(Link Status), but is NOT qualified with Auto-Negotiation.

 

 

• When high, link synchronization has been obtained and

 

 

in the synchronization state machine, sync_status =

 

 

OK.

 

 

• When low, synchronization has failed.

 

 

Bit[2]: RUDI(/C/)

 

 

The core is receiving /C/ ordered sets (Auto-Negotiation

 

 

Configuration sequences).

 

 

Bit[3]: RUDI(/I/)

 

 

The core is receiving /I/ ordered sets (Idles).

 

 

Bit[4]: RUDI(INVALID)

 

 

The core has received invalid data whilst receiving/C/ or

 

 

/I/ ordered set. See “status_vector[4:0] signals” in

 

 

Chapter 5 for more information.

 

 

 

1.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

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Chapter 2: Core Architecture

MDIO Management Interface Pinout (Optional)

Table 2-3 describes the optional MDIO interface signals of the core used to access the PCS Management Registers. These signals are typically connected to the MDIO port of a MAC device, either off-chip or to an internally integrated MAC core. For more information, see “Management Registers” in Chapter 9.

Table 2-3: Optional MDIO Interface Signal Pinout

Signal

Direction

Clock

Description

Domain

 

 

 

 

mdc

Input

N/A

Management clock (<= 2.5 MHz).

 

 

 

 

mdio__in1

Input

mdc

Input data signal for communication with

 

 

 

MDIO controller (for example, an Ethernet

 

 

 

MAC). Tie high if unused.

 

 

 

 

mdio_out1

Output

mdc

Output data signal for communication with

 

 

 

MDIO controller (for example, an Ethernet

 

 

 

MAC).

 

 

 

 

mdio_tri1

Output

mdc

Tri-state control for MDIO signals; ‘0’ signals

 

 

 

that the value on mdio_out should be asserted

 

 

 

onto the MDIO interface.

 

 

 

 

phyad[4:0]

Input

N/A

Physical Address of the PCS Management

 

 

 

register set. It is expected that this signal will be

 

 

 

tied off to a logical value.

 

 

 

 

1.These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC).

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Configuration Vector (Optional)

Table 2-4 shows the alternative to the optional MDIO Management Interface, the configuration vector. See “Optional Configuration Vector” in Chapter 9.

Table 2-4: Optional Configuration and Status Vectors

Signal

Direction

Description

 

 

 

configuration_vector[3:0]1

Input

Bit[0]: Reserved (currently unused)

 

 

Bit[1]: Loopback Control

 

 

• When the core with RocketIO transceiver is

 

 

used, the core is placed in internal loopback

 

 

mode.

 

 

• With the TBI version, Bit 1 is connected to

 

 

ewrap. When set to ‘1,’ this indicates to the

 

 

external PMA module to enter loopback mode.

 

 

Bit[2]: Power Down

 

 

• When the RocketIO transceiver is used (when

 

 

set to ‘1’), the MGT is placed in a low power

 

 

state. A reset must be applied to clear.

 

 

• With the TBI version this bit is unused.

 

 

Bit[3]: Isolate

 

 

When set to ‘1,’ the GMII should be electrically

 

 

isolated. When set to ‘0,’ normal operation is

 

 

enabled.

 

 

 

1.This signal is synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

Auto-Negotiation Signal Pinout

Table 2-5 describes the signals present when the optional Auto-Negotiation functionality is present. For more information, see Chapter 10, “Auto-Negotiation.”

Table 2-5: Optional Auto-Negotiation Interface Signal Pinout

Signal

Direction

Description

 

 

 

link_timer_value[8:0]1

Input

Used to configure the duration of the Auto-

 

 

Negotiation Link Timer period. The duration of this

 

 

timer is set to the binary number input into this port

 

 

multiplied by 4096 clock periods of the 125 MHz

 

 

reference clock (8 ns). It is expected that this signal

 

 

will be tied off to a logical value.

 

 

This port is replaced when using the dynamic

 

 

switching mode.

 

 

 

an_interrupt1

Output

Active high interrupt to signal the completion of an

 

 

Auto-Negotiation cycle. This interrupt can be

 

 

enabled/disabled and cleared by writing to the

 

 

appropriate PCS Management Register.

 

 

 

1.These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

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Chapter 2: Core Architecture

Dynamic Switching Signal Pinout

Table 2-6 describes the signals present when the optional Dynamic Switching mode (between 1000BASE-X and SGMII standards) is selected. In this case, the MDIO (Table 2-3) and RocketIO transceiver (Table 2-7) interfaces are always present.

Table 2-6: Optional Dynamic Standard Switching Signals

Signal

Direction

Description

 

 

 

link_timer_basex[8:0]1

Input

Used to configure the duration of the Auto-

 

 

Negotiation Link Timer period when performing

 

 

the 1000BASE-X standard. The duration of this

 

 

timer is set to the binary number input into this port

 

 

multiplied by 4096 clock periods of the 125 MHz

 

 

reference clock (8 ns). It is expected that this signal

 

 

will be tied off to a logical value.

 

 

 

link_timer_sgmii[8:0]1

Input

Used to configure the duration of the Auto-

 

 

Negotiation Link Timer period when performing

 

 

the SGMII standard. The duration of this timer is set

 

 

to the binary number input into this port multiplied

 

 

by 4096 clock periods of the 125 MHz reference

 

 

clock (8 ns). It is expected that this signal will be tied

 

 

off to a logical value.

 

 

 

basex_or_sgmii1

Input

Used as the reset default to select the standard. It is

 

 

expected that this signal will be tied off to a logical

 

 

value.

 

 

‘0’ signals that the core will come out of reset

 

 

operating as 1000BASE-X.

 

 

‘1’ signals that the core will come out of reset

 

 

operating as SGMII.

 

 

Note: The standard can be set following reset

 

 

through the MDIO Management.

 

 

 

1. Clock domain is userclk2.

Physical Side Interface

1000BASE-X PCS with PMA Using RocketIO Transceiver Signal Pinout (Optional)

Table 2-7 describes the optional interface to the RocketIO transceiver. The core is connected to a RocketIO transceiver in the appropriate HDL example design delivered with the core. For more information, see:

Chapter 7, “1000BASE-X with RocketIO Transceivers”

Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers”

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Table 2-7: Optional RocketIO Transceiver Interface Pinout

R

Signal

Direction

Description

 

 

 

mgt_rx_reset1

Output

Reset signal issued by the core to the RocketIO

 

 

transceiver receiver path. Connect to RXRESET signal

 

 

of RocketIO transceiver.

 

 

 

mgt_tx_reset1

Output

Reset signal issued by the core to the RocketIO

 

 

transceiver transmitter path. Connect to TXRESET

 

 

signal of RocketIO transceiver.

 

 

 

userclk

Input

Also connected to TXUSRCLK and RXUSRCLK of the

 

 

RocketIO transceiver. Clock domain is not applicable.

 

 

 

userclk2

Input

Also connected to TXUSRCLK2 and RXUSRCLK2 of

 

 

the RocketIO transceiver. Clock domain is not

 

 

applicable.

 

 

 

dcm_locked

Input

A DCM may be used to derive userclk and userclk2.

 

 

This is implemented in the HDL design example

 

 

delivered with the core. The core will use this input to

 

 

hold the RocketIO transceiver in reset until the DCM

 

 

obtains lock. Clock domain is not applicable.

 

 

 

rxbufstatus[1:0]1

Input

Connect to RocketIO signal of the same name.

rxchariscomma1

Input

Connects to RocketIO signal of the same name.

rxcharisk1

Input

Connects to RocketIO signal of the same name.

rxclkcorcnt[2:0]1

Input

Connect to RocketIO signal of the same name.

rxdata[7:0]1

Input

Connect to RocketIO signal of the same name.

rxdisperr1

Input

Connects to RocketIO signal of the same name.

rxnotintable1

Input

Connects to RocketIO signal of the same name.

rxrundisp1

Input

Connects to RocketIO signal of the same name.

txbuferr1

Input

Connects to RocketIO signal of the same name.

powerdown1

Output

Connects to RocketIO signal of the same name.

txchardispmode1

Output

Connects to RocketIO signal of the same name.

txchardispval1

Output

Connects to RocketIO signal of the same name.

txcharisk1

Output

Connects to RocketIO signal of the same name.

txdata[7:0]1

Output

Connect to RocketIO signal of the same name.

enablealign1

Output

Allows the transceivers to serially realign to a comma

 

 

character. Connects to ENMCOMMAALIGN and

 

 

ENPCOMMAALIGN of the RocketIO.

 

 

 

1.When the core is used with a RocketIO transceiver, userclk2 is used as the 125 MHz reference clock for the entire core.

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Chapter 2: Core Architecture

1000BASE-X PCS with TBI Pinout

Table 2-8 describes the optional TBI signals, used as an alternative to the RocketIO receiver interface. The appropriate HDL example design delivered with the core connects these signals to IOBs to provide an external TBI suitable for connection to an off-chip PMA SERDES device. When the core is used with the TBI, gtx_clk is used as the 125 MHz reference clock for the entire core. For more information, see Chapter 6, “The Ten-Bit Interface.”

Table 2-8: Optional TBI Interface Signal Pinout

Signal

Direction

Clock Domain

Description

 

 

 

 

gtx_clk

Input

N/A

Clock signal at 125 MHz. Tolerance

 

 

 

must be within IEEE 802.3

 

 

 

specification.

 

 

 

 

tx_code_group[9:0]

Output

gtx_clk

10-bit parallel transmit data to PMA

 

 

 

Sublayer (SERDES).

 

 

 

 

loc_ref

Output

N/A

Causes the PMA sublayer clock

 

 

 

recovery unit to lock to pma_tx_clk.

 

 

 

This signal is currently tied to Ground.

 

 

 

 

ewrap

Output

gtx_clk

When ’1,’ this indicates to the external

 

 

 

PMA SERDES device to enter loopback

 

 

 

mode. When ’0,’ this indicates normal

 

 

 

operation

 

 

 

 

rx_code_group0[9:0]

Input

pma_rx_clk0

10-bit parallel received data from PMA

 

 

 

Sublayer (SERDES). This is

 

 

 

synchronous to pma_rx_clk0.

 

 

 

 

rx_code_group1[9:0]

Input

pma_rx_clk1

10-bit parallel received data from PMA

 

 

 

Sublayer (SERDES). This is

 

 

 

synchronous to pma_rx_clk1.

 

 

 

 

pma_rx_clk0

Input

N/A

Received clock signal from PMA

 

 

 

Sublayer (SERDES) at 62.5 MHz.

 

 

 

 

pma_rx_clk1

Input

N/A

Received clock signal from PMA

 

 

 

Sublayer (SERDES) at 62.5 MHz. This

 

 

 

is 180 degrees out of phase with

 

 

 

pma_rx_clk0.

 

 

 

 

en_cdet

Output

gtx_clk

Enables the PMA Sublayer to perform

 

 

 

comma realignment. This is driven

 

 

 

from the PCS Receive Engine during

 

 

 

the Loss-Of-Sync state.

 

 

 

 

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Chapter 3

Generating and Customizing the Core

The Ethernet 1000BASE-X PCS/PMA or SGMII core is generated using the CORE Generator. This chapter describes the GUI options used to generate and customize the core.

GUI Interface

Figure 3-1 displays the Ethernet 1000BASE-X PCS/PMA or SGMII customization screen, used to set core parameters and options. For help starting and using CORE Generator on your system, see the documentation included with ISE™, including the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm.

Figure 3-1: Core Customization Screen

Component Name

The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and “_.”

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Select Standard

Select from the following standards for the core:

1000BASE-X. 1000BASE-X Physical Coding Sublayer (PCS) functionality is designed to the IEEE 802.3 specification. Depending on the choice of physical interface, the functionality may be extended to include the 1000BASE-X Physical Medium Attachment (PMA) sublayer. Default setting.

SGMII. Provides the functionality to provide a Gigabit Media Independent Interface (GMII) to Serial-GMII (SGMII) bridge, as defined in the Serial-GMII Specification (Cisco Systems, ENG-46158). SGMII may be used to replace GMII at a much lower pin count and for this reason often favored by PCB designers.

Both (a combination of 1000BASE-X and SGMII). Combining the 1000BASE-X and SGMII standards lets you dynamically configure the core to switch between 1000BASE-X and SGMII standards. The core can be switched by writing through the MDIO Management Interface. For more information, see Chapter 9, “Configuration and Status.”

Core Functionality

Figure 3-2 displays the Ethernet 1000BASE-X PCS/PMA or SGMII functionality screen.

Figure 3-2: 1000BASE-X Standard Options Screen

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GUI Interface

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Physical Interface

Depending on the target architecture, two physical interface options are available for the core.

RocketIO. Uses a RocketIO transceiver specific to the selected device family to extend the 1000BASE-X functionality to include both PCS and PMA sub-layers. For this reason, it is available only for Virtex-II Pro, Virtex-4 FX, Virtex-5 LXT, Virtex-5 SXT, and Virtex-5 FXT devices. For additional information, see “RocketIO Transceiver Logic” in Chapter 7.

Ten Bit Interface (TBI). Available in all supported families and provides 1000BASE-X or SGMII functionality with a parallel TBI used to interface to an external SERDES. For more information, see “Ten-Bit-Interface Logic” in Chapter 6. Default setting.

MDIO Management Interface

Select this option to include the MDIO Management Interface to access the PCS

Configuration Registers. See “MDIO Management Interface” in Chapter 9.

If this option is not selected, the core is generated with a replacement configuration vector. See “Optional Configuration Vector” in Chapter 9. The Management Interface is selected by default.

Auto-Negotiation

Select this option to include Auto-Negotiation functionality with the core, available only if the core includes the optional Management Interface. For more information, see Chapter 10, “Auto-Negotiation.” The default is to include Auto-Negotiation.

RocketIO Transceiver CRC Logic

This option is visible in the GUI only when a Virtex-II Pro device family is selected, and then only when the RocketIO Interface is selected with the 1000BASE-X standard.

Select this option to use the built-in CRC functionality of the Virtex-II Pro RocketIO transceiver. See Chapter 5, “Using the Virtex-II Pro RocketIO Transceiver CRC Functionality.” This option is disabled (not displayed) by default.

SGMII/Dynamic Standard Switching Elastic Buffer Options

The SGMII/Dynamic Standard Switching Options screen, used to customize the Ethernet 1000BASE-X PCS/PMA or SGMII core, is only displayed if either SGMII or Both is selected in the Select Standard section of the initial customization screen, and only if RocketIO is selected as the Physical Standard.

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Figure 3-3: SGMII/Dynamic Standard Switching Options Screen

This screen lets you select the Receiver Elastic Buffer type to be used with the core. Before selecting this option, see “Receiver Elastic Buffer Implementations” in Chapter 8.

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Parameter Values in the XCO File

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RocketIO Tile Configuration

The RocketIO Tile Configuration screen is only displayed if the RocketIO interface is used with the Virtex-4 or Virtex-5 device families.

Figure 3-4: RocketIO Tile Configuration Screen

RocketIO transceivers for Virtex-4 FX and Virtex-5 device families are available in tiles, each tile consisting of a pair of transceivers. The RocketIO Tile Selection has no effect on the functionality of the core netlist, but determines the functionality of the example design delivered with the core.

Depending on the option selected, the example design instantiates a single core netlist and does one of the following:

MGT A (0). Connects to RocketIO transceiver A

MGT B (1). Connects to RocketIO transceiver B

Both MGTs. Two instantiations of the core are created in the example design and connected to both RocketIO transceiver A and B.

Parameter Values in the XCO File

XCO file parameters are used to run the CORE Generator from the command line. XCO file parameter names and their values are similar to the names and values shown in the GUI, except that underscore characters (_) may be used instead of spaces. The text in an XCO file is not case sensitive.

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Table 3-1 describes the XCO file parameters, values and summarizes the GUI defaults. The following is an example of the CSET parameters in an XCO file:

CSET component_name=gig_eth_pcs_pma_v9_1

CSET standard=1000BASEX

CSET physical_interface=TBI

CSET management_interface=true

CSET auto_negotiation=true

CSET mgt_crc_enabled=false

CSET sgmii_mode=10_100_1000

CSET rocketio_tile=A

Table 3-1: XCO File Values and Default Values

Parameter

XCO File Values

Default GUI

Setting

 

 

 

 

 

component_name

ASCII text starting with a letter and based upon

gig_eth_pcs

 

the following character set: a..z, 0..9 and _

_pma_v9_1

 

 

 

standard

One of the following keywords: 1000BASEX,

1000BASEX

 

SGMII, Both

 

 

 

 

physical_interface

One of the following keywords: TBI, RocketIO

TBI

 

 

 

management_interface

One of the following keywords: true, false

true

 

 

 

auto_negotiation

One of the following keywords: true, false

true

 

 

 

mgt_crc_enabled

One of the following keywords: true, false

false

 

 

 

sgmii_mode

One of the following keywords: 10_100_1000,

10_100_1000

 

100_1000

 

 

10_100_1000 corresponds to “10/100/1000

 

 

Mbps (clock tolerance compliant with

 

 

Ethernet specification)“

 

 

100_1000 corresponds to “10/100/1000

 

 

Mbps (restricted tolerance for clocks) OR

 

 

100/1000 Mbps“

 

 

 

 

rocketio_tile

One of the following keywords: A, B, Both

A

 

 

 

Output Generation

The files output by the CORE Generator are placed in the CORE Generator project directory and include the following:

The netlist file for the core

Supporting CORE Generator files

Release notes and documentation

Subdirectories containing an HDL example design

Scripts to run the core through the back-end tools and simulate the core using either Mentor Graphics® ModelSim®, Cadence® IUS, and Synopsys® simulators

See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for a complete description of the CORE Generator output files, simulation requirements, and detailed information about the HDL example design.

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Chapter 4

Designing with the Core

This chapter provides information about creating your own designs using the Ethernet 1000BASE-X PCS/PMA or SGMII core. Design guidelines, as well as the variety of implementations presented, are based on the example design delivered with the core. See the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for information about the example design delivered with the core.

Note that not all implementations require all of the design steps defined in this chapter. Carefully follow the provided logic design guidelines to ensure success.

Design Overview

An HDL example design built around the core is provided through the CORE Generator and allows for a demonstration of core functionality using either a simulation package or in hardware if placed on a suitable board. Four implementations of the core, based on the provided example design, are illustrated in the following sections.

“1000BASE-X Standard Using RocketIO Transceiver Example Design”

“1000BASE-X Standard with TBI Example Design”

“SGMII Standard Using a RocketIO Transceiver Example Design”

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1000BASE-X Standard Using RocketIO Transceiver Example Design

Figure 4-1 illustrates the example design in 1000BASE-X mode using the Virtex-II Pro or Virtex-4 MGT, Virtex-5 GTP or Virtex-5 GTX transceiver. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into your design and performs the following functions:

Instantiates the core from HDL

Connects the physical-side interface of the core to a RocketIO transceiver

The top level of the example design creates a specific example that can be simulated, synthesized, implemented, and if required, placed on a suitable board and demonstrated in hardware. The top level of the example design performs the following functions:

Instantiates the block level from HDL

Derives the clock management logic for RocketIO and the core

Implements an external GMII

component_name_example_design

 

 

 

component_name_block

 

 

GMII

 

Transceiver

 

 

 

 

IOBs

Tx

 

 

Elastic

 

 

In

 

 

Buffer

 

 

 

 

 

 

Ethernet

 

PMA

Connect to

 

(Connect to

1000BASE-X

RocketIO

Client MA

Optical

PCS/PMA

Transceiver

 

ansceiver)

 

Core

 

 

 

 

IOBs

 

 

 

Out

 

 

 

 

Clock

 

 

Management

 

 

 

Logic

 

 

Figure 4-1:

1000BASE-X Standard Using a RocketIO Transceiver

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1000BASE-X Standard with TBI Example Design

Figure 4-2 illustrates the example design in 1000BASE-X mode using a TBI. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

Instantiates the core from HDL

Connects the physical-side interface of the core to device IOBs, creating an external TBI. See Chapter 6, “The Ten-Bit Interface.”

The top level of the example design creates a specific example that can be simulated, synthesized, implemented, and if required, placed on a suitable board and demonstrated in hardware. The top level of the example design performs the following functions:

Instantiates the block level from HDL

Derives the clock management logic for the core

Implements an external GMII

component_name_example_design

 

 

component_name_block

 

GMII

 

 

 

 

TBI

IOBs

Tx

 

Elastic

IOBs

In

Buffer

Out

 

Connect to

Ethernet

TBI

1000BASE-X

(Connect to

Client MAC

PCS/PMA

SERDES)

 

Core

 

IOBs

 

IOBs

 

In

Out

 

 

(DDR)

 

 

 

Clock

 

 

Management

 

 

Logic

 

Figure 4-2: Example Design 1000BASE-X Standard Using TBI

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SGMII Standard Using a RocketIO Transceiver Example Design

Figure 4-3 illustrates the example design in SGMII mode using the Virtex-II Pro or Virtex- 4 MGT, Virtex-5 GTP or Virtex-5 GTX transceiver. This is also the example design created when the Dynamic Switching capability between SGMII and 1000BASE-X standards is present. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

Instantiates the core from HDL

Connects the physical-side interface of the core to a RocketIO transceiver

Connects the client side GMII of the core to an SGMII Adaptation Module, which provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps

The top level of the example design creates a specific example which can be simulated, synthesized and implemented. The top level of the example design performs the following functions:

Instantiates the block level from HDL

Derives the clock management logic for RocketIO and the core

Implements an external GMII-style interface

 

 

component_name_example_design

 

 

 

 

 

 

component_name_block

 

 

 

GMII

 

 

Transceiver

 

 

 

IOBs

 

 

 

 

 

 

In

 

 

 

 

 

GMII-style

SGMII

Ethernet

 

Serial GMII

 

Adaptation

1000BASE-X

 

 

8-bit I/F

RocketIO

(SGMII)

 

Module

PCS/PMA

 

 

 

 

 

 

 

 

Core

 

 

 

 

 

 

 

Fabric

 

 

 

IOBs

 

 

Rx

 

 

 

Out

 

 

Elastic

 

 

 

 

 

 

Buffer

 

 

 

Clock

 

 

 

 

 

 

Management

 

 

 

 

 

 

Logic

 

 

 

 

 

 

Figure 4-3: Example Design Performing the SGMII Standard

 

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SGMII Standard with TBI Transceiver Example Design

Figure 4-3 illustrates the example design with the SGMII standard using a TBI. This is also the example design created when the Dynamic Switching capability between SGMII and 1000BASE-X standards is present. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

Instantiates the core from HDL

Connects the physical-side interface of the core to device IOBs, creating an external TBI. See Chapter 6, “The Ten-Bit Interface.”

Connects the client side GMII of the core to an SGMII Adaptation Module, which provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps

The top level of the example design creates a specific example which can be simulated, synthesized and implemented. The top level of the example design performs the following functions:

Instantiates the block level from HDL

Derives the clock management logic for the core

Implements an external GMII-style interface

 

component_name_example_design

 

 

 

component_name_block

 

 

GMII

 

 

 

 

 

TBI

 

IOBs

 

IOBs

 

In

 

 

 

Out

 

 

 

GMII-style

SGMII

Ethernet

TBI

Adaptation

1000BASE-X

(Connect to

8-bit I/F

Module

PCS/PMA

SERDES)

 

 

 

Core

 

 

IOBs

 

IOBs

 

Out

 

In

 

 

 

(DDR)

 

Clock

 

 

 

Management

 

 

 

Logic

 

 

 

Figure 4-4: Example Design Performing the SGMII Standard

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Design Guidelines

Generate the Core

Generate the core using the CORE Generator, as described in Chapter 3, “Generating and Customizing the Core.”

Examine the Example Design Provided with the Core

Before implementing the core in your application, examine the example design provided with the core to identify the steps that can be performed:

Edit the HDL top level of the example design file to change the clocking scheme, add or remove IOBs as required, and replace the GMII IOB logic with user-specific application logic (for example, an Ethernet MAC).

Synthesize the entire design.

The Xilinx Synthesis Tool (XST) script and Project file in the /implement/vhdl (or /implement/verilog) directory may be adapted to include any added user’s HDL files.

Run the implement script in the /implement directory to create a top-level netlist for the design.

The script may also run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. SimPrim-based simulation models for the entire design are also produced by the implement scripts.

Simulate the entire design using the demonstration test bench provided in

/test/vhdl (or /test/verilog) as a template.

Download the bitstream to a target device.

Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application

Before implementing your application, examine the example design delivered with the core for information about the following:

Instantiating the core from HDL

Connecting the physical-side interface of the core (RocketIO transceiver or TBI)

Deriving the clock management logic

It is expected that the block level module from the example design will be instantiated directly into customer designs rather than the core netlist itself. The block level contains the core and a completed physical interface.

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