Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Getting Started Manual
LogiCORE™ Ethernet
1000BASE-X PCS/PMA
or SGMII v7.0
Getting Started Guide
UG145 January 18, 2006
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R
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Ethernet 1000BASE-X PCS/PMA or SGMII v7.0 Getting Started Guide
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The following table shows the revision history for this document.
Date Version Revision
09/30/04 1.0 Initial Xilinx release.
04/28/05 2.0 Updated to version 6.0 of the core, and Xilinx Tools v7.1i SP2.
01/18/06 3.0 Updated to version 7.0 of the core, and Xilinx Tools v8.1i, updated Licensing chapter.
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Table of Contents
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 1: Introduction
About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended Design Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ethernet 1000BASE-X PCS/PMA or SGMII Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 2: Installing and Licensing the Core
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Installing the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CORE Generator IP Updates Installer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Manual Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Verifying the Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Simulation Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Obtaining Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Installing the License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3: Quick Start Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Simulating the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Setting up for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
What’s Next? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Chapter 4: Detailed Example Design
Directory Structure and File Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VHDL Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Verilog Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Implementation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Simulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Functional simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timing simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Core Example Design Using RocketIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Top-Level HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Transmitter Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Customizing the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Core Example Design with Ten-Bit Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example Design Top-Level HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Transmitter Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Customizing the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SGMII Example Design / Dynamic Switching Example Design . . . . . . . . . . . . . . 40
Example Design Top-Level HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SGMII Adaptation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Johnson Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Transmitter Rate Adaptation Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Receiver Rate Adaptation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Customizing the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Schedule of Figures
Chapter 1: Introduction
Chapter 2: Installing and Licensing the Core
Figure 2-1: CORE Generator Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 3: Quick Start Example Design
Figure 3-1: Ethernet 1000BASE-X PCS/PMA Example Design and Test Bench . . . . . . . . 19
Figure 3-2: Core Customization Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 4: Detailed Example Design
Figure 4-1: Core Directories and Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4-2: Core Directories and Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4-3: Top-Level HDL for the Ethernet 1000BASE-X PCS/PMA using RocketIO . 32
Figure 4-4: Demonstration Test Bench Using RocketIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4-5: Example Design Top-Level HDL for the Ethernet 1000BASE-X PCS
with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4-6: Demonstration Test Bench for the Ethernet 1000BASE-X PCS with TBI . . . 38
Figure 4-7: Top- Level HDL for the Ethernet 1000BASE-X PCS/PMA or SGMII
LogiCORE in SGMII mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 4-8: SGMII Adaptation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 4-9: Clock Generator Output Clocks and Clock Enable. . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-10: Transmitter Rate Adaptation Module Data Sampling . . . . . . . . . . . . . . . . . . 46
Figure 4-11: Receiver Rate Adaptation Module Data Sampling . . . . . . . . . . . . . . . . . . . . . 47
Figure 4-12: Demonstration Test Bench for the Ethernet 1000BASE-X PCS/PMA
or SGMII Core in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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About This Guide
The LogiCORE™ Ethernet 1000Base-X PCS/PMA or SGMII v7.0 Getting Started Guide
provides information about generating an Ethernet 1000BASE-X PCS/PMA core,
customizing and simulating the core using the provided example designs, and running the
design files through implementation using the Xilinx tools.
Guide Contents
The following chapters are included in this guide:
• Preface, “About this Guide” introduces the organization and purpose of the Getting
Started Guide, a list of additional resources, and the conventions used in the guide.
• Chapter 1, “Introduction” describes the core and related information, including
recommended design experience, additional resources, technical support, and
submitting feedback to Xilinx.
• Chapter 2, “Installing and Licensing the Core” provides information about installing
and licensing the core.
• Chapter 3, “Quick Start Example Design” provides instructions to quickly generate
the core and run the example design through implementation and simulation using
the default settings.
• Chapter 4, “Detailed Example Design” describes the demonstration test bench in
detail and provides directions for how to customize the demonstration test bench for
use in an application.
Preface
Additional Resources
For additional information, go to http://www.xilinx.com/support. The following table
lists some of the resources you can access from this website or by using the provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to
Answer Browser Database of Xilinx solution records
Application Notes Descriptions of device-specific design techniques and approaches
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verification and debugging
http://www.xilinx.com/support/techsup/tutorials/index.htm
http://www.xilinx.com/xlnx/xil_ans_browser.jsp
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?c
ategory=Application+Notes
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Conventions
Typographical
Preface: About This Guide
Resource Description/URL
Data Sheets Device-specific information on Xilinx device characteristics,
including readback, boundary scan, configuration, length count,
and debugging
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
Problem Solvers Interactive tools that allow you to troubleshoot your design issues
http://www.xilinx.com/support/troubleshoot/psolvers.htm
Tech Tips Latest news, design tips, and patch information for the Xilinx
design environment
http://www.xilinx.com/xlnx/xil_tt_home.jsp
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
program files that the system
speed grade: - 100
displays
Courier bold
Italic font
Literal commands you enter in
a syntactical statement
Variables in a syntax
statement for which you must
supply values
ngdbuild design_name
See the Development System
Reference Guide for more
information.
References to other manuals See the User Guide for details.
If a wire is drawn so that it
Emphasis in text
overlaps the pin of a symbol,
the two nets are not connected.
Dark Shading
Items that are not supported
or reserved
This feature is not supported
An optional entry or
Square brackets [ ]
parameter. However, in bus
specifications, such as
ngdbuild [ option_name]
design_name
bus[7:0], they are required.
Braces { }
Vertical bar |
10 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
A list of items from which you
must choose one or more
Separates items in a list of
choices
lowpwr ={on|off}
lowpwr ={on|off}
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Conventions
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Convention Meaning or Use Example
Vertical ellipsis
Horizontal ellipsis . . .
Notations
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
IOB #1: Name = QOUT’
.
.
Repetitive material that has
been omitted
.
Repetitive material that has
been omitted
The prefix ‘0x’ or the suffix ‘h’
indicate hexadecimal notation
A ‘_n’ means the signal is
active low
Cross-reference link to a
location in the current
document
IOB #2: Name = CLKIN’
.
.
.
allow block block_name
loc1 loc2 ... locn;
A read of address
0x00112975 returned
45524943h.
usr_teof_n is active low.
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Blue, underlined text
Hyperlink to a website (URL)
Go to http://www.xilinx.com
for the latest speed files.
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Preface: About This Guide
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Introduction
The Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution that
supports Verilog-HDL and VHDL. In addition, the example design in this guide is
provided in both Verilog and VHDL formats.
This chapter introduces the core and provides some related information, including
recommended design experience, additional resources, technical support, and how to
submit feedback to Xilinx.
About the Core
The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™ IP core,
included in the latest IP Update on the Xilinx IP Center. For detailed information about the
core, see http://www.xilinx.com/systemio/1gbsx_phy/index.htm
about system requirements, installation, and licensing options, see Chapter 2, “Installing
and Licensing the Core.”
Chapter 1
. For information
Recommended Design Experience
Although the Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution,
the challenge associated with implementing a complete design varies, depending on the
configuration and functionality of the application. For best results, previous experience
building high-performance, pipelined FPGA designs using Xilinx implementation
software and user constraint files (UCFs) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
Additional Core Resources
For detailed information and updates about the Ethernet 1000BASE-X PCS/PMA or
SGMII core, see the following documents, located on the Ethernet 1000BASE-X PCS/PMA
or SGMII product page at http://www.xilinx.com/systemio/1gbsx_phy/index.htm.
•
Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII Data Sheet
•
Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII Release Notes
•
Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII User Guide
For updates to this document, see the Ethernet 1000BASE-X PCS/PMA or SGMII Getting
Started Guide, also located on the Ethernet 1000BASE-X PCS/PMA or SGMII product page.
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Technical Support
For technical support, see http://support.xilinx.com/. Questions are routed to a team of
engineers with expertise using the Ethernet 1000BASE-X PCS/PMA or SGMII core.
Xilinx will provide technical support for use of this product as described in the Xilinx
Ethernet 1000BASE-X PCS/PMA or the Xilinx SGMII User Guide and the Ethernet 1000BASEX PCS/PMA or SGMII Getting Started Guide. Xilinx cannot guarantee timing, functionality,
or support of this product for designs that do not follow these guidelines.
Feedback
Xilinx welcomes comments and suggestions about the Ethernet 1000BASE-X PCS/PMA or
SGMII core and the documentation supplied with the core.
Ethernet 1000BASE-X PCS/PMA or SGMII Core
For comments or suggestions about the Ethernet 1000BASE-X PCS/PMA or SGMII core,
please submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htm/
Be sure to include the following information:
Chapter 1: Introduction
Document
• Product name
• Core version number
• Explanation of your comments
For comments or suggestions about this document, please submit a WebCase from
www.xilinx.com/support/clearexpress/websupport.htm/
Be sure to include the following information:
• Document title
• Document number
• Page number(s) to which your comments refer
• Explanation of your comments
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Installing and Licensing the Core
This chapter provides instructions for installing the Ethernet 1000BASE-X PCS/PMA or
SGMII core and obtaining a license for the core, which you must do before using the core in
your designs. The Ethernet 1000BASE-X PCS/PMA or SGMII core is provided under the
terms of the Xilinx LogiCORE Site License Agreement
SignOnce
IP License standard defined by the Common License Consortium.
System Requirements
Windows
• Windows® 2000 Professional with Service Pack 2-4
• Windows XP Professional with Service Pack 1
, which conforms to the terms of the
Chapter 2
Solaris/Linux
• Sun Solaris® 8/9
• Red Hat®
Software
• Xilinx ISETM 8.1i
Before You Begin
Before installing the core, you must have a Xilinx.com account and the ISE 8.1i software
installed on your system. If you have already completed these steps, go to “Installing the
Core.”
1. Click Login at the top of the Xilinx home page
create a support account.
2. Install the ISE 8.1i software and the applicable Service Pack software. ISE Service Packs
can be downloaded from www.xilinx.com/support/download.htm
Installing the Core
You can install the core in two ways—using the CORE Generator IP Updates Installer,
which lets you select from a list of updates—or by performing a manual installation after
downloading the core from the web.
Enterprise Linux 3.0 (32-bit and 64-bit)
; then follow the onscreen instructions to
.
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CORE Generator IP Updates Installer
Note: To use this installation method behind a firewall, you must know your proxy
settings. Contact your administrator to determine the proxy host address and port number
before you begin, if necessary.
1. Start the CORE Generator; then open an existing project or create a new one.
2. From the main CORE Generator window, choose Tools > Updates Installer to start the
Updates Installer. If you are behind a firewall, you will be prompted to enter your
proxy host and port settings.
3. If necessary, enter your proxy settings; then click Set. The IP Updates installer appears.
4. Click the checkbox next to 8.1i_IP_Update1 to select it; then click Install Selected.
Informational messages may appear indicating that additional installations are
required.
5. Click OK to accept any messages and continue. The User Login dialog box appears.
6. Enter your login name and password; then click OK. The Updates Installer Generator
downloads and installs the selected products, and then exits.
7. To confirm the installation, check the following file:
C:\Xilinx\coregen\install\install_history
Note that this step assumes your Xilinx software is installed in C:\Xilinx.
Chapter 2: Installing and Licensing the Core
.
Manual Installation
1. Close the CORE Generator application if it is running.
2. Download the IP Update ZIP file from the following location and save it to a
temporary directory:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=8.1i
3. Unpack the ZIP files using either WinZip (Windows) or Unzip (UNIX).
4. Extract the ZIP file (ise_81i_ip_update1.zip) archive to the root directory of your Xilinx
software installation. (Allow the extractor utility you use to overwrite all existing files
and maintain the directory structure defined in the archive.)
5. If you do not have a zip utility, do one of the following:
− Windows. From a command window, type the following:
%XILINX%/bin/nt/unzip -d %XILINX% ise_81i_ip_update1.zip
− Linux. From a UNIX shell, type the following:
$XILINX/bin/lin/unzip -d $XILINX ise_81i_ip_update1.zip
− Solaris. From a UNIX shell, type the following:
$XILINX/bin/sol/unzip -d $XILINX ise_81i_ip_update1.zip
6. To verify the root directory of your Xilinx installation, do one of the following:
− Windows. Type echo %XILINX% from a DOS prompt.
− UNIX. If you have already installed the Xilinx ISE software, the Xilinx variable
defined by your set-up script identifies the location of the Xilinx installation
directory. After sourcing the Xilinx set-up script, type
the location of the Xilinx installation.
echo $XILINX to determine
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