Xilinx LogiCORE User Manual
LogiCORE™ IP
Endpoint Block Plus v1.8
for PCI Express®
Getting Started Guide
UG343 June 27, 2008
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© 2006–2008 Xilinx, Inc. All rights reserved.
XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks
are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
10/23/06 1.1 Initial Xilinx release.
2/15/07 2.0 Update core to version 1.2; Xilinx tools 9.1i.
5/17/06 3.0 Update core to version 1.3; updated for PCI-SIG compliance.
8/8/07 4.0 Update core to version 1.4; Xilinx tools 9.2i, Cadence IUS v5.8.
10/10/07 5.0 Update core to version 1.5, Cadence IUS v6.1.
3/24/08 6.0 Update core to version 1.6; Xilinx tools 10.1.
4/25/08 7.0 Update core to version 1.7.
6/27/08 8.0 Update core to version 1.8.
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UG343 June 27, 2008
Table of Contents
Preface: About This Guide
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1: Introduction
About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Design Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2: Licensing the Core
Before you Begin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Simulation Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Obtaining Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Installing Your License File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3: Quickstart Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Simulation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Implementation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Example Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Simulating the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Setting up for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Directory Structure and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
<project directory> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
<project directory>/<component name> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
<component name>/doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
<component name>/example_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
<component name>/implement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
implement/results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
<component name>/simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
simulation/dsport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
simulation/functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
simulation/tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Dual Core Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dual Core Directory Structure and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
<component name>/example_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
example_design/dual_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
<component name>/simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
simulation/functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
<component name>/implement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Appendix: Additional Design Considerations
Package Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
User Constraints Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Wrapper File Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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About This Guide
The Endpoint Block Plus for PCI Express® Getting Started Guide provides information about
generating an Endpoint Block Plus for PCI Express (PCIe
simulating the core using the provided example design, and running the design files
through implementation using the Xilinx tools.
Contents
This guide contains the following chapters:
• Preface, “About this Guide,” introduces the organization and purpose of this guide
and the conventions used in this document.
• Chapter 1, “Introduction,” describes the core and related information, including
system requirements, recommended design experience, additional resources,
technical support, and submitting feedback to Xilinx.
• Chapter 2, “Licensing the Core” provides instructions for selecting a license option for
the core.
• Chapter 3, “Quickstart Example Design,” provides instructions for quickly
generating, simulating, and implementing the example design and the dual core
example design using the demonstration test bench.
• Appendix, “Additional Design Considerations,” defines additional considerations
when implementing the example design.
Preface
®) core, customizing and
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
Courier bold
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program files that the system
displays
Literal commands you enter in
a syntactical statement
speed grade: - 100
ngdbuild design_name
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Preface: About This Guide
Convention Meaning or Use Example
References to other manuals See the User Guide for details.
Italic font
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
<text in brackets>
Dark Shading
User-defined variable for
directory names.
Items that are not supported
or reserved
An optional entry or
Square brackets [ ]
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
Braces { }
Vertical bar |
A list of items from which you
must choose one or more
Separates items in a list of
choices
Vertical ellipsis
.
.
Repetitive material that has
been omitted
.
Horizontal ellipsis . . . Omitted repetitive material
The prefix ‘
0x’ or the suffix ‘h’
indicate hexadecimal notation
Notations
An ‘
_n’ means the signal is
active low
<component_name>
Unsupported feature
ngdbuild
design_name
[option_name]
lowpwr ={on|off}
lowpwr ={on|off}
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
allow block
loc1 loc2 ... locn;
block_name
A read of address 0x00112975
returned 45524943h.
usr_teof_n is active low.
Online Document
The following linking conventions are used in this document:
Convention Meaning or Use Example
Cross-reference link to a
Blue text
location in the current
document
Blue, underlined text
6 www.xilinx.com Endpoint Block Plus v1.8 for PCI Express
Hyperlink to a website (URL)
See the section “Additional
Resources” for details.
See “Title Formats” in Chapter
1 for details.
Go to w
ww.xilinx.com for the
latest speed files.
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Introduction
The Endpoint Block Plus for PCI Express is a high-bandwidth, scalable, and reliable serial
interconnect building block for use with Virtex™-5 FPGA devices. This core supports
Verilog® and VHDL. The example design described in this guide is provided in Verilog
and VHDL.
This chapter introduces the core and provides related information, including system
requirements, recommended design experience, additional resources, technical support,
and submitting feedback to Xilinx.
About the Core
The Endpoint Block Plus for PCIe core is a Xilinx CORE Generator™ IP core, included in
the latest IP Update on the Xilinx IP Center.
Block Plus for PCIe p
Chapter 2, “Licensing the Core.”
roduct page.
Chapter 1
For additional information about the core, see the
For information about obtaining a license for the core, see
System Requirements
Windows
• Windows XP® Professional 32-bit/64-bit
• Windows Vista® Business 32-bit/64-bit
Linux
• Red Hat® Enterprise Linux WS v4.0 32-bit/64-bit
• Red Hat® Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option)
• SUSE Linux Enterprise (SLE) v10.1 32-bit/64-bit
Software
• ISE™ 10.1
Check the release notes for the required Service Pack; I
downloaded from www.xilinx.com/support/download/index.htm
Recommended Design Experience
Although the Endpoint Block Plus for PCIe is a fully verified solution, the challenge
associated with implementing a complete design varies depending on the configuration
and functionality of the application. For best results, previous experience building high
SE Service Packs can be
.
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performance, pipelined FPGA designs using Xilinx implementation software and User
Constraints Files (UCF) is recommended.
Additional Core Resources
For detailed information and updates about the core, see the following documents,
available from the Block Plus for PCIe
• LogiCORE IP Endpoint Block Plus for PCI Express Data Sheet
• LogiCORE IP Endpoint Block Plus for PCI Express User Guide
• LogiCORE IP Endpoint Block Plus for PCI Express Release Notes (available from the core
directory after generating the core)
• Virtex-5
Additional information and resources related to the PCI Express technology are available
from the following web sites:
Integrated Endpoint Block for PCI Express Designs User Guide (UG197)
product page
Chapter 1: Introduction
unless otherwise noted.
• PCI Express at PCI-SI
• PCI Express Developer’s Forum
Technical Support
For technical support, go to www.xilinx.com/support. Questions are routed to a team of
engineers with expertise using the Endpoint Block Plus for PCI Express core.
Xilinx provides technical support for use of this product as described in the LogiCORE IP
Endpoint Block Plus for PCI Express User Guide and the LogiCORE IP Endpoint Block Plus for
PCI Express Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support
of this product for designs that do not follow these guidelines.
Feedback
Xilinx welcomes comments and suggestions about the core and the accompanying
documentation.
Core
For comments or suggestions about the core, please submit a WebCase from
www.xilinx.com/support
• Product name
• Core version number
• Explanation of your comments
G
. Be sure to include the following information:
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Feedback
Document
For comments or suggestions about this document, please submit a WebCase from
www.xilinx.com/support
. Be sure to include the following information:
• Document title
• Document number
• Page number(s) to which your comments refer
• Explanation of your comments
R
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