KCU1250 10GBASE-KR
Ethernet TRD
User Guide
KUCon-TRD05
Vivado Design Suite
UG1058 (v2017.1) April 19, 2017
Revision History
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The following table shows the revision history for this document.
Date Version Revision
Updated for Vivado Design Suite 2017.1. Updated design file
04/19/2017 2017.1
rdf0310-kcu1250-trd05-2017-1.zip. Updated sections Configure VIO and
Forward Error Correction. Added a note about screens in Install Vivado Design Suite.
12/15/2016 2016.4
11/28/2016 2016.3
10/12/2016 2016.3
06/08/2016 2016.2 Replaced all references to Vivado Design Suite version 2016.1 with version 2016.2.
04/13/2016 2016.1 Replaced all references to Vivado Design Suite version 2015.4 with version 2016.1.
11/23/2015 2015.4 Replaced all references to Vivado Design Suite version 2015.3 with version 2015.4.
10/02/2015 2015.3 Replaced all references to Vivado Design Suite version 2015.2 with version 2015.3.
06/30/2015 2015.2
04/27/2015 2015.1
Updated for Vivado Design Suite 2016.4. Updated design file
rdf0310-kcu1250-trd05-2016-4.zip.
Changed rdf310-kcu1250-trd05-2016-3.zip file name to
rdf0310-kcu1250-trd05-2016-3.zip.
Updated for Vivado Design Suite 2016.3. Re-added Chapter 3, Bringing Up the
Design. Updated Appendix D, Additional Resources and Legal Notices.
Replaced all references to Vivado Design Suite version 2015.1 with version 2015.2.
Added step c, page 23 under step 6, page 23. Added new step 2, page 25 and new
step 2, page 39.
Replaced all references to Vivado Design Suite version 2014.4.1 with version 2015.1.
added [Ref 1] to the to the first listed item under Hardware, page 10. Updated the
Quad Transceiver names in step 1 and TX and RX cable names in step 2 under Connect
Bulls Eye Cables, page 19. Updated the Quad Transceiver names in Figure 3-1.
Updated step 4, page 20. Updated screen capture in Figure 3-8. Reversed the order of
content in the VIO_Tab column in Table 3-1 from hw_vio_1 > hw_vio_6 to
hw_vio_6 > hw_vio_1. Updated screen captures in Figure 3-9, Figure 3-10,
Figure 3-11, Figure 3-18, Figure 3-19, and Figure 3-20. Revised the order of content
in the VIO_Tab column in Table 3-2.
03/04/2015 2014.4.1 Initial Xilinx release.
10GBASE-KR Ethernet TRD 2
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Table of Contents
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
10GBASE-KR TRD Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2: Setup
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Preliminary Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 3: Bringing Up the Design
Set Up the KCU1250 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program the Clocks Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Configure VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Dynamic Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Chapter 4: Implementing and Simulating the Design
Implementing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 5: Reference Design Details
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix A: Directory Structure
Directory Content Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Appendix B: Performance Estimates
Appendix C: User-Space Registers
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Appendix D: Additional Resources and Legal Notices
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Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Introduction
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This document describes the features and functions of the 10GBASE-KR Ethernet targeted
reference design (10GBASE-KR TRD). It also describes how to set up, operate, test, and modify
the design.
10GBASE-KR TRD Overview
The 10GBASE-KR TRD (Figure 1-1) targets the Kintex® UltraScale™ XCKU040-2FFVA1156C
FPGA running on the KCU1250 characterization board. It demonstrates connectivity
between the 10-Gigabit Ethernet PCS/PMA IP core (10GBASE-KR) and the 10-Gigabit
Ethernet MAC IP core (10G MAC) and error free traffic flow on this 10-Gigabit Ethernet
channel across a backplane.
Chapter 1
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X-Ref Target - Figure 1-1
Integrated Blocks in FPGA
Xilinx IP
Custom Logic
On Board
AXI-Lite (Master to Slave)
AXI-Stream
SMA
Line
CARD
SMA
Line
CARD
Backplane
KCU1250 Board
CHANNEL 1
CHANNEL 0
C
C
0
XCKU040-2FFGA1156C FPGA
64 bits
XGMII
64 bits at 156.25MHz
10GBASE -KR
64 bits at 156.25MHz
AXI Interconnect
AXI UART
Lite
MicroBlaze
Subsystem
64 bits
XGMII
10G
MAC
10GBASE -KR
GTH Transceiver
AXI LITE
10G
MAC
AXI LITE
GTH Transceiver
To the
UART
Java GUI/Driver
and Vivado
Design Suite
USB -UART
SiLabs CP2105
Control
Computer
Traffic
Generator
and
Monitor
Traffic
Generator
and
Monitor
USB -JTAG
AXI Interconnect
JTAG to
AXI
MicroBlaze
Subsystem
AXI DRP
Bridge
AXI BRAM
Controller
BRAM
AXI DRP
Bridge
DRP
DRP
Eyescan System
X18426-120716
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Chapter 1: Introduction
HANNEL 1
HANNEL
Figure 1-1: The 10GBASE-KR TRD
10GBASE-KR is defined in IEEE Std 802.3-2012 [Ref 1]. It specifies the 10 Gb/s physical layer
specification using 10GBASE-R encoding over an electrical backplane.
The 10GBASE-KR TRD has two 10 Gb/s Ethernet channels; channel 0 and channel 1. Transmit
data is generated by the Traffic Generator and Monitor block. Data from one channel is
looped back to the other channel on a backplane through SMA cables as shown in
Figure 3-2. The looped-back data becomes the receive data on the other channel and the
frame length and frame check sequence (FCS) are verified by the 10-Gigabit Ethernet MAC
IP core.
A MicroBlaze™ processor subsystem monitors the 10-Gigabit Ethernet MAC IP core
statistics. It also controls the Traffic Generator and Monitor block and reports Ethernet
performance. It passes this information to the Ethernet Controller application GUI running
on the control computer via the USB-to-UART port on the KCU1250 board.
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Components, Features, and Functions
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The 10GBASE-KR TRD includes:
• 10-Gigabit Ethernet PCS/PMA IP core (10GBASE-KR):
Uses GTH transceivers running at 10.3125 Gb/s line rate.
°
Provides a single data rate (SDR) 10-Gigabit Ethernet Media Independent Interface
°
(XGMII) which connects to the 10-Gigabit Ethernet MAC IP core. The XGMII interface
runs at 156.25 MHz and the data path is 64-bits wide.
Provides a serial interface to connect to the backplane.
°
Auto-negotiation (AN) and forward error connection (FEC) is enabled.
°
Is monitored and configured through status and configuration vectors.
°
• 10-Gigabit Ethernet MAC IP core (10G MAC):
Connects to the 10-Gigabit Ethernet PCS/PMA IP core using the XGMII interface.
°
Provides AXI4-Stream protocol support on the user interface running at
°
156.25 MHz.
Chapter 1: Introduction
Is monitored through an AXI4-Lite interface.
°
• Traffic Generator and Monitor:
Generates Ethernet traffic.
°
Monitors bandwidth utilization on the transmit and receive AXI4-Stream interfaces
°
of the 10-Gigabit Ethernet MAC IP core.
Is configured and monitored through an AXI4-Lite interface.
°
•AXI UART Lite:
Provides the controller interface for asynchronous serial data transfer. This interface
°
connects to the USB-to-UART port on the KCU1250 board, and is used to
communicate with the control computer.
Provides an AXI4-Lite interface to communicate with the MicroBlaze processor
°
subsystem.
• MicroBlaze processor subsystem and AXI Interconnect:
Communicates with the 10-Gigabit Ethernet MAC IP core, Traffic Generator and
°
Monitor, and AXI UART Lite using the AXI4-Lite protocol.
Drivers running on the MicroBlaze processor subsystem interpret commands
°
received from the Ethernet Controller application GUI running on the control
computer and convert them to AXI4-Lite transactions.
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• Ethernet Controller application GUI/Driver:
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Provides a graphical user interface running on the control computer to pass user
°
inputs to the 10GBASE-KR TRD and to display status through the KCU1250 board
USB-to-UART port.
• Eye scan system:
AXI DRP bridge:
°
- Custom logic that allows access to DRP registers of the transceiver through any
AXI master such as the MicroBlaze processor subsystem.
AXI block RAM controller:
°
- An AXI slave IP core that allows access to local block RAM by AXI master devices
such as the MicroBlaze processor subsystem and the JTAG to AXI Master IP core.
- The block RAM stores the data read from the DRP port of the transceiver.
JTAG to AXI Master:
°
- An AXI Master IP core that can generate AXI transactions and drive AXI signals
internal to FPGA in the system.
Chapter 1: Introduction
- Communicates with the AXI block RAM controller via the AXI Interconnect.
- Allows the Vivado® tools logic analyzer Tcl console running on the control
computer to interact with FPGA through the USB-to-JTAG port on the KCU1250
board.
MicroBlaze processor subsystem:
°
- An AXI Master that communicates with the AXI DRP bridge and AXI block RAM
controller via the AXI Interconnect.
- Drivers running on the MicroBlaze processor subsystem implement an algorithm
to measure a statistical eye (bit error ratio (BER) versus time and voltage offset).
Data sampling points are available to read via the DRP port of the transceiver.
Point-by-point measured data is stored in a block RAM to be burst read by the
control computer via the JTAG to AXI Master.
AXI Interconnect:
°
- Allows multiple AXI masters (MicroBlaze processor subsystem and JTAG to AXI
Master) to communicate with multiple AXI slaves (AXI DRP Bridge and AXI block
RAM controller).
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Chapter 1: Introduction
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Resource Utilization
Table 1-1 lists the resources used by the 10GBASE-KR TRD after synthesis has run. Place and
route can alter these numbers based on placements and routing paths, so use these
numbers as a rough estimate of resource utilization. These numbers might vary based on
the version of the 10GBASE-KR TRD and the tools used to regenerate the design.
Table 1-1: 10GBASE-KR TRD Resource Utilization
Site Type Used Available Usage (%)
CLB LUTs 29,846 242,400 12.31
CLB Registers 41,794 484,800 8.62
Block RAM Tile 42 600 6.91
Global Clock Buffers 2 240 0.83
BUFG_GT_SYNC 6 55 10.90
BUFG_GT 6 120 5.00
GTHE3_CHANNEL 2 20 10.00
GTHE3_COMMON 2 5 40.00
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Setup
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This chapter lists the requirements and describes how to do all preliminary setup of the
KCU1250 board, control computer, and software before bringing up the 10GBASE-KR TRD.
IMPORTANT: Perform the procedures described in this chapter before performing the bring up
procedures described in Chapter 3, Bringing Up the Design.
Requirements
Hardware
• KCU1250 board with the Kintex® UltraScale™ XCKU040-2FFVA1156C FPGA [Ref 2]
Chapter 2
• Two USB cables, standard-A plug to micro-B plug
• Power Supply: 100 VAC–240 VAC input, 12 VDC 5.0A output
• Backplane: Z-Pack TINMAN Customer System kit from Tyco Electronics [Ref 3]
• Two Samtec Bulls Eye® cables from Avnet [Ref 4]
• Four DC Blocks/AC capacitors from Aeroflex [Ref 5]
Computer
One computer is required, and is identified as the control computer throughout this
document. It is required for running the Vivado® Design Suite, configuring the FPGA, and
running the Ethernet Controller application GUI to control and monitor the reference
design. It can be a laptop or desktop computer with Microsoft Windows 7 Operating
system.
Design Tools and Software
• Vivado Design Suite 2017.1
• USB UART drivers (CP210x VCP drivers) [Ref 6]
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•Tera Term [Ref 7]
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Chapter 2: Setup
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• Java SE Runtime Environment 7
• Ethernet Controller application GUI (included with the 10GBASE-KR TRD)
• 10GBASE-KR Ethernet targeted reference design files
Download and installation instructions for each required software application and for the
10GBASE-KR Ethernet targeted reference design files are described in Preliminary Setup.
Preliminary Setup
Complete these tasks before bringing up the design described in Chapter 3, Bringing Up
the Design.
Install Vivado Design Suite
Install Vivado Design Suite 2017.1 on the control computer. Follow the installation
instructions provided in Vivado Design Suite User Guide Release Notes, Installation, and
Licensing (UG973) [Ref 8].
Note:
older version of Vivado tools, but the text and fields are still relevant to the current version.
Snapshots of the Vivado integrated design environment (IDE) in this document are from an
Download Targeted Reference Design Files
1. Download the 10GBASE-R TRD ZIP file rdf0310-kcu1250-trd05-2017-1.zip from
KCU1250 Characterization Kit Documentation.
2. Unzip the contents of the file to a working directory.
3. The unzipped contents will be located at
<working_dir>/kcu1250_10gbasekr_trd.
The 10GBASE-KR TRD directory structure is described in Appendix A, Directory Structure.
Install the USB UART Drivers
Download the CP210x USB to UART Bridge VCP drivers (for Windows 7) from Silicon Labs.
Follow the instructions in Silicon Labs CP210x USB-to-UART Installation Guide (UG1033)
[Ref 9].
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X-Ref Target - Figure 2-1
To U80
USB JTAG
J1
USB UART
USB cable
standard-A plug
to micro-B plug
J28 12 VDC
Power Supply
100VAC–240VAC Input
12 VDC 5.0A Output
ON
OFF
Board
Power
Switch SW1
Wally
&RQWURO
&RPSXWHU
X18427-120716
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Chapter 2: Setup
Configure the Control Computer COM Port
The TRD uses the Tera Term Pro terminal emulator and the Ethernet Controller application
GUI to communicate between the control computer and the KCU1250 board. To configure
the control computer COM ports for this purpose:
1. Place switch SW1 to the OFF position. (SW1 in Figure 2-1).
2. Connect the KCU1250 board to the control computer and power supply as shown in
Figure 2-1.
TIP: Figure 2-1 shows only the top edge of the KCU1250 board.
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Figure 2-1: Connections for Preliminary Setup
3. Power on the KCU1250 board by placing switch SW1 to the ON position. (SW1 in
Figure 2-1).
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Chapter 2: Setup
X18434-120716
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4. Open the control computer Device Manager. In the Windows task bar, click Start, click
Control Panel, and then click Device Manager.
5. In the Device Manager window (Figure 2-2), expand Ports (COM & LPT), right-click
Silicon Labs CP210x USB to UART Bridge: Standard COM Port, and then click
Properties.
X-Ref Target - Figure 2-2
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Figure 2-2: Device Manager
TIP: Make note of the COM port numbers assigned by the cont rol com puter OS in your setup to Silicon
Labs CP210x USB to UART Bridge: Standard COM Port and Silicon Labs CP210x USB to UART
Bridge: Enhanced COM Port. The Enhanced COM port number must be provided to the Tera Term Pro
terminal emulator in step 2, page 15. The Standard COM port number must be provided to the Ethernet
Controller application in step 2, page 31.
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Chapter 2: Setup
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6. In the properties window, select the Port Settings tab (Figure 2-3).
7. Set Bits per second, Data bits, Parity, Stop bits, and Flow control to the values shown
in Figure 2-3, and click OK.
X-Ref Target - Figure 2-3
Figure 2-3: Port Settings
8. In the Device Manager window (Figure 2-2), expand Ports (COM & LPT), right-click
Silicon Labs CP210x USB to UART Bridge: Enhanced COM Port and then click
Properties.
9. In the properties window, select the Port Settings tab and set Bits per second, Data
bits, Parity, Stop bits, and Flow control to the values shown in (Figure 2-3), and then
click OK.
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Chapter 2: Setup
;
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Instal l Tera Term Pro Software
1. Follow the download and installation instructions provided in Tera Term Terminal
Emulator Installation Guide (UG1036) [Ref 10].
2. To communicate with the KCU1250 board, configure the new Tera Term connection and
serial port settings as shown in Figure 2-4. These settings must match the control
computer COM port settings shown in Figure 2-3. Select the serial COM port associated
with Silicon Labs Dual CP210x USB to UART Bridge: Enhanced COM Port.
X-Ref Target - Figure 2-4
Figure 2-4: Tera Ter m Pro S e t ting s
Install Java
Download Java SE Runtime Environment 7 from Oracle [Ref 11] and install the program on
the control computer. Follow the installation instructions provided with the software.
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X-Ref Target - Figure 2-5
X18437-120716
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Chapter 2: Setup
Install the Ethernet Controller Application
1. Browse to <working_dir>/kcu1250_10gbasekr_trd/software/GUI
(Figure 2-5).
Figure 2-5: Directory Location, Ethernet Controller Installer
2. Right-click either the EthernetController-32-installer (for a 32-bit operating system)
or EthernetController-64-installer (for a 64-bit operating system) and select Run as
administrator (Figure 2-5).
3. Click Yes in the dialog box that opens.
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Chapter 2: Setup
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4. In the License Agreement display (Figure 2-6), click I Agree to continue installation.
X-Ref Target - Figure 2-6
Figure 2-6: License Agreement
5. Browse to the location where the Ethernet Controller application will be installed and
click Install (Figure 2-7).
X-Ref Target - Figure 2-7
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Figure 2-7: Ethernet Controller Installation Location
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6. Click Close after installation is complete (Figure 2-8).
X18440-120716
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X-Ref Target - Figure 2-8
Chapter 2: Setup
Figure 2-8: Installation Complete
TIP: To uninstall the Ethernet Controller application after design bring up, open the Control Panel. In
the Control Panel click All Control Panel Items > Programs and Features and uninstall program
Xilinx Ethernet Controller - Powered by Xilinx.
Ready to Bring Up the Design
After all procedures in this chapter are complete, go to Chapter 3, Bringing Up the Design.
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Bringing Up the Design
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This chapter describes how to bring up the 10GBASE-KR TRD. Instructions are provided for
setting up the KCU1250 board and backplane, programming the clock, programming the
FPGA, configuring virtual input/output (VIO), and running the Ethernet Controller
application.
IMPORTANT: Perform the preliminary setup procedures described in Chapter 2, Setup before
performing the bring up procedures described in this chapter.
Set Up the KCU1250 Board
Chapter 3
Connect Bulls Eye Cables
1. Connect the SAMTEC Bulls Eye cables to J41 (GTH Transceiver Quad_226) and J42 (GTH
Transceiver Quad_227) as described in this video:
VIDEO: New GTX/GTH/GTZ Interconnect on Xilinx Characterization Boards
2. The Bulls Eye SMA cables are numbered. Cable 15 is TX0_P, cable 16 is TX0_N, cable 17
is RX0_P and cable 18 is RX0_N. Connect the AC capacitors (Aeroflex SMA DC Blocks—
[Ref 5]) to TXN and TXP SMA connector on both Bulls Eye cables. Refer to pages 51 and
52 of the KCU1250 Characterization Board Schematics (XTP398) [Ref 12].
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X-Ref Target - Figure 3-1
COL6
COUNTER
BORED
COL6
COUNTER
BORED
Trace Length 16"
TYCO BACKPLANE
RX0_P – SMA 17
TX0_P – SMA 15
TX0_N – SMA 16
RX0_N – SMA 18
J41
GT X0Y8
Bank 226
TX0_P – SMA 15
RX0_P – SMA 17
RX0_N – SMA 18
TX0_N – SMA 16
J42
GT X0Y12
Bank 227
Transmit
Receive
X18441-120716
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Chapter 3: Bringing Up the Design
3. Connect the SMA cables on the Bulls Eye connector to the Tyco backplane as shown in
Figure 3-1.
Figure 3-1: SMA Connections to the Backplane
4. SMA cable 19 is REFCLK0_C_P and cable 20 is REFCLK0_C_N. Connect cable 19 and cable
20 from J41 to the clock out pins of Oscillator Si5368 on the Superclock module.
Connect cable 19 and cable 20 from J42 to the clock out pins of Oscillator Si570 on the
Superclock module.
5. Connect the power supply to the KCU1250 board.
6. Connect one end of the Micro-USB cable to USB-UART port (J1) and the other to the
Control PC.
7. Connect one end of the Micro-USB cable to USB-JTAG port (U80) and the other to the
Control PC.
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X-Ref Target - Figure 3-2
Power Supply
100VAC–240VAC Input
12 VDC 5.0A Output
Board
Power
Switch
SW1
To U80
USB JTAG
J1
USB UART
USB cable
standard-A plug
to micro-B plug
Connect SMA cables
15,16,17 and 18 from
J42 to the backpane
Connect SMA cables
15,16,17 and 18 from
J41 to the backpane
Connect AC caps
toTXN/TXP SMAs
Connect AC caps
toTXN/TXP SMAs
Connect SMA
cables 19 and 20
from J41 to Si5368
Connect SMA
cables 19 and 20
from J42 to Si570
Super-Clock II
Module
J41J42
Wally
&RQWURO
&RPSXWHU
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All above connections are shown in Figure 3-2.
Figure 3-2: KCU1250 Board Connections Including SMA Connections to the Backplane
8. Power on the KCU1250 board by placing switch SW1 to the ON position.
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Program the Clocks Sources
The KCU1250 board uses the SuperClock-2 module to provides programmable, low-noise
and low-jitter clock sources for the KCU1250 board. See HW-CLK-101-SCLK2 SuperClock-2
Module User Guide (UG770) [Ref 13] for more information.
To program the clock sources:
1. On the control computer, open the Tera Term Pro terminal program. Click Start > All
Programs > Tera Term > Tera Term.
2. In the New connection window, configure the settings as shown in Figure 3-3. Select the
serial COM port associated with Silicon Labs Dual CP210x USB to UART Bridge: Enhanced COM Port.
Click OK.
X-Ref Target - Figure 3-3
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Figure 3-3: Connect to Enhanced COM Port on Tera Term
3. On the control computer keyboard, press the Enter key. The Tera Term window will
display the SuperClock-2 configuration menu.
4. Set Programmable Clocks:
a. Select option 1 (Set Programmable Clocks): Type 1, and press Enter.
5. Set the Si570 frequency to 156.25 MHz:
a. Select option 1 (Set KCU1250 Si570 frequency): Type 1, and press Enter.
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b. Enter the Si570 frequency in MHz: Type 156.25 and press Enter.
6. Set the Si5368 frequency to 156.25 MHz:
a. Select option 2 (Set KCU1250 Si5368 frequency): Type 2, and press Enter.
b. Enter the Si5368 frequency in MHz: Type 156.25 and press Enter.
c. Choose Si5368 operating mode (Select Free-Run using XA-XB crystal): Type 2, and
press Enter.
7. Close the Tera Term Pro terminal program window.
Program the FPGA
1. Launch the Vivado® Integrated Design Environment (IDE) on the control computer:
a. In Windows, select Start > All Programs > Xilinx Design Tools >
Vivado 2017.1 > Vivado 2017.1.
b. On the getting started page, click Open Hardware Manager (Figure 3-4).
X-Ref Target - Figure 3-4
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Figure 3-4: Open Hardware Manager
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2. Open the connection wizard to initiate a connection to the KCU1250 board:
a. Click Open a new hardware target (Figure 3-5).
X-Ref Target - Figure 3-5
Figure 3-5: Open a New Hardware Target
b. Configure the wizard to establish connection with the KCU1250 board by selecting
the default value on each wizard page. Click Next > Next > Next > Finish.
c. In the hardware view, right-click xcku040 and click Program Device (Figure 3-6).
X-Ref Target - Figure 3-6
Figure 3-6: Select Device to Program
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d. In the Bitstream file field, browse to the location of the BIT file:
<working_dir>/kcu1250_10gbasekr_trd/ready_to_test/kcu1250_10gb
asekr_download.bit
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e. In the Debug Probes file field, browse to the location of the probes file:
<working_dir>/kcu1250_10gbasekr_trd/ready_to_test/debug_nets.ltx
and click Program (Figure 3-7).
X-Ref Target - Figure 3-7
Figure 3-7: Program Device Window
After completing these steps, continue on to Configure VIO.
Configure VIO
There are six virtual I/O (VIO) cores in the reference design. After programming, each VIO
core can be controlled in the Vivado IDE. To add probes to each VIO window:
1. Open the VIO dashboard. On the top panel of the Vivado IDE, click Window >
Dashboard > Reset to default.
2. Open the Debug Probes window: on the top panel of the Vivado IDE click Window >
Debug Probes.
3. In the Debug Probes window, right click on hw_vio_1 and select Add probes to VIO
Window (Figure 3-8).
4. Repeat the same procedure for hw_vio_2, hw_vio_3, hw_vio_4, hw_vio_5 and
hw_vio_6.
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X-Ref Target - Figure 3-8Add probes to the VIO dashboard
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Figure 3-8: Adding a Probe to a VIO Window
Table 3-1 shows what each VIO window configures and monitors.
Table 3-1: VIO Tab Mapping
VIO Tab Mapping Comments
hw_vio_6
hw_vio_5
hw_vio_4
hw_vio_3
hw_vio_2
hw_vio_1
Notes:
1. The value of n in hw_vio_n might change based on how the Vivado Synthesis tool processes the netlist. You might have to
redo the above mapping accordingly.
(1)
(1)
(1)
(1)
(1)
(1)
training_*_ch1
training_*_ch0
stat_ch1_*
stat_ch0_*
ch1_*
ch0_*
Configures the DRP port for channel 1 through the training port of the
10-Gigabit Ethernet PCS/PMA IP core.
Configures the DRP port for channel 0 through the training port of the
10-Gigabit Ethernet PCS/PMA IP core.
Monitors the status vector signals of the 10-Gigabit Ethernet PCS/PMA
IP core for channel 1.
Monitors the status vector signals of the 10-Gigabit Ethernet PCS/PMA
IP core for channel 0.
Configures the configuration vector signals of the 10-Gigabit Ethernet
PCS/PMA IP core for channel 1.
Configures the configuration vector signals of the 10-Gigabit Ethernet
PCS/PMA IP core for channel 0.
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X-Ref Target - Figure 3-9
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5. Verify if stat_ch0_pcs_rx_link_status and stat_ch1_pcs_rx_link_status is 1. This indicates
that the 10GBASE-R link is up (Figure 3-9).
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Figure 3-9: Verify Link Status
6. Enable FEC, Training and Auto Negotiation on both channels by configuring signals in
the ch0_* and ch1_* VIO windows. Here is the sequence to follow:
a. Advertise Channel 1 is KR capable:
Set value 0080 on ch1_an_adv_data_31_16
b. Advertise Channel 1 supports FEC and is requesting FEC support from the partner:
Set value C000 on ch1_an_adv_data_47_32
c. Pulse ch1_an_ad to load the AN data bits for Channel 1:
Set value 1 on ch1_an_ad
Set value 0 on ch1_an_ad
d. Advertise Channel 0 is KR capable:
Set value 0080 on ch0_an_adv_data_31_16
e. Advertise Channel 0 supports FEC and is requesting FEC support from the partner:
Set value C000 on ch0_an_adv_data_47_32
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f. Pulse ch0_an_ad to load the AN data bits for Channel 0:
Set value 1 on ch0_an_ad
Set value 0 on ch0_an_ad
g. Enable FEC on channel 1:
Set value 1 on ch1_enable_fec
h. Enable FEC on channel 0:
Set value 1 on ch0_enable_fec
i. Set Training done to 1 on channel 1. This indicates to Training Algorithm that the LP
transmitter has been successfully trained:
Set value 1 on ch1_training_done
j. Enable Training on channel 1:
Set value 1 on ch1_enable_training
IMPORTANT: Due to strict timing requirements on ch1_training_done, and the slow nature of executing
Tcl commands in Vivado, the ch1_training_done command is executed before the ch1_enable_training
command. This might not be true if executing these commands from a microprocessor.
k. Set Training done to 1 on channel 0. This indicates to the Training Algorithm that the
LP transmitter has been successfully trained:
Set value 1 on ch0_training_done
l. Enable Training on channel 0:
Set value 1 on ch0_enable_training
IMPORTANT: Due to strict timing requirements on ch0_training_done, and the slow nature of executing
Tcl commands in Vivado, the ch0_training_done command is executed before ch0_enable_training
command. This may not be true if executing these commands from a microprocessor.
m. Enable Auto Negotiation on channel 1:
Set value 1 on ch1_en_auto_negotiation
n. Enable Auto Negotiation on channel 0:
Set value 1 on ch0_en_auto_negotiation
o. Pulse Reset Auto Negotiation on channel 1:
Set value 1 on ch1_reset_autonegotiation, and then
Set value 0 on ch1_reset_autonegotiation
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IMPORTANT: Only reset one side of the channel. In this example, only Channel 1 is reset.
To toggle the VIO signals in the sequence as described in step 6 a Tcl script is provided
in:
<working_dir>/kcu1250_10gbasekr_trd/ready_to_test/en_fec_tr_an.tcl
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