Xilinx KC724 IBERT Getting Started Manual

KC724 IBERT
Getting Started Guide
(ISE Design Suite 14.3)

UG930 (v1.0) October 23, 2012

This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4

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Revision History

The following table shows the revision history for this document.

Date Version Revision

10/23/12 1.0 Initial Xilinx release.

KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: KC724 IBERT Getting Started Guide

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Setting Up the KC724 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Running the GTX IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Connecting the GTX Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . 7

Attach the GTX Quad Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

GTX Transceiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

GTX TX/RX Loopback Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Setting Up the ChipScope Pro Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Starting the SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Viewing GTX Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

In Case of RX Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Closing the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SuperClock-2 Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Creating the GTX IBERT Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Appendix A: Warranty

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Chapter 1

KC724 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the KC724 Kintex™-7 FPGA
GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the ISE Design Suite. The designs that are required to run the IBERT
demonstration are stored in a Secure Digital (SD) memory card that is provided with the
KC724 board. The demonstration shows the capabilities of the Kintex-7 XC7K325T FPGA
GTX transceiver.

Overview

The KC724 board is described in detail in UG932
Characterization Board User Guide.

The IBERT demonstrations operate one GTX Quad at a time. The procedure consists of:

1. Setting Up the KC724 Board.

2. Extracting the Project Files.

3. Connecting the GTX Transceivers and Reference Clocks.

4. Configuring the FPGA.

5. Setting Up the ChipScope Pro Software.

6. Viewing GTX Transceiver Operation.

7. Closing the IBERT Demonstration.

, KC724 Kintex-7 FPGA GTX Transceiver

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UG930 (v1.0) October 23, 2012

Chapter 1: KC724 IBERT Getting Started Guide

Requirements

The hardware and software required to run the GTX IBERT demonstrations are:

• KC724 Kintex-7 FPGA GTX Transceiver Characterization Board including:

• One SD card containing the IBERT demonstration designs

•One Samtec BullsEye cable

• Eight SMA female-to-female (F-F) adapters

•Six 50Ω SMA terminators

• GTX transceiver power supply module (installed on board)

• SuperClock-2 module, Rev 1.0 (installed on board)

•Active BGA Heatsink (installed on FPGA)

• 12V DC power adapter

• USB cable, standard-A plug to micro-B plug

• Host PC with:

• SD card reader

•USB ports

• Xilinx® ChipScope™ Pro software, version 14.3 or higher.
Software is available at: http://www.xilinx.com/chipscopepro

The hardware and software required to rebuild the IBERT demonstration designs are:

• Xilinx ISE® Design Suite version 14.3 or higher

• PC with a version of the Windows operating system supported by Xilinx ISE Design
Suite

Setting Up the KC724 Board

This section describes how to set up the KC724 board.

Caution!

ESD prevention measures when handling the board.

When the KC724 board ships from the factory, it is configured for the GTX IBERT
demonstrations described in this document. If the board has been re-configured it must be
returned to the default set-up before running the IBERT demonstrations.

1. Move all jumpers and switches to their default positions. The default jumper and

2. Install the GTX transceiver power module by plugging it into connectors J66 and J97.

3. Install the SuperClock-2 module:

The KC724 board can be damaged by electrostatic discharge (ESD). Follow standard

switch positions are listed in UG932
Characterization Board User Guide.

a. Align the three metal standoffs on the bottom side of the module with the three

mounting holes in the SUPERCLOCK-2 MODULE interface of the KC724 board.

b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the

bottom of the KC724 board.

c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the

CONTROL VOLTAGE header, J18, and place another jumper across Si570 INH
header J11.

, KC724 Kintex-7 FPGA GTX Transceiver

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d. Screw down a 50Ω SMA terminator onto each of the six unused Si5368 clock

output SMA connectors: J7, J8, J12, J15, J16 and J17.

Extracting the Project Files

The ChipScope Pro Software .cpj project files for the IBERT demonstrations are located in
kc724_cpj.zip on the SD card provided with the KC724 board. They are also available
online along with .bit files for all four designs (as collection rdf0183_<ISE
version>.zip) at:

http://www.xilinx.com/kc724

kc724_cpj.zip contains four project files: kc724_q115.cpj,kc724_q116.cpj,
kc724_q117.cpj, and kc724_q118.cpj. These files are used to load pre-saved

MGT/IBERT and SuperClock-2 module control settings for the GTX demonstrations.

To copy the files from the Secure Digital memory card:

1. Connect the Secure Digital memory card to the host computer.

2. Locate the file kc724_cpj.zip on the Secure Digital memory card.

3. Unzip the files to a working directory on the host computer.

Extracting the Project Files

Running the GTX IBERT Demonstration

The GTX IBERT demonstration operates one GTX Quad at a time. This section describes
how to test GTX Quad 115. The remaining GTX Quads are tested following a similar series
of steps.

Connecting the GTX Transceivers and Reference Clocks

Figure 1-1 shows the locations for GTX transceiver Quads 115, 116, 117, and 118 on the

KC724 board.

Note:

Figure 1-1 is for reference only and might not reflect the current revision of the board.

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UG930_c1_01_061412

QUAD_116

QUAD_115

QUAD_118

QUAD_117

X-Ref Target - Figure 1-1

Figure 1-1: GTX Quad Locations

All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors. Figure 1-2
pad. Figure 1-2

B shows the connector pinout.

A shows the connector

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X-Ref Target - Figure 1-2

Running the GTX IBERT Demonstration

X-Ref Target - Figure 1-3

SI570_CLK_P

A

B

GTX

CLK1

P

N

GTX Connector Pad

P

CLK0

P

RX0

P

TX0

P

TX1

P

RX1

GTX Connector Pinout

N

P

N

N

P

N

N

P

N

N

P

N

N

UG930_c1_02_101612

RX3

TX3

TX2

RX2

Figure 1-2: A – GTX Connector Pad. B – GTX Connector Pinout

The SuperClock-2 module provides LVDS clock outputs for the GTX transceiver reference
clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the differential clock
SMA connectors on the clock module which can be connected to the reference clock cables.

Note:

board.

The image in Figure 1-3 is for reference only and might not reflect the current revision of the

CLKOUT1_P

CLKOUT2_P CLKOUT3_P CLKOUT4_P

SI570_CLK_N

Figure 1-3: SuperClock-2 Module Output Clock SMA Locations

The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.

Note:

SuperClock-2 module.

The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the

For the GTX IBERT demonstration, the output clock frequencies are preset to 125.000 MHz.
For more information regarding the SuperClock-2 module, refer to UG770
HW-CLK-101-SCLK2 SuperClock-2 Module User Guide.

Attach the GTX Quad Connector

Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if

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CLKOUT1_N

CLKOUT2_N CLKOUT4_N

CLKOUT3_N

UG930_c1_03_061412

,