Xilinx KC705 Evaluation Board for the Kintex-7 FPGA User Manual

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KC705 Evaluation Board for the Kintex-7 FPGA

User Guide

UG810 (v1.8) March 20, 2018

Revision History

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The following table shows the revision history for this document.

Date Version Revision

03/20/2018 1.8 In Table 1-1, Quad SPI Flash Memory, and [Ref 5], added Micron

MT25QL128ABA8ESF-0SIT as a possible part for U7. In Table 1-24, the I2C addresses were updated for the FMC HPC and FMC LPC device rows.

07/08/2016 1.7 Updated VRP/VRN resistor connection information in DDR3 Memory Module.

Moved the Additional Resources and Legal Notices appendix to the end of the book.

08/26/2015 1.6.2 In Table 1-9, the I/O standard for SYSCLK_N and SYSCLK_P were updated to LVDS.

In Table 1-27, under Directional Pushbutton Switches, the I/O standard for GPIO_SW_C was updated to LVCMOS25. Updated the #USB UART section of

Appendix C, Master Constraints File Listing.

04/13/2015 1.6.1 In HPC Connector J22, page 63, the GTX clock count changed from 1 to 2. Updated

links.

12/08/2014 1.6 Added a note about jumper header locations below Table 1-1. Changed Table 1-5

heading J1 DDR3 Memory to U58 BPI Flash Memory. Parts PC28F00AP30TF and N25Q128A13BSF40F changed from Numonyx to Micron. Described J11 and J12 connections in User SMA Clock Input, page 30. Made these updates in

Programmable User Clock Source, page 29: XTP186 became XTP204, RDF0175

became RDF0194, XTP187 became XTP203, and RDF0176 became RDF0193. Corrected the device in the heading of Table 1-20 from CP2013 to CP2103. Updated

I2C Bus Switch, page 52. Updated Table 1-24 I2C devices. In Table 1-28, J22 pin G7

connects to FPGA U1 pin C27. Replaced Table A-3, KC705 Default Jumper Settings and added

Appendix C, Master Constraints File Listing. Added information about ordering the

custom ATX cable to Appendix F, Regulatory Compliance and Information, [Ref 20].

07/11/2014 1.5 Corrected MGT Quad connection information in GTX Transceivers, page 33 and a

connection in Table 1-10. Added MGTREFCLK1 - PCIE_CLK from P1 to Quad 115 in

GTX Transceivers, page 33. Updated Table 1-4, Table 1-5, Table 1-6, Table 1-7, Table 1-9, Table 1-18, Table 1-21, Table 1-23, Table 1-27, Table 1-28, and Table 1-29. Added table footnotes regarding I/O standard and pins prior to board

revision 1.1 to Table 1-14. Clarified default jumper positions in Table 1-15. Corrected the J2 C19 pin number in Table 1-29. In Figure 1-40, changed pin names VBATT to VCCBATT and POUC_B to PUDC_B. Removed three pins from KC705 Board

XDC Listing, page 88 (PACKAGE _PIN R8, R7, and W8). The Appendix C title changed

to Master Constraints File Listing and the constraints file in Appendix C was replaced. The Declaration of Conformity link in Appendix F was updated.

07/18/2013 1.4 Revised the format of Table 1-20 and added the I/O standard column. Revised the

FPGA U1 pin for FMC_HPC_CLK0_M2C_N in Table 1-28 to C27 on page 59. Revised the descriptions of the functions for SW13 position 3 and position 5 in Table A-2. In Appendix C, Master Constraints File Listing, changed appendix title from Master UCF Listing to Master Board Constraints, replaced references to the term UCF with the term XDC and replaced the KC705 Board UCF Listing with the KC705 Board XDC

Listing.

Figure A-3 to show jumper locations. Replaced the constraints file in

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Date Version Revision

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05/10/2013 1.3 Updated Figure 1-1 to show v 1.1 board. Updated Table 1-1, page 10: callout 1 to

identify Fansink, callouts 25and 26 pointing to User I/O. Added Table 1-9 Clock Source to FPGA U1 Connections. Updated Programmable User Clock Source,

page 29 to include I2C address. Updated Table 1-17, page 43 for naming pins 18

and 19. Added Note to Table 1-14, page 42. Updated I2C Bus Switch, page 52 to show TI device instead of NXP Semiconductor, deleted; updated [Ref 19]. Added

Figure 1-28, page 57 Rotary Switch, and Figure 1-29, page 58 GPIO SMAs J13 and

J14. Added Note to Appendix C, Master Constraints File Listing. Updated

Appendix D, Board Setup, step 1 of installation procedure. Updated Appendix F,

Additional Resources to include CE PC Test reference.

12/10/2012 1.2 Replaced direct, inline links to external references in the body text with indirect

references to the links in a numbered list in Appendix G, Additional Resources and

Legal Notices. Revised the value for frequency jitter for the System Clock Source, page 29. Reset conditions are added to Jitter Attenuated Clock, page 32 Revised

jumper information for SFP_RS1, page 42 in Table 1-15. Revised contents and organization of Appendix F, Additional Resources.

04/05/2012 1.1 Updated links from Table 1-1, page 10. Revised the JTAG configuration mode USB

cable description under FPGA Configuration, page 12. Added Encryption Key

Backup Circuit, page 13 and Table 1-4, page 15. Added links to User SMA Clock

Input in Table 1-8, page 28. Added link to Si570 device vendor on page 30. Added

Ethernet PHY Status LEDs, page 54 and Figure 1-24, page 54. Updated Power On/Off Slide Switch SW15, page 60 and added Figure 1-32, page 61. Revised FPGA Mezzanine Card Interface, page 63 and Table 1-28, page 64 and Table 1-29, page 69. Added description of power module cooling requirement to Power Management, page 71. Added Cooling Fan Control, page 74. Updated Table 1-35, page 80. Added references to Documents, page 85. Added Appendix E, Compliance with European Union Directives and Standards, Appendix D, Board Setup, and Appendix E, Board Specifications.

01/23/2012 1.0 Initial Xilinx release.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: KC705 Evaluation Board Features

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Appendix A: Default Switch and Jumper Settings

DIP Switch SW11 User GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

DIP Switch SW13 Mode and Flash Memory Address Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Appendix B: VITA 57.1 FMC Connector Pinouts

Appendix C: Master Constraints File Listing

KC705 Board XDC Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Appendix D: Board Setup

Installing KC705 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Appendix E: Board Specifications

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Appendix F: Regulatory Compliance and Information

Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Appendix G: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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KC705 Evaluation Board Features

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Overview

The KC705 evaluation board for the Kintex®-7 FPGA provides a hardware environment for developing and evaluating designs targeting the Kintex-7 XC7K325T-2FFG900C FPGA. The KC705 board provides features common to many embedded processing systems, including a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART interface. Other features can be added by using FPGA Mezzanine Cards (FMCs) attached to either of two VITA-57 FPGA mezzanine connectors provided on the board. High pin count (HPC) and low pin count (LPC) FMCs are provided. See KC705 Board Features for a complete list of features. The details for each feature are described in Feature Descriptions, page 9.

Chapter 1

Additional Information

See Appendix G, Additional Resources and Legal Notices for references to documents, files, and resources relevant to the KC705 board.

KC705 Board Features

• Kintex-7 XC7K325T-2FFG900C FPGA

• 1 GB DDR3 memory SODIMM

• 128 MB Linear Byte Peripheral Interface (BPI) flash memory

• 128 Mb Quad Serial Peripheral Interface (SPI) flash memory

• Secure Digital (SD) connector

• USB JTAG via Digilent module

•Clock generation

Fixed 200 MHz LVDS oscillator (differential)

Inter-integrated circuit (I2C) programmable LVDS oscillator (differential)

SMA connectors (differential)

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SMA connectors for GTX transceiver clocking

• GTX transceivers

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FMC HPC connector (four GTX transceivers)

FMC LPC connector (one GTX transceiver)

SMA connectors (one pair each for TX, RX, and REFCLK)

PCI Express (eight lanes)

Small form-factor pluggable plus (SFP+) connector

Ethernet PHY SGMII interface (RJ-45 connector)

• PCI Express endpoint connectivity

Gen1 8-lane (x8)

Gen2 8-lane (x8)

• SFP+ Connector

• 10/100/1000 tri-speed Ethernet PHY

• USB-to-UART bridge

Chapter 1: KC705 Evaluation Board Features

• High-Definition Multimedia Interface ™ (HDMI) technology codec

•I2C bus

I2C mux

I2C EEPROM (1 KB)

USER I2C programmable LVDS oscillator

DDR3 SODIMM socket

HDMI codec

FMC HPC connector

FMC LPC connector

SFP+ connector

I2C programmable jitter-attenuating precision clock multiplier

•Status LEDs

Ethernet status

Power good

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FPGA INIT

FPGA DONE

•User I/O

USER LEDs (eight GPIO)

User pushbuttons (five directional)

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CPU reset pushbutton

User DIP switch (4-pole GPIO)

User edge drive rotary encoder switch

User SMA GPIO connectors (one pair)

LCD character display (16 characters x 2 lines)

•Switches

Power on/off slide switch

FPGA_PROG_B pushbutton switch

• VITA 57.1 FMC HPC Connector

• VITA 57.1 FMC LPC Connector

• Power management

PMBus voltage and current monitoring via TI power controller

Chapter 1: KC705 Evaluation Board Features

• XADC header

• Configuration options

Linear BPI flash memory

Quad SPI flash memory

USB JTAG configuration port

Platform cable header JTAG configuration port

The KC705 board block diagram is shown in Figure 1-1. The KC705 board schematics are available for download from the Kintex-7 FPGA KC705 Evaluation Kit website.

CAUTION! The KC705 board can be damaged by electrostatic discharge (ESD). Follow standard ESD

prevention measures when handling the board.

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X-Ref Target - Figure 1-1

UG810_c1_01_011812

Kintex-7 FPGA

XC7K325T-2FFG900C

128 MB Linear BPI

Flash memory

128 Mb Quad-SPI

Flash Memory

8-lane PCI Express

Edge Connector

LCD Display

(2 line x 16 characters)

1 KB EEPROM (I2C)

I2C Bus Switch

XADC Header

User Switches,

Buttons, and LEDs

HDMI Video

Interface

Differential Clock

GTX SMA Clock

1 GB DDR3 Memory

(SODIMM)

FMC Connectors

(HPC/LPC)

10/100/1000 Ethernet

Interface

DIP Switch SW13

Config and Flash Addr

USB-to-UART Bridge

JTAG Interface

mini-B USB Connector

SFP+ Single Cage

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Chapter 1: KC705 Evaluation Board Features

Figure 1-1: KC705 Board Block Diagram

Feature Descriptions

Figure 1-2 shows the KC705 board. Each numbered feature that is referenced in Figure 1-2

is described in the sections that follow.

Note:

board.

The image in Figure 1-2 is for reference only and might not reflect the current revision of the

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X-Ref Target - Figure 1-2

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Round callout references a component

on the front side of the board

Chapter 1: KC705 Evaluation Board Features

Square callout references a component

on the back side of the board

Figure 1-2: KC705 Board Components

Table 1-1: KC705 Board Component Descriptions

User rotary switch

located under LCD

UG841_c1_02_042313

Callout

1U1Kintex-7 FPGA (Located under

2J1DDR3 Memory Module, under EMI

Reference

Designator

Component Description Notes

XC7K325T-2FFG900C, Radian

fansink)

INC3001-7_1.5BU_LI98

Micron MT8JTF12864HZ-1G6G1 15

Page Number

shield

3U58Linear BPI Flash Memory Micron PC28F00AP30TF 26

4U7Quad SPI Flash Memory Micron N25Q128A13BSF40F or

Micron MT25QL128ABA8ESF-0SIT

5U9SD Card Interface Molex 67840-8001 28

6 USB JTAG Module Digilent USB JTAG Module (with

micro-B receptacle)

7U6System Clock Source (back side of

SiTime SIT9102-243N25E200.0000 23

board)

8U45Programmable User Clock Source

Silicon Labs SI570BAB0000544DG 23

(back side of board)

9 J11, J12 User SMA Clock Input Rosenberger 32K10K-400L5 23

10 J15, J16 GTX SMA Clock Input Rosenberger 32K10K-400L5 23

11 U70 Jitter Attenuated Clock Silicon Labs SI5324C-C-GM 24

Schematic

0381397

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Table 1-1: KC705 Board Component Descriptions (Cont’d)

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Chapter 1: KC705 Evaluation Board Features

Callout

12 GTX Transceivers Embedded within FPGA U1 9

13 P1 PCI Express Edge Connector 8-lane card edge connector 21

14 P5 SFP/SFP+ Connector Molex 74441-0010 22

15 U37 10/100/1000 Tri-Speed Ethernet

16 U2 SGMII GTX Transceiver Clock

17 J6, U12 USB-to-UART Bridge Silicon Labs CP2103GM bridge

18 P6, U65 HDMI Video Output Molex 500254-1927, Analog

19 J31 LCD Character Display 2 x 7 0.1 in male pin header 30

20 U49 I2C Bus Switch, page 52 TI PCA9548ARGER 32

21 DS11 - DS13 Ethernet PHY Status LEDs EPHY status LED, dual green 25

34 DS14, DS20 -

22 DS1 - DS4,

Reference

Designator

DS24

Ds10,

DS25 - DS27

Component Description Notes

Page Number

Marvell M88E1111-BAB1C000 25

PHY

ICS ICS84402IAGI-01LF 23

Generator

(back side of board) and min-B receptacle (front side of board)

Devices ADV7511KSTZ-P

Status LEDs Status LEDs, green 29

User GPIO LEDs GPIO LEDs, green 29

Schematic

0381397

34, 33

23 SW2 – SW6 User Pushbuttons E-Switch TL3301EP100QG 29

24 SW11 GPIO DIP Switch C and K 4-pole, SDA05H1SBD 29

25 SW8 Rotary Switch Panasonic EVQ-WK4001 29

26 J13, J14 GPIO SMA Connectors Rosenberger 32K10K-400L5 23

27 SW15 Power On/Off Slide Switch SW15 C and K 1201M2S3AQE2 35

28 SW14 FPGA_PROG_B Pushbutton SW14

(Active-Low)

29 SW13 Configuration Mode and Upper

Linear Flash Address Switch (SW13)

30 J22 HPC Connector J22 Samtec ASP_134486_01 16-19

31 J2 LPC Connector J2 Samtec ASP_134603_01 20

32 U55, U21,

U103, U17, U56, U104, U105, U89, U106, U99,

U71, U62,

U17, U18, U33

33 J46 XADC Header 2X10 0.1" male header 31

Power Management (voltage

regulators front side of board, controllers back side of board)

E-Switch TL3301EP100QG 29

5-pole C and K SDA05H1IBD 27

TI UCD9248PFC controllers in conjunction with various regulators

35-46

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Table 1-1: KC705 Board Component Descriptions (Cont’d)

UG810_c1_03_011112

SW13

OFF Position = 0

ON Position = 1

2345

A25

A24

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Chapter 1: KC705 Evaluation Board Features

Callout

34 J60 2 x 7 2 mm shrouded JTAG cable

35 J39 2 x 5 shrouded PMBus connector Assman HW10G-0202 35

36 J49 12V power input 2 x 3 connector Molex 39-30-1060 35

37 SW7 CPU Reset Pushbutton E-Switch TL3301EP100QG 35

Reference

Designator

Component Description Notes

Page Number

Molex 87832-1420 16

connector

Note: Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.

Kintex-7 FPGA

[Figure 1-2, callout 1]

The KC705 board is populated with the Kintex-7 XC7K325T-2FFG900C FPGA.

For further information on Kintex-7 FPGAs, see

FPGA Configuration

7 Series FPGAs Overview (DS180) [Ref 1].

Schematic

0381397

The KC705 board supports three of the five 7 series FPGA configuration modes:

• Master SPI flash memory using the onboard Quad SPI flash memory

• Master BPI flash memory using the onboard Linear BPI flash memory

• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the KC705 board configuration port

Each configuration interface corresponds to one or more configuration modes and bus widths as listed in Table 1-2. The mode switches M2, M1, and M0 are on SW13 positions 3, 4, and 5 respectively as shown in Figure 1-3.

X-Ref Target - Figure 1-3

Figure 1-3: SW13 Default Settings

The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on. Refer to the Configuration Options, page 80 for detailed information about the mode switch SW13.

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Table 1-2: KC705 Board FPGA Configuration Modes

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Chapter 1: KC705 Evaluation Board Features

Configuration Mode

SW13 DIP Switch Settings (M[2:0])

Bus Width CCLK Direction

Master SPI 001 x1, x2, x4 Output

Master BPI 010 x8, x16 Output

JTAG 101 x1 Not applicable

For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide (UG470) [Ref 2].

Encryption Key Backup Circuit

FPGA U1 implements bitstream encryption key technology. The KC705 board provides the encryption key backup battery circuit shown in Figure 1-4. The rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to FPGA U1 VCCBATT pin C10. The battery supply current I board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series diode with a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.62V.

X-Ref Target - Figure 1-4

D11 40V

200 mW

specification is 150 nA max when

BATT

VCCAUX_IO (2.0V)

BAS40-04

R406

4.70K 1%

To FPGA U1 Pin C10

(VCCBATT)

FPGA_VBATT

1/16W

Lithium Battery Seiko TS518SE_FL35E

GND

UG810_c1_04_031214

Figure 1-4: Encryption Key Backup Circuit

I/O Voltage Rails

There are 10 I/O banks available on the Kintex-7 device. The voltages applied to the FPGA I/O banks used by the KC705 board are listed in Table 1-3.

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Chapter 1: KC705 Evaluation Board Features

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Table 1-3: I/O Voltage Rails

U1 FPGA Bank Power Supply Rail Net Name Voltage

Bank 0 VCC2V5_FPGA 2.5V

Bank 12

Bank 13

Bank 14 VCC2V5_FPGA 2.5V

Bank 15 VCC2V5_FPGA 2.5V

Bank 16

Bank 17

Bank 18

Bank 32 VCC1V5_FPGA 1.5V

Bank 33 VCC1V5_FPGA 1.5V

Bank 34 VCC1V5_FPGA 1.5V

Notes:

1. The VADJ_FPGA rail can support 1.8V, 2.5V, or 3.3V. For more information on VADJ_FPGA see Power Management,

page 71.

(1)

VADJ_FPGA 2.5V (default)

DDR3 Memory Module

[Figure 1-2, callout 2]

The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code and data.

• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)

• Supply voltage: 1.5V

• Datapath width: 64 bits

• Data rate: Up to 1,600 MT/s

The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V high-performance (HP) bank. The VRP/VRN DCI resistor connection to bank 33 is cascaded to the data interface banks 32 and 34 by adding the DCI cascade constraint to the XDC:

# Set DCI_CASCADE set_property slave_banks {32 34} [get_iobanks 33]

An external 0.75V reference VTTREF is provided for data interface banks 32 and 34. Any interface connected to these banks that requires a reference voltage must use this FPGA voltage reference. The connections between the DDR 3 memory and the FPGA are listed in

Table 1-4.

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Chapter 1: KC705 Evaluation Board Features

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Table 1-4: DDR3 Memory Connections to the FPGA

J1 DDR3 Memory

U1 FPGA

Net Name I/O Standard

Number

AH12 DDR3_A0 SSTL15 98 A0

AG13 DDR3_A1 SSTL15 97 A1

AG12 DDR3_A2 SSTL15 96 A2

AF12 DDR3_A3 SSTL15 95 A3

AJ12 DDR3_A4 SSTL15 92 A4

AJ13 DDR3_A5 SSTL15 91 A5

AJ14 DDR3_A6 SSTL15 90 A6

AH14 DDR3_A7 SSTL15 86 A7

AK13 DDR3_A8 SSTL15 89 A8

AK14 DDR3_A9 SSTL15 85 A9

Pin Name

AF13 DDR3_A10 SSTL15 107 A10/AP

AE13 DDR3_A11 SSTL15 84 A11

AJ11 DDR3_A12 SSTL15 83 A12_BC_N

AH11 DDR3_A13 SSTL15 119 A13

AK10 DDR3_A14 SSTL15 80 A14

AK11 DDR3_A15 SSTL15 78 A15

AH9 DDR3_BA0 SSTL15 109 BA0

AG9 DDR3_BA1 SSTL15 108 BA1

AK9 DDR3_BA2 SSTL15 79 BA2

AA15 DDR3_D0 SSTL15 5 DQ0

AA16 DDR3_D1 SSTL15 7 DQ1

AC14 DDR3_D2 SSTL15 15 DQ2

AD14 DDR3_D3 SSTL15 17 DQ3

AA17 DDR3_D4 SSTL15 4 DQ4

AB15 DDR3_D5 SSTL15 6 DQ5

AE15 DDR3_D6 SSTL15 16 DQ6

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Y15 DDR3_D7 SSTL15 18 DQ7

AB19 DDR3_D8 SSTL15 21 DQ8

AD16 DDR3_D9 SSTL15 23 DQ9

AC19 DDR3_D10 SSTL15 33 DQ10

AD17 DDR3_D11 SSTL15 35 DQ11

Chapter 1: KC705 Evaluation Board Features

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Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

U1 FPGA

AA18 DDR3_D12 SSTL15 22 DQ12

AB18 DDR3_D13 SSTL15 24 DQ13

AE18 DDR3_D14 SSTL15 34 DQ14

AD18 DDR3_D15 SSTL15 36 DQ15

AG19 DDR3_D16 SSTL15 39 DQ16

AK19 DDR3_D17 SSTL15 41 DQ17

AG18 DDR3_D18 SSTL15 51 DQ18

AF18 DDR3_D19 SSTL15 53 DQ19

AH19 DDR3_D20 SSTL15 40 DQ20

AJ19 DDR3_D21 SSTL15 42 DQ21

AE19 DDR3_D22 SSTL15 50 DQ22

AD19 DDR3_D23 SSTL15 52 DQ23

AK16 DDR3_D24 SSTL15 57 DQ24

Net Name I/O Standard

Number

Pin Name

J1 DDR3 Memory

AJ17 DDR3_D25 SSTL15 59 DQ25

AG15 DDR3_D26 SSTL15 67 DQ26

AF15 DDR3_D27 SSTL15 69 DQ27

AH17 DDR3_D28 SSTL15 56 DQ28

AG14 DDR3_D29 SSTL15 58 DQ29

AH15 DDR3_D30 SSTL15 68 DQ30

AK15 DDR3_D31 SSTL15 70 DQ31

AK8 DDR3_D32 SSTL15 129 DQ32

AK6 DDR3_D33 SSTL15 131 DQ33

AG7 DDR3_D34 SSTL15 141 DQ34

AF7 DDR3_D35 SSTL15 143 DQ35

AF8 DDR3_D36 SSTL15 130 DQ36

AK4 DDR3_D37 SSTL15 132 DQ37

AJ8 DDR3_D38 SSTL15 140 DQ38

AJ6 DDR3_D39 SSTL15 142 DQ39

AH5 DDR3_D40 SSTL15 147 DQ40

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AH6 DDR3_D41 SSTL15 149 DQ41

AJ2 DDR3_D42 SSTL15 157 DQ42

Chapter 1: KC705 Evaluation Board Features

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Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

U1 FPGA

AH2 DDR3_D43 SSTL15 159 DQ43

AH4 DDR3_D44 SSTL15 146 DQ44

AJ4 DDR3_D45 SSTL15 148 DQ45

AK1 DDR3_D46 SSTL15 158 DQ46

AJ1 DDR3_D47 SSTL15 160 DQ47

AF1 DDR3_D48 SSTL15 163 DQ48

AF2 DDR3_D49 SSTL15 165 DQ49

AE4 DDR3_D50 SSTL15 175 DQ50

AE3 DDR3_D51 SSTL15 177 DQ51

AF3 DDR3_D52 SSTL15 164 DQ52

AF5 DDR3_D53 SSTL15 166 DQ53

AE1 DDR3_D54 SSTL15 174 DQ54

AE5 DDR3_D55 SSTL15 176 DQ55

Net Name I/O Standard

Number

Pin Name

J1 DDR3 Memory

AC1 DDR3_D56 SSTL15 181 DQ56

AD3 DDR3_D57 SSTL15 183 DQ57

AC4 DDR3_D58 SSTL15 191 DQ58

AC5 DDR3_D59 SSTL15 193 DQ59

AE6 DDR3_D60 SSTL15 180 DQ60

AD6 DDR3_D61 SSTL15 182 DQ61

AC2 DDR3_D62 SSTL15 192 DQ62

AD4 DDR3_D63 SSTL15 194 DQ63

Y16 DDR3_DM0 SSTL15 11 DM0

AB17 DDR3_DM1 SSTL15 28 DM1

AF17 DDR3_DM2 SSTL15 46 DM2

AE16 DDR3_DM3 SSTL15 63 DM3

AK5 DDR3_DM4 SSTL15 136 DM4

AJ3 DDR3_DM5 SSTL15 153 DM5

AF6 DDR3_DM6 SSTL15 170 DM6

AC7 DDR3_DM7 SSTL15 187 DM7

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AC15 DDR3_DQS0_N DIFF_SSTL15 10 DQS0_N

AC16 DDR3_DQS0_P DIFF_SSTL15 12 DQS0_P

Chapter 1: KC705 Evaluation Board Features

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Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

U1 FPGA

Y18 DDR3_DQS1_N DIFF_SSTL15 27 DQS1_N

Y19 DDR3_DQS1_P DIFF_SSTL15 29 DQS1_P

AK18 DDR3_DQS2_N DIFF_SSTL15 45 DQS2_N

AJ18 DDR3_DQS2_P DIFF_SSTL15 47 DQS2_P

AJ16 DDR3_DQS3_N DIFF_SSTL15 62 DQS3_N

AH16 DDR3_DQS3_P DIFF_SSTL15 64 DQS3_P

AJ7 DDR3_DQS4_N DIFF_SSTL15 135 DQS4_N

AH7 DDR3_DQS4_P DIFF_SSTL15 137 DQS4_P

AH1 DDR3_DQS5_N DIFF_SSTL15 152 DQS5_N

AG2 DDR3_DQS5_P DIFF_SSTL15 154 DQS5_P

AG3 DDR3_DQS6_N DIFF_SSTL15 169 DQS6_N

AG4 DDR3_DQS6_P DIFF_SSTL15 171 DQS6_P

AD1 DDR3_DQS7_N DIFF_SSTL15 186 DQS7_N

Net Name I/O Standard

Number

Pin Name

J1 DDR3 Memory

AD2 DDR3_DQS7_P DIFF_SSTL15 188 DQS7_P

AD8 DDR3_ODT0 SSTL15 116 ODT0

AC10 DDR3_ODT1 SSTL15 120 ODT1

AK3 DDR3_RESET_B LVCMOS15 30 RESET_B

AC12 DDR3_S0_B SSTL15 114 S0_B

AE8 DDR3_S1_B SSTL15 121 S1_B

AJ9 DDR3_TEMP_EVENT SSTL15 198 EVENT_B

AE9 DDR3_WE_B SSTL15 113 WE_B

AC11 DDR3_CAS_B SSTL15 115 CAS_B

AD9 DDR3_RAS_B SSTL15 110 RAS_B

AF10 DDR3_CKE0 SSTL15 73 CKE0

AE10 DDR3_CKE1 SSTL15 74 CKE1

AH10 DDR3_CLK0_N DIFF_SSTL15 103 CK0_N

AG10 DDR3_CLK0_P DIFF_SSTL15 101 CK0_P

AF11 DDR3_CLK1_N DIFF_SSTL15 104 CK1_N

AE11 DDR3_CLK1_P DIFF_SSTL15 102 CK1_P

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The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions

Chapter 1: KC705 Evaluation Board Features

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User Guide (UG586) [Ref 3]. The KC705 DDR3 SODIMM interface is a 40Ω impedance implementation. Other memory interface details are available in UG586 and 7SeriesFPGAs Memory Resources User Guide (UG473) [Ref 4] . For more information about the Micron MT8JTF12864HZ-1G6G1 part, see [Ref 5].

Linear BPI Flash Memory

[Figure 1-2, callout 3]

The Linear BPI flash memory located at U58 provides 128 MB of nonvolatile storage that can be used for configuration or software storage. The data, address, and control signals are connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.

• Part number: PC28F00AP30TF (Micron)

• Supply voltage: 2.5V

• Datapath width: 16 bits (26 address lines and 7 control signals)

• Data rate: Up to 33 MHz

The Linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at the 33 MHz data rate supported by the PC28F00AP30TF flash memory by using a configuration bitstream generated with BitGen options for synchronous configuration and for configuration clock division. The fastest configuration method uses the external 66 MHz oscillator connected to the FPGA EMCCLK pin with a bitstream that has been built to divide the configuration clock by two. The division is necessary to remain within the synchronous read timing specifications of the flash memory.

Multiple bitstreams can be stored in the Linear BPI flash memory. The two most significant address bits (A25, A24) of the flash memory are connected to DIP switch SW13 positions 1 and 2 respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325T bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can be selected to configure the FPGA by appropriately setting the DIP switch SW13. The connections between the BPI flash memory and the FPGA are listed in Table 1-5.

Table 1-5: BPI Flash Memory Connections to the FPGA

U58 BPI Flash Memory

U1 FPGA Pin Net Name I/O Standard

Pin Number Pin Name

W22 FLASH_A0 LVCMOS25 A1 A1

W21 FLASH_A1 LVCMOS25 B1 A2

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V24 FLASH_A2 LVCMOS25 C1 A3

U24 FLASH_A3 LVCMOS25 D1 A4

V22 FLASH_A4 LVCMOS25 D2 A5

V21 FLASH_A5 LVCMOS25 A2 A6

Chapter 1: KC705 Evaluation Board Features

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Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)

U1 FPGA Pin Net Name I/O Standard

U58 BPI Flash Memory

Pin Number Pin Name

U23 FLASH_A6 LVCMOS25 C2 A7

W24 FLASH_A7 LVCMOS25 A3 A8

W23 FLASH_A8 LVCMOS25 B3 A9

V20 FLASH_A9 LVCMOS25 C3 A10

V19 FLASH_A10 LVCMOS25 D3 A11

W26 FLASH_A11 LVCMOS25 C4 A12

V25 FLASH_A12 LVCMOS25 A5 A13

V30 FLASH_A13 LVCMOS25 B5 A14

V29 FLASH_A14 LVCMOS25 C5 A15

V27 FLASH_A15 LVCMOS25 D7 A16

P22 FLASH_A16 LVCMOS25 D8 A17

P21 FLASH_A17 LVCMOS25 A7 A18

N24 FLASH_A18 LVCMOS25 B7 A19

N22 FLASH_A19 LVCMOS25 C7 A20

N21 FLASH_A20 LVCMOS25 C8 A21

N20 FLASH_A21 LVCMOS25 A8 A22

N19 FLASH_A22 LVCMOS25 G1 A23

N26 FLASH_A23 LVCMOS25 H8 A24

M23 FLASH_A24 LVCMOS25 B6 A25

M22 FLASH_A25 LVCMOS25 B8 A26

P24 FLASH_D0 LVCMOS25 F2 DQ0

R25 FLASH_D1 LVCMOS25 E2 DQ1

R20 FLASH_D2 LVCMOS25 G3 DQ2

R21 FLASH_D3 LVCMOS25 E4 DQ3

T20 FLASH_D4 LVCMOS25 E5 DQ4

T21 FLASH_D5 LVCMOS25 G5 DQ5

T22 FLASH_D6 LVCMOS25 G6 DQ6

T23 FLASH_D7 LVCMOS25 H7 DQ7

U20 FLASH_D8 LVCMOS25 E1 DQ8

P29 FLASH_D9 LVCMOS25 E3 DQ9

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R29 FLASH_D10 LVCMOS25 F3 DQ10

P27 FLASH_D11 LVCMOS25 F4 DQ11

Chapter 1: KC705 Evaluation Board Features

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Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)

U1 FPGA Pin Net Name I/O Standard

U58 BPI Flash Memory

Pin Number Pin Name

P28 FLASH_D12 LVCMOS25 F5 DQ12

T30 FLASH_D13 LVCMOS25 H5 DQ13

P26 FLASH_D14 LVCMOS25 G7 DQ14

R26 FLASH_D15 LVCMOS25 E7 DQ15

U29 FLASH_WAIT LVCMOS25 F7 WAIT

M25 FPGA_FWE_B LVCMOS25 G8 WE_B

M24 FLASH_OE_B LVCMOS25 F8 OE_B

B10 FPGA_CCLK LVCMOS25 E6 CLK

U63.6 FLASH_CE_B LVCMOS25 B4 CE_B

M30 FLASH_ADV_B LVCMOS25 F6 ADV_B

A10 FPGA_INIT_B LVCMOS25 D4 RST_B

Additional FPGA bitstreams can be stored and used for configuration by setting the Warm Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is available in the reconfiguration and multiboot section in 7 Series FPGAs Configuration User Guide (UG470) [Ref 2]. The configuration section in this document provides details on the Master BPI configuration mode.

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Chapter 1: KC705 Evaluation Board Features

PC28F00AP30TF

64-Pin BGA (8 x 10 mm)

U58

FLASH_A0

FLASH_A1

FLASH_A2

FLASH_A3

FLASH_A4

FLASH_A5

FLASH_A6

FLASH_A7

FLASH_A8

FLASH_A9

A10

FLASH_A10

A11

FLASH_A11

A12

FLASH_A12

A13

FLASH_A13

A14

FLASH_A14

A15

FLASH_A15

A16

FLASH_A16

A17

FLASH_A17

A18

FLASH_A18

A19

FLASH_A19

A20

FLASH_A20

A21

FLASH_A21

A22

FLASH_A22

A23

FLASH_A23

A24

FLASH_A24

A25

FLASH_A25

A26

A27

VCC2

VCCQ1 VCCQ2 VCCQ3

VPP

VCC1

FLASH_D0_R

DQ0

FLASH_D1_R

DQ1

FLASH_D2_R

DQ2

FLASH_D3_R

DQ3

FLASH_D4_R

DQ4

FLASH_D5_R

DQ5

FLASH_D6_R

DQ6

FLASH_D7_R

DQ7

FLASH_D8_R

DQ8

FLASH_D9_R

DQ9

FLASH_D10_R

DQ10

FLASH_D11_R

DQ11

FLASH_D12_R

DQ12

FLASH_D13_R

DQ13

FLASH_D14_R

DQ14

FLASH_D15_R

DQ15

WE_B

FLASH_WP_B

WP_B ADV_B RST_B OE_B CE_B

FLASH_WAIT_R

WAIT

GND

VSS0 VSS1 VSS2 VSS3

RFU1

RFU2

RFU3

2.5V

1.8V

CLK

UG810_c1_05_031214

A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5

D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 B8

D5 D6 G4

A6 H3

F2 E2

E5 G5 G6 H7

F5 H5 G7

G8 C6

F6 D4

F1 G2

B2 H2 H4

FLASH_ADV_B FPGA_INIT_B FLASH_OE_B FLASH_CE_B

FLASH_PWE_B

FPGA_CCLK

Send Feedback

Figure 1-5 shows the connections of the linear BPI flash memory on the KC705 board.

For more information about the Micron PC28F00AP30TF part, see [Ref 5].

X-Ref Target - Figure 1-5

Figure 1-5: 128 MB Linear Flash Memory (U58)

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Chapter 1: KC705 Evaluation Board Features

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Quad SPI Flash Memory

[Figure 1-2, callout 4]

The Quad SPI flash memory located at U7 on the back side of the board provides 128 Mb of nonvolatile storage that can be used for configuration and data storage.

• Part number: Micron N25Q128A13BSF40F or MT25QL128ABA8ESF-0SIT

• Supply voltage: 2.8V

• Datapath width: 4 bits

• Data rate: Various depending on Single/Dual/Quad mode and CCLK rate

Four data lines and the FPGA CCLK pin are wired to the Quad SPI flash memory. A common chip select (FPGA_FCS) shared between the Linear BPI flash memory and the Quad SPI flash memory is controlled by the configuration mode settings on DIP switch SW13 position 5 (M0) and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the SPI flash memory device is selected. If mode pin M0 = 0, the Linear BPI flash memory device is selected. The connections between the SPI flash memory and the FPGA are listed in Table 1-6.

Table 1-6: Quad SPI Flash Memory Connections to the FPGA

J1 DDR3 Memory

U1 FPGA Pin Net Name I/O Standard

Pin Number Pin Name

P24 FLASH_D0 LVCMOS25 15 DQ0

R25 FLASH_D1 LVCMOS25 8 DQ1

R20 FLASH_D2 LVCMOS25 9 DQ2

R21 FLASH_D3 LVCMOS25 1 DQ3

B10 FPGA_CCLK N/A 16 C

U19 QSPI_IC_CS_B

Notes:

1. FPGA_FCS connected to FPGA U1 pin U19 becomes QSPI_IC_CS_B through U64 and J3.

(1)

LVCMOS25 7 S_B

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X-Ref Target - Figure 1-6

UG810_c1_06_031214

VCC2V5

N25Q128 128 Mb Serial Flash Memory

GND

VCC_SPI

C18

0.1μF 25V X5R

FLASH_D2

DQ1

NC3

NC2

NC1

NC0

VCC

HOLD_B/DQ3

WB/VPP/DQ2

VSS

NC4

NC5

NC6

NC7

DQ0

R17

DNP

R18

4.7kΩ 5%

R431

15Ω 1%

R432

15Ω 1%

FLASH_D0

FPGA_CCLK

FLASH_D2_R

FLASH_D0_R

GND

VCC2V5

R20

DNP

R19

4.7kΩ 5%

R21

4.7kΩ 5%

R430

15Ω 1%

R429

15Ω 1%

FLASH_D2_R

FLASH_D3_R

FLASH_D3

FLASH_D1

QSPI_IC_CS_B

Send Feedback

Chapter 1: KC705 Evaluation Board Features

The configuration section of7 Series FPGAs Configuration User Guide (UG470) [Ref 2] provides details on using the Quad SPI flash memory. Figure 1-6 shows the connections of the Quad SPI flash memory on the KC705 board.

For more information about the Micron N25Q128A13BSF40F or MT25QL128ABA8ESF-0SIT parts, see [Ref 5].

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Figure 1-6: 128 Mb Quad SPI Flash Memory

SD Card Interface

[Figure 1-2, callout 5]

The KC705 board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The SD card slot is designed to support 50 MHz high speed SD cards.

The SDIO signals are connected to I/O bank 12 which has its VCCO set to VADJ. A Texas Instruments I TXB0108 8-bit bidirectional voltage-level translator is used between the FPGA

X-Ref Target - Figure 1-7

Send Feedback

Chapter 1: KC705 Evaluation Board Features

and the SD card connector (U9). Figure 1-7 shows the connections of the SD card interface on the KC705 board.

VCC3V3

SDIO_DAT0 7

SDIO_DAT1

SDIO_DAT2

SDIO_CMD

SDIO_CLK

SDIO_SDWP

NC 12

8 9 1SDIO_CD_DAT3 2

5 10 11

GND

C22

0.1μF 25V X5R

GND

SDIO Card

Connector

VDD

DAT0

DAT1

DAT2

CD_DAT3

CMD

CLK

DETECT

PROTECT

D_P

VSS2

IOGND2

IOGND1

GNDTAB4

GNDTAB3

GNDTAB2VSS1

GNDTAB1

FPGA

Bank 12

(U1)

51.1K 1% Six Places

SDIO_DAT0_LS

SDIO_DAT1_LS

SDIO_DAT2_LS

SDIO_CD_DAT3_LS

SDIO_CMD_LS

SDIO_CLK_LS

R447

R449

R448

0.1μF 25V

R450

C543

R451

X5R

GND

VADJ

R452

C22

0.1μF 25V X5R

U57

GND

TXB0108

Voltage-Level

Translator

VCCB

VCCA

A8 B8

GND

VCC3V3

51.1K 1% Six Places

FPGA

Bank 12

(U1)

R453

R454

VADJ

R455

VCC3V3

R457

R456

4.7K

R35

R458

SDIO_SDDET

R34

4.7K

18 17 16

14 13

GND

UG810_c1_07_031214

Figure 1-7: SD Card Interface

Table 1-7 lists the SD card interface connections to the FPGA.

Table 1-7: SDIO Connections to the FPGA

U57 Level Shifter U9 SDIO Connector

U1 FPGA Pin Schematic Net Name I/O Standard

Pin Name (A) Pin Name (B) Pin Number Pin Name

Y21 SDIO_SDWP LVCMOS25 N/A N/A 11 SDWP

AA21 SDIO_SDDET LVCMOS25 N/A N/A 10 SDDET

AB22 SDIO_CMD_LS LVCMOS25 A5 B6 2 CMD

AB23 SDIO_CLK_LS LVCMOS25 A6 B7 5 CLK

AA22 SDIO_DAT2_LS LVCMOS25 A3 B4 9 DAT2

AA23 SDIO_DAT1_LS LVCMOS25 A2 B3 8 DAT1

AC20 SDIO_DAT0_LS LVCMOS25 A1 B1 7 DAT0

AC21 SDIO_CD_DAT3_LS LVCMOS25 A4 B5 1 CD_DAT3

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X-Ref Target - Figure 1-8

UG810_c1_08_031214

2.5V3.3V

FMC HPC Connector

TDI

TDO

J22

USB

Module

JTAG

Connector

(J60)

TDO

TDI

Kintex-7

FPGA

TDI

TDO

SN74AVC1T45

Voltage

Translator

TDI TDO

U102

FMC LPC

Connector

TDI

TDO

SPST Bus Switch U76

N.C. N.C.

SPST Bus Switch U77

Send Feedback

Chapter 1: KC705 Evaluation Board Features

USB JTAG Module

[Figure 1-2, callout 6]

JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration logic module (U59) where a host computer accesses the KC705 board JTAG chain through a standard-A plug (host side) to micro-B plug (KC705 board side) USB cable.

A 2-mm JTAG header (J60) is also provided in parallel for access by Xilinx® download cables such as the Platform Cable USB II and the Parallel Cable IV.

The JTAG chain of the KC705 board is illustrated in Figure 1-8. JTAG configuration is allowed at any time regardless of FPGA mode pin settings. JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pin settings at SW13.

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Figure 1-8: JTAG Chain Block Diagram

When an FMC card is attached to the KC705 board, it is automatically added to the JTAG chain through electronically controlled single-pole single-throw (SPST) switches U76 and U77. The SPST switches are in a normally closed state and transition to an open state when an FMC mezzanine card is attached. Switch U76 adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U77 adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the FMC_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO connection via a device or bypass jumper for the JTAG chain to be completed to the FPGA U1.

The JTAG connectivity on the KC705 board allows a host computer to download bitstreams to the FPGA using the Xilinx software. In addition, the JTAG connector allows debug tools or a software debugger to access the FPGA. The Xilinx software tool can also indirectly program the Linear BPI or the Quad SPI flash memory. To accomplish this, the software

X-Ref Target - Figure 1-9

UG810_c1_09_031214

JTAG_TDI

FMC_TDI_BUF

FPGA_TMS_BUF

FPGA_TDO

FPGA_TCK_BUF

FMC_LPC_TCK_BUF

FMC_HPC_TDO

FMC_LPC_TDO

FMC_TMS_BUF

LPC_PRSNT_M2C_B

HPC_PRSNT_M2C_B

JTAG_TMS

JTAG_TCK

JTAG_TDO

FMC_LPC_TMS_BUF

FMC_HPC_TCK_BUF

FMC_HPC_PRSNT_M2C_B

FMC_LPC_PRSNT_M2C_B

FMC HPC Connector

TDI

TDO

J22

TMS

TCK

PRSNT_L

VCC3V3

FMC LPC Connector

TDI

TDO

TMS

TCK

PRSNT_L

Kintex-7

FPGA

TDI

TDO

TMS

TCK

Digilent

USB-JTAG

Module

TMS

TDI

SN74AVC1T45

Voltage

Translator

U102

SN74AVC2T45

Voltage

Translator

U69

SN74LV541A

Voltage

Translator

R381 15Ω

U59

R382 15Ω

R380 15Ω

TCK

TDO

TMS

TDI

J60

TCK

TDO

JTAG

Header

VCC2V5

VCC3V3

U76

U77

Send Feedback

Chapter 1: KC705 Evaluation Board Features

configures the FPGA with a temporary design to access and program the BPI or Quad SPI flash memory device. The JTAG circuit is shown in Figure 1-9.

Figure 1-9: JTAG Circuit

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Chapter 1: KC705 Evaluation Board Features

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Clock Generation

There are five clock sources available for the FPGA fabric on the KC705 board (refer to

Table 1-8).

Table 1-8: KC705 Board Clock Sources

Clock Name Reference Description

System Clock

User Clock

User SMA Clock (differential pair)

GTX SMA REF Clock

(differential pair)

Jitter Attenuated Clock

U45

J11

J12

J16

J15

U70

SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time). See

System Clock Source, page 29.

Si570 3.3V LVDS I2C Programmable Oscillator

(Silicon Labs). Default power-on frequency 156.250 MHz. See

Programmable User Clock Source, page 29.

USER_SMA_CLOCK_P (net name).

See User SMA Clock Input, page 30.

USER_SMA_CLOCK_N (net name)

See User SMA Clock Input, page 30

SMA_MGT_REFCLK_P (net name).

See GTX SMA Clock Input, page 31.

SMA_MGT_REFCLK_N (net name).

See GTX SMA Clock Input, page 31.

Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).

See Jitter Attenuated Clock, page 32.

Table 1-9 lists the pin-to-pin connections from each clock source to the FPGA.

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Table 1-9: Clock Source to FPGA U1 Connections

Clock Source Pin Schematic Net Name I/O Standard U1 FPGA Pin

U6.5 SYSCLK_N LVDS AD11

U6.4 SYSCLK_P LVDS AD12

U45.5 USER_CLOCK_N LVDS_25 K29

U45.4 USER_CLOCK_P LVDS_25 K28

J12.1 USER_SMA_CLOCK_N LVDS_25 K25

J11.1 USER_SMA_CLOCK_P LVDS_25 L25

J15.1 SMA_MGT_REFCLK_N N/A (MGT REFCLK INPUT) J7

J16.1 SMA_MGT_REFCLK_P N/A (MGT REFCLK INPUT) J8

U70.29 Si5326_OUT_N N/A (MGT REFCLK INPUT) L7

U70.28 Si5326_OUT_P N/A (MGT REFCLK INPUT) L8

Chapter 1: KC705 Evaluation Board Features

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System Clock Source

[Figure 1-2, callout 7]

The KC705 board has a 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the back side of the board and wired to an FPGA MRCC clock input on bank 33. This 200 MHz signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins AD12 and AD11 respectively.

• Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)

• PPM frequency jitter: 50 ppm

• Differential Output

The system clock circuit is shown in Figure 1-10.

X-Ref Target - Figure 1-10

VCC2V5

SIT9102

200 MHz

1 2 3

Oscillator

OE NC GND

VCC

OUT_B

OUT

6 5 4

R459 100Ω 1%

SYSCLK_N

SYSCLK_P

C550

0.1 μF 10V X5R

GND

UG810_c1_10_031214

Figure 1-10: System Clock Source

For more about the Si Time SiT9102 see [Ref 6].

Programmable User Clock Source

[Figure 1-2, callout 8]

The KC705 board has a programmable low-jitter 3.3V differential oscillator (U45) the FPGA MRCC inputs of bank 15. This USER_CLOCK_P and USER_CLOCK_N clock signal pair are connected to FPGA U1 pins K28 and K29 respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz. User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the KC705 board reverts the user clock to its default frequency of 156.250 MHz.

• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)

• Differential Output

• I2C address 0x5D

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The user clock circuit is shown in Figure 1-11.

UG810_c1_11_031214

GND

VCC3V3

Si570

Programmable

Oscillator

NC OE

GND

SCL

SDA

VDD

1 2

U45

4.7KΩ 5%

USER CLOCK N

C77

0.01 μF 25V X7R

CLK-

GND

VCC3V3

CLK+

USER CLOCK P

USER CLOCK SDA

USER CLOCK SCL

10 MHz - 810 MHz

50 PPM

I2C

Bus Switch

(U49)

Send Feedback

X-Ref Target - Figure 1-11

Figure 1-11: User Clock Source

Chapter 1: KC705 Evaluation Board Features

For more information about the Silicon Labs Si570 see [Ref 7].

Reference design files are available to demonstrate how to program the Si570 programmable oscillator. See these files and presentations:

• XTP186, KC705 Si570 Programming [Ref 8]

• RDF0175, KC705 Si570 Programming Design Files [Ref 9]

• XTP187, KC705 Si570 Fixed Frequencies [Ref 10]

• RDF0176, KC705 Si570 Fixed Frequencies Design Files [Ref 11]

User SMA Clock Input

[Figure 1-2, callout 9]

An external high-precision clock signal can be provided to the FPGA bank 15 by connecting differential clock signals through the onboard 50Ω SMA connectors J11 (P) and J12 (N). The differential clock has signal names are USER_SMA_CLOCK_P and USER_SMA_CLOCK_N, which are connected to FPGA U1 pins L25 and K25, respectively. J11 (P) and J12 (N) are connected directly to the noted FPGA pins (no series capacitors and no external parallel

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Chapter 1: KC705 Evaluation Board Features

UG810_c1_13_031214

SMA_MGT_REFCLK_PSMA_MGT_REFCLK_C_P

SMA

Connector

J16

GND

C11

0.01 μF 25V X7R

SMA_MGT_REFCLK_NSMA_MGT_REFCLK_C_N

SMA

Connector

J15

GND

C10

0.01 μF 25V X7R

Send Feedback

termination resistor). The user-provided 2.5V differential clock circuit is shown in

Figure 1-12.

X-Ref Target - Figure 1-12

J11

SMA

Connector

J12

SMA

Connector

USER_SMA_CLOCK_P

GND

USER_SMA_CLOCK_N

GND

UG810_c1_12_031214

Figure 1-12: User SMA Clock Source

GTX SMA Clock Input

[Figure 1-2, callout 10]

The KC705 board includes a pair of SMA connectors for a GTX clock wired to GTX Quad bank

117. This differential clock has signal names SMA_MGT_REFCLK_P and SMA_REFCLK_N, which are connected to FPGA U1 pins J8 and J7 respectively. Figure 1-13 shows this AC-coupled clock circuit.

• External user-provided GTX reference clock on SMA input connectors

• Differential Input

X-Ref Target - Figure 1-13

Figure 1-13: GTX SMA Clock Source

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Chapter 1: KC705 Evaluation Board Features

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Jitter Attenuated Clock

[Figure 1-2, callout 11]

The KC705 board includes a Silicon Labs Si5324 jitter attenuator U70 on the back side of the board. FPGA user logic can implement a clock recovery circuit and then output this clock to a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin W27 and REC_CLOCK_C_N, FPGA U1 pin W28) for jitter attenuation. The jitter attenuated clock (SI5326_OUT_C_P, SI5326_OUT_C_N) is then routed as a reference clock to GTX Quad 116 inputs MGTREFCLK0P (FPGA U1 pin L8) and MGTREFCLK0N (FPGA U1 pin L7).

The Silicon Labs Si5324 U70 pin 1 reset net SI5326_RST must be driven High to enable the device. U70 pin 1 net SI5326_RST is level-shifted to VADJ by U75 and is connected to U1 bank 12 pin AE20. An active-Low input performs an external hardware reset of the device. This resets all internal logic to a known state and forces the device registers to their default value. The clock outputs are disabled during reset. The part must be programmed after a reset or power-up to get a clock output. The reset pin 1 has a weak internal pull-up.

The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock circuit is shown in Figure 1-14.

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X-Ref Target - Figure 1-14

UG810_c1_14_031214

R424

4.7KΩ 5%

SI5326_VCC

Si5324C-C-GM Clock Multiplier/ Jitter Attenuator

VDDA

GND

NC5

U70

CKOUT1_N

CKOUT1_P

C473

0.1μF 25V X5R

C474

0.1μF 25V X5R

SI5326_XTAL_XA

GND2

GND1

114.285 MHz 20 ppm

SI5326_OUT_C_N

SI5326_OUT_C_P

SI5326_OUT_N

SI5326_OUT_P

SI5326_XTAL_XB

GND

NC4

C475

0.1μF 25V X5R

C476

0.1μF 25V X5R

REC_CLOCK_P

REC_CLOCK_N

REC_CLOCK_C_P

REC_CLOCK_C_N

R337

100Ω

CKIN1_P

CKIN1_N

NCNC12

CKIN2_P

CKIN2_N

VDDA

NC3

NC2

NC1

CKOUT2_N

CKOUT2_P

SI5326_INT_ALM 3

NC 4

NC 11

NC 15

NC 18

NC 19

NC 20

SI5326_RST 1

GND2

GND1

A2_SS

SI5326_SCL

SCL

SI5326_SDA

SDA_SDO

SDI

CMODE

GND

INC

DEC

LOL

RATE1

RATE0

C2B

INT_C1B

CS_CA

RST_B

GNDPAD

Send Feedback

Chapter 1: KC705 Evaluation Board Features

For more information about the Silicon Labs Si5324 see [Ref 7].

GTX Transceivers

[Figure 1-2, callout 12]

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The KC705 board provides access to 16 GTX transceivers:

• Eight of the GTX transceivers are wired to the PCI Express® x8 endpoint edge connector (P1) fingers

• Four of the GTX transceivers are wired to the FMC HPC connector (J22)

• One GTX is wired to the FMC LPC connector (J2)

• One GTX is wired to SMA connectors (RX: J17, J18 TX: J19, J20)

• One GTX is wired to the SFP/SFP+ Module connector (P5)

• One GTX is used for the SGMII connection to the Ethernet PHY (U37)

Figure 1-14: Jitter Attenuated Clock

Chapter 1: KC705 Evaluation Board Features

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The GTX transceivers in 7 series FPGAs are grouped into four channels described as Quads. The reference clock for a Quad can be sourced from the Quad above or Quad below the GTX Quad of interest. There are four GTX Quads on the KC705 board with connectivity as shown here:

• Quad 115:

Contains 4 GTX transceivers for PCI Express lanes 4-7

MGTREFCLK1 - PCIE_CLK from P1

• Quad 116:

MGTREFCLK0 - Si5326 jitter attenuator

MGTREFCLK1 - FMC LPC GBT clock 0

Contains 4 GTX transceivers for PCIe lanes 0-3

• Quad 117:

MGTREFCLK0 - SGMII clock

MGTREFCLK1 - SMA clock

Contains 4 GTX transceivers with one allocated for: SMA, SGMII, SFP, and FMC LPC

(DP0)

• Quad 118:

MGTREFCLK0 - FMC HPC GBT clock 0

MGTREFCLK1 - FMC HPC GBT clock 1

Contains 4 GTX transceivers for FMC HPC (DP0 - DP3)

Table 1-10 lists the GTX interface connections to the FPGA (U1).

Table 1-10: GTX Interface Connections for FPGA U1

Transceiver Bank Associated Net Name Connections

MGT_BANK_115 GTXE2_CHANNEL_X0Y0 PCIe7

GTXE2_CHANNEL_X0Y1 PCIe6

GTXE2_CHANNEL_X0Y2 PCIe5

GTXE2_CHANNEL_X0Y3 PCIe4

MGTREFCLK0 N/C

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MGTREFCLK1 PCIe_CLK

Chapter 1: KC705 Evaluation Board Features

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Table 1-10: GTX Interface Connections for FPGA U1 (Cont’d)

Transceiver Bank Associated Net Name Connections

MGT_BANK_116 GTXE2_CHANNEL_X0Y4 PCIe3

GTXE2_CHANNEL_X0Y5 PCIe2

GTXE2_CHANNEL_X0Y6 PCIe1

GTXE2_CHANNEL_X0Y7 PCIe0

MGTREFCLK0 Si5326

MGTREFCLK1 FMC LPC GBT_CLK0

MGT_BANK_117 GTXE2_CHANNEL_X0Y8 SMA

GTXE2_CHANNEL_X0Y9 SGMII

GTXE2_CHANNEL_X0Y10 SFP+

GTXE2_CHANNEL_X0Y11 FMC LPC DP0

MGTREFCLK0 SGMII_CLK

MGTREFCLK1 SMA_CLK

MGT_BANK_118 GTXE2_CHANNEL_X0Y12 FMC HPC DP0

GTXE2_CHANNEL_X0Y13 FMC HPC DP1

GTXE2_CHANNEL_X0Y14 FMC HPC DP2

GTXE2_CHANNEL_X0Y15 FMC HPC DP3

MGTREFCLK0 FMC HPC GBT_CLK0

MGTREFCLK1 FMC HPC GBT_CLK1

For more information on the GTX transceivers, see 7 Series FPGAs GTX Transceivers User Guide (UG476) [Ref 12].

PCI Express Edge Connector

[Figure 1-2, callout 13]

The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair. The 7 series FPGAs GTX transceivers are used for multi-gigabit per second serial interfaces.

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The XC7K325T-2FFG900C FPGA (-2 speed grade) included with the KC705 board supports up to Gen2 x8.

Chapter 1: KC705 Evaluation Board Features

UG810_c1_15_031214

PCI Express

Eight-Lane

Edge connector

GND

A15

A13

A14

REFCLK+

A12

GND

C544

0.01μF 25V X7R

C545

0.01μF 25V X7R

PCIE_CLK_Q0_P

PCIE_CLK_Q0_N

PCIE_CLK_Q0_C_P

PCIE_CLK_Q0_C_N

REFCLK-

Send Feedback

The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin U8, and the _N net is connected to pin U7. The PCI Express clock circuit is shown in Figure 1-15.

X-Ref Target - Figure 1-15

Figure 1-15: PCI Express Clock

PCIe lane width/size is selected via jumper J32 (Figure 1-16). The default lane size selection is 8-lane (J32 pins 5 and 6 jumpered).

X-Ref Target - Figure 1-16

PCIE_PRSNT_X1 PCIE_PRSNT_X4 PCIE_PRSNT_X8

J32

1 3 5

2 4 6

PCIE_PRSNT_B

UG810_c1_16_031214

Figure 1-16: PCI Express Lane Size Select Jumper J32

Table 1-11 lists the PCIe edge connector connections.

Table 1-11: PCIe Edge Connector Connections

Schematic Net

Name

FPGA Pin

(U1)

PCIE_RX0_P M6 B14 PETp0 Integrated Endpoint block

PCIE_RX0_N M5 B15 PETn0 Integrated Endpoint block

PCIE_RX1_P P6 B19 PETp1 Integrated Endpoint block

PCIE_RX1_N P5 B20 PETn1 Integrated Endpoint block

PCIE_RX2_P R4 B23 PETp2 Integrated Endpoint block

PCIe Edge

Connector

PCIe Edge Pin Name

Function FFG900 Placement

receive pair

GTXE2_CHANNEL_X0Y7

GTXE2_CHANNEL_X0Y6

GTXE2_CHANNEL_X0Y5

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PCIE_RX2_N R3 B24 PETn2 Integrated Endpoint block

receive pair

PCIE_RX3_P T6 B27 PETp3 Integrated Endpoint block

receive pair

GTXE2_CHANNEL_X0Y5

GTXE2_CHANNEL_X0Y4

Table 1-11: PCIe Edge Connector Connections (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Schematic Net

Name

PCIE_RX3_N T5 B28 PETn3 Integrated Endpoint block

PCIE_RX4_P V6 B33 PETp4 Integrated Endpoint block

PCIE_RX4_N V5 B34 PETn4 Integrated Endpoint block

PCIE_RX5_P W4 B37 PETp5 Integrated Endpoint block

PCIE_RX5_N W3 B38 PETn5 Integrated Endpoint block

PCIE_RX6_P Y6 B41 PETp6 Integrated Endpoint block

PCIE_RX6_N Y5 B42 PETn6 Integrated Endpoint block

PCIE_RX7_P AA4 B45 PETp7 Integrated Endpoint block

PCIE_RX7_N AA3 B46 PETn7 Integrated Endpoint block

FPGA Pin

(U1)

PCIe Edge

Connector

PCIe Edge Pin Name

Function FFG900 Placement

receive pair

GTXE2_CHANNEL_X0Y4

GTXE2_CHANNEL_X0Y3

GTXE2_CHANNEL_X0Y2

GTXE2_CHANNEL_X0Y1

GTXE2_CHANNEL_X0Y0

PCIE_TX0_P L4 A16 PERp0 Integrated Endpoint block

transmit pair

PCIE_TX0_N L3 A17 PERn0 Integrated Endpoint block

transmit pair

PCIE_TX1_P M2 A21 PERp1 Integrated Endpoint block

transmit pair

PCIE_TX1_N M1 A22 PERn1 Integrated Endpoint block

transmit pair

PCIE_TX2_P N4 A25 PERp2 Integrated Endpoint block

transmit pair

PCIE_TX2_N N3 A26 PERn2 Integrated Endpoint block

transmit pair

PCIE_TX3_P P2 A29 PERp3 Integrated Endpoint block

transmit pair

PCIE_TX3_N P1 A30 PERn3 Integrated Endpoint block

transmit pair

PCIE_TX4_P T2 A35 PERp4 Integrated Endpoint block

transmit pair

PCIE_TX4_N T1 A36 PERn4 Integrated Endpoint block

transmit pair

GTXE2_CHANNEL_X0Y7

GTXE2_CHANNEL_X0Y6

GTXE2_CHANNEL_X0Y5

GTXE2_CHANNEL_X0Y4

GTXE2_CHANNEL_X0Y3

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Table 1-11: PCIe Edge Connector Connections (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Schematic Net

Name

PCIE_TX5_P U4 A39 PERp5 Integrated Endpoint block

PCIE_TX5_N U3 A40 PERn5 Integrated Endpoint block

PCIE_TX6_P V2 A43 PERp6 Integrated Endpoint block

PCIE_TX6_N V1 A44 PERn6 Integrated Endpoint block

PCIE_TX7_P Y2 A47 PERp7 Integrated Endpoint block

PCIE_TX7_N Y1 A48 PERn7 Integrated Endpoint block

PCIE_CLK_QO_P U8 A13 REFCLK+ Integrated Endpoint block

PCIE_CLK_QO_N U7 A14 REFCLK- Integrated Endpoint block

FPGA Pin

(U1)

PCIe Edge

Connector

PCIe Edge Pin Name

Function FFG900 Placement

transmit pair

differential clock pair from PCIe

GTXE2_CHANNEL_X0Y2

GTXE2_CHANNEL_X0Y1

GTXE2_CHANNEL_X0Y0

MGT_BANK_115

PCIE_PRSNT_B J32 2, 4, 6 A1 PRSNT#1 J42 Lane Size Select jumper N/A

PCIE_WAKE_B F23 B11 WAKE# Integrated Endpoint block

wake signal, not connected on KC705 board

PCIE_PERST_B G25 A11 PERST Integrated Endpoint block

reset signal

N/A

Table 1-12 lists the PCIe edge connector connections for Quad 115.

Table 1-12: GTX Quad 115 PCIe Edge Connector Connections

Quad 115 Pin Name

MGTXTXP0_115_Y2 Y2 PCIE_TX7_P A47 PERp7 GTXE2_CHANNEL_X0Y0

MGTXTXN0_115_Y1 Y1 PCIE_TX7_N A48 PERn7 GTXE2_CHANNEL_X0Y0

MGTXRXP0_115_AA4 AA4 PCIE_RX7_P B45 PETp7 GTXE2_CHANNEL_X0Y0

MGTXRXN0_115_AA3 AA3 PCIE_RX7_N B46 PETn7 GTXE2_CHANNEL_X0Y0

MGTXTXP1_115_V2 V2 PCIE_TX6_P A43 PERp6 GTXE2_CHANNEL_X0Y1

MGTXTXN1_115_V1 V1 PCIE_TX6_N A44 PERn6 GTXE2_CHANNEL_X0Y1

MGTXRXP1_115_Y6 Y6 PCIE_RX6_P B41 PETp6 GTXE2_CHANNEL_X0Y1

MGTXRXN1_115_Y5 Y5 PCIE_RX6_N B42 PETn6 GTXE2_CHANNEL_X0Y1

FPGA

Pin (U1)

Schematic Net Name

PCIe Edge

Connector

PCIe Edge Pin Name

FFG900 Placement

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Table 1-12: GTX Quad 115 PCIe Edge Connector Connections (Cont’d)

Quad 115 Pin Name

MGTXTXP2_115_U4 U4 PCIE_TX5_P A39 PERp5 GTXE2_CHANNEL_X0Y2

MGTXTXN2_115_U3 U3 PCIE_TX5_N A40 PERn5 GTXE2_CHANNEL_X0Y2

MGTXRXP2_115_W4 W4 PCIE_RX5_P B37 PETp5 GTXE2_CHANNEL_X0Y2

MGTXRXN2_115_W3 W3 PCIE_RX5_N B38 PETn5 GTXE2_CHANNEL_X0Y2

MGTXTXP3_115_T2 T2 PCIE_TX4_P A35 PERp4 GTXE2_CHANNEL_X0Y3

MGTXTXN3_115_T1 T1 PCIE_TX4_N A36 PERn4 GTXE2_CHANNEL_X0Y3

MGTXRXP3_115_V6 V6 PCIE_RX4_P B33 PETp4 GTXE2_CHANNEL_X0Y3

MGTXRXN3_115_V5 V5 PCIE_RX4_N B34 PETn4 GTXE2_CHANNEL_X0Y3

MGTREFCLK0P_115_R8 R8 NC MGT_BANK_115

MGTREFCLK0N_115_R7 R7 NC MGT_BANK_115

MGTREFCLK1P_115_U8 U8 PCIE_CLK_QO_P A13 REFCLK+ MGT_BANK_115

MGTREFCLK1N_115_U7 U7 PCIE_CLK_QO_N A14 REFCLK- MGT_BANK_115

MGTAVTTRCAL_115_W7 W7 MGTAVTT MGT_BANK_115

MGTRREF_115_W8 W8 100 ohm P/U to MGTAVTT MGT_BANK_115

FPGA

Pin (U1)

Schematic Net Name

PCIe Edge

Connector

PCIe Edge Pin Name

FFG900 Placement

Table 1-13 lists the PCIe edge connector connections for Quad 116.

Table 1-13: GTX Quad 116 to PCIe Edge Connector Connections

Quad 116 Pin Name

MGTXTXP0_116_P2 P2 PCIE_TX3_P A29 PERp3 GTXE2_CHANNEL_X0Y4

MGTXTXN0_116_P1 P1 PCIE_TX3_N A30 PERn3 GTXE2_CHANNEL_X0Y4

MGTXRXP0_116_T6 T6 PCIE_RX3_P B27 PETp3 GTXE2_CHANNEL_X0Y4

MGTXRXN0_116_T5 T5 PCIE_RX3_N B28 PETn3 GTXE2_CHANNEL_X0Y4

MGTXTXP1_116_N4 N4 PCIE_TX2_P A25 PERp2 GTXE2_CHANNEL_X0Y5

MGTXTXN1_116_N3 N3 PCIE_TX2_N A26 PERn2 GTXE2_CHANNEL_X0Y5

MGTXRXP1_116_R4 R4 PCIE_RX2_P B23 PETp2 GTXE2_CHANNEL_X0Y5

MGTXRXN1_116_R3 R3 PCIE_RX2_N B24 PETn2 GTXE2_CHANNEL_X0Y5

MGTXTXP2_116_M2 M2 PCIE_TX1_P A21 PERp1 GTXE2_CHANNEL_X0Y6

MGTXTXN2_116_M1 M1 PCIE_TX1_N A22 PERn1 GTXE2_CHANNEL_X0Y6

FPGA

Pin (U1)

Schematic Net Name

PCIe Edge

Connector

PCIe

Edge in

Name

FFG900 Placement

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Table 1-13: GTX Quad 116 to PCIe Edge Connector Connections (Cont’d)

Quad 116 Pin Name

MGTXRXP2_116_P6 P6 PCIE_RX1_P B19 PETp1 GTXE2_CHANNEL_X0Y6

MGTXRXN2_116_P5 P5 PCIE_RX1_N B20 PETn1 GTXE2_CHANNEL_X0Y6

MGTXTXP3_116_L4 L4 PCIE_TX0_P A16 PERp0 GTXE2_CHANNEL_X0Y7

MGTXTXN3_116_L3 L3 PCIE_TX0_N A17 PERn0 GTXE2_CHANNEL_X0Y7

MGTXRXP3_116_M6 M6 PCIE_RX0_P B14 PETp0 GTXE2_CHANNEL_X0Y7

MGTXRXN3_116_M5 M5 PCIE_RX0_N B15 PETn0 GTXE2_CHANNEL_X0Y7

MGTREFCLK0P_116_L8 L8 SI5326_OUT_C_P MGT_BANK_116

MGTREFCLK0N_116_L7 L7 SI5326_OUT_C_N MGT_BANK_116

MGTREFCLK1P_116_N8 N8 FMC_LPC_GBTCLK0_M2C_C_P MGT_BANK_116

MGTREFCLK1N_116_N7 N7 FMC_LPC_GBTCLK0_M2C_C_N MGT_BANK_116

FPGA

Pin (U1)

Schematic Net Name

PCIe Edge

Connector

PCIe

Edge in

Name

FFG900 Placement

For more information refer to 7 Series FPGAs GTX Transceivers User Guide (UG476) [Ref 12] and 7 Series FPGAs Integrated Block for PCI Express User Guide (AXI) (PG054) [Ref 13].

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X-Ref Target - Figure 1-17

UG810_c1_17_031413

GND12

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

TD_N

TD_P

VCCT

VCCR

RD_P

RD_N

LOS

VEET_3

VEET_2

VEER_3

VEER_1

VEER_2

VEET_1

RS0

RS1

MOD_ABS

SCL

SDA

TX_DISABLE

TX_FAULT

GND11

2-3: LOW BW TX2-3: LOW BW RX

1-2: FULL BW RX

SFP Enable

1-2: FULL BW TX

SFP_RS1

SFP_VCCT

SFP+ Module

Connector

74441-0010

SFP_LOS

SFP_TX_FAULT

SFP_IIC_SDA

SFP_IIC_SCL

SFP_RX_P

SFP_RX_N

SFP_TX_P

SFP_TX_DISABLE_TRANS

SFP_RS0

J27 J28

HDR_1X2

SFP_MOD_DETECT

SFP_TX_N

SFP_VCCR

R552

4.7KΩ

4.7μH

3.0 A

VCC3V3

C28

0.1μF

GND

VCC3V3

4.7μH

3.0 A

C587 22μF

C29

0.1μF

C55 22μF

GND

Q2 NDS331N 460 mW

SFP_TX_DISABLE

R37

4.7KΩ

VCC3V3

GND

R36

4.7KΩ

R40

4.7KΩ

R41

4.7KΩ

J10

HDR_1X1

HDR_1X3

R551

4.7KΩ

VCC3V3

GNDGND

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Chapter 1: KC705 Evaluation Board Features

SFP/SFP+ Connector

[Figure 1-2, callout 14]

The KC705 board contains a small form-factor pluggable (SFP+) connector and cage assembly that accepts SFP or SFP+ modules. Figure 1-17 shows the SFP+ module connector circuitry.

Figure 1-17: SFP+ Module Connector

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Table 1-14 lists the SFP+ module RX and TX connections to the FPGA.

Table 1-14: FPGA U1 to SFP+ Module Connections

FPGA Pin (U1) Schematic Net Name SFP+ Pin (P5) SFP+ Pin Name (P5)

G3 SFP_RX_N 12 RD_N

G4 SFP_RX_P 13 RD_P

H1 SFP_TX_N 19 TX_N

H2 SFP_TX_P 18 TX_P

Y20 SFP_TX_DISABLE_TRANS

Notes:

1. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 RD_P is connected to net SFP_RX_N, and pin 19 RD_N is connected to net SFP_RX_P.

2. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 TD_P is connected to net SFP_TX_N, and pin 19 TD_N is connected to net SFP_TX_P.

3. SFP_TX_DISABLE_TRANS I/O standard = LVCMOS25.

(3)

3TX_DISABLE

(1)

(2)

Table 1-15 lists the SFP+ module control and status connections to the FPGA.

Table 1-15: SFP+ Module Control and Status

SFP Control/Status Signal Board Connection

SFP_TX_FAULT Test Point J10

High = Fault

Low = Normal Operation

SFP_TX_DISABLE Jumper J4

Off = FP Disabled

On = SFP Enabled

SFP_MOD_DETECT Test Point J9

High = Module Not Present

Low = Module Present

SFP_RS0 Jumper J27

Jumper Pins 1-2 = Full RX Bandwidth

Jumper Pins 2-3 = Reduced RX Bandwidth

SFP_RS1 Jumper J28

Jumper Pins 1-2 = Full TX Bandwidth

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Jumper Pins 2-3 = Reduced TX Bandwidth

Chapter 1: KC705 Evaluation Board Features

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Table 1-15: SFP+ Module Control and Status (Cont’d)

SFP Control/Status Signal Board Connection

SFP_LOS Test Point J8

High = Loss of Receiver Signal

Low = Normal Operation

Notes:

1. Default jumper shunt positions are shown in bold text.

10/100/1000 Tri-Speed Ethernet PHY

[Figure 1-2, callout 15]

The KC705 board utilizes the Marvell Alaska PHY device (88E1111) U37 for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII interfaces from the FPGA to the PHY (Table 1-16). The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with built-in magnetics.

Table 1-16: PHY Default Interface Mode

Jumper Settings

Mode

J29 J30 J64

GMII/MII to copper (default) Jumper over pins 1-2 Jumper over pins 1-2 No jumper

SGMII to copper, no clock Jumper over pins 2-3 Jumper over pins 2-3 No jumper

RGMII Jumper over pins 1-2 No jumper Jumper on

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-17. These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-17: Board Connections for PHY Configuration Pins

CFG0 VCC 2.5V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1

CFG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0

CFG2 V

CFG3 V

CFG4 V

CFG5 V

CFG6 PHY_LED_RX SEL_BDT = 0 INT_POL = 1 75/50Ω= 0

Connection on

Board

2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1

2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1

2.5V HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1

2.5V DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MD[3] = 1

Bit[2] Definition and

Valu e

Bit[1] Definition and

Value

Bit[0] Definition and

Value

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X-Ref Target - Figure 1-18

UG810_c1_18_031214

GND_SGMIICLK

VDD_SGMIICLK

ICS844021I-01

Clock Generator

VDDA

GND_SGMIICLK

XTAL_IN

XTAL_OUT

VDD

R134

1.0MΩ 5%

NQ0

VDDA_SGMIICLK

C93 18pF 50V NPO

C94 18pF 50V NPO

C14

0.1μF 25V X5R

C15

0.1μF 25V X5R

SGMIICLK_XTAL_OUT

GND2

25.00 MHz

SGMIICLK_Q0_P

SGMIICLK_Q0_N

SGMIICLK_Q0_C_P

SGMIICLK_Q0_C_NSGMIICLK_XTAL_IN

GND_SGMIICLK

GND

Send Feedback

Chapter 1: KC705 Evaluation Board Features

SGMII GTX Transceiver Clock Generator

[Figure 1-2, callout 16]

An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125 MHz LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, bank 117 GTX transceiver (clock pins G8 (P) and G7 (N)) driving the SGMII interface. Series AC coupling capacitors are present to allow the clock input of the FPGA to set the common mode voltage. Figure 1-18 shows the Ethernet SGMII clock source.

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Figure 1-18: Ethernet 125 MHz SGMII GTX Clock

Table 1-18 shows the connections and pin numbers for the M88E1111 PHY.

Table 1-18: Ethernet PHY Connections

M88E1111 (U37)

U1 FPGA Pin Schematic Net Name I/O Standard

Pin Number Pin Name

J21 PHY_MDIO LVCMOS25 M1 MDIO

R23 PHY_MDC LVCMOS25 L3 MDC

N30 PHY_INT LVCMOS25 L1 INT_B

L20 PHY_RESET LVCMOS25 K3 RESET_B

R30 PHY_CRS LVCMOS25 B5 CRS

W19 PHY_COL LVCMOS25 B6 COL

U27 PHY_RXCLK LVCMOS25 C1 RXCLK

V26 PHY_RXER LVCMOS25 D2 RXER

R28 PHY_REXCTL_RXDV LVCMOS25 B1 RXDV

U30 PHY_RXD0 LVCMOS25 B2 RXD0

U25 PHY_RXD1 LVCMOS25 D3 RXD1

T25 PHY_RXD2 LVCMOS25 C3 RXD2

Table 1-18: Ethernet PHY Connections (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

U1 FPGA Pin Schematic Net Name I/O Standard

M88E1111 (U37)

Pin Number Pin Name

U28 PHY_RXD3 LVCMOS25 B3 RXD3

R19 PHY_RXD4 LVCMOS25 C4 RXD4

T27 PHY_RXD5 LVCMOS25 A1 RXD5

T26 PHY_RXD6 LVCMOS25 A2 RXD6

T28 PHY_RXD7 LVCMOS25 C5 RXD7

K30 PHY_TXC_GTXCLK LVCMOS25 E2 GTXCLK

M28 PHY_TXCLK LVCMOS25 D1 TXCLK

N29 PHY_TXER LVCMOS25 F2 TXER

M27 PHY_TXCTL_TXEN LVCMOS25 E1 TXEN

N27 PHY_TXD0 LVCMOS25 F1 TXD0

N25 PHY_TXD1 LVCMOS25 G2 TXD1

M29 PHY_TXD2 LVCMOS25 G3 TXD2

L28 PHY_TXD3 LVCMOS25 H2 TXD3

J26 PHY_TXD4 LVCMOS25 H1 TXD4

K26 PHY_TXD5 LVCMOS25 H3 TXD5

L30 PHY_TXD6 LVCMOS25 J1 TXD6

J28 PHY_TXD7 LVCMOS25 J2 TXD7

J4 SGMII_TX_P LVCMOS25 A3 SIN_P

J3 SGMII_TX_N LVCMOS25 A4 SIN_N

H6 SGMII_RX_P LVCMOS25 A7 SOUT_P

H5 SGMII_RX_N LVCMOS25 A8 SOUT_N

Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet MAC User Guide (PG051) [Ref 14].

For more information about the Marvell 88E1111, see [Ref 15].

For more information about the ICS 844021-01, see [Ref 16].

USB-to-UART Bridge

[Figure 1-2, callout 17]

The KC705 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U12) which allows a connection to a host computer with a USB port. The USB cable is supplied in the Evaluation Kit (standard-A plug to host computer, mini-B plug to KC705 board

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Chapter 1: KC705 Evaluation Board Features

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connector J6). The CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the KC705 board.

Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications application software (for example, Tera Term or HyperTerm) that runs on the host computer. The VCP device drivers must be installed on the host PC prior to establishing communications with the KC705 board.

Table 1-19 shows the USB signal definitions at J6.

Table 1-19: USB J6 Mini-B Receptacle Pin Assignments and Signal Definitions

USB Receptacle

Pins (J6)

1 VBUS USB_VBUS +5V from host system

2 D_N USB_D_N Bidirectional

3 D_P USB_D_P Bidirectional

4 GND USB_GND Signal ground 2, 29 GND, GND

Receptacle Pin

Name

Schematic Net

Name

Description

- U12 CP2103 power

differential serial data (N-side)

differential serial data (P-side)

U12 Pin

(CP2103GM)

7, 8 REGIN, VBUS

4D-

3D+

U12 Pin Name

(CP2103GM)

Table 1-20 shows the USB connections between the FPGA and the UART.

Table 1-20: FPGA to UART Connections

FPGA U1

CP2103 Device U12

Schematic

Pin Function Direction

L27 RTS Output LVCMOS25 USB_CTS 22 CTS Input

K23 CTS Input LVCMOS25 USB_RTS 23 RTS Output

I/O

Standard

Net Name

Pin Function Direction

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K24 TX Output LVCMOS25 USB_RX 24 RXD Input

M19 RX Input LVCMOS25 USB_TX 25 TXD Output

For more information about the CP2103GM and to download the VCP drivers see [Ref 7].

Chapter 1: KC705 Evaluation Board Features

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HDMI Video Output

[Figure 1-2, callout 18]

The KC705 board provides a High-Definition Multimedia Interface (HDMI) video output using the Analog Devices ADV7511KSTZ-P HDMI transmitter (U65). The HDMI output is provided on a Molex 500254-1927 HDMI type-A connector (P6). The ADV7511 is wired to support 1080P 60Hz, YCbCr 4:2:2 encoding via 16-bit input data mapping.

The KC705 board supports the following HDMI device interfaces:

• 18 data lines

•Independent VSYNC, HSYNC

• Single-ended input CLK

• Interrupt Out Pin to FPGA

•I2C

•SPDIF

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X-Ref Target - Figure 1-19

UG810_c1_19_031214

GND

VCC3V3

GND

GNDOUT

VCC

D31

D32

D33

D34

D35

D12

D13

D14

D15

D29

D30

D28 D27 D26 D25 D24 D23 D22 D21 D20

D19

D3 D2

D11 D10 D9 D8 D7

D16

GND10

CLK

D18 D17

SPDIF

VSYNC HSYNC

SDA

SCL CEC_CLK

SPDIF_OUT

INT PD

PVDD1 PVDD2 PVDD3

AVDD2 AVDD3

AVDD1

GND1 GND2

GND6

GND3 GND4 GND5

GND7 GND8 GND9

GND11

DVDD_3V

BGVDD

DVDD1 DVDD2 DVDD3 DVDD4 DVDD5

HPD

To HDMI Connector

HDMI_CEC_CLK_R HDMI_CEC_CLK

HDMI_SPDIF_OUT

R607

24.9 1/10W 1%

64 65 66 67 68 69 70 71 72

93 94

85 86 87 88 89

74 78

45 38

21 24 25

34 41

99 100

18 20

27 31 37

76 77 49 19 1

U65

ADV7511

HDMI_D10

VADJ

HDMI_HEAC_C_N

HDMI_AVDDHDMI_PLVDD

HDMI_PLVDD

X5R

25V

0.1UF

C592

HDMI_CLK

HDMI_HSYNC

HDMI_VSYNC

HDMI_INT

1/10W

2.43K

R389

R435

2.43K 1/10W 1%

IIC_SCL_HDMI

U72

12.00000 MHZ

SIT8102

50PPM

VCC2V5

IIC_SDA_HDMI

HDMI_DVDD

HDMI_DE

R388

2.43K 1/10W 1%

HDMI_SPDIF

HDMI_AVDD

HDMI_DVDD_3V

HDMI_D3

HDMI_D0

HDMI_D1

HDMI_D4

HDMI_D5

HDMI_D7

HDMI_D8

HDMI_D9

HDMI_D11

HDMI_D6

HDMI_D2

HDMI_D13

HDMI_D14

HDMI_D15

HDMI_D17 HDMI_D16

HDMI_D12

HEAC_P HEAC_N

TX2_P

TX2_N

TX1_P TX1_N

TX0_P TX0_N

TXC_P TXC_N

DDCSDA

DDCSCL

CEC

52 51

43 42

40 39

36 35

33 32

54 53

HDMI_CEC

HDMI_DDCSDA

HDMI_D0_P

HDMI_DDCSCL

HDMI_HEAC_N

HDMI_HEAC_P

HDMI_CLK_N

HDMI_CLK_P

HDMI_D2_N

HDMI_D2_P

HDMI_D1_N

HDMI_D1_P

HDMI_D0_N

To HDMI

Connector to

FPGA U1

DSD0 DSD1 DSD2 DSD3 DSD4 DSD5 DSD_CLK

I2S0

I2S2

I2S1

LRCLK

SCLK

I2S3

R_EXT

MCLK

3 4 5 6 7 8 9

R433 887

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Figure 1-19 shows the HDMI codec circuit.

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Figure 1-19: HDMI Codec Circuit

Chapter 1: KC705 Evaluation Board Features

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Table 1-21 lists the connections between the codec and the FPGA.

Table 1-21: FPGA to HDMI Codec Connections (ADV7511)

U1 FPGA Pin Schematic Net Name I/O Standard

ADV7511 (U65)

Pin Number Pin Name

B23 HDMI_D0 LVCMOS25 88 D8

A23 HDMI_D1 LVCMOS25 87 D9

E23 HDMI_D2 LVCMOS25 86 D10

D23 HDMI_D3 LVCMOS25 85 D11

F25 HDMI_D4 LVCMOS25 84 D12

E25 HDMI_D5 LVCMOS25 83 D13

E24 HDMI_D6 LVCMOS25 82 D14

D24 HDMI_D7 LVCMOS25 81 D15

F26 HDMI_D8 LVCMOS25 80 D16

E26 HDMI_D9 LVCMOS25 78 D17

G23 HDMI_D10 LVCMOS25 74 D18

G24 HDMI_D11 LVCMOS25 73 D19

J19 HDMI_D12 LVCMOS25 72 D20

H19 HDMI_D13 LVCMOS25 71 D21

L17 HDMI_D14 LVCMOS25 70 D22

L18 HDMI_D15 LVCMOS25 69 D23

K19 HDMI_D16 LVCMOS25 68 D24

K20 HDMI_D17 LVCMOS25 67 D25

H17 HDMI_DE LVCMOS25 97 DE

J17 HDMI_SPDIF LVCMOS25 10 SPDIF

K18 HDMI_CLK LVCMOS25 79 CLK

H20 HDMI_VSYNC LVCMOS25 2 VSYNC

J18 HDMI_HSYNC LVCMOS25 98 HSYNC

AH24 HDMI_INT LVCMOS25 45 INT

G20 HDMI_SPDIF_OUT LVCMOS25 46 SPDIF_OUT

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UG810_c1_20_031214

LCD Display (16 x 2)

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Table 1-22 lists the connections between the codec and the HDMI connector P6.

Table 1-22: ADV7511 to HDMI Connector Connections

ADV7511 (U65) Schematic Net Name HDMI Connector P6 Pin

36 HDMI_D0_P 7

35 HDMI_D0_N 9

40 HDMI_D1_P 4

39 HDMI_D1_N 6

43 HDMI_D2_P 1

42 HDMI_D2_N 3

33 HDMI_CLK_P 10

32 HDMI_CLK_N 12

54 HDMI_DDCSDA 16

53 HDMI_DDCSCL 15

52 HDMI_HEAC_P 14

51 HDMI_HEAC_N 19

48 HDMI_CRC 13

For more information about the ADV7511KSTZ-P part, see [Ref 17].

LCD Character Display

[Figure 1-2, callout 19]

A 2-line by 16-character display is provided on the KC705 board (Figure 1-20).

X-Ref Target - Figure 1-20

Figure 1-20: LCD Display

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X-Ref Target - Figure 1-21

UG810_c1_22_031214

LCD Display Assembly

KC705 PWA

10 mm

Low Profile Socket

Samtec SLW-107-01-L-D

Low Profile Terminal

Samtec MTLW-107-07-G-D-265

Send Feedback

Chapter 1: KC705 Evaluation Board Features

The character display runs at 5.0V and is connected to the FPGA's 1.5V HP bank 33 through a Texas Instruments TXS0108E 8-bit bidirectional voltage level translator (U10). Figure 1-21 shows the LCD interface circuit.

VCC1V5_FPGA

VCC5V0

C23

0.1μF 25V X5R

GND

LCD_E_LS LCD_RW_LS LCD_DB4_LS LCD_DB5_LS LCD_DB6_LS LCD_DB7_LS LCD_RS_LS

U10

VCCA

TXS0108E 8-Bit

Bidirectional

Voltage Level

Translator

VCCB

GND

C24

0.1μF 25V X5R

GND

B1 B2 B3 B4 B5 B6 B7 B8

LCD_DB7 LCD_DB5

LCD_E LCD_RS

19 20 18 17 16 15 14 13

12 11

GND

NC NC

GND

LCD_RW LCD_DB4 LCD_DB5 LCD_DB6 LCD_DB7

J31

9 11 13

LCD_E

LCD_RS

2 43 65 87 10 12 14

NC NC

VCC5V0

Figure 1-21: LCD Interface Circuit

LCD_DB6 LCD_DB4

LCD_RW LCD_VEE

R92

6.81kΩ

GND

VCC5V0

R133

LCD Contrast

2 kΩ

Potentiometer

UG810_c1_21_031214

The KC705 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J31) with 0.025-inch square posts on 0.100-inch centers for connecting to a Samtec SLW-107-01-L-D female socket on the LCD display panel assembly. The LCD header shown in Figure 1-22.

X-Ref Target - Figure 1-22

Figure 1-22: LCD Header Details

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Table 1-23 lists the connections between the FPGA and the LCD header.

Table 1-23: FPGA to LCD Header Connections

FPGA Pin (U1) Schematic Net Name I/O Standard LCD Header Pin (J31)

AA13 LCD_DB4_LS LVCMOS15 4

AA10 LCD_DB5_LS LVCMOS15 3

AA11 LCD_DB6_LS LVCMOS15 2

Y10 LCD_DB7_LS LVCMOS15 1

AB13 LCD_RW_LS LVCMOS15 10

Y11 LCD_RS_LS LVCMOS15 11

AB10 LCD_E_LS LVCMOS15 9

For more information about the Displaytech S162D LCD, see [Ref 18].

I2C Bus Switch

[Figure 1-2, callout 20]

The KC705 board implements a single I2C port on the FPGA (IIC_SDA_MAIN, IIC_SDA_SCL), which is routed through a TI PCA9548 1-to-8 channel I2C switch (U49). U49 pin 24 net IIC_MUX_RESET_B is connected to U1 bank 15 pin P23. This is an active-Low signal and must be driven High (FPGA U1 pin P23) to enable I2C bus transactions between the FPGA U1 and the other components on the I2C bus. The I2C switch can operate at speeds up to 400 kHz. The U49 bus switch at I2C address 0x74/0b01110100 must be addressed and configured to select the desired target back-side device.

The KC705 board I2C bus topology is shown in Figure 1-23.

X-Ref Target - Figure 1-23

U49

PCA9548

FPGA

Bank 15

(2.5V)

IIC_SDA/SCL_MAIN

12C 1-to-8

Bus Switch

CH0 - USER_CLOCK_SDA/SCL

CH1 - FMC_HPC_IIC_SDA/SCL

CH2 - FMC_LPC_IIC_SDA/SCL

CH3 - EEPROM_IIC_SDA/SCL

CH4 - SFP_IIC_SDA/SCL

CH5 - IIC_SDA/SCL_HDMI

CH6 - IIC_SDA/SCL_DDR3

CH7 - SI5326_SDA/SCL

UG810_C1_23_031214

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Figure 1-23: I2C Bus Topology

User applications that communicate with devices on one of the downstream I2C buses must first set up a path to the desired bus through the U49 bus switch at I2C address 0x74/0b01110100.

Chapter 1: KC705 Evaluation Board Features

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Table 1-24 lists the address for each device on the I2C bus.

Table 1-24: I2C Devices

I2C Device

Si570 Clock 0 0b1011101

FMC HPC 1 0bXXXXXXX

FMC LPC 2 0bXXXXXXX

IIC EEPROM 3 0b1010100

SFP Module 4 0b1010000

ADV7511 HDMI 5 0b0111001

DDR3 SODIMM 6 0b1010000, 0b0011000

Si5324 Clock 7 0b1101000

I2C Switch

Position

I2C Address

For more information about the TI PCA9548 part, see [Ref 19].

Status LEDs

[Figure 1-2, callout 21]

Table 1-25 defines the status LEDs. For user controlled LEDs see User I/O.

Table 1-25: Status LEDs

Reference

Designator

DS14 PWRCTL1_VCC4A_PG Green FMC power good

DS20 FPGA_DONE Green FPGA configured successfully

DS21 FPGA_INIT_B Green/red GREEN: FPGA initialization successful,

DS22 VCC12_P_IN Green 12V power ON

DS23 PWRCTL_PWRGOOD Green UCD9248 power controllers (U55, U56) power

DS24 LINEAR_POWER_GOOD Green TPS51200 (U33) VTTDDR Power Good

Signal Name Color Description

RED: FPGA initialization in progress

good

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Ethernet PHY Status LEDs

[Figure 1-2, callout 21]

The Ethernet PHY status LEDs are mounted to be visible through the metal bracket on the left edge of the KC705 board when it is installed into a PCIe slot in a PC chassis. The six PHY status LEDs are located above the RJ45 Ethernet jack as shown in Figure 1-24.

X-Ref Target - Figure 1-24

Direction Indicator

Half Duplex 10

TX 100

RJ45 Ethernet

Jack

Link Rate (Mb/s)

1000

UG810_c1_24_031214

Figure 1-24: Ethernet PHY Status LEDs

Table 1-26 lists the Ethernet PHY status LEDs.

Table 1-26: Ethernet PHY Status LEDs

Reference

Designator

DS11 PHY_LED_RX GREEN Ethernet PHY RX

DS11 PHY_LED_LINK1000 GREEN Ethernet Link Speed is 1000 Mb/s

DS12 PHY_LED_TX GREEN Ethernet PHY TX

Signal Name Color Description

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DS12 PHY_LED_LINK100 GREEN Ethernet Link Speed is 100 Mb/s

DS13 PHY_LED_DUPLEX GREEN Ethernet Link is Half-duplex

DS13 PHY_LED_LINK10 GREEN Ethernet Link Speed is 10 Mb/s

User I/O

[Figure 1-2, callout 22 - 26]

The KC705 board provides the following user and general purpose I/O capabilities:

• Eight user LEDs (callout 22)

GPIO_LED_[7-0]: DS27, DS26, DS25, DS3, DS10, DS1, DS4

• Five user pushbuttons and reset switch (callout 23)

Chapter 1: KC705 Evaluation Board Features

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GPIO_SW_[NESWC]: SW2, SW3, SW4, SW6, SW5

CPU_RESET: SW7

• 4-position user DIP Switch (callout 24)

GPIO_DIP_SW[3:0]: SW11

• User Rotary Switch (callout 25, hidden beneath the LCD)

ROTARY_PUSH, ROTARY_INCA, ROTARY_INCB: SW8

• User SMA (callout 26)

USER_SMA_GPIO_P, USER_SMA_GPIO_N: J13, J14

• 2 line x 16 character LCD Character Display (callout 19)

If the display is unmounted, connector J31 pins are available as 7 independent 5V

GPIOs

User GPIO LEDs

[Figure 1-2, callout 34]

Figure 1-25 shows the user LED circuits.

X-Ref Target - Figure 1-25

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

GPIO_LED_4

GPIO_LED_5

GPIO_LED_6

GPIO_LED_7

DS27

R442

49.9Ω 1%

GND

DS26

R441

49.9Ω 1%

DS25

R440

49.9Ω 1%

Figure 1-25: User LEDs

DS3

R97

49.9Ω 1%

DS2

R96

49.9Ω 1%

DS10

R95

49.9Ω 1%

DS1

R94

49.9Ω 1%

UG810_c1_25_031214

DS4

R93

49.9Ω 1%

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X-Ref Target - Figure 1-26

UG810_c1_26_031214

VADJ

GPIO SW C

R13

4.7kΩ

0.1 W 5%

GND

SW5

VCC1V5

GPIO SW N

R13

4.7kΩ

0.1 W 5%

GND

SW2

VCC1V5

GPIO SW S

R12

4.7kΩ

0.1 W 5%

GND

SW4

VCC1V5

GPIO SW W

R14

4.7kΩ

0.1 W 5%

GND

SW6

VCC1V5

GPIO SW E

R11

4.7kΩ

0.1 W 5%

GND

SW3

Send Feedback

Chapter 1: KC705 Evaluation Board Features

User Pushbuttons

[Figure 1-2, callout 23]

Figure 1-26 shows the user pushbutton switch circuits.

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Figure 1-26: User Pushbuttons

X-Ref Target - Figure 1-27

UG810_c1_27_031214

VCC1V5

CPU_RESET

R15

4.7kΩ

0.1 W 5%

GND

SW7

UG810_c1_28_031214

SDA04H1SBD

SW11

VADJ

GPIO_DIP_SW3

GPIO_DIP_SW2

GPIO_DIP_SW1

GPIO_DIP_SW0

R25

4.7kΩ

0.1 W 5%

R24

4.7kΩ

0.1 W 5%

R23

4.7kΩ

0.1 W 5%

R22

4.7kΩ

0.1 W 5%

GND

Send Feedback

Chapter 1: KC705 Evaluation Board Features

CPU Reset Pushbutton

[Figure 1-2, callout 37]

Figure 1-27 shows the CPU reset pushbutton circuit.

Figure 1-27: CPU Reset Pushbutton

GPIO DIP Switch

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[Figure 1-2, callout 24]

Figure 1-28 shows the GPIO DIP Switch circuit.

X-Ref Target - Figure 1-28

Figure 1-28: GPIO DIP Switch

Rotary Switch

VCC1V8

GND

SW8

R31

4.7K 1/10W 5%

R30

4.7K 1/10W 5%

R32

4.7K 1/10W 5%

Edge Drive

Jog Encoder

EVQ-WK4001

GND

ROTARY INCB ROTARY PUSH

6 5 4 3 2 1

SW1B

SW2

SW1A

COM

UG810_c1_29_031214

ROTARY INCA

Send Feedback

Figure 1-29 shows the rotary switch SW8.

[Figure 1-2, callout 25]

X-Ref Target - Figure 1-29

Chapter 1: KC705 Evaluation Board Features

Figure 1-29: Rotary Switch SW8

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GPIO SMA Connectors

Send Feedback

Figure 1-30 shows the GPIO SMAs J13 and J14.

[Figure 1-2, callout 26]

X-Ref Target - Figure 1-30

J13

Chapter 1: KC705 Evaluation Board Features

SMA

Connector

GND

J14

SMA

Connector

GND

USER SMA GPIO P

USER SMA GPIO N

UG885_c1_30_031214

Figure 1-30: GPIO SMAs J13 and J14

Table 1-27 lists the GPIO Connections to FPGA U1.

Table 1-27: GPIO Connections to FPGA U1

U1 FPGA Pin Schematic Net Name I/O Standard GPIO Pin

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Indicator LEDs (Active High)

AB8 GPIO_LED_0 LVCMOS15 DS4.2

AA8 GPIO_LED_1 LVCMOS15 DS1.2

AC9 GPIO_LED_2 LVCMOS15 DS10.2

AB9 GPIO_LED_3 LVCMOS15 DS2.2

AE26 GPIO_LED_4 LVCMOS25 DS3.2

G19 GPIO_LED_5 LVCMOS25 DS25.2

E18 GPIO_LED_6 LVCMOS25 DS26.2

F16 GPIO_LED_7 LVCMOS25 DS27.2

Directional Pushbutton Switches

AA12 GPIO_SW_N LVCMOS15 SW2.1

AG5 GPIO_SW_E LVCMOS15 SW3.1

Chapter 1: KC705 Evaluation Board Features

Send Feedback

Table 1-27: GPIO Connections to FPGA U1 (Cont’d)

U1 FPGA Pin Schematic Net Name I/O Standard GPIO Pin

AB12 GPIO_SW_S LVCMOS15 SW4.1

AC6 GPIO_SW_W LVCMOS15 SW6.1

G12 GPIO_SW_C LVCMOS25 SW5.1

AB7 CPU_RESET LVCMOS15 SW7.1

4-Pole DIP Switch

Y29 GPIO_DIP_SW0 LVCMOS25 SW11.4

W29 GPIO_DIP_SW1 LVCMOS25 SW11.3

AA28 GPIO_DIP_SW2 LVCMOS25 SW11.2

Y28 GPIO_DIP_SW3 LVCMOS25 SW11.1

User Rotary Switch

Y25 ROTARY_INCB SW LVCMOS25 SW8.6

AA26 ROTARY_PUSH SW LVCMOS25 SW8.5

Y26 ROTARY_INCA SW LVCMOS25 SW8.1

User SMA

Y23 USER_SMA_GPIO_P LVCMOS25 J13.1

Y24 USER_SMA_GPIO_N LVCMOS25 J14.1

Switches

[Figure 1-2, callout 27 - 28]

The KC705 evaluation board includes a power and a configuration switch:

• Power on/off slide switch SW15 (callout 27)

• FPGA_PROG_B SW14, active-Low (callout 28)

Power On/Off Slide Switch SW15

[Figure 1-2, callout 27]

The KC705 board power switch is SW15. Sliding the switch actuator from the Off to On position applies 12V power from J49, a 6-pin mini-fit connector. Green LED DS22 illuminates when the KC705 board power is on. See Power Management for details on the onboard power system.

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Chapter 1: KC705 Evaluation Board Features

VCC12_P_IN

VCC12_P

R369 1kΩ 1%

INPUT_GND

SW15

GND

C539 330μF 25V

C804

1μF 25V

GND

DS22

J49

12V

N/C

COM

12V

N/C

COM

INPUT_GND

Powe r

PCIe

U115

UG810_c1_31_031214

UG810_c1_32_031214

To ATX 4-Pin Peripheral

Power Connector

To J49 on KC705 Board

Send Feedback

CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J49 on the KC705 board The ATX

6-pin connector has a different pinout than J49. Connecting an ATX 6-pin connector into J49 will damage the KC705 board and void the board warranty.

Figure 1-31 shows the power connector J49, power switch SW15 and indicator LED DS22.

X-Ref Target - Figure 1-31

Figure 1-31: Power On/Off Switch SW15

The KC705 Evaluation Kit provides the adapter cable shown in Figure 1-32 for powering the KC705 board from the ATX power supply 4-pin peripheral connector. The Xilinx part number for this cable is 2600304, and is equivalent to Sourcegate Technologies part number AZCBL-WH-1109-RA4. For information on ordering this cable, see [Ref 20].

X-Ref Target - Figure 1-32

Figure 1-32: ATX Power Supply Adapter Cable

FPGA_PROG_B Pushbutton SW14 (Active-Low)

[Figure 1-2, callout 28]

Switch SW14 grounds the FPGA PROG_B pin when pressed. This action initiates an FPGA reconfiguration. The FPGA_PROG_B signal is connected to FPGA U1 pin K10.

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See 7 Series FPGAs Configuration User Guide (UG470) [Ref 2] for further details on configuring the 7 series FPGAs.

Chapter 1: KC705 Evaluation Board Features

Send Feedback

Figure 1-33 shows SW14.

X-Ref Target - Figure 1-33

VCC2V5

R295

4.7kΩ

0.1 W 5%

FPGA_PROG_B

SW14

GND

UG810_c1_33_031214

Figure 1-33: FPGA_PROG_B Pushbutton SW14

Configuration Mode and Upper Linear Flash Address Switch (SW13)

[Figure 1-2, callout 29]

FPGA Configuration Mode: DIP switch SW13 positions 3, 4, and 5 control which configuration mode is used at power-up or when the PROG pushbutton is pressed.

Linear BPI Flash Memory Upper Addresses: DIP switch SW13 positions 1 and 2 control the setting of address bits FLASH_A25 and FLASH_A24. The mode signals FPGA_M2, _M1 and _M0 are connected to FPGA U1 pins AB1, AB2 and AB5 respectively. The BPI flash memory U58 address signals FLASH_A24 AND FLASH_A25 are connected to FPGA U1 pins M23 and M22 respectively. Configuration mode is used at power-up or when the PROG pushbutton is pressed.

Figure 1-34 shows the SW13 circuit.

X-Ref Target - Figure 1-34

VCC2V5

SW13

FLASH_A25

FLASH_A24

FPGA_M2

FPGA_M1

FPGA_M0

R396

1.21kΩ

0.1 W 1%

R397

1.21kΩ

0.1 W 1%

R398

1.21kΩ

0.1 W 1%

R399

1.21kΩ

0.1 W 1%

SDA05H1SBD

R400

1.21kΩ

0.1 W 1%

R401 220Ω

0.1 W 1%

R402 220Ω

0.1 W 1%

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GND

UG810_c1_34_031214

Figure 1-34: Configuration Mode and Upper Linear Flash Address Switch

Chapter 1: KC705 Evaluation Board Features

Send Feedback

FPGA Mezzanine Card Interface

[Figure 1-2, callout 30 - 31]

The KC705 evaluation board for the Kintex-7 FPGA supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by providing subset implementations of a high pin count (HPC) connector at J22 and a low pin count (LPC) connector at J2. Both connectors use the same 10 x 40 form factor, except the HPC version is fully populated with 400 pins and the LPC version is partially populated with 160 pins. Both connectors are keyed so that a the mezzanine card faces away from the KC705 board when connected.

Signaling Speed Ratings:

• Single-ended: 9 GHz (18 Gb/s)

• Differential Optimal Vertical: 9 GHz (18 Gb/s)

• Differential Optimal Horizontal: 16 GHz (32 Gb/s)

• High Density Vertical: 7 GHz (15 Gb/s)

The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3 dB insertion loss point within a two-level signaling environment.

Connector Type:

• Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector

For more information about SEAF series connectors see [Ref 19].

HPC Connector J22

[Figure 1-2, callout 30]

The 400-pin HPC connector defined by the FMC specification (Figure B-1, page 86) provides connectivity for up to:

• 160 single-ended or 80 differential user-defined signals

• 10 GTX transceivers

•2 GTX clocks

• 4 differential clocks

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• 159 ground and 15 power connections

The connections between the HPC connector at J22 and FPGA U1 (Table 1-28) implement a subset of this connectivity:

• 58 differential user defined pairs

Chapter 1: KC705 Evaluation Board Features

Send Feedback

34 LA pairs (LA00-LA33)

24 HA pairs (HA00-HA23)

•4 GTX transceivers

•2 GTX clocks

• 2 differential clocks

• 159 ground and 15 power connections

The HPC signals are distributed across GTX Quads 116, 117, and 118. Each of these Quads have their VCCO voltage connected to VADJ.

Note:

power sequencing logic described in Power Management, page 71.

The KC705 board VADJ voltage for the J22 and J2 connectors is determined by the FMC VADJ

Table 1-28: HPC Connections, J22 to FPGA U1

J22 Pin Schematic Net Name

A2 FMC_HPC_DP1_M2C_P D6 B1 NC

A3 FMC_HPC_DP1_M2C_N D5 B4 NC

A6 FMC_HPC_DP2_M2C_P B6 B5 NC

A7 FMC_HPC_DP2_M2C_N B5 B8 NC

A10 FMC_HPC_DP3_M2C_P A8 B9 NC

A11 FMC_HPC_DP3_M2C_N A7 B12 NC

A14 NC B13 NC

A15 NC B16 NC

A18 NC B17 NC

A19 NC B20 FMC_HPC_GBTCLK1_M2C_P LVDS E8

A22 FMC_HPC_DP1_C2M_P C4 B21 FMC_HPC_GBTCLK1_M2C_N LVDS E7

A23 FMC_HPC_DP1_C2M_N C3 B24 NC

I/O

Standard

FPGA

U1 Pin

J22 Pin Schematic Net Name

I/O

Standard

FPGA

U1 Pin

A26 FMC_HPC_DP2_C2M_P B2 B25 NC

A27 FMC_HPC_DP2_C2M_N B1 B28 NC

A30 FMC_HPC_DP3_C2M_P A4 B29 NC

A31 FMC_HPC_DP3_C2M_N A3 B32 NC

A34 NC B33 NC

A35 NC B36 NC

A38 NC B37 NC

A39 NC B40 NC

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Table 1-28: HPC Connections, J22 to FPGA U1 (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

J22 Pin Schematic Net Name

C2 FMC_HPC_DP0_C2M_P D2 D1 PWRCTL1_VCC4A_PG

C3 FMC_HPC_DP0_C2M_N D1 D4 FMC_HPC_GBTCLK0_M2C_P LVDS C8

C6 FMC_HPC_DP0_M2C_P E4 D5 FMC_HPC_GBTCLK0_M2C_N LVDS C7

C7 FMC_HPC_DP0_M2C_N E3 D8 FMC_HPC_LA01_CC_P LVDS D26

C10 FMC_HPC_LA06_P LVDS H30 D9 FMC_HPC_LA01_CC_N LVDS C26

C11 FMC_HPC_LA06_N LVDS G30 D11 FMC_HPC_LA05_P LVDS G29

C14 FMC_HPC_LA10_P LVDS D29 D12 FMC_HPC_LA05_N LVDS F30

C15 FMC_HPC_LA10_N LVDS C30 D14 FMC_HPC_LA09_P LVDS B30

C18 FMC_HPC_LA14_P LVDS B28 D15 FMC_HPC_LA09_N LVDS A30

C19 FMC_HPC_LA14_N LVDS A28 D17 FMC_HPC_LA13_P LVDS A25

C22 FMC_HPC_LA18_CC_P LVDS F21 D18 FMC_HPC_LA13_N LVDS A26

C23 FMC_HPC_LA18_CC_N LVDS E21 D20 FMC_HPC_LA17_CC_P LVDS F20

C26 FMC_HPC_LA27_P LVDS C19 D21 FMC_HPC_LA17_CC_N LVDS E20

C27 FMC_HPC_LA27_N LVDS B19 D23 FMC_HPC_LA23_P LVDS B22

C30 FMC_HPC_IIC_SCL D24 FMC_HPC_LA23_N LVDS A22

I/O

Standard

FPGA

U1 Pin

J22 Pin Schematic Net Name

I/O

Standard

U1 Pin

FPGA

C31 FMC_HPC_IIC_SDA D26 FMC_HPC_LA26_P LVDS B18

C34 GA0=0=GND D27 FMC_HPC_LA26_N LVDS A18

C35 VCC12_P D29 FMC_HPC_TCK_BUF

C37 VCC12_P D30 FMC_TDI_BUF

C39 VCC3V3 D31 FMC_HPC_TDO_LPC_TDI

D32 VCC3V3

D33 FMC_TMS_BUF

D34 NC

D35 GA1=0=GND

D36 VCC3V3

D38 VCC3V3

D40 VCC3V3

E2 FMC_HPC_HA01_CC_P LVDS H14 F1 FMC_HPC_PG_M2C LVDS J29

E3 FMC_HPC_HA01_CC_N LVDS G14 F4 FMC_HPC_HA00_CC_P LVDS D12

E6 FMC_HPC_HA05_P LVDS F15 F5 FMC_HPC_HA00_CC_N LVDS D13

E7 FMC_HPC_HA05_N LVDS E16 F7 FMC_HPC_HA04_P LVDS F11

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Table 1-28: HPC Connections, J22 to FPGA U1 (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

J22 Pin Schematic Net Name

E9 FMC_HPC_HA09_P LVDS F12 F8 FMC_HPC_HA04_N LVDS E11

E10 FMC_HPC_HA09_N LVDS E13 F10 FMC_HPC_HA08_P LVDS E14

E12 FMC_HPC_HA13_P LVDS L16 F11 FMC_HPC_HA08_N LVDS E15

E13 FMC_HPC_HA13_N LVDS K16 F13 FMC_HPC_HA12_P LVDS C15

E15 FMC_HPC_HA16_P LVDS L15 F14 FMC_HPC_HA12_N LVDS B15

E16 FMC_HPC_HA16_N LVDS K15 F16 FMC_HPC_HA15_P LVDS H15

E18 FMC_HPC_HA20_P LVDS K13 F17 FMC_HPC_HA15_N LVDS G15

E19 FMC_HPC_HA20_N LVDS J13 F19 FMC_HPC_HA19_P LVDS H11

E21 NC F20 FMC_HPC_HA19_N LVDS H12

E22 NC F22 NC

E24 NC F23 NC

E25 NC F25 NC

E27 NC F26 NC

E28 NC F28 NC

E30 NC F29 NC

I/O

Standard

FPGA

U1 Pin

J22 Pin Schematic Net Name

I/O

Standard

U1 Pin

FPGA

E31 NC F31 NC

E33 NC F32 NC

E34 NC F34 NC

E36 NC F35 NC

E37 NC F37 NC

E39 VADJ F38 NC

F40 VADJ

G2 FMC_HPC_CLK1_M2C_P LVDS D17 H1 NC

G3 FMC_HPC_CLK1_M2C_N LVDS D18 H2 FMC_HPC_PRSNT_M2C_B LVCMOS25M20

G6 FMC_HPC_LA00_CC_P LVDS C25 H4 FMC_HPC_CLK0_M2C_P LVDS D27

G7 FMC_HPC_LA00_CC_N LVDS B25 H5 FMC_HPC_CLK0_M2C_N LVDS C27

G9 FMC_HPC_LA03_P LVDS H26 H7 FMC_HPC_LA02_P LVDS H24

G10 FMC_HPC_LA03_N LVDS H27 H8 FMC_HPC_LA02_N LVDS H25

G12 FMC_HPC_LA08_P LVDS E29 H10 FMC_HPC_LA04_P LVDS G28

G13 FMC_HPC_LA08_N LVDS E30 H11 FMC_HPC_LA04_N LVDS F28

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Table 1-28: HPC Connections, J22 to FPGA U1 (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

J22 Pin Schematic Net Name

G15 FMC_HPC_LA12_P LVDS C29 H13 FMC_HPC_LA07_P LVDS E28

G16 FMC_HPC_LA12_N LVDS B29 H14 FMC_HPC_LA07_N LVDS D28

G18 FMC_HPC_LA16_P LVDS B27 H16 FMC_HPC_LA11_P LVDS G27

G19 FMC_HPC_LA16_N LVDS A27 H17 FMC_HPC_LA11_N LVDS F27

G21 FMC_HPC_LA20_P LVDS E19 H19 FMC_HPC_LA15_P LVDS C24

G22 FMC_HPC_LA20_N LVDS D19 H20 FMC_HPC_LA15_N LVDS B24

G24 FMC_HPC_LA22_P LVDS C20 H22 FMC_HPC_LA19_P LVDS G18

G25 FMC_HPC_LA22_N LVDS B20 H23 FMC_HPC_LA19_N LVDS F18

G27 FMC_HPC_LA25_P LVDS G17 H25 FMC_HPC_LA21_P LVDS A20

G28 FMC_HPC_LA25_N LVDS F17 H26 FMC_HPC_LA21_N LVDS A21

G30 FMC_HPC_LA29_P LVDS C17 H28 FMC_HPC_LA24_P LVDS A16

G31 FMC_HPC_LA29_N LVDS B17 H29 FMC_HPC_LA24_N LVDS A17

G33 FMC_HPC_LA31_P LVDS G22 H31 FMC_HPC_LA28_P LVDS D16

G34 FMC_HPC_LA31_N LVDS F22 H32 FMC_HPC_LA28_N LVDS C16

G36 FMC_HPC_LA33_P LVDS H21 H34 FMC_HPC_LA30_P LVDS D22

I/O

Standard

FPGA

U1 Pin

J22 Pin Schematic Net Name

I/O

Standard

U1 Pin

FPGA

G37 FMC_HPC_LA33_N LVDS H22 H35 FMC_HPC_LA30_N LVDS C22

G39 VADJ H37 FMC_HPC_LA32_P LVDS D21

H38 FMC_HPC_LA32_N LVDS C21

H40 VADJ

J2 NC K1 NC

J3 NC K4 NC

J6 FMC_HPC_HA03_P LVDS C12 K5 NC

J7 FMC_HPC_HA03_N LVDS B12 K7 FMC_HPC_HA02_P LVDS D11

J9 FMC_HPC_HA07_P LVDS B14 K8 FMC_HPC_HA02_N LVDS C11

J10 FMC_HPC_HA07_N LVDS A15 K10 FMC_HPC_HA06_P LVDS D14

J12 FMC_HPC_HA11_P LVDS B13 K11 FMC_HPC_HA06_N LVDS C14

J13 FMC_HPC_HA11_N LVDS A13 K13 FMC_HPC_HA10_P LVDS A11

J15 FMC_HPC_HA14_P LVDS J16 K14 FMC_HPC_HA10_N LVDS A12

J16 FMC_HPC_HA14_N LVDS H16 K16 FMC_HPC_HA17_CC_P LVDS G13

J18 FMC_HPC_HA18_P LVDS K14 K17 FMC_HPC_HA17_CC_N LVDS F13

J19 FMC_HPC_HA18_N LVDS J14 K19 FMC_HPC_HA21_P LVDS J11

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Table 1-28: HPC Connections, J22 to FPGA U1 (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

J22 Pin Schematic Net Name

J21 FMC_HPC_HA22_P LVDS L11 K20 FMC_HPC_HA21_N LVDS J12

J22 FMC_HPC_HA22_N LVDS K11 K22 FMC_HPC_HA23_P LVDS L12

J24 NC K23 FMC_HPC_HA23_N LVDS L13

J25 NC K25 NC

J27 NC K26 NC

J28 NC K28 NC

J30 NC K29 NC

J31 NC K31 NC

J33 NC K32 NC

J34 NC K34 NC

J36 NC K35 NC

J37 NC K37 NC

J39 NC K38 NC

I/O

Standard

FPGA

U1 Pin

J22 Pin Schematic Net Name

K40 NC

I/O

Standard

FPGA

U1 Pin

LPC Connector J2

[Figure 1-2, callout 31]

The 160-pin LPC connector defined by the FMC specification (Figure B-2, page 87) provides connectivity for up to:

• 68 single-ended or 34 differential user-defined signals

•1 GTX transceiver

•1 GTX clock

• 2 differential clocks

• 61 ground and 10 power connections

The connections between the LPC connector at J2 and FPGA U1 (Table 1-29) implement a subset of this connectivity:

• 34 differential user defined pairs

34 LA pairs (LA00-LA33)

•1 GTX transceiver

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•1 GTX clock

• 2 differential clocks

Send Feedback

• 61 ground and 9 power connections

Table 1-29: LPC Connections, J2 to FPGA U1

Chapter 1: KC705 Evaluation Board Features

J2 Pin Schematic Net Name

C2 FMC_LPC_DP0_C2M_P F2 D1 PWRCTL1_VCC4A_PG

C3 FMC_LPC_DP0_C2M_N F1 D4 FMC_LPC_GBTCLK0_M2C_P LVDS N8

C6 FMC_LPC_DP0_M2C_P F6 D5 FMC_LPC_GBTCLK0_M2C_N LVDS N7

C7 FMC_LPC_DP0_M2C_N F5 D8 FMC_LPC_LA01_CC_P LVDS AE23

C10 FMC_LPC_LA06_P LVDS AK20 D9 FMC_LPC_LA01_CC_N LVDS AF23

C11 FMC_LPC_LA06_N LVDS AK21 D11 FMC_LPC_LA05_P LVDS AG22

C14 FMC_LPC_LA10_P LVDS AJ24 D12 FMC_LPC_LA05_N LVDS AH22

C15 FMC_LPC_LA10_N LVDS AK25 D14 FMC_LPC_LA09_P LVDS AK23

C18 FMC_LPC_LA14_P LVDS AD21 D15 FMC_LPC_LA09_N LVDS AK24

C19 FMC_LPC_LA14_N LVDS AE21 D17 FMC_LPC_LA13_P LVDS AB24

C22 FMC_LPC_LA18_CC_P LVDS AD27 D18 FMC_LPC_LA13_N LVDS AC25

C23 FMC_LPC_LA18_CC_N LVDS AD28 D20 FMC_LPC_LA17_CC_P LVDS AB27

C26 FMC_LPC_LA27_P LVDS AJ28 D21 FMC_LPC_LA17_CC_N LVDS AC27

C27 FMC_LPC_LA27_N LVDS AJ29 D23 FMC_LPC_LA23_P LVDS AH26

I/O

Standard

FPGA

Schematic Net Name

I/O

Standard

FPGA

C30 FMC_LPC_IIC_SCL D24 FMC_LPC_LA23_N LVDS AH27

C31 FMC_LPC_IIC_SDA D26 FMC_LPC_LA26_P LVDS AK29

C34 GA0=0=GND D27 FMC_LPC_LA26_N LVDS AK30

C35 VCC12_P D29 FMC_LPC_TCK_BUF

C37 VCC12_P D30 FMC_HPC_TDO_LPC_TDI

C39 VCC3V3 D31 FMC_LPC_TDO_FPGA_TDI

D32 VCC3V3

D33 FMC_LPC_TMS_BUF

D34 NC

D35 GA1=0=GND

D36 VCC3V3

D38 VCC3V3

D40 VCC3V3

G2 FMC_LPC_CLK1_M2C_P LVDS AG29 H1 NC

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Table 1-29: LPC Connections, J2 to FPGA U1 (Cont’d)

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Chapter 1: KC705 Evaluation Board Features

J2 Pin Schematic Net Name

G3 FMC_LPC_CLK1_M2C_N LVDS AH29 H2 FMC_LPC_PRSNT_M2C_B LVCMOS25

G6 FMC_LPC_LA00_CC_P LVCOMS18AD23 H4 FMC_LPC_CLK0_M2C_P LVDS AF22

G7 FMC_LPC_LA00_CC_N LVCOMS18AE24 H5 FMC_LPC_CLK0_M2C_N LVDS AG23

G9 FMC_LPC_LA03_P LVDS AG20 H7 FMC_LPC_LA02_P LVDS AF20

G10 FMC_LPC_LA03_N LVDS AH20 H8 FMC_LPC_LA02_N LVDS AF21

G12 FMC_LPC_LA08_P LVDS AJ22 H10 FMC_LPC_LA04_P LVDS AH21

G13 FMC_LPC_LA08_N LVDS AJ23 H11 FMC_LPC_LA04_N LVDS AJ21

G15 FMC_LPC_LA12_P LVDS AA20 H13 FMC_LPC_LA07_P LVDS AG25

G16 FMC_LPC_LA12_N LVDS AB20 H14 FMC_LPC_LA07_N LVDS AH25

G18 FMC_LPC_LA16_P LVDS AC22 H16 FMC_LPC_LA11_P LVDS AE25

G19 FMC_LPC_LA16_N LVDS AD22 H17 FMC_LPC_LA11_N LVDS AF25

G21 FMC_LPC_LA20_P LVDS AF26 H19 FMC_LPC_LA15_P LVDS AC24

G22 FMC_LPC_LA20_N LVDS AF27 H20 FMC_LPC_LA15_N LVDS AD24

I/O

Standard

FPGA

Schematic Net Name

I/O

Standard

FPGA

G24 FMC_LPC_LA22_P LVDS AJ27 H22 FMC_LPC_LA19_P LVDS AJ26

G25 FMC_LPC_LA22_N LVDS AK28 H23 FMC_LPC_LA19_N LVDS AK26

G27 FMC_LPC_LA25_P LVDS AC26 H25 FMC_LPC_LA21_P LVDS AG27

G28 FMC_LPC_LA25_N LVDS AD26 H26 FMC_LPC_LA21_N LVDS AG28

G30 FMC_LPC_LA29_P LVDS AE28 H28 FMC_LPC_LA24_P LVDS AG30

G31 FMC_LPC_LA29_N LVDS AF28 H29 FMC_LPC_LA24_N LVDS AH30

G33 FMC_LPC_LA31_P LVDS AD29 H31 FMC_LPC_LA28_P LVDS AE30

G34 FMC_LPC_LA31_N LVDS AE29 H32 FMC_LPC_LA28_N LVDS AF30

G36 FMC_LPC_LA33_P LVDS AC29 H34 FMC_LPC_LA30_P LVDS AB29

G37 FMC_LPC_LA33_N LVDS AC30 H35 FMC_LPC_LA30_N LVDS AB30

G39 VADJ H37 FMC_LPC_LA32_P LVDS Y30

H38 FMC_LPC_LA32_N LVDS AA30

H40 VADJ

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Chapter 1: KC705 Evaluation Board Features

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Power Management

[Figure 1-2, callout 32]

The KC705 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply core and auxiliary voltages. The Texas Instruments Fusion Digital Power graphical user interface (GUI) is used to monitor the current and temperature levels of the board power modules. If any module temperature approaches 85°C then forced air cooling must be provided to keep the module temperature within rated limits.

The PCB layout and power system have been designed to meet the recommended criteria described in 7 Series FPGAs PCB Design and Pin Planning Guide (UG483) [Ref 21].

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UG810_c1_35_031214

VCCAUX

VCC3V3

VAD J

VCC1V8

VCC1V5

VCC2V5

MGTAVTT

VCC12_P

Power Plane

From SW15

MGTAVCC

VCCINT

XADC VCC

VCC5V0

VCCAUX_IO

VCC_SPI

VCCBRAM

MGTVCCAUX

Power Controller 2 (Aux) U56 Address 53

Switching Regulator

2.5V at 10A

U104

Switching Regulator

1.5V at 10A

Switching Regulator

1.2V at 10A

U105

Switching Regulator

1.0V at 10A

Linear Regulator

5.0V at 2A

U71

Linear Regulator

1.7V - 2.0V at 300 mA

U39

Linear Regulator

2.8V at 300 MA

U62

Switching Regulator

1.8V at 10A

U99

Power Controller 3 U89 Address 54

Switching Regulator

1.0V at 10A

U106

Switching Regulator

2.0V at 10A

Switching Regulator 0V - 3.3V at 10A

U17

Switching Regulator

1.0V at 20A

U21

Linear Regulator

1.8V at 1.5A

U62

Power Controller 1 (Core) U55 Address 52

Switching Regulator

3.3V at 10A

U103

Switching Regulator

1.8V at 20A

U55

U56

U89

Send Feedback

The KC705 board power distribution diagram is shown in Figure 1-35.

X-Ref Target - Figure 1-35

Chapter 1: KC705 Evaluation Board Features

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Figure 1-35: KC705 Board Onboard Power Regulators

The KC705 board core and auxiliary voltages are listed in Table 1-30.

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Table 1-30: Onboard Power System Devices

Chapter 1: KC705 Evaluation Board Features

Device Type

Reference

Designator

Description

Core Voltage Controller and Regulators

UCD9248PFC

PTD08A020W U21 Adjustable switching regulator

PTD08D021W

OUT

PTD08D021W

OUT

PTD08A010W U17 Adjustable switching regulator

(1)

U55 PMBus Controller (Addr = 52) 36

20A, 0.6V to 3.6V

U103 Adjustable switching regulator

dual 10A, 0.6Vto 3.6V

Adjustable switching regulator dual 10A, 0.6Vto 3.6V

10A, 0.6V to 3.6V

Auxiliary Voltage Controller and Regulators

UCD9248PFC

PTD08D021W

OUT

PTD08D021W

OUT

PTD08D021W

OUT

PTD08D021W

OUT

UCD9248PFC

(2)

(3)

U56 PMBus Controller

(Addr = 53)

U104 Adjustable switching regulator

dual 10A, 0.6Vto 3.6V

Adjustable switching regulator dual 10A, 0.6Vto 3.6V

U105 Adjustable switching regulator

dual 10A, 0.6Vto 3.6V

Adjustable switching regulator dual 10A, 0.6Vto 3.6V

U89 PMBus Controller

(Addr = 54)

Power Rail Net

Name

VCCINT_FPGA 1.00V 37

VCCAUX 1.80V 38

VCC3V3 3.30V 38

VCC_ADJ 0-3.30V 39

VCC2V5_FPGA 2.50V 41

VCC1V5_FPGA 1.50V 41

MGTAVCC 1.00V 42

MGTAVTT 1.20V 42

Power Rail

Voltage

Schematic

Page

PTD08D021W (V

OUT

PTD08D021W (V

OUT

PTD08A010W U99 10A 0.6V - 3.6V Adj. Switching

Linear Regulators

LMZ12002 U71 Fixed Linear Regulator 2A VCC5V0 5.00V 46

TL1962ADC U62 Fixed Linear Regulator, 1.5A VCC1V8 1.80V 46

ADP123 U17 Fixed Linear Regulator, 300mA VCC_SPI 2.80V 46

ADP123 U18 Fixed Linear Regulator, 300mA XADC_VCC 1.80V 31

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U106 Dual 10A 0.6V - 3.6V Adj. Switching

Regulator

Dual 10A 0.6V - 3.6V Adj. Switching Regulator

Regulator

VCCAUX_IO 2.00V 44

VCCBRAM 1.00V 44

MGTVCCAUX 1.80V 45

Table 1-30: Onboard Power System Devices (Cont’d)

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Chapter 1: KC705 Evaluation Board Features

Device Type

TPS51200DR U33 Tracking Regulator, 3A VTTDDR 0.75V 46

Notes:

1. See Table 1-31.

2. See Table 1-32.

3. See Table 1-33.

Reference

Designator

Description

Power Rail Net

Name

Power Rail

Voltage

Schematic

Page

FMC_VADJ Voltage Control

The FMC_VADJ rail is set to 2.5V. When the KC705 board is powered on, the state of the FMC_VADJ_ON_B signal wired to header J65 is sampled by the Texas Instruments UCD9248 controller U55. If a jumper is installed on J65, signal FMC_VADJ_ON_B is held low, and the TI controller U55 energizes the FMC_VADJ rail at power on.

Because the rail turn on decision is made at power on time based on the presence of the J65 jumper, removing the jumper at J65 after the board is powered up does not affect the 2.5V power delivered to the FMC_VADJ rail and it remains on.

A jumper installed at J65 is the default setting.

If a jumper is not installed on J65, signal FMC_VADJ_ON_B is High, and the KC705 board does not energize the FMC_VADJ 2.5V at power on. In this mode you can control when to turn on FMC_VADJ and to what voltage level (1.8V - 3.3V). With FMC_VADJ off, the FPGA still configures and has access to the TI controller PMBUS (on bank 32) along with the FMC_VADJ_ON_B signal (on bank 15 pin J27). The combination of these allows you to develop code to command the FMC_VADJ rail to be set to something other than the default setting of 2.5V. After the new FMC_VADJ voltage level has been programmed into TI controller U55, the FMC_VADJ_ON_B signal can be driven Low by the user logic and the FMC_VADJ rail comes up at the new FMC_VADJ voltage level. Installing a jumper at J65 after a KC705 board powers up in this mode turns on the FMC_VADJ rail.

For access to Texas Instruments fusion tools documentation describing PMBUS programming for the UCD9248 digital power controller, see [Ref 19].

Cooling Fan Control

Cooling fan RPM is controlled and monitored by user-created IP in the FPGA using the fan control circuit is shown in Figure 1-36.

FPGA U1 is cooled by a 12V DC fan connected to J61. 12V J61 pin 2. The fan GND return is provided through J61 pin 1 and transistor Q17. Fan speed is controlled by a pulse-width-modulated signal from FPGA U1 pin L26 (on bank 15) driving the gate of Q17. The default unprogrammed FPGA fan operation mode is ON. The fan speed tachometer signal on J61 pin 3 can be monitored on FPGA U1 pin U22 (on bank 14).

is provided to the fan through

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X-Ref Target - Figure 1-36

GND

SM_FAN_PWM

SM_FAN_TACH

J61

R392

10.0K 1% 1/10W

GND

R391

1.00K 1% 1/16W

D15

2.7V 500 mW MM3Z2V7B

R390

4.75K 1% 1/10W

R393

10.0K 1% 1/10W

VCC12_P

D14 100V 500 mW DL4148

Q17 NDT30555L

1.3 W

VCC2V5

UG810_c1_36_031214

Cooling

Fan

FPGA

U1 Pin L26

FPGA

U1 Pin U22

Fan GND

Fan +12V

Fan Tach

Send Feedback

Figure 1-36: FPGA Cooling Fan Circuit

Monitoring Voltage and Current

Chapter 1: KC705 Evaluation Board Features

Voltage and current monitoring and control are available for selected power rails through the Texas Instruments Fusion Digital Power GUI. The three onboard TI power controllers (U55 at address 52, U56 at address 53, and U89 at address 54) are wired to the same PMBus. The PMBus connector, J39, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the TI website [Ref 23], and the associated TI Fusion Digital Power Designer GUI (downloadable from [Ref 24]). This is the simplest and most convenient way to monitor the voltage and current values for the power rail listed in Table 1-31, Table 1-32 and Table 1-33.

In each of these the three tables (one per controller), the Power Good (PG) On Threshold is the set-point at or below which the particular rail is deemed “good”. The PG Off Threshold is the set-point at or below which the particular rail is no longer deemed “good”. The controller internally ORs these PG conditions together and drives an output PG pin High only if all active rail PG states are “good”. The On and Off Delay and rise and fall times are relative to when the board power on-off slide switch SW15 is turned on and off.

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Chapter 1: KC705 Evaluation Board Features

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Table 1-31 defines the voltage and current values for each power rail controlled by the

UCD9248 PMBus controller at Address 52 (U55).

Table 1-31: Power Rail Specifications for UCD9248 PMBus controller at Address 52

Shutdown

Threshold

Rail Number

Rail Name

Schematic Rail Name

(V)

OUT

Over Fault (V)

Nominal V

1 Rail #1 VCCINT_FPGA 1 0.9 0.85 0 5 10 1 1.15 20 90

2 Rail #2 VCCAUX 1.8 1.62 1.53 0 5 5 1 2.07 10.41 90

3 Rail #3 VCC3V3 3.3 2.97 2.805 0 5 4 1 3.795 10.41 90

4 Rail #4 VADJ 2.5 2.25 2.125 0 5 3 1 2.875 10.41 90

Notes:

1. The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded.

PG On Threshold (V)

PG Off Threshold (V)

On Delay (ms)

Rise Time (ms)

Off Delay (ms)

Fall Time (ms)

OUT

(1)

Over Fault (A)

OUT

Temp Ove r Faul t ( ° C)

Table 1-32 defines the voltage and current values for each power rail controlled by the

UCD9248 PMBus controller at Address 53 (U56).

Table 1-32: Power Rail Specifications for UCD9248 PMBus controller at Address 53

Shutdown

Threshold

Rail Number

Rail Name

Schematic Rail Name

(V)

OUT

Over Fault (V)

Nominal V

1 Rail #1 VCC2V5_FPGA 2.5 2.25 2.125 0 5 1 1 2.875 10.41 90

2 Rail #2 VCC1V5 1.5 1.35 1.275 0 5 0 1 1.725 10.41 90

3 Rail #3 MGTAVCC 1 0.9 0.85 0 5 7 1 1.45 10.41 90

PG On Threshold (V)

PG Off Threshold (V)

On Delay (ms)

Rise Time (ms)

Off Delay (ms)

Fall Time (ms)

OUT

(1)

Over Fault (A)

OUT

Temp Ove r Fa ul t (° C )

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Chapter 1: KC705 Evaluation Board Features

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Table 1-32: Power Rail Specifications for UCD9248 PMBus controller at Address 53 (Cont’d)

Shutdown

Threshold

Rail Number

Rail Name

Schematic Rail Name

(V)

OUT

Over Fault (V)

Nominal V

4 Rail #4 MGTAVTT 1.2 1.08 1.02 0 5 8 1 1.38 10.41 90

Notes:

1. The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded.

PG On Threshold (V)

PG Off Threshold (V)

On Delay (ms)

Rise Time (ms)

Off Delay (ms)

Fall Time (ms)

OUT

(1)

Over Fault (A)

OUT

Temp Ove r Fa ul t (° C )

Table 1-33 defines the voltage and current values for each power rail controlled by the

UCD9248 PMBus controller at Address 54 (U89).

Table 1-33: Power Rail Specifications for UCD9248 PMBus controller at Address 54

Shutdown

Threshold

Rail Number

Rail Name

Schematic Rail Name

(V)

OUT

Over Fault (V)

Nominal V

1 Rail #1 VCCAUX_IO 2 1.8 1.7 0 5 2 1 10.41 90

2 Rail #2 VCC_BRAM 1 0.9 0.85 0 5 9 1 10.41 90

3 Rail #3 MGTVCCAUX 1.8 1.62 1.53 0 5 6 1 10.41 90

Notes:

1. The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded.

PG On Threshold (V)

PG Off Threshold (V)

On Delay (ms)

Rise Time (ms)

Off Delay (ms)

Fall Time (ms)

OUT

(1)

Over Fault (A)

OUT

Tem p Ov er F a ul t ( ° C)

For more information about the UCD9248PFC, PTD08A010W, PTD08A020W, PTD08D021W, LMZ12002, TL1962ADC, and TPS51200DR power system components, see [Ref 19].

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X-Ref Target - Figure 1-37

Send Feedback

Chapter 1: KC705 Evaluation Board Features

XADC Header

[Figure 1-2, callout 33]

7 series FPGAs provide an analog-to-digital converter (XADC) block. The XADC block includes a dual 12-bit, 1 MSPS analog-to-digital converter (ADC) and on-chip sensors.

See 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 25] for details on the capabilities of the analog front end. Figure 1-37 shows the KC705 board XADC support features.

VCCAUX

Ferrite Bead

FPGA

VCCADC

To J69.3

XADC_VCC

100 nF Close to Package Pins

XADC_AGND

J48

XADC_VCC Header J46

1.8V 150 mV max

U39

ADP123

1 μF

Out

Gnd

AV_5V To Header J46

10 μF

J68

Ferrite Bead

100 nF

VCC5V0

1 nF

Header

J46

Dual Use IO

(Analog/Digital)

100Ω

1 nF

100Ω

1 nF

100Ω

GNDADC

VAUX0P

VAUX0N

VAUX8P

VAUX8N

REFP

REFN

DXP

DXN

XADC_AGND

J47

REFP

100 nF

Close to Package Pins

100Ω

1 nF

100Ω

XADC_AGND

To Header J46

REF (1.25V)

Internal Reference

XADC_AGND

Header

J46

U42

REF3012

Out In

Gnd

10 μF

Star Grid

Connection

Figure 1-37: Header XADC_VREF Voltage Source Options

J69

Ferrite Bead

J42

Filter 5V Supply

Locate Components on Board

XADC_VCC

J43

GND

UG810_c1_37_031214

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The KC705 board supports both the internal FPGA sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available. The KC705 board VCCINT and VCCBRAM are provided by a common 1.0 V supply.

X-Ref Target - Figure 1-38

UG810_c1_38_031214

XADC_VP

XADC_VAUX0N

XADC_VAUX8P

XADC_DXN

XADC_VCC_HEADER

XADC_VN XADC_VAUX0P

XADC_VAUX8N XADC_DXP XADC_VREF

XADC_GPIO_0 XADC_GPIO_2

XADC_GPIO_1 XADC_GPIO_3

J46

1 3 5 7

9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

GND

XADC_AGNDXADC_AGND

XADC_VCC5V0

VADJ

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Jumper J47 can be used to select either an external differential voltage reference (XADC_VREF) or on-chip voltage reference (jumper J47 2–3) for the analog-to-digital converter.

For external measurements an XADC header (J46) is provided. This header can be used to provide analog inputs to the FPGA dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0], VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.

A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-38 shows the XADC header connections.

Figure 1-38: XADC Header (J46)

Table 1-34 describes the XADC header J46 pin functions.

Table 1-34: XADC Header J46 Pinout

Net Name

VN, VP 1, 2 Dedicated analog input channel for the XADC.

XADC_VAUX0P, N 3, 6 Auxiliary analog input channel 0. Also supports use as I/O inputs when

XADC_VAUX8N, P 7, 8 Auxiliary analog input channel 8. Also supports use as I/O inputs when

DXP, DXN 9, 12 Access to thermal diode.

XADC_AGND 4, 5, 10 Analog ground reference.

XADC_VREF 11 1.25V reference from the board.

XADC_VCC5V0 13 Filtered 5V supply from board.

XADC_VCC_HEADER 14 Analog 1.8V supply for XADC.

VADJ 15 VCCO supply for bank which is the source of DIO pins.

J46 Pin

Number

Description

anti alias capacitor is not present.

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Table 1-34: XADC Header J46 Pinout (Cont’d)

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Net Name

GND 16 Digital Ground (board) Reference

XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18 Digital I/O. These pins should come from the same bank. These I/Os

J46 Pin

Number

Description

should not be shared with other functions because they are required to support 3-state operation.

Configuration Options

The FPGA on the KC705 board can be configured by the following methods:

• Master BPI (uses the Linear BPI flash memory)

• Master SPI (uses the Quad SPI flash memory)

• JTAG (uses the USB-to-JTAG Bridge or Download cable). See USB JTAG Module, page 26 for more information

See 7 Series FPGAs Configuration User Guide (UG470) [Ref 2] for details on configuration modes.

The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) settings selected through DIP switch SW13. Table 1-35 lists the supported mode switch settings.

Table 1-35: Mode Switch SW13 Settings

Configuration Mode Mode Pins (M[2:0]) Bus Width CCLK Direction

Master SPI 001 x1, x2, x4 Output

Master BPI 010 x8, x16 Output

JTAG 101 x1 Not Applicable

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Figure 1-39 shows mode switch SW13.

Send Feedback

X-Ref Target - Figure 1-39

Chapter 1: KC705 Evaluation Board Features

VCC2V5

R402 220Ω

0.1 W 1%

FLASH_A25

FLASH_A24

FPGA_M2

FPGA_M1

FPGA_M0

R396

1.21kΩ

0.1 W 1%

GND

R397

1.21kΩ

0.1 W 1%

R398

1.21kΩ

0.1 W 1%

R399

1.21kΩ

0.1 W 1%

SW13

SDA05H1SBD

R400

1.21kΩ

0.1 W 1%

R401 220Ω

0.1 W 1%

UG810_c1_39_031214

Figure 1-39: Mode Switch

The mode pins settings on SW13 determine if the Linear BPI or the Quad SPI flash memory is used for configuring the FPGA. DIP switch SW13 also provides the upper two address bits for the Linear BPI flash memory and can be used to select one of multiple stored configuration bitstreams. Figure 1-40 shows the connectivity between the onboard nonvolatile flash devices used for configuration and the FPGA.

To obtain the fastest configuration speed an external 66 MHz oscillator is wired to the EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit datapath from the Linear BPI flash memory at a maximum synchronous read rate of 33 MHz. The bitstream stored in the flash memory must be generated with a BitGen option to divide the EMCCLK by two.

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X-Ref Target - Figure 1-40

UG810_c1_40_070114

RST_B

CLK

WE_B

OE_B

ADV_B

D[15:00]

A[27:01]

U58

P30 1Gb

Flash Memory

HOLD_B

W_B

S-B

N25Q128A13BSF-40F

QUAD SPI

TCK TMS

TDI

TDO

Bank 0

CCLK

INIT_B

VCCBATT

M[2:0]

DONE

PROG_B

FPGA

SW14

Bank 15

Bank 14

FWE_B

FOE_B

ADV_B

RS1

RS0

A[26:25]

A[24:16]

A[15:00]

D[15:00]

FCS_B

EMCCLK

CSO_B

PUDC_B

GND

VCCAUXIO (2.0V)

4.7 kΩ

GND

27.4 Ω

GND

R405 1 kΩ

300 Ω

D11 BAS40-04

DS20 GREEN

GND

ETHERNET MDC

U64

Oscillator

66 MHz

SW13

Mode

Switch

CE_B

Part of

SW13

GND

U63

Boot Select Demultiplexer

2.5 V

A[26:00]

A26

A25

Send Feedback

Chapter 1: KC705 Evaluation Board Features

Figure 1-40: KC705 Board Configuration Circuit

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Appendix A

Send Feedback

Default Switch and Jumper Settings

DIP Switch SW11 User GPIO

See Figure 1-2, page 10 Item 24 for location of SW11. Default settings are shown in

Figure A-1 and details are listed in Table A-1.

X-Ref Target - Figure A-1

ON Position = 1

234

SW11

GPIO DIP SW

OFF Position = 0

UG810_aA_01_03214

Figure A-1: SW11 Default Settings

Table A-1: SW11 Default Switch Settings

Position Function Default

1 GPIO_DIP_SW3 Off

2 GPIO_DIP_SW2 Off

3 GPIO_DIP_SW1 Off

4 GPIO_DIP_SW0 Off

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Appendix A: Default Switch and Jumper Settings

UG810_aA_02_031214

SW13

OFF Position = 0

ON Position = 1

2345

A25

A24

Send Feedback

DIP Switch SW13 Mode and Flash Memory Address Settings

See Figure 1-2, page 10 Item 29 for location of SW13. Default settings are shown in

Figure A-2 and details are listed in Table A-2.

X-Ref Target - Figure A-2

Figure A-2: SW13 Default Settings

The default mode setting M[2:0] = 010 selects Master BPI configuration at board power-on.

Table A-2: SW13 Default Switch Settings

Position Function Default

1FLASH_A25A25 Off

2FLASH_A24A24 Off

3FPGA_M2M2 Off

4FPGA_M1M1 On

5FPGA_M0M0 Off

Default Jumper Settings

See Figure A-3 for the locations of jumpers listed in Table A-3.

Table A-3: KC705 Default Jumper Settings

Callout

2-pin

Header

Reference

Designator

Jumper

Position

Description

Schematic

0381502 Page

1 J3 1-2 SPI SELECT = Onboard SPI flash memory device 26

2 J42 None U35 REF3012 XADC_AGND L17 bypassed 31

3 J43 1-2 U35 REF3012 XADC_AGND = GND 31

4 J53 None U55 UCD9248 RESET_B = LOGIC 1 (NOT RESET) 36

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Table A-3: KC705 Default Jumper Settings (Cont’d)

1110

UG810_aA_03_111414

Send Feedback

Appendix A: Default Switch and Jumper Settings

Callout

Header

Reference

Designator

Jumper

Position

Description

5 J56 None U56 UCD9248 RESET_B = LOGIC 1 (NOT RESET) 40

6 J65 1-2 FMC VADJ = ON 36

7 J68 1-2 XADC_VCC5V0 =VCC5V0 (5V) 31

3-pin

8 J27 2-3 SFP RX BW = FULL 22

9 J28 2-3 SFP TX BW = FULL 22

10 J29 1-2 U32 EPHY CONFIG5 = LOGIC 1 25

11 J30 1-2 U32 EPHY CONFIG4 = LOGIC 1 25

12 J47 1-2 XADC_VREFP = REF3012 XADC_VREF 31

13 J48 2-3 XADC_VCC = ADP123 1.85V 31

14 J69 1-2 REF3012 VIN = XADC_VCC5V0 31

2x3

15 J32 5-6 PCIe lane width = 8 21

X-Ref Target - Figure A-3

Schematic

0381502 Page

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Figure A-3: KC705 Jumper Locations

VITA 57.1 FMC Connector Pinouts

UG810_aB_01_031214

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

VREF_B_M2C

GND

GND CLK2_M2C_P CLK2_M2C_N

GND

HA02_P

HA02_N

GND

HA06_P

HA06_N

GND

HA10_P

HA10_N

GND

HA17_P_CC HA17_N_CC

GND

HA21_P

HA21_N

GND

HA23_P

HA23_N

GND

HB00_P_CC HB00_N_CC

GND

HB06_P_CC HB06_N_CC

GND

HB10_P

HB10_N

GND

HB14_P

HB14_N

GND

HB17_P_CC HB17_N_CC

GND

VIO_B_M2C

GND CLK3_M2C_P CLK3_M2C_N

GND

HA03_P HA03_N

GND

HA07_P HA07_N

GND

HA11_P HA11_N

GND

HA14_P HA14_N

GND

HA18_P HA18_N

GND

HA22_P HA22_N

GND

HB01_P HB01_N

GND

HB07_P HB07_N

GND

HB11_P HB11_N

GND

HB15_P HB15_N

GND

HB18_P HB18_N

GND

VIO_B_M2C

GND

VREF_A_M2C

PRSNT_M2C_L

GND CLK0_M2C_P CLK0_M2C_N

GND

LA02_P LA02_N

GND

LA04_P LA04_N

GND

LA07_P LA07_N

GND

LA11_P LA11_N

GND

LA15_P LA15_N

GND

LA19_P LA19_N

GND

LA21_P LA21_N

GND

LA24_P LA24_N

GND

LA28_P LA28_N

GND

LA30_P LA30_N

GND

LA32_P LA32_N

GND

VADJ

GND DP1_M2C_P DP1_M2C_N

GND

GND DP2_M2C_P DP2_M2C_N

GND

GND DP3_M2C_P DP3_M2C_N

GND

GND DP4_M2C_P DP4_M2C_N

GND

GND DP5_M2C_P DP5_M2C_N

GND

GND DP1_C2M_P DP1_C2M_N

GND

GND DP2_C2M_P DP2_C2M_N

GND

GND DP3_C2M_P DP3_C2M_N

GND

GND DP4_C2M_P DP4_C2M_N

GND

GND DP5_C2M_P DP5_C2M_N

GND

RES1

GND

GND DP9_M2C_P DP9_M2C_N

GND

GND DP8_M2C_P DP8_M2C_N

GND

GND DP7_M2C_P DP7_M2C_N

GND

GND DP6_M2C_P DP6_M2C_N

GND

GBTCLK1_M2C_P GBTCLK1_M2C_N

GND

GND DP9_C2M_P DP9_C2M_N

GND

GND DP8_C2M_P DP8_C2M_N

GND

GND DP7_C2M_P DP7_C2M_N

GND

GND DP6_C2M_P DP6_C2M_N

GND

RES0

GND DP0_C2M_P DP0_C2M_N

GND

GND DP0_M2C_P DP0_M2C_N

GND

LA06_P LA06_N

GND

LA10_P LA10_N

GND

LA14_P LA14_N

GND

LA18_P_CC

LA18_N_CC

GND

LA27_P LA27_N

GND

SCL SDA GND GND GA0

12P0V

GND

12P0V

GND

3P3V

GND

PG_C2M

GND

GND GBTCLK0_M2C_P GBTCLK0_M2C_N

GND

LA01_P_CC LA01_N_CC

GND

LA05_P LA05_N

GND

LA09_P LA09_N

GND

LA13_P LA13_N

GND

LA17_P_CC LA17_N_CC

GND

LA23_P LA23_N

GND

LA26_P LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TRST_L

GA1 3P3V GND 3P3V GND 3P3V

GND HA01_P_CC HA01_N_CC

GND

HA05_P HA05_N

GND

HA09_P HA09_N

GND

HA13_P HA13_N

GND

HA16_P HA16_N

GND

HA20_P HA20_N

GND

HB03_P HB03_N

GND

HB05_P HB05_N

GND

HB09_P HB09_N

GND

HB13_P HB13_N

GND

HB19_P HB19_N

GND

HB21_P HB21_N

GND

VADJ

GND

PG_M2C

GND

GND HA00_P_CC HA00_N_CC

GND

HA04_P HA04_N

GND

HA08_P HA08_N

GND

HA12_P HA12_N

GND

HA15_P HA15_N

GND

HA19_P HA19_N

GND

HB02_P HB02_N

GND

HB04_P HB04_N

GND

HB08_P HB08_N

GND

HB12_P HB12_N

GND

HB16_P HB16_N

GND

HB20_P HB20_N

GND

VADJ

GND

CLK1_M2C_P

CLK1_M2C_N

GND

GND LA00_P_CC LA00_N_CC

GND

LA03_P LA03_N

GND

LA08_P LA08_N

GND

LA12_P LA12_N

GND

LA16_P LA16_N

GND

LA20_P LA20_N

GND

LA22_P LA22_N

GND

LA25_P LA25_N

GND

LA29_P LA29_N

GND

LA31_P LA31_N

GND

LA33_P LA33_N

GND

VADJ

GND

KJHGFEDCBA

Send Feedback

Figure B-1 shows the pinout of the FPGA Mezzanine Card (FMC) high pin count (HPC)

connector defined by the VITA 57.1 FMC specification. For a description of how the KC705 board implements the FMC specification, see FPGA Mezzanine Card Interface, page 63 and

HPC Connector J22, page 63.

X-Ref Target - Figure B-1

Appendix B

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Figure B-1: FMC HPC Connector Pinout

X-Ref Target - Figure B-2

Send Feedback

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Appendix B: VITA 57.1 FMC Connector Pinouts

Figure B-2 shows the pinout of the FMC card low pin count (LPC) connector defined by the

VITA 57.1 FMC specification. For a description of how the KC705 board implements the FMC specification, see FPGA Mezzanine Card Interface, page 63 and LPC Connector J2, page 68.

KJHGFEDCBA

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

VREF_A_M2C

PRSNT_M2C_L

GND

CLK0_M2C_P

CLK0_M2C_N

GND

LA02_P

LA02_N

GND

LA04_P

LA04_N

GND

LA07_P

LA07_N

GND

LA11_P

LA11_N

GND

LA15_P

LA15_N

GND

LA19_P

LA19_N

GND

LA21_P

LA21_N

GND

LA24_P

LA24_N

GND

LA28_P

LA28_N

GND

LA30_P

LA30_N

GND

LA32_P

LA32_N

GND

VADJ

GND CLK1_M2C_P CLK1_M2C_N

GND

LA00_P_CC

LA00_N_CC

GND

LA03_P

LA03_N

GND

LA08_P

LA08_N

GND

LA12_P

LA12_N

GND

LA16_P

LA16_N

GND

LA20_P

LA20_N

GND

LA22_P

LA22_N

GND

LA25_P

LA25_N

GND

LA29_P

LA29_N

GND

LA31_P

LA31_N

GND

LA33_P

LA33_N

GND

VADJ

GND

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

PG_C2M

GND

GND GBTCLK0_M2C_P GBTCLK0_M2C_N

GND

LA01_P_CC

LA01_N_CC

GND

LA05_P LA05_N

GND

LA09_P LA09_N

GND

LA13_P LA13_N

GND

LA17_P_CC

LA17_N_CC

GND

LA23_P LA23_N

GND

LA26_P LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TRST_L

GA1

3P3V

GND

3P3V

GND

3P3V

GND DP0_C2M_P DP0_C2M_N

GND

GND DP0_M2C_P DP0_M2C_N

GND

LA06_P

LA06_N

GND

LA10_P

LA10_N

GND

LA14_P

LA14_N

GND

LA18_P_CC

LA18_N_CC

GND

LA27_P

LA27_N

GND

SCL SDA GND GND GA0

12P0V

GND

12P0V

GND

3P3V

GND

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

UG810_aB_02_031214

Figure B-2: FMC LPC Connector Pinout

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Master Constraints File Listing

Send Feedback

The KC705 board Xilinx® design constraints (XDC) file template provides for designs targeting the KC705 board. Net names in the constraints listed below correlate with net names on the latest KC705 board schematic. Users must identify the appropriate pins and replace the net names below with net names in the user RTL. See

Guide: Using Constraints

Users can refer to the XDC files generated by tools such as Memory Interface Generator (MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O standards information required for each particular interface. The FMC connectors J2 and J22 are connected to 2.5V V circuitry, the FMC bank I/O standards must be uniquely defined by each customer.

(UG903) [Ref 26] for more information.

banks. Because each FMC card implements customer-specific

cco

Appendix C

Vivado Design Suite User

Note:

Kintex-7 KC705 Evaluation Kit product page Doc & Designs tab for the latest versions of the FPGA

pins constraints files (XDC files). Choose the Xilinx tools link. In the search box, search for KC705 Master XDC File.

The constraints file listed in this appendix might not be the latest version. Always refer to the

KC705 Board XDC Listing

#CLOCKS #SYSCLK set_property PACKAGE_PIN AD11 [get_ports SYSCLK_N] set_property IOSTANDARD LVDS [get_ports SYSCLK_N] set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P] set_property IOSTANDARD LVDS [get_ports SYSCLK_P]

#USERCLK set_property PACKAGE_PIN K29 [get_ports USER_CLOCK_N] set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N] set_property PACKAGE_PIN K28 [get_ports USER_CLOCK_P] set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]

#USER SMA CLOCK set_property PACKAGE_PIN K25 [get_ports USER_SMA_CLOCK_N] set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N] set_property PACKAGE_PIN L25 [get_ports USER_SMA_CLOCK_P] set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]

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#SI5326 set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N] set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]

Appendix C: Master Constraints File Listing

Send Feedback

set_property PACKAGE_PIN W28 [get_ports REC_CLOCK_C_N] set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N] set_property PACKAGE_PIN W27 [get_ports REC_CLOCK_C_P] set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P] set_property PACKAGE_PIN AG24 [get_ports SI5326_INT_ALM_LS] set_property IOSTANDARD LVCMOS25 [get_ports SI5326_INT_ALM_LS] set_property PACKAGE_PIN AE20 [get_ports SI5326_RST_LS] set_property IOSTANDARD LVCMOS25 [get_ports SI5326_RST_LS]

#SMA MGT REFCLK set_property PACKAGE_PIN J7 [get_ports SMA_MGT_REFCLK_N] set_property PACKAGE_PIN J8 [get_ports SMA_MGT_REFCLK_P]

#EMCCLK set_property PACKAGE_PIN R24 [get_ports FPGA_EMCCLK] set_property IOSTANDARD LVCMOS25 [get_ports FPGA_EMCCLK]

#DDR3 #DATA set_property PACKAGE_PIN AA15 [get_ports DDR3_D0] set_property IOSTANDARD SSTL15 [get_ports DDR3_D0] set_property PACKAGE_PIN AA16 [get_ports DDR3_D1] set_property IOSTANDARD SSTL15 [get_ports DDR3_D1] set_property PACKAGE_PIN AC14 [get_ports DDR3_D2] set_property IOSTANDARD SSTL15 [get_ports DDR3_D2] set_property PACKAGE_PIN AD14 [get_ports DDR3_D3] set_property IOSTANDARD SSTL15 [get_ports DDR3_D3] set_property PACKAGE_PIN AA17 [get_ports DDR3_D4] set_property IOSTANDARD SSTL15 [get_ports DDR3_D4] set_property PACKAGE_PIN AB15 [get_ports DDR3_D5] set_property IOSTANDARD SSTL15 [get_ports DDR3_D5] set_property PACKAGE_PIN AE15 [get_ports DDR3_D6] set_property IOSTANDARD SSTL15 [get_ports DDR3_D6] set_property PACKAGE_PIN Y15 [get_ports DDR3_D7] set_property IOSTANDARD SSTL15 [get_ports DDR3_D7] set_property PACKAGE_PIN AB19 [get_ports DDR3_D8] set_property IOSTANDARD SSTL15 [get_ports DDR3_D8] set_property PACKAGE_PIN AD16 [get_ports DDR3_D9] set_property IOSTANDARD SSTL15 [get_ports DDR3_D9] set_property PACKAGE_PIN AC19 [get_ports DDR3_D10] set_property IOSTANDARD SSTL15 [get_ports DDR3_D10] set_property PACKAGE_PIN AD17 [get_ports DDR3_D11] set_property IOSTANDARD SSTL15 [get_ports DDR3_D11] set_property PACKAGE_PIN AA18 [get_ports DDR3_D12] set_property IOSTANDARD SSTL15 [get_ports DDR3_D12] set_property PACKAGE_PIN AB18 [get_ports DDR3_D13] set_property IOSTANDARD SSTL15 [get_ports DDR3_D13] set_property PACKAGE_PIN AE18 [get_ports DDR3_D14] set_property IOSTANDARD SSTL15 [get_ports DDR3_D14] set_property PACKAGE_PIN AD18 [get_ports DDR3_D15] set_property IOSTANDARD SSTL15 [get_ports DDR3_D15] set_property PACKAGE_PIN AG19 [get_ports DDR3_D16] set_property IOSTANDARD SSTL15 [get_ports DDR3_D16] set_property PACKAGE_PIN AK19 [get_ports DDR3_D17] set_property IOSTANDARD SSTL15 [get_ports DDR3_D17] set_property PACKAGE_PIN AG18 [get_ports DDR3_D18] set_property IOSTANDARD SSTL15 [get_ports DDR3_D18] set_property PACKAGE_PIN AF18 [get_ports DDR3_D19] set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]

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Appendix C: Master Constraints File Listing

Send Feedback

set_property PACKAGE_PIN AH19 [get_ports DDR3_D20] set_property IOSTANDARD SSTL15 [get_ports DDR3_D20] set_property PACKAGE_PIN AJ19 [get_ports DDR3_D21] set_property IOSTANDARD SSTL15 [get_ports DDR3_D21] set_property PACKAGE_PIN AE19 [get_ports DDR3_D22] set_property IOSTANDARD SSTL15 [get_ports DDR3_D22] set_property PACKAGE_PIN AD19 [get_ports DDR3_D23] set_property IOSTANDARD SSTL15 [get_ports DDR3_D23] set_property PACKAGE_PIN AK16 [get_ports DDR3_D24] set_property IOSTANDARD SSTL15 [get_ports DDR3_D24] set_property PACKAGE_PIN AJ17 [get_ports DDR3_D25] set_property IOSTANDARD SSTL15 [get_ports DDR3_D25] set_property PACKAGE_PIN AG15 [get_ports DDR3_D26] set_property IOSTANDARD SSTL15 [get_ports DDR3_D26] set_property PACKAGE_PIN AF15 [get_ports DDR3_D27] set_property IOSTANDARD SSTL15 [get_ports DDR3_D27] set_property PACKAGE_PIN AH17 [get_ports DDR3_D28] set_property IOSTANDARD SSTL15 [get_ports DDR3_D28] set_property PACKAGE_PIN AG14 [get_ports DDR3_D29] set_property IOSTANDARD SSTL15 [get_ports DDR3_D29] set_property PACKAGE_PIN AH15 [get_ports DDR3_D30] set_property IOSTANDARD SSTL15 [get_ports DDR3_D30] set_property PACKAGE_PIN AK15 [get_ports DDR3_D31] set_property IOSTANDARD SSTL15 [get_ports DDR3_D31] set_property PACKAGE_PIN AK8 [get_ports DDR3_D32] set_property IOSTANDARD SSTL15 [get_ports DDR3_D32] set_property PACKAGE_PIN AK6 [get_ports DDR3_D33] set_property IOSTANDARD SSTL15 [get_ports DDR3_D33] set_property PACKAGE_PIN AG7 [get_ports DDR3_D34] set_property IOSTANDARD SSTL15 [get_ports DDR3_D34] set_property PACKAGE_PIN AF7 [get_ports DDR3_D35] set_property IOSTANDARD SSTL15 [get_ports DDR3_D35] set_property PACKAGE_PIN AF8 [get_ports DDR3_D36] set_property IOSTANDARD SSTL15 [get_ports DDR3_D36] set_property PACKAGE_PIN AK4 [get_ports DDR3_D37] set_property IOSTANDARD SSTL15 [get_ports DDR3_D37] set_property PACKAGE_PIN AJ8 [get_ports DDR3_D38] set_property IOSTANDARD SSTL15 [get_ports DDR3_D38] set_property PACKAGE_PIN AJ6 [get_ports DDR3_D39] set_property IOSTANDARD SSTL15 [get_ports DDR3_D39] set_property PACKAGE_PIN AH5 [get_ports DDR3_D40] set_property IOSTANDARD SSTL15 [get_ports DDR3_D40] set_property PACKAGE_PIN AH6 [get_ports DDR3_D41] set_property IOSTANDARD SSTL15 [get_ports DDR3_D41] set_property PACKAGE_PIN AJ2 [get_ports DDR3_D42] set_property IOSTANDARD SSTL15 [get_ports DDR3_D42] set_property PACKAGE_PIN AH2 [get_ports DDR3_D43] set_property IOSTANDARD SSTL15 [get_ports DDR3_D43] set_property PACKAGE_PIN AH4 [get_ports DDR3_D44] set_property IOSTANDARD SSTL15 [get_ports DDR3_D44] set_property PACKAGE_PIN AJ4 [get_ports DDR3_D45] set_property IOSTANDARD SSTL15 [get_ports DDR3_D45] set_property PACKAGE_PIN AK1 [get_ports DDR3_D46] set_property IOSTANDARD SSTL15 [get_ports DDR3_D46] set_property PACKAGE_PIN AJ1 [get_ports DDR3_D47] set_property IOSTANDARD SSTL15 [get_ports DDR3_D47] set_property PACKAGE_PIN AF1 [get_ports DDR3_D48] set_property IOSTANDARD SSTL15 [get_ports DDR3_D48] set_property PACKAGE_PIN AF2 [get_ports DDR3_D49]

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Appendix C: Master Constraints File Listing

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set_property IOSTANDARD SSTL15 [get_ports DDR3_D49] set_property PACKAGE_PIN AE4 [get_ports DDR3_D50] set_property IOSTANDARD SSTL15 [get_ports DDR3_D50] set_property PACKAGE_PIN AE3 [get_ports DDR3_D51] set_property IOSTANDARD SSTL15 [get_ports DDR3_D51] set_property PACKAGE_PIN AF3 [get_ports DDR3_D52] set_property IOSTANDARD SSTL15 [get_ports DDR3_D52] set_property PACKAGE_PIN AF5 [get_ports DDR3_D53] set_property IOSTANDARD SSTL15 [get_ports DDR3_D53] set_property PACKAGE_PIN AE1 [get_ports DDR3_D54] set_property IOSTANDARD SSTL15 [get_ports DDR3_D54] set_property PACKAGE_PIN AE5 [get_ports DDR3_D55] set_property IOSTANDARD SSTL15 [get_ports DDR3_D55] set_property PACKAGE_PIN AC1 [get_ports DDR3_D56] set_property IOSTANDARD SSTL15 [get_ports DDR3_D56] set_property PACKAGE_PIN AD3 [get_ports DDR3_D57] set_property IOSTANDARD SSTL15 [get_ports DDR3_D57] set_property PACKAGE_PIN AC4 [get_ports DDR3_D58] set_property IOSTANDARD SSTL15 [get_ports DDR3_D58] set_property PACKAGE_PIN AC5 [get_ports DDR3_D59] set_property IOSTANDARD SSTL15 [get_ports DDR3_D59] set_property PACKAGE_PIN AE6 [get_ports DDR3_D60] set_property IOSTANDARD SSTL15 [get_ports DDR3_D60] set_property PACKAGE_PIN AD6 [get_ports DDR3_D61] set_property IOSTANDARD SSTL15 [get_ports DDR3_D61] set_property PACKAGE_PIN AC2 [get_ports DDR3_D62] set_property IOSTANDARD SSTL15 [get_ports DDR3_D62] set_property PACKAGE_PIN AD4 [get_ports DDR3_D63] set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]

#ADDRESS set_property PACKAGE_PIN AH12 [get_ports DDR3_A0] set_property IOSTANDARD SSTL15 [get_ports DDR3_A0] set_property PACKAGE_PIN AG13 [get_ports DDR3_A1] set_property IOSTANDARD SSTL15 [get_ports DDR3_A1] set_property PACKAGE_PIN AG12 [get_ports DDR3_A2] set_property IOSTANDARD SSTL15 [get_ports DDR3_A2] set_property PACKAGE_PIN AF12 [get_ports DDR3_A3] set_property IOSTANDARD SSTL15 [get_ports DDR3_A3] set_property PACKAGE_PIN AJ12 [get_ports DDR3_A4] set_property IOSTANDARD SSTL15 [get_ports DDR3_A4] set_property PACKAGE_PIN AJ13 [get_ports DDR3_A5] set_property IOSTANDARD SSTL15 [get_ports DDR3_A5] set_property PACKAGE_PIN AJ14 [get_ports DDR3_A6] set_property IOSTANDARD SSTL15 [get_ports DDR3_A6] set_property PACKAGE_PIN AH14 [get_ports DDR3_A7] set_property IOSTANDARD SSTL15 [get_ports DDR3_A7] set_property PACKAGE_PIN AK13 [get_ports DDR3_A8] set_property IOSTANDARD SSTL15 [get_ports DDR3_A8] set_property PACKAGE_PIN AK14 [get_ports DDR3_A9] set_property IOSTANDARD SSTL15 [get_ports DDR3_A9] set_property PACKAGE_PIN AF13 [get_ports DDR3_A10] set_property IOSTANDARD SSTL15 [get_ports DDR3_A10] set_property PACKAGE_PIN AE13 [get_ports DDR3_A11] set_property IOSTANDARD SSTL15 [get_ports DDR3_A11] set_property PACKAGE_PIN AJ11 [get_ports DDR3_A12] set_property IOSTANDARD SSTL15 [get_ports DDR3_A12] set_property PACKAGE_PIN AH11 [get_ports DDR3_A13] set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]

KC705 Evaluation Board 91

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

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set_property PACKAGE_PIN AK10 [get_ports DDR3_A14] set_property IOSTANDARD SSTL15 [get_ports DDR3_A14] set_property PACKAGE_PIN AK11 [get_ports DDR3_A15] set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]

#BA set_property PACKAGE_PIN AH9 [get_ports DDR3_BA0] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0] set_property PACKAGE_PIN AG9 [get_ports DDR3_BA1] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1] set_property PACKAGE_PIN AK9 [get_ports DDR3_BA2] set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]

#CLK set_property PACKAGE_PIN AH10 [get_ports DDR3_CLK0_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N] set_property PACKAGE_PIN AG10 [get_ports DDR3_CLK0_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P] set_property PACKAGE_PIN AF11 [get_ports DDR3_CLK1_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N] set_property PACKAGE_PIN AE11 [get_ports DDR3_CLK1_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]

#CTRL set_property PACKAGE_PIN AC11 [get_ports DDR3_CAS_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B] set_property PACKAGE_PIN AF10 [get_ports DDR3_CKE0] set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0] set_property PACKAGE_PIN AE10 [get_ports DDR3_CKE1] set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1] set_property PACKAGE_PIN AD8 [get_ports DDR3_ODT0] set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0] set_property PACKAGE_PIN AC10 [get_ports DDR3_ODT1] set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1] set_property PACKAGE_PIN AD9 [get_ports DDR3_RAS_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B] set_property PACKAGE_PIN AK3 [get_ports DDR3_RESET_B] set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B] set_property PACKAGE_PIN AC12 [get_ports DDR3_S0_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B] set_property PACKAGE_PIN AE8 [get_ports DDR3_S1_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B] set_property PACKAGE_PIN AJ9 [get_ports DDR3_TEMP_EVENT] set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT] set_property PACKAGE_PIN AE9 [get_ports DDR3_WE_B] set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]

KC705 Evaluation Board 92

UG810 (v1.8) March 20, 2018 www.xilinx.com

#DM set_property PACKAGE_PIN Y16 [get_ports DDR3_DM0] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0] set_property PACKAGE_PIN AB17 [get_ports DDR3_DM1] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1] set_property PACKAGE_PIN AF17 [get_ports DDR3_DM2] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2] set_property PACKAGE_PIN AE16 [get_ports DDR3_DM3] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3] set_property PACKAGE_PIN AK5 [get_ports DDR3_DM4] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4] set_property PACKAGE_PIN AJ3 [get_ports DDR3_DM5]

Appendix C: Master Constraints File Listing

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set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5] set_property PACKAGE_PIN AF6 [get_ports DDR3_DM6] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6] set_property PACKAGE_PIN AC7 [get_ports DDR3_DM7] set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]

#DQS set_property PACKAGE_PIN AC15 [get_ports DDR3_DQS0_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N] set_property PACKAGE_PIN AC16 [get_ports DDR3_DQS0_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P] set_property PACKAGE_PIN Y18 [get_ports DDR3_DQS1_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N] set_property PACKAGE_PIN Y19 [get_ports DDR3_DQS1_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P] set_property PACKAGE_PIN AK18 [get_ports DDR3_DQS2_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N] set_property PACKAGE_PIN AJ18 [get_ports DDR3_DQS2_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P] set_property PACKAGE_PIN AJ16 [get_ports DDR3_DQS3_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N] set_property PACKAGE_PIN AH16 [get_ports DDR3_DQS3_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P] set_property PACKAGE_PIN AJ7 [get_ports DDR3_DQS4_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N] set_property PACKAGE_PIN AH7 [get_ports DDR3_DQS4_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P] set_property PACKAGE_PIN AH1 [get_ports DDR3_DQS5_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N] set_property PACKAGE_PIN AG2 [get_ports DDR3_DQS5_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P] set_property PACKAGE_PIN AG3 [get_ports DDR3_DQS6_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N] set_property PACKAGE_PIN AG4 [get_ports DDR3_DQS6_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P] set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS7_N] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N] set_property PACKAGE_PIN AD2 [get_ports DDR3_DQS7_P] set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]

KC705 Evaluation Board 93

UG810 (v1.8) March 20, 2018 www.xilinx.com

#BPI FLASH #DATA set_property PACKAGE_PIN P24 [get_ports FLASH_D0] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D0] set_property PACKAGE_PIN R25 [get_ports FLASH_D1] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D1] set_property PACKAGE_PIN R20 [get_ports FLASH_D2] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D2] set_property PACKAGE_PIN R21 [get_ports FLASH_D3] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D3] set_property PACKAGE_PIN T20 [get_ports FLASH_D4] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D4] set_property PACKAGE_PIN T21 [get_ports FLASH_D5] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D5] set_property PACKAGE_PIN T22 [get_ports FLASH_D6] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D6] set_property PACKAGE_PIN T23 [get_ports FLASH_D7] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D7] set_property PACKAGE_PIN U20 [get_ports FLASH_D8]

Appendix C: Master Constraints File Listing

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set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D8] set_property PACKAGE_PIN P29 [get_ports FLASH_D9] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D9] set_property PACKAGE_PIN R29 [get_ports FLASH_D10] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D10] set_property PACKAGE_PIN P27 [get_ports FLASH_D11] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D11] set_property PACKAGE_PIN P28 [get_ports FLASH_D12] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D12] set_property PACKAGE_PIN T30 [get_ports FLASH_D13] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D13] set_property PACKAGE_PIN P26 [get_ports FLASH_D14] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D14] set_property PACKAGE_PIN R26 [get_ports FLASH_D15] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D15]

#ADDRESS set_property PACKAGE_PIN W22 [get_ports FLASH_A0] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A0] set_property PACKAGE_PIN W21 [get_ports FLASH_A1] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A1] set_property PACKAGE_PIN V24 [get_ports FLASH_A2] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A2] set_property PACKAGE_PIN U24 [get_ports FLASH_A3] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A3] set_property PACKAGE_PIN V22 [get_ports FLASH_A4] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A4] set_property PACKAGE_PIN V21 [get_ports FLASH_A5] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A5] set_property PACKAGE_PIN U23 [get_ports FLASH_A6] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A6] set_property PACKAGE_PIN W24 [get_ports FLASH_A7] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A7] set_property PACKAGE_PIN W23 [get_ports FLASH_A8] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A8] set_property PACKAGE_PIN V20 [get_ports FLASH_A9] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A9] set_property PACKAGE_PIN V19 [get_ports FLASH_A10] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A10] set_property PACKAGE_PIN W26 [get_ports FLASH_A11] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A11] set_property PACKAGE_PIN V25 [get_ports FLASH_A12] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A12] set_property PACKAGE_PIN V30 [get_ports FLASH_A13] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A13] set_property PACKAGE_PIN V29 [get_ports FLASH_A14] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A14] set_property PACKAGE_PIN V27 [get_ports FLASH_A15] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A15] set_property PACKAGE_PIN P22 [get_ports FLASH_A16] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A16] set_property PACKAGE_PIN P21 [get_ports FLASH_A17] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A17] set_property PACKAGE_PIN N24 [get_ports FLASH_A18] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A18] set_property PACKAGE_PIN N22 [get_ports FLASH_A19] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A19] set_property PACKAGE_PIN N21 [get_ports FLASH_A20] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A20]

KC705 Evaluation Board 94

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

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set_property PACKAGE_PIN N20 [get_ports FLASH_A21] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A21] set_property PACKAGE_PIN N19 [get_ports FLASH_A22] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A22] set_property PACKAGE_PIN N26 [get_ports FLASH_A23] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A23] set_property PACKAGE_PIN M23 [get_ports FLASH_A24] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A24] set_property PACKAGE_PIN M22 [get_ports FLASH_A25] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A25]

#CTRL set_property PACKAGE_PIN M30 [get_ports FLASH_ADV_B] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_ADV_B] set_property PACKAGE_PIN M25 [get_ports FLASH_FWE_B] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_FWE_B] set_property PACKAGE_PIN M24 [get_ports FLASH_OE_B] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_OE_B] set_property PACKAGE_PIN U29 [get_ports FLASH_WAIT] set_property IOSTANDARD LVCMOS25 [get_ports FLASH_WAIT] set_property PACKAGE_PIN U19 [get_ports FPGA_FCS] set_property IOSTANDARD LVCMOS25 [get_ports FPGA_FCS]

#FMC set_property PACKAGE_PIN H29 [get_ports FMC_C2M_PG_LS] set_property IOSTANDARD LVCMOS25 [get_ports FMC_C2M_PG_LS]

#FMC HPC MISC set_property PACKAGE_PIN J29 [get_ports FMC_HPC_PG_M2C_LS] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PG_M2C_LS] set_property PACKAGE_PIN M20 [get_ports FMC_HPC_PRSNT_M2C_B_LS] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PRSNT_M2C_B_LS]

#FMC HPC CLK set_property PACKAGE_PIN C27 [get_ports FMC_HPC_CLK0_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_N] set_property PACKAGE_PIN D27 [get_ports FMC_HPC_CLK0_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_P] set_property PACKAGE_PIN D18 [get_ports FMC_HPC_CLK1_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_N] set_property PACKAGE_PIN D17 [get_ports FMC_HPC_CLK1_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_P]

#FMC HPC GBTCLK set_property PACKAGE_PIN C7 [get_ports FMC_HPC_GBTCLK0_M2C_C_N] set_property PACKAGE_PIN C8 [get_ports FMC_HPC_GBTCLK0_M2C_C_P] set_property PACKAGE_PIN E7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N] set_property PACKAGE_PIN E8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]

#FMC HPC DP set_property PACKAGE_PIN D1 [get_ports FMC_HPC_DP0_C2M_N] set_property PACKAGE_PIN D2 [get_ports FMC_HPC_DP0_C2M_P] set_property PACKAGE_PIN E3 [get_ports FMC_HPC_DP0_M2C_N] set_property PACKAGE_PIN E4 [get_ports FMC_HPC_DP0_M2C_P] set_property PACKAGE_PIN C3 [get_ports FMC_HPC_DP1_C2M_N] set_property PACKAGE_PIN C4 [get_ports FMC_HPC_DP1_C2M_P] set_property PACKAGE_PIN D5 [get_ports FMC_HPC_DP1_M2C_N] set_property PACKAGE_PIN D6 [get_ports FMC_HPC_DP1_M2C_P] set_property PACKAGE_PIN B1 [get_ports FMC_HPC_DP2_C2M_N]

KC705 Evaluation Board 95

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

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set_property PACKAGE_PIN B2 [get_ports FMC_HPC_DP2_C2M_P] set_property PACKAGE_PIN B5 [get_ports FMC_HPC_DP2_M2C_N] set_property PACKAGE_PIN B6 [get_ports FMC_HPC_DP2_M2C_P] set_property PACKAGE_PIN A3 [get_ports FMC_HPC_DP3_C2M_N] set_property PACKAGE_PIN A4 [get_ports FMC_HPC_DP3_C2M_P] set_property PACKAGE_PIN A7 [get_ports FMC_HPC_DP3_M2C_N] set_property PACKAGE_PIN A8 [get_ports FMC_HPC_DP3_M2C_P]

#FMC HPC LA set_property PACKAGE_PIN B25 [get_ports FMC_HPC_LA00_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_N] set_property PACKAGE_PIN C25 [get_ports FMC_HPC_LA00_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_P] set_property PACKAGE_PIN C26 [get_ports FMC_HPC_LA01_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_N] set_property PACKAGE_PIN D26 [get_ports FMC_HPC_LA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_P] set_property PACKAGE_PIN H25 [get_ports FMC_HPC_LA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_N] set_property PACKAGE_PIN H24 [get_ports FMC_HPC_LA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_P] set_property PACKAGE_PIN H27 [get_ports FMC_HPC_LA03_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_N] set_property PACKAGE_PIN H26 [get_ports FMC_HPC_LA03_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_P] set_property PACKAGE_PIN F28 [get_ports FMC_HPC_LA04_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_N] set_property PACKAGE_PIN G28 [get_ports FMC_HPC_LA04_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_P] set_property PACKAGE_PIN F30 [get_ports FMC_HPC_LA05_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_N] set_property PACKAGE_PIN G29 [get_ports FMC_HPC_LA05_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_P] set_property PACKAGE_PIN G30 [get_ports FMC_HPC_LA06_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_N] set_property PACKAGE_PIN H30 [get_ports FMC_HPC_LA06_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_P] set_property PACKAGE_PIN D28 [get_ports FMC_HPC_LA07_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_N] set_property PACKAGE_PIN E28 [get_ports FMC_HPC_LA07_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_P] set_property PACKAGE_PIN E30 [get_ports FMC_HPC_LA08_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_N] set_property PACKAGE_PIN E29 [get_ports FMC_HPC_LA08_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_P] set_property PACKAGE_PIN A30 [get_ports FMC_HPC_LA09_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_N] set_property PACKAGE_PIN B30 [get_ports FMC_HPC_LA09_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_P] set_property PACKAGE_PIN C30 [get_ports FMC_HPC_LA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_N] set_property PACKAGE_PIN D29 [get_ports FMC_HPC_LA10_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_P] set_property PACKAGE_PIN F27 [get_ports FMC_HPC_LA11_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_N] set_property PACKAGE_PIN G27 [get_ports FMC_HPC_LA11_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_P] set_property PACKAGE_PIN B29 [get_ports FMC_HPC_LA12_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_N]

KC705 Evaluation Board 96

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

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set_property PACKAGE_PIN C29 [get_ports FMC_HPC_LA12_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_P] set_property PACKAGE_PIN A26 [get_ports FMC_HPC_LA13_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_N] set_property PACKAGE_PIN A25 [get_ports FMC_HPC_LA13_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_P] set_property PACKAGE_PIN A28 [get_ports FMC_HPC_LA14_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_N] set_property PACKAGE_PIN B28 [get_ports FMC_HPC_LA14_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_P] set_property PACKAGE_PIN B24 [get_ports FMC_HPC_LA15_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_N] set_property PACKAGE_PIN C24 [get_ports FMC_HPC_LA15_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_P] set_property PACKAGE_PIN A27 [get_ports FMC_HPC_LA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_N] set_property PACKAGE_PIN B27 [get_ports FMC_HPC_LA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_P] set_property PACKAGE_PIN E20 [get_ports FMC_HPC_LA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_N] set_property PACKAGE_PIN F20 [get_ports FMC_HPC_LA17_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_P] set_property PACKAGE_PIN E21 [get_ports FMC_HPC_LA18_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_N] set_property PACKAGE_PIN F21 [get_ports FMC_HPC_LA18_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_P] set_property PACKAGE_PIN F18 [get_ports FMC_HPC_LA19_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_N] set_property PACKAGE_PIN G18 [get_ports FMC_HPC_LA19_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_P] set_property PACKAGE_PIN D19 [get_ports FMC_HPC_LA20_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_N] set_property PACKAGE_PIN E19 [get_ports FMC_HPC_LA20_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_P] set_property PACKAGE_PIN A21 [get_ports FMC_HPC_LA21_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_N] set_property PACKAGE_PIN A20 [get_ports FMC_HPC_LA21_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_P] set_property PACKAGE_PIN B20 [get_ports FMC_HPC_LA22_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_N] set_property PACKAGE_PIN C20 [get_ports FMC_HPC_LA22_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_P] set_property PACKAGE_PIN A22 [get_ports FMC_HPC_LA23_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_N] set_property PACKAGE_PIN B22 [get_ports FMC_HPC_LA23_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_P] set_property PACKAGE_PIN A17 [get_ports FMC_HPC_LA24_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_N] set_property PACKAGE_PIN A16 [get_ports FMC_HPC_LA24_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_P] set_property PACKAGE_PIN F17 [get_ports FMC_HPC_LA25_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_N] set_property PACKAGE_PIN G17 [get_ports FMC_HPC_LA25_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_P] set_property PACKAGE_PIN A18 [get_ports FMC_HPC_LA26_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_N] set_property PACKAGE_PIN B18 [get_ports FMC_HPC_LA26_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_P] set_property PACKAGE_PIN B19 [get_ports FMC_HPC_LA27_N]

KC705 Evaluation Board 97

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

Send Feedback

set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_N] set_property PACKAGE_PIN C19 [get_ports FMC_HPC_LA27_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_P] set_property PACKAGE_PIN C16 [get_ports FMC_HPC_LA28_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_N] set_property PACKAGE_PIN D16 [get_ports FMC_HPC_LA28_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_P] set_property PACKAGE_PIN B17 [get_ports FMC_HPC_LA29_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_N] set_property PACKAGE_PIN C17 [get_ports FMC_HPC_LA29_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_P] set_property PACKAGE_PIN C22 [get_ports FMC_HPC_LA30_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_N] set_property PACKAGE_PIN D22 [get_ports FMC_HPC_LA30_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_P] set_property PACKAGE_PIN F22 [get_ports FMC_HPC_LA31_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_N] set_property PACKAGE_PIN G22 [get_ports FMC_HPC_LA31_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_P] set_property PACKAGE_PIN C21 [get_ports FMC_HPC_LA32_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_N] set_property PACKAGE_PIN D21 [get_ports FMC_HPC_LA32_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_P] set_property PACKAGE_PIN H22 [get_ports FMC_HPC_LA33_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_N] set_property PACKAGE_PIN H21 [get_ports FMC_HPC_LA33_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_P]

#FMC HPC HA set_property PACKAGE_PIN D13 [get_ports FMC_HPC_HA00_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_N] set_property PACKAGE_PIN D12 [get_ports FMC_HPC_HA00_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_P] set_property PACKAGE_PIN G14 [get_ports FMC_HPC_HA01_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_N] set_property PACKAGE_PIN H14 [get_ports FMC_HPC_HA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_P] set_property PACKAGE_PIN C11 [get_ports FMC_HPC_HA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_N] set_property PACKAGE_PIN D11 [get_ports FMC_HPC_HA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_P] set_property PACKAGE_PIN B12 [get_ports FMC_HPC_HA03_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_N] set_property PACKAGE_PIN C12 [get_ports FMC_HPC_HA03_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_P] set_property PACKAGE_PIN E11 [get_ports FMC_HPC_HA04_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_N] set_property PACKAGE_PIN F11 [get_ports FMC_HPC_HA04_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_P] set_property PACKAGE_PIN E16 [get_ports FMC_HPC_HA05_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_N] set_property PACKAGE_PIN F15 [get_ports FMC_HPC_HA05_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_P] set_property PACKAGE_PIN C14 [get_ports FMC_HPC_HA06_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_N] set_property PACKAGE_PIN D14 [get_ports FMC_HPC_HA06_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_P] set_property PACKAGE_PIN A15 [get_ports FMC_HPC_HA07_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_N]

KC705 Evaluation Board 98

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

Send Feedback

set_property PACKAGE_PIN B14 [get_ports FMC_HPC_HA07_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_P] set_property PACKAGE_PIN E15 [get_ports FMC_HPC_HA08_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_N] set_property PACKAGE_PIN E14 [get_ports FMC_HPC_HA08_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_P] set_property PACKAGE_PIN E13 [get_ports FMC_HPC_HA09_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_N] set_property PACKAGE_PIN F12 [get_ports FMC_HPC_HA09_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_P] set_property PACKAGE_PIN A12 [get_ports FMC_HPC_HA10_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_N] set_property PACKAGE_PIN A11 [get_ports FMC_HPC_HA10_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_P] set_property PACKAGE_PIN A13 [get_ports FMC_HPC_HA11_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_N] set_property PACKAGE_PIN B13 [get_ports FMC_HPC_HA11_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_P] set_property PACKAGE_PIN B15 [get_ports FMC_HPC_HA12_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_N] set_property PACKAGE_PIN C15 [get_ports FMC_HPC_HA12_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_P] set_property PACKAGE_PIN K16 [get_ports FMC_HPC_HA13_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_N] set_property PACKAGE_PIN L16 [get_ports FMC_HPC_HA13_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_P] set_property PACKAGE_PIN H16 [get_ports FMC_HPC_HA14_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_N] set_property PACKAGE_PIN J16 [get_ports FMC_HPC_HA14_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_P] set_property PACKAGE_PIN G15 [get_ports FMC_HPC_HA15_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_N] set_property PACKAGE_PIN H15 [get_ports FMC_HPC_HA15_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_P] set_property PACKAGE_PIN K15 [get_ports FMC_HPC_HA16_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_N] set_property PACKAGE_PIN L15 [get_ports FMC_HPC_HA16_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_P] set_property PACKAGE_PIN F13 [get_ports FMC_HPC_HA17_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_N] set_property PACKAGE_PIN G13 [get_ports FMC_HPC_HA17_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_P] set_property PACKAGE_PIN J14 [get_ports FMC_HPC_HA18_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_N] set_property PACKAGE_PIN K14 [get_ports FMC_HPC_HA18_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_P] set_property PACKAGE_PIN H12 [get_ports FMC_HPC_HA19_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_N] set_property PACKAGE_PIN H11 [get_ports FMC_HPC_HA19_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_P] set_property PACKAGE_PIN J13 [get_ports FMC_HPC_HA20_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_N] set_property PACKAGE_PIN K13 [get_ports FMC_HPC_HA20_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_P] set_property PACKAGE_PIN J12 [get_ports FMC_HPC_HA21_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_N] set_property PACKAGE_PIN J11 [get_ports FMC_HPC_HA21_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_P] set_property PACKAGE_PIN K11 [get_ports FMC_HPC_HA22_N]

KC705 Evaluation Board 99

UG810 (v1.8) March 20, 2018 www.xilinx.com

Appendix C: Master Constraints File Listing

Send Feedback

set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_N] set_property PACKAGE_PIN L11 [get_ports FMC_HPC_HA22_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_P] set_property PACKAGE_PIN L13 [get_ports FMC_HPC_HA23_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_N] set_property PACKAGE_PIN L12 [get_ports FMC_HPC_HA23_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_P]

#FMC LPC MISC set_property PACKAGE_PIN J22 [get_ports FMC_LPC_PRSNT_M2C_B_LS] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_PRSNT_M2C_B_LS]

#FMC LPC CLK set_property PACKAGE_PIN AG23 [get_ports FMC_LPC_CLK0_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_N] set_property PACKAGE_PIN AF22 [get_ports FMC_LPC_CLK0_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_P] set_property PACKAGE_PIN AH29 [get_ports FMC_LPC_CLK1_M2C_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_N] set_property PACKAGE_PIN AG29 [get_ports FMC_LPC_CLK1_M2C_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_P]

#FMC LPC GBTCLK set_property PACKAGE_PIN N7 [get_ports FMC_LPC_GBTCLK0_M2C_C_N] set_property PACKAGE_PIN N8 [get_ports FMC_LPC_GBTCLK0_M2C_C_P]

#FMC LPC DP set_property PACKAGE_PIN F1 [get_ports FMC_LPC_DP0_C2M_N] set_property PACKAGE_PIN F2 [get_ports FMC_LPC_DP0_C2M_P] set_property PACKAGE_PIN F5 [get_ports FMC_LPC_DP0_M2C_N] set_property PACKAGE_PIN F6 [get_ports FMC_LPC_DP0_M2C_P]

#FMC LPC LA set_property PACKAGE_PIN AE24 [get_ports FMC_LPC_LA00_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_N] set_property PACKAGE_PIN AD23 [get_ports FMC_LPC_LA00_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_P] set_property PACKAGE_PIN AF23 [get_ports FMC_LPC_LA01_CC_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_N] set_property PACKAGE_PIN AE23 [get_ports FMC_LPC_LA01_CC_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_P] set_property PACKAGE_PIN AF21 [get_ports FMC_LPC_LA02_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_N] set_property PACKAGE_PIN AF20 [get_ports FMC_LPC_LA02_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_P] set_property PACKAGE_PIN AH20 [get_ports FMC_LPC_LA03_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_N] set_property PACKAGE_PIN AG20 [get_ports FMC_LPC_LA03_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_P] set_property PACKAGE_PIN AJ21 [get_ports FMC_LPC_LA04_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_N] set_property PACKAGE_PIN AH21 [get_ports FMC_LPC_LA04_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_P] set_property PACKAGE_PIN AH22 [get_ports FMC_LPC_LA05_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_N] set_property PACKAGE_PIN AG22 [get_ports FMC_LPC_LA05_P] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_P] set_property PACKAGE_PIN AK21 [get_ports FMC_LPC_LA06_N] set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_N]

KC705 Evaluation Board 100

UG810 (v1.8) March 20, 2018 www.xilinx.com

Xilinx KC705 Evaluation Board for the Kintex-7 FPGA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Table of Contents

Overview

Additional Information

KC705 Board Features

Feature Descriptions

Kintex-7 FPGA

FPGA Configuration

Encryption Key Backup Circuit

I/O Voltage Rails

DDR3 Memory Module

Linear BPI Flash Memory

Quad SPI Flash Memory

SD Card Interface

USB JTAG Module

Clock Generation

System Clock Source

Programmable User Clock Source

User SMA Clock Input

GTX SMA Clock Input

Jitter Attenuated Clock

GTX Transceivers

PCI Express Edge Connector

SFP/SFP+ Connector

10/100/1000 Tri-Speed Ethernet PHY

SGMII GTX Transceiver Clock Generator

USB-to-UART Bridge

HDMI Video Output

LCD Character Display

I2C Bus Switch

Status LEDs

Ethernet PHY Status LEDs

User I/O

User GPIO LEDs

User Pushbuttons

CPU Reset Pushbutton

GPIO DIP Switch

Rotary Switch

GPIO SMA Connectors

Switches

Power On/Off Slide Switch SW15

FPGA_PROG_B Pushbutton SW14 (Active-Low)

Configuration Mode and Upper Linear Flash Address Switch (SW13)

FPGA Mezzanine Card Interface

HPC Connector J22

LPC Connector J2

Power Management

FMC_VADJ Voltage Control

Cooling Fan Control

Monitoring Voltage and Current

XADC Header

Configuration Options

DIP Switch SW11 User GPIO

DIP Switch SW13 Mode and Flash Memory Address Settings

Default Jumper Settings

KC705 Board XDC Listing