Xilinx KC705 Evaluation Board for the Kintex-7 FPGA User Manual
KC705 Evaluation Board
for the Kintex-7 FPGA
User Guide
UG810 (v1.8) March 20, 2018
Revision History
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The following table shows the revision history for this document.
Date Version Revision
03/20/2018 1.8 In Table 1-1, Quad SPI Flash Memory, and [Ref 5], added Micron
MT25QL128ABA8ESF-0SIT as a possible part for U7. In Table 1-24, the I2C addresses
were updated for the FMC HPC and FMC LPC device rows.
07/08/2016 1.7 Updated VRP/VRN resistor connection information in DDR3 Memory Module.
Moved the Additional Resources and Legal Notices appendix to the end of the
book.
08/26/2015 1.6.2 In Table 1-9, the I/O standard for SYSCLK_N and SYSCLK_P were updated to LVDS.
In Table 1-27, under Directional Pushbutton Switches, the I/O standard for
GPIO_SW_C was updated to LVCMOS25. Updated the #USB UART section of
Appendix C, Master Constraints File Listing.
04/13/2015 1.6.1 In HPC Connector J22, page 63, the GTX clock count changed from 1 to 2. Updated
links.
12/08/2014 1.6 Added a note about jumper header locations below Table 1-1. Changed Table 1-5
heading J1 DDR3 Memory to U58 BPI Flash Memory. Parts PC28F00AP30TF and
N25Q128A13BSF40F changed from Numonyx to Micron. Described J11 and J12
connections in User SMA Clock Input, page 30. Made these updates in
Programmable User Clock Source, page 29: XTP186 became XTP204, RDF0175
became RDF0194, XTP187 became XTP203, and RDF0176 became RDF0193.
Corrected the device in the heading of Table 1-20 from CP2013 to CP2103. Updated
I2C Bus Switch, page 52. Updated Table 1-24 I2C devices. In Table 1-28, J22 pin G7
connects to FPGA U1 pin C27. Replaced Table A-3, KC705 Default Jumper Settings
and added
Appendix C, Master Constraints File Listing. Added information about ordering the
custom ATX cable to Appendix F, Regulatory Compliance and Information, [Ref 20].
07/11/2014 1.5 Corrected MGT Quad connection information in GTX Transceivers, page 33 and a
connection in Table 1-10. Added MGTREFCLK1 - PCIE_CLK from P1 to Quad 115 in
GTX Transceivers, page 33. Updated Table 1-4, Table 1-5, Table 1-6, Table 1-7,
Table 1-9, Table 1-18, Table 1-21, Table 1-23, Table 1-27, Table 1-28, and
Table 1-29. Added table footnotes regarding I/O standard and pins prior to board
revision 1.1 to Table 1-14. Clarified default jumper positions in Table 1-15.
Corrected the J2 C19 pin number in Table 1-29. In Figure 1-40, changed pin names
VBATT to VCCBATT and POUC_B to PUDC_B. Removed three pins from KC705 Board
XDC Listing, page 88 (PACKAGE _PIN R8, R7, and W8). The Appendix C title changed
to Master Constraints File Listing and the constraints file in Appendix C was
replaced. The Declaration of Conformity link in Appendix F was updated.
07/18/2013 1.4 Revised the format of Table 1-20 and added the I/O standard column. Revised the
FPGA U1 pin for FMC_HPC_CLK0_M2C_N in Table 1-28 to C27 on page 59. Revised
the descriptions of the functions for SW13 position 3 and position 5 in Table A-2.
In Appendix C, Master Constraints File Listing, changed appendix title from Master
UCF Listing to Master Board Constraints, replaced references to the term UCF with
the term XDC and replaced the KC705 Board UCF Listing with the KC705 Board XDC
Listing.
Figure A-3 to show jumper locations. Replaced the constraints file in
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Date Version Revision
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05/10/2013 1.3 Updated Figure 1-1 to show v 1.1 board. Updated Table 1-1, page 10: callout 1 to
identify Fansink, callouts 25and 26 pointing to User I/O. Added Table 1-9 Clock
Source to FPGA U1 Connections. Updated Programmable User Clock Source,
page 29 to include I2C address. Updated Table 1-17, page 43 for naming pins 18
and 19. Added Note to Table 1-14, page 42. Updated I2C Bus Switch, page 52 to
show TI device instead of NXP Semiconductor, deleted; updated [Ref 19]. Added
Figure 1-28, page 57 Rotary Switch, and Figure 1-29, page 58 GPIO SMAs J13 and
J14. Added Note to Appendix C, Master Constraints File Listing. Updated
Appendix D, Board Setup, step 1 of installation procedure. Updated Appendix F,
Additional Resources to include CE PC Test reference.
12/10/2012 1.2 Replaced direct, inline links to external references in the body text with indirect
references to the links in a numbered list in Appendix G, Additional Resources and
Legal Notices. Revised the value for frequency jitter for the System Clock Source,
page 29. Reset conditions are added to Jitter Attenuated Clock, page 32 Revised
jumper information for SFP_RS1, page 42 in Table 1-15. Revised contents and
organization of Appendix F, Additional Resources.
04/05/2012 1.1 Updated links from Table 1-1, page 10. Revised the JTAG configuration mode USB
cable description under FPGA Configuration, page 12. Added Encryption Key
Backup Circuit, page 13 and Table 1-4, page 15. Added links to User SMA Clock
Input in Table 1-8, page 28. Added link to Si570 device vendor on page 30. Added
Ethernet PHY Status LEDs, page 54 and Figure 1-24, page 54. Updated Power
On/Off Slide Switch SW15, page 60 and added Figure 1-32, page 61. Revised FPGA
Mezzanine Card Interface, page 63 and Table 1-28, page 64 and Table 1-29,
page 69. Added description of power module cooling requirement to Power
Management, page 71. Added Cooling Fan Control, page 74. Updated Table 1-35,
page 80. Added references to Documents, page 85. Added Appendix E, Compliance
with European Union Directives and Standards, Appendix D, Board Setup, and
Appendix E, Board Specifications.
01/23/2012 1.0 Initial Xilinx release.
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Table of Contents
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: KC705 Evaluation Board Features
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Appendix A: Default Switch and Jumper Settings
DIP Switch SW11 User GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DIP Switch SW13 Mode and Flash Memory Address Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix B: VITA 57.1 FMC Connector Pinouts
Appendix C: Master Constraints File Listing
KC705 Board XDC Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix D: Board Setup
Installing KC705 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Appendix E: Board Specifications
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Appendix F: Regulatory Compliance and Information
Declaration of Conformity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Appendix G: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
KC705 Evaluation Board 5
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KC705 Evaluation Board Features
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Overview
The KC705 evaluation board for the Kintex®-7 FPGA provides a hardware environment for
developing and evaluating designs targeting the Kintex-7 XC7K325T-2FFG900C FPGA. The
KC705 board provides features common to many embedded processing systems, including
a DDR3 SODIMM memory, an 8-lane PCI Express® interface, a tri-mode Ethernet PHY,
general purpose I/O, and a UART interface. Other features can be added by using FPGA
Mezzanine Cards (FMCs) attached to either of two VITA-57 FPGA mezzanine connectors
provided on the board. High pin count (HPC) and low pin count (LPC) FMCs are provided.
See KC705 Board Features for a complete list of features. The details for each feature are
described in Feature Descriptions, page 9.
Chapter 1
Additional Information
See Appendix G, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the KC705 board.
KC705 Board Features
• Kintex-7 XC7K325T-2FFG900C FPGA
• 1 GB DDR3 memory SODIMM
• 128 MB Linear Byte Peripheral Interface (BPI) flash memory
• 128 Mb Quad Serial Peripheral Interface (SPI) flash memory
• Secure Digital (SD) connector
• USB JTAG via Digilent module
•Clock generation
Fixed 200 MHz LVDS oscillator (differential)
°
Inter-integrated circuit (I2C) programmable LVDS oscillator (differential)
°
SMA connectors (differential)
°
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SMA connectors for GTX transceiver clocking
°
• GTX transceivers
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FMC HPC connector (four GTX transceivers)
°
FMC LPC connector (one GTX transceiver)
°
SMA connectors (one pair each for TX, RX, and REFCLK)
°
PCI Express (eight lanes)
°
Small form-factor pluggable plus (SFP+) connector
°
Ethernet PHY SGMII interface (RJ-45 connector)
°
• PCI Express endpoint connectivity
Gen1 8-lane (x8)
°
Gen2 8-lane (x8)
°
• SFP+ Connector
• 10/100/1000 tri-speed Ethernet PHY
• USB-to-UART bridge
Chapter 1: KC705 Evaluation Board Features
• High-Definition Multimedia Interface ™ (HDMI) technology codec
•I2C bus
I2C mux
°
I2C EEPROM (1 KB)
°
USER I2C programmable LVDS oscillator
°
DDR3 SODIMM socket
°
HDMI codec
°
FMC HPC connector
°
FMC LPC connector
°
SFP+ connector
°
I2C programmable jitter-attenuating precision clock multiplier
°
•Status LEDs
Ethernet status
°
Power good
°
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FPGA INIT
°
FPGA DONE
°
•User I/O
USER LEDs (eight GPIO)
°
User pushbuttons (five directional)
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°
CPU reset pushbutton
°
User DIP switch (4-pole GPIO)
°
User edge drive rotary encoder switch
°
User SMA GPIO connectors (one pair)
°
LCD character display (16 characters x 2 lines)
°
•Switches
Power on/off slide switch
°
FPGA_PROG_B pushbutton switch
°
• VITA 57.1 FMC HPC Connector
• VITA 57.1 FMC LPC Connector
• Power management
PMBus voltage and current monitoring via TI power controller
°
Chapter 1: KC705 Evaluation Board Features
• XADC header
• Configuration options
Linear BPI flash memory
°
Quad SPI flash memory
°
USB JTAG configuration port
°
Platform cable header JTAG configuration port
°
The KC705 board block diagram is shown in Figure 1-1. The KC705 board schematics are
available for download from the Kintex-7 FPGA KC705 Evaluation Kit website.
CAUTION! The KC705 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
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X-Ref Target - Figure 1-1
UG810_c1_01_011812
Kintex-7 FPGA
XC7K325T-2FFG900C
128 MB Linear BPI
Flash memory
128 Mb Quad-SPI
Flash Memory
8-lane PCI Express
Edge Connector
LCD Display
(2 line x 16 characters)
1 KB EEPROM (I2C)
I2C Bus Switch
XADC Header
User Switches,
Buttons, and LEDs
HDMI Video
Interface
Differential Clock
GTX SMA Clock
1 GB DDR3 Memory
(SODIMM)
FMC Connectors
(HPC/LPC)
10/100/1000 Ethernet
Interface
DIP Switch SW13
Config and Flash Addr
USB-to-UART Bridge
JTAG Interface
mini-B USB Connector
SFP+ Single Cage
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Chapter 1: KC705 Evaluation Board Features
Figure 1-1: KC705 Board Block Diagram
Feature Descriptions
Figure 1-2 shows the KC705 board. Each numbered feature that is referenced in Figure 1-2
is described in the sections that follow.
Note:
board.
The image in Figure 1-2 is for reference only and might not reflect the current revision of the
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X-Ref Target - Figure 1-2
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Round callout references a component
00
on the front side of the board
Chapter 1: KC705 Evaluation Board Features
Square callout references a component
00
on the back side of the board
35
17
21
18
33
14
20
6
34
4
15
11
13
30
9
26
8
3
29
10
7
1
12
16
Figure 1-2: KC705 Board Components
Table 1-1: KC705 Board Component Descriptions
2
19
User rotary switch
25
located under LCD
31
37
22
27
5
36
24
28
23
UG841_c1_02_042313
Callout
1U1Kintex-7 FPGA (Located under
2J1DDR3 Memory Module, under EMI
Reference
Designator
Component Description Notes
XC7K325T-2FFG900C, Radian
fansink)
INC3001-7_1.5BU_LI98
Micron MT8JTF12864HZ-1G6G1 15
Page Number
shield
3U58Linear BPI Flash Memory Micron PC28F00AP30TF 26
4U7Quad SPI Flash Memory Micron N25Q128A13BSF40F or
Micron MT25QL128ABA8ESF-0SIT
5U9SD Card Interface Molex 67840-8001 28
6 USB JTAG Module Digilent USB JTAG Module (with
micro-B receptacle)
7U6System Clock Source (back side of
SiTime SIT9102-243N25E200.0000 23
board)
8U45Programmable User Clock Source
Silicon Labs SI570BAB0000544DG 23
(back side of board)
9 J11, J12 User SMA Clock Input Rosenberger 32K10K-400L5 23
10 J15, J16 GTX SMA Clock Input Rosenberger 32K10K-400L5 23
11 U70 Jitter Attenuated Clock Silicon Labs SI5324C-C-GM 24
Schematic
0381397
26
14
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Table 1-1: KC705 Board Component Descriptions (Cont’d)
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Chapter 1: KC705 Evaluation Board Features
Callout
12 GTX Transceivers Embedded within FPGA U1 9
13 P1 PCI Express Edge Connector 8-lane card edge connector 21
14 P5 SFP/SFP+ Connector Molex 74441-0010 22
15 U37 10/100/1000 Tri-Speed Ethernet
16 U2 SGMII GTX Transceiver Clock
17 J6, U12 USB-to-UART Bridge Silicon Labs CP2103GM bridge
18 P6, U65 HDMI Video Output Molex 500254-1927, Analog
19 J31 LCD Character Display 2 x 7 0.1 in male pin header 30
20 U49 I2C Bus Switch, page 52 TI PCA9548ARGER 32
21 DS11 - DS13 Ethernet PHY Status LEDs EPHY status LED, dual green 25
34 DS14, DS20 -
22 DS1 - DS4,
Reference
Designator
DS24
Ds10,
DS25 - DS27
Component Description Notes
Page Number
Marvell M88E1111-BAB1C000 25
PHY
ICS ICS84402IAGI-01LF 23
Generator
(back side of board) and min-B
receptacle (front side of board)
Devices ADV7511KSTZ-P
Status LEDs Status LEDs, green 29
User GPIO LEDs GPIO LEDs, green 29
Schematic
0381397
27
34, 33
23 SW2 – SW6 User Pushbuttons E-Switch TL3301EP100QG 29
24 SW11 GPIO DIP Switch C and K 4-pole, SDA05H1SBD 29
25 SW8 Rotary Switch Panasonic EVQ-WK4001 29
26 J13, J14 GPIO SMA Connectors Rosenberger 32K10K-400L5 23
27 SW15 Power On/Off Slide Switch SW15 C and K 1201M2S3AQE2 35
28 SW14 FPGA_PROG_B Pushbutton SW14
(Active-Low)
29 SW13 Configuration Mode and Upper
Linear Flash Address Switch
(SW13)
30 J22 HPC Connector J22 Samtec ASP_134486_01 16-19
31 J2 LPC Connector J2 Samtec ASP_134603_01 20
32 U55, U21,
U103, U17,
U56, U104,
U105, U89,
U106, U99,
U71, U62,
U17, U18, U33
33 J46 XADC Header 2X10 0.1" male header 31
Power Management (voltage
regulators front side of board,
controllers back side of board)
E-Switch TL3301EP100QG 29
5-pole C and K SDA05H1IBD 27
TI UCD9248PFC controllers in
conjunction with various
regulators
35-46
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Table 1-1: KC705 Board Component Descriptions (Cont’d)
UG810_c1_03_011112
1
SW13
OFF Position = 0
ON Position = 1
2345
A25
A24
M2
M1
M0
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Chapter 1: KC705 Evaluation Board Features
Callout
34 J60 2 x 7 2 mm shrouded JTAG cable
35 J39 2 x 5 shrouded PMBus connector Assman HW10G-0202 35
36 J49 12V power input 2 x 3 connector Molex 39-30-1060 35
37 SW7 CPU Reset Pushbutton E-Switch TL3301EP100QG 35
Reference
Designator
Component Description Notes
Page Number
Molex 87832-1420 16
connector
Note: Jumper header locations are identified in Appendix A, Default Switch and Jumper Settings.
Kintex-7 FPGA
[Figure 1-2, callout 1]
The KC705 board is populated with the Kintex-7 XC7K325T-2FFG900C FPGA.
For further information on Kintex-7 FPGAs, see
FPGA Configuration
7 Series FPGAs Overview (DS180) [Ref 1].
Schematic
0381397
The KC705 board supports three of the five 7 series FPGA configuration modes:
• Master SPI flash memory using the onboard Quad SPI flash memory
• Master BPI flash memory using the onboard Linear BPI flash memory
• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the KC705
board configuration port
Each configuration interface corresponds to one or more configuration modes and bus
widths as listed in Table 1-2. The mode switches M2, M1, and M0 are on SW13 positions 3,
4, and 5 respectively as shown in Figure 1-3.
X-Ref Target - Figure 1-3
Figure 1-3: SW13 Default Settings
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on.
Refer to the Configuration Options, page 80 for detailed information about the mode
switch SW13.
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Table 1-2: KC705 Board FPGA Configuration Modes
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Chapter 1: KC705 Evaluation Board Features
Configuration Mode
SW13 DIP Switch
Settings (M[2:0])
Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 Output
Master BPI 010 x8, x16 Output
JTAG 101 x1 Not applicable
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide
(UG470) [Ref 2].
Encryption Key Backup Circuit
FPGA U1 implements bitstream encryption key technology. The KC705 board provides the
encryption key backup battery circuit shown in Figure 1-4. The rechargeable 1.5V lithium
button-type battery B1 is soldered to the board with the positive output connected to FPGA
U1 VCCBATT pin C10. The battery supply current I
board power is off. B1 is charged from the VCCAUX_IO 2.0V rail through a series diode with
a typical forward voltage drop of 0.38V. and 4.7 KΩ current limit resistor. The nominal
charging voltage is 1.62V.
X-Ref Target - Figure 1-4
D11
40V
200 mW
specification is 150 nA max when
BATT
NC
1
VCCAUX_IO (2.0V)
3
BAS40-04
2
R406
4.70K 1%
To FPGA U1 Pin C10
(VCCBATT)
FPGA_VBATT
B1
1/16W
1
+
Lithium Battery
Seiko
TS518SE_FL35E
2
GND
UG810_c1_04_031214
Figure 1-4: Encryption Key Backup Circuit
I/O Voltage Rails
There are 10 I/O banks available on the Kintex-7 device. The voltages applied to the FPGA
I/O banks used by the KC705 board are listed in Table 1-3.
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Chapter 1: KC705 Evaluation Board Features
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Table 1-3: I/O Voltage Rails
U1 FPGA Bank Power Supply Rail Net Name Voltage
Bank 0 VCC2V5_FPGA 2.5V
Bank 12
Bank 13
Bank 14 VCC2V5_FPGA 2.5V
Bank 15 VCC2V5_FPGA 2.5V
Bank 16
Bank 17
Bank 18
Bank 32 VCC1V5_FPGA 1.5V
Bank 33 VCC1V5_FPGA 1.5V
Bank 34 VCC1V5_FPGA 1.5V
Notes:
1. The VADJ_FPGA rail can support 1.8V, 2.5V, or 3.3V. For more information on VADJ_FPGA see Power Management,
page 71.
(1)
(1)
(1)
(1)
(1)
VADJ_FPGA 2.5V (default)
VADJ_FPGA 2.5V (default)
VADJ_FPGA 2.5V (default)
VADJ_FPGA 2.5V (default)
VADJ_FPGA 2.5V (default)
DDR3 Memory Module
[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM) for
storing user code and data.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: Up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 32, 33, and 34. Each bank is a 1.5V
high-performance (HP) bank. The VRP/VRN DCI resistor connection to bank 33 is cascaded
to the data interface banks 32 and 34 by adding the DCI cascade constraint to the XDC:
# Set DCI_CASCADE
set_property slave_banks {32 34} [get_iobanks 33]
An external 0.75V reference VTTREF is provided for data interface banks 32 and 34. Any
interface connected to these banks that requires a reference voltage must use this FPGA
voltage reference. The connections between the DDR 3 memory and the FPGA are listed in
Table 1-4.
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Chapter 1: KC705 Evaluation Board Features
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Table 1-4: DDR3 Memory Connections to the FPGA
J1 DDR3 Memory
U1 FPGA
Pin
Net Name I/O Standard
Pin
Number
AH12 DDR3_A0 SSTL15 98 A0
AG13 DDR3_A1 SSTL15 97 A1
AG12 DDR3_A2 SSTL15 96 A2
AF12 DDR3_A3 SSTL15 95 A3
AJ12 DDR3_A4 SSTL15 92 A4
AJ13 DDR3_A5 SSTL15 91 A5
AJ14 DDR3_A6 SSTL15 90 A6
AH14 DDR3_A7 SSTL15 86 A7
AK13 DDR3_A8 SSTL15 89 A8
AK14 DDR3_A9 SSTL15 85 A9
Pin Name
AF13 DDR3_A10 SSTL15 107 A10/AP
AE13 DDR3_A11 SSTL15 84 A11
AJ11 DDR3_A12 SSTL15 83 A12_BC_N
AH11 DDR3_A13 SSTL15 119 A13
AK10 DDR3_A14 SSTL15 80 A14
AK11 DDR3_A15 SSTL15 78 A15
AH9 DDR3_BA0 SSTL15 109 BA0
AG9 DDR3_BA1 SSTL15 108 BA1
AK9 DDR3_BA2 SSTL15 79 BA2
AA15 DDR3_D0 SSTL15 5 DQ0
AA16 DDR3_D1 SSTL15 7 DQ1
AC14 DDR3_D2 SSTL15 15 DQ2
AD14 DDR3_D3 SSTL15 17 DQ3
AA17 DDR3_D4 SSTL15 4 DQ4
AB15 DDR3_D5 SSTL15 6 DQ5
AE15 DDR3_D6 SSTL15 16 DQ6
KC705 Evaluation Board 15
UG810 (v1.8) March 20, 2018 www.xilinx.com
Y15 DDR3_D7 SSTL15 18 DQ7
AB19 DDR3_D8 SSTL15 21 DQ8
AD16 DDR3_D9 SSTL15 23 DQ9
AC19 DDR3_D10 SSTL15 33 DQ10
AD17 DDR3_D11 SSTL15 35 DQ11
Chapter 1: KC705 Evaluation Board Features
Send Feedback
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
AA18 DDR3_D12 SSTL15 22 DQ12
AB18 DDR3_D13 SSTL15 24 DQ13
AE18 DDR3_D14 SSTL15 34 DQ14
AD18 DDR3_D15 SSTL15 36 DQ15
AG19 DDR3_D16 SSTL15 39 DQ16
AK19 DDR3_D17 SSTL15 41 DQ17
AG18 DDR3_D18 SSTL15 51 DQ18
AF18 DDR3_D19 SSTL15 53 DQ19
AH19 DDR3_D20 SSTL15 40 DQ20
AJ19 DDR3_D21 SSTL15 42 DQ21
AE19 DDR3_D22 SSTL15 50 DQ22
AD19 DDR3_D23 SSTL15 52 DQ23
AK16 DDR3_D24 SSTL15 57 DQ24
Net Name I/O Standard
Pin
Number
Pin Name
J1 DDR3 Memory
AJ17 DDR3_D25 SSTL15 59 DQ25
AG15 DDR3_D26 SSTL15 67 DQ26
AF15 DDR3_D27 SSTL15 69 DQ27
AH17 DDR3_D28 SSTL15 56 DQ28
AG14 DDR3_D29 SSTL15 58 DQ29
AH15 DDR3_D30 SSTL15 68 DQ30
AK15 DDR3_D31 SSTL15 70 DQ31
AK8 DDR3_D32 SSTL15 129 DQ32
AK6 DDR3_D33 SSTL15 131 DQ33
AG7 DDR3_D34 SSTL15 141 DQ34
AF7 DDR3_D35 SSTL15 143 DQ35
AF8 DDR3_D36 SSTL15 130 DQ36
AK4 DDR3_D37 SSTL15 132 DQ37
AJ8 DDR3_D38 SSTL15 140 DQ38
AJ6 DDR3_D39 SSTL15 142 DQ39
AH5 DDR3_D40 SSTL15 147 DQ40
KC705 Evaluation Board 16
UG810 (v1.8) March 20, 2018 www.xilinx.com
AH6 DDR3_D41 SSTL15 149 DQ41
AJ2 DDR3_D42 SSTL15 157 DQ42
Chapter 1: KC705 Evaluation Board Features
Send Feedback
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
AH2 DDR3_D43 SSTL15 159 DQ43
AH4 DDR3_D44 SSTL15 146 DQ44
AJ4 DDR3_D45 SSTL15 148 DQ45
AK1 DDR3_D46 SSTL15 158 DQ46
AJ1 DDR3_D47 SSTL15 160 DQ47
AF1 DDR3_D48 SSTL15 163 DQ48
AF2 DDR3_D49 SSTL15 165 DQ49
AE4 DDR3_D50 SSTL15 175 DQ50
AE3 DDR3_D51 SSTL15 177 DQ51
AF3 DDR3_D52 SSTL15 164 DQ52
AF5 DDR3_D53 SSTL15 166 DQ53
AE1 DDR3_D54 SSTL15 174 DQ54
AE5 DDR3_D55 SSTL15 176 DQ55
Net Name I/O Standard
Pin
Number
Pin Name
J1 DDR3 Memory
AC1 DDR3_D56 SSTL15 181 DQ56
AD3 DDR3_D57 SSTL15 183 DQ57
AC4 DDR3_D58 SSTL15 191 DQ58
AC5 DDR3_D59 SSTL15 193 DQ59
AE6 DDR3_D60 SSTL15 180 DQ60
AD6 DDR3_D61 SSTL15 182 DQ61
AC2 DDR3_D62 SSTL15 192 DQ62
AD4 DDR3_D63 SSTL15 194 DQ63
Y16 DDR3_DM0 SSTL15 11 DM0
AB17 DDR3_DM1 SSTL15 28 DM1
AF17 DDR3_DM2 SSTL15 46 DM2
AE16 DDR3_DM3 SSTL15 63 DM3
AK5 DDR3_DM4 SSTL15 136 DM4
AJ3 DDR3_DM5 SSTL15 153 DM5
AF6 DDR3_DM6 SSTL15 170 DM6
AC7 DDR3_DM7 SSTL15 187 DM7
KC705 Evaluation Board 17
UG810 (v1.8) March 20, 2018 www.xilinx.com
AC15 DDR3_DQS0_N DIFF_SSTL15 10 DQS0_N
AC16 DDR3_DQS0_P DIFF_SSTL15 12 DQS0_P
Chapter 1: KC705 Evaluation Board Features
Send Feedback
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
Y18 DDR3_DQS1_N DIFF_SSTL15 27 DQS1_N
Y19 DDR3_DQS1_P DIFF_SSTL15 29 DQS1_P
AK18 DDR3_DQS2_N DIFF_SSTL15 45 DQS2_N
AJ18 DDR3_DQS2_P DIFF_SSTL15 47 DQS2_P
AJ16 DDR3_DQS3_N DIFF_SSTL15 62 DQS3_N
AH16 DDR3_DQS3_P DIFF_SSTL15 64 DQS3_P
AJ7 DDR3_DQS4_N DIFF_SSTL15 135 DQS4_N
AH7 DDR3_DQS4_P DIFF_SSTL15 137 DQS4_P
AH1 DDR3_DQS5_N DIFF_SSTL15 152 DQS5_N
AG2 DDR3_DQS5_P DIFF_SSTL15 154 DQS5_P
AG3 DDR3_DQS6_N DIFF_SSTL15 169 DQS6_N
AG4 DDR3_DQS6_P DIFF_SSTL15 171 DQS6_P
AD1 DDR3_DQS7_N DIFF_SSTL15 186 DQS7_N
Net Name I/O Standard
Pin
Number
Pin Name
J1 DDR3 Memory
AD2 DDR3_DQS7_P DIFF_SSTL15 188 DQS7_P
AD8 DDR3_ODT0 SSTL15 116 ODT0
AC10 DDR3_ODT1 SSTL15 120 ODT1
AK3 DDR3_RESET_B LVCMOS15 30 RESET_B
AC12 DDR3_S0_B SSTL15 114 S0_B
AE8 DDR3_S1_B SSTL15 121 S1_B
AJ9 DDR3_TEMP_EVENT SSTL15 198 EVENT_B
AE9 DDR3_WE_B SSTL15 113 WE_B
AC11 DDR3_CAS_B SSTL15 115 CAS_B
AD9 DDR3_RAS_B SSTL15 110 RAS_B
AF10 DDR3_CKE0 SSTL15 73 CKE0
AE10 DDR3_CKE1 SSTL15 74 CKE1
AH10 DDR3_CLK0_N DIFF_SSTL15 103 CK0_N
AG10 DDR3_CLK0_P DIFF_SSTL15 101 CK0_P
AF11 DDR3_CLK1_N DIFF_SSTL15 104 CK1_N
AE11 DDR3_CLK1_P DIFF_SSTL15 102 CK1_P
KC705 Evaluation Board 18
UG810 (v1.8) March 20, 2018 www.xilinx.com
The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions
Chapter 1: KC705 Evaluation Board Features
Send Feedback
User Guide (UG586) [Ref 3]. The KC705 DDR3 SODIMM interface is a 40Ω impedance
implementation. Other memory interface details are available in UG586 and 7SeriesFPGAs
Memory Resources User Guide (UG473) [Ref 4] . For more information about the Micron
MT8JTF12864HZ-1G6G1 part, see [Ref 5].
Linear BPI Flash Memory
[Figure 1-2, callout 3]
The Linear BPI flash memory located at U58 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.
• Part number: PC28F00AP30TF (Micron)
• Supply voltage: 2.5V
• Datapath width: 16 bits (26 address lines and 7 control signals)
• Data rate: Up to 33 MHz
The Linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at
the 33 MHz data rate supported by the PC28F00AP30TF flash memory by using a
configuration bitstream generated with BitGen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external 66 MHz
oscillator connected to the FPGA EMCCLK pin with a bitstream that has been built to divide
the configuration clock by two. The division is necessary to remain within the synchronous
read timing specifications of the flash memory.
Multiple bitstreams can be stored in the Linear BPI flash memory. The two most significant
address bits (A25, A24) of the flash memory are connected to DIP switch SW13 positions 1
and 2 respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW13. The
connections between the BPI flash memory and the FPGA are listed in Table 1-5.
Table 1-5: BPI Flash Memory Connections to the FPGA
U58 BPI Flash Memory
U1 FPGA Pin Net Name I/O Standard
Pin Number Pin Name
W22 FLASH_A0 LVCMOS25 A1 A1
W21 FLASH_A1 LVCMOS25 B1 A2
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UG810 (v1.8) March 20, 2018 www.xilinx.com
V24 FLASH_A2 LVCMOS25 C1 A3
U24 FLASH_A3 LVCMOS25 D1 A4
V22 FLASH_A4 LVCMOS25 D2 A5
V21 FLASH_A5 LVCMOS25 A2 A6
Chapter 1: KC705 Evaluation Board Features
Send Feedback
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name I/O Standard
U58 BPI Flash Memory
Pin Number Pin Name
U23 FLASH_A6 LVCMOS25 C2 A7
W24 FLASH_A7 LVCMOS25 A3 A8
W23 FLASH_A8 LVCMOS25 B3 A9
V20 FLASH_A9 LVCMOS25 C3 A10
V19 FLASH_A10 LVCMOS25 D3 A11
W26 FLASH_A11 LVCMOS25 C4 A12
V25 FLASH_A12 LVCMOS25 A5 A13
V30 FLASH_A13 LVCMOS25 B5 A14
V29 FLASH_A14 LVCMOS25 C5 A15
V27 FLASH_A15 LVCMOS25 D7 A16
P22 FLASH_A16 LVCMOS25 D8 A17
P21 FLASH_A17 LVCMOS25 A7 A18
N24 FLASH_A18 LVCMOS25 B7 A19
N22 FLASH_A19 LVCMOS25 C7 A20
N21 FLASH_A20 LVCMOS25 C8 A21
N20 FLASH_A21 LVCMOS25 A8 A22
N19 FLASH_A22 LVCMOS25 G1 A23
N26 FLASH_A23 LVCMOS25 H8 A24
M23 FLASH_A24 LVCMOS25 B6 A25
M22 FLASH_A25 LVCMOS25 B8 A26
P24 FLASH_D0 LVCMOS25 F2 DQ0
R25 FLASH_D1 LVCMOS25 E2 DQ1
R20 FLASH_D2 LVCMOS25 G3 DQ2
R21 FLASH_D3 LVCMOS25 E4 DQ3
T20 FLASH_D4 LVCMOS25 E5 DQ4
T21 FLASH_D5 LVCMOS25 G5 DQ5
T22 FLASH_D6 LVCMOS25 G6 DQ6
T23 FLASH_D7 LVCMOS25 H7 DQ7
U20 FLASH_D8 LVCMOS25 E1 DQ8
P29 FLASH_D9 LVCMOS25 E3 DQ9
KC705 Evaluation Board 20
UG810 (v1.8) March 20, 2018 www.xilinx.com
R29 FLASH_D10 LVCMOS25 F3 DQ10
P27 FLASH_D11 LVCMOS25 F4 DQ11
Chapter 1: KC705 Evaluation Board Features
Send Feedback
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name I/O Standard
U58 BPI Flash Memory
Pin Number Pin Name
P28 FLASH_D12 LVCMOS25 F5 DQ12
T30 FLASH_D13 LVCMOS25 H5 DQ13
P26 FLASH_D14 LVCMOS25 G7 DQ14
R26 FLASH_D15 LVCMOS25 E7 DQ15
U29 FLASH_WAIT LVCMOS25 F7 WAIT
M25 FPGA_FWE_B LVCMOS25 G8 WE_B
M24 FLASH_OE_B LVCMOS25 F8 OE_B
B10 FPGA_CCLK LVCMOS25 E6 CLK
U63.6 FLASH_CE_B LVCMOS25 B4 CE_B
M30 FLASH_ADV_B LVCMOS25 F6 ADV_B
A10 FPGA_INIT_B LVCMOS25 D4 RST_B
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in 7 Series FPGAs Configuration
User Guide (UG470) [Ref 2]. The configuration section in this document provides details on
the Master BPI configuration mode.
KC705 Evaluation Board 21
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
PC28F00AP30TF
64-Pin BGA (8 x 10 mm)
U58
FLASH_A0
A1
FLASH_A1
A2
FLASH_A2
A3
FLASH_A3
A4
FLASH_A4
A5
FLASH_A5
A6
FLASH_A6
A7
FLASH_A7
A8
FLASH_A8
A9
FLASH_A9
A10
FLASH_A10
A11
FLASH_A11
A12
FLASH_A12
A13
FLASH_A13
A14
FLASH_A14
A15
FLASH_A15
A16
FLASH_A16
A17
FLASH_A17
A18
FLASH_A18
A19
FLASH_A19
A20
FLASH_A20
A21
FLASH_A21
A22
FLASH_A22
A23
FLASH_A23
A24
FLASH_A24
A25
FLASH_A25
A26
NC
A27
VCC2
VCCQ1
VCCQ2
VCCQ3
VPP
VCC1
FLASH_D0_R
DQ0
FLASH_D1_R
DQ1
FLASH_D2_R
DQ2
FLASH_D3_R
DQ3
FLASH_D4_R
DQ4
FLASH_D5_R
DQ5
FLASH_D6_R
DQ6
FLASH_D7_R
DQ7
FLASH_D8_R
DQ8
FLASH_D9_R
DQ9
FLASH_D10_R
DQ10
FLASH_D11_R
DQ11
FLASH_D12_R
DQ12
FLASH_D13_R
DQ13
FLASH_D14_R
DQ14
FLASH_D15_R
DQ15
WE_B
FLASH_WP_B
WP_B
ADV_B
RST_B
OE_B
CE_B
FLASH_WAIT_R
WAIT
GND
VSS0
VSS1
VSS2
VSS3
NC
RFU1
NC
RFU2
NC
RFU3
2.5V
1.8V
CLK
UG810_c1_05_031214
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
H1
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
D5
D6
G4
A4
A6
H3
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
G8
C6
F6
D4
F8
B4
F7
E6
H6
E8
F1
G2
B2
H2
H4
FLASH_ADV_B
FPGA_INIT_B
FLASH_OE_B
FLASH_CE_B
FLASH_PWE_B
FPGA_CCLK
Send Feedback
Figure 1-5 shows the connections of the linear BPI flash memory on the KC705 board.
For more information about the Micron PC28F00AP30TF part, see [Ref 5].
X-Ref Target - Figure 1-5
Figure 1-5: 128 MB Linear Flash Memory (U58)
KC705 Evaluation Board 22
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Chapter 1: KC705 Evaluation Board Features
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Quad SPI Flash Memory
[Figure 1-2, callout 4]
The Quad SPI flash memory located at U7 on the back side of the board provides 128 Mb of
nonvolatile storage that can be used for configuration and data storage.
• Part number: Micron N25Q128A13BSF40F or MT25QL128ABA8ESF-0SIT
• Supply voltage: 2.8V
• Datapath width: 4 bits
• Data rate: Various depending on Single/Dual/Quad mode and CCLK rate
Four data lines and the FPGA CCLK pin are wired to the Quad SPI flash memory. A common
chip select (FPGA_FCS) shared between the Linear BPI flash memory and the Quad SPI flash
memory is controlled by the configuration mode settings on DIP switch SW13 position 5
(M0) and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the SPI flash memory
device is selected. If mode pin M0 = 0, the Linear BPI flash memory device is selected. The
connections between the SPI flash memory and the FPGA are listed in Table 1-6.
Table 1-6: Quad SPI Flash Memory Connections to the FPGA
J1 DDR3 Memory
U1 FPGA Pin Net Name I/O Standard
Pin Number Pin Name
P24 FLASH_D0 LVCMOS25 15 DQ0
R25 FLASH_D1 LVCMOS25 8 DQ1
R20 FLASH_D2 LVCMOS25 9 DQ2
R21 FLASH_D3 LVCMOS25 1 DQ3
B10 FPGA_CCLK N/A 16 C
U19 QSPI_IC_CS_B
Notes:
1. FPGA_FCS connected to FPGA U1 pin U19 becomes QSPI_IC_CS_B through U64 and J3.
(1)
LVCMOS25 7 S_B
KC705 Evaluation Board 23
UG810 (v1.8) March 20, 2018 www.xilinx.com
X-Ref Target - Figure 1-6
UG810_c1_06_031214
VCC2V5
N25Q128
128 Mb Serial
Flash Memory
GND
1
2
3
5
7
6
U7
4
8
VCC_SPI
C18
0.1μF 25V
X5R
FLASH_D2
DQ1
16
15
14
12
10
11
13
9
SB
NC3
NC2
NC1
NC0
VCC
HOLD_B/DQ3
WB/VPP/DQ2
VSS
NC4
NC5
NC6
NC7
DQ0
C
R17
DNP
R18
4.7kΩ 5%
R431
15Ω 1%
R432
15Ω 1%
FLASH_D0
FPGA_CCLK
FLASH_D2_R
FLASH_D0_R
GND
VCC2V5
R20
DNP
R19
4.7kΩ 5%
R21
4.7kΩ 5%
R430
15Ω 1%
R429
15Ω 1%
FLASH_D2_R
FLASH_D3_R
FLASH_D3
FLASH_D1
QSPI_IC_CS_B
Send Feedback
Chapter 1: KC705 Evaluation Board Features
The configuration section of7 Series FPGAs Configuration User Guide (UG470) [Ref 2]
provides details on using the Quad SPI flash memory. Figure 1-6 shows the connections of
the Quad SPI flash memory on the KC705 board.
For more information about the Micron N25Q128A13BSF40F or MT25QL128ABA8ESF-0SIT
parts, see [Ref 5].
KC705 Evaluation Board 24
UG810 (v1.8) March 20, 2018 www.xilinx.com
Figure 1-6: 128 Mb Quad SPI Flash Memory
SD Card Interface
[Figure 1-2, callout 5]
The KC705 board includes a secure digital input/output (SDIO) interface to provide
user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The
SD card slot is designed to support 50 MHz high speed SD cards.
The SDIO signals are connected to I/O bank 12 which has its VCCO set to VADJ. A Texas
Instruments I TXB0108 8-bit bidirectional voltage-level translator is used between the FPGA
X-Ref Target - Figure 1-7
Send Feedback
To
Chapter 1: KC705 Evaluation Board Features
and the SD card connector (U9). Figure 1-7 shows the connections of the SD card interface
on the KC705 board.
VCC3V3
SDIO_DAT0 7
SDIO_DAT1
SDIO_DAT2
SDIO_CMD
SDIO_CLK
SDIO_SDWP
NC 12
U9
4
8
9
1SDIO_CD_DAT3
2
5
10
11
3
6
GND
C22
0.1μF 25V
X5R
GND
SDIO Card
Connector
VDD
DAT0
DAT1
DAT2
CD_DAT3
CMD
CLK
DETECT
PROTECT
D_P
VSS2
IOGND2
IOGND1
GNDTAB4
GNDTAB3
GNDTAB2VSS1
GNDTAB1
FPGA
Bank 12
(U1)
51.1K 1% Six Places
SDIO_DAT0_LS
SDIO_DAT1_LS
SDIO_DAT2_LS
SDIO_CD_DAT3_LS
SDIO_CMD_LS
SDIO_CLK_LS
R447
R449
R448
0.1μF 25V
R450
C543
R451
X5R
GND
VADJ
R452
NC
NC
C22
0.1μF 25V
X5R
U57
GND
TXB0108
Voltage-Level
Translator
VCCB
VCCA
A1
A2
A3
A4
A5
A6
A7
A8 B8
OE
GND
B1
B2
B3
B4
B5
B6
B7
GND
VCC3V3
51.1K 1% Six Places
To
FPGA
Bank 12
(U1)
R453
R454
VADJ
R455
VCC3V3
R457
R456
4.7K
R35
R458
SDIO_SDDET
R34
4.7K
18
17
16
15
14
13
GND
UG810_c1_07_031214
Figure 1-7: SD Card Interface
Table 1-7 lists the SD card interface connections to the FPGA.
Table 1-7: SDIO Connections to the FPGA
U57 Level Shifter U9 SDIO Connector
U1 FPGA Pin Schematic Net Name I/O Standard
Pin Name (A) Pin Name (B) Pin Number Pin Name
Y21 SDIO_SDWP LVCMOS25 N/A N/A 11 SDWP
AA21 SDIO_SDDET LVCMOS25 N/A N/A 10 SDDET
AB22 SDIO_CMD_LS LVCMOS25 A5 B6 2 CMD
AB23 SDIO_CLK_LS LVCMOS25 A6 B7 5 CLK
AA22 SDIO_DAT2_LS LVCMOS25 A3 B4 9 DAT2
AA23 SDIO_DAT1_LS LVCMOS25 A2 B3 8 DAT1
AC20 SDIO_DAT0_LS LVCMOS25 A1 B1 7 DAT0
AC21 SDIO_CD_DAT3_LS LVCMOS25 A4 B5 1 CD_DAT3
KC705 Evaluation Board 25
UG810 (v1.8) March 20, 2018 www.xilinx.com
X-Ref Target - Figure 1-8
UG810_c1_08_031214
2.5V3.3V
FMC HPC
Connector
TDI
TDO
J22
USB
Module
or
JTAG
Connector
(J60)
TDO
TDI
U1
Kintex-7
FPGA
TDI
TDO
SN74AVC1T45
Voltage
Translator
TDI TDO
U102
FMC LPC
Connector
TDI
TDO
J2
SPST Bus Switch
U76
N.C. N.C.
SPST Bus Switch
U77
Send Feedback
Chapter 1: KC705 Evaluation Board Features
USB JTAG Module
[Figure 1-2, callout 6]
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U59) where a host computer accesses the KC705 board JTAG chain through a
standard-A plug (host side) to micro-B plug (KC705 board side) USB cable.
A 2-mm JTAG header (J60) is also provided in parallel for access by Xilinx® download cables
such as the Platform Cable USB II and the Parallel Cable IV.
The JTAG chain of the KC705 board is illustrated in Figure 1-8. JTAG configuration is allowed
at any time regardless of FPGA mode pin settings. JTAG initiated configuration takes
priority over the configuration method selected through the FPGA mode pin settings at
SW13.
KC705 Evaluation Board 26
UG810 (v1.8) March 20, 2018 www.xilinx.com
Figure 1-8: JTAG Chain Block Diagram
When an FMC card is attached to the KC705 board, it is automatically added to the JTAG
chain through electronically controlled single-pole single-throw (SPST) switches U76 and
U77. The SPST switches are in a normally closed state and transition to an open state when
an FMC mezzanine card is attached. Switch U76 adds an attached FMC HPC mezzanine card
to the FPGAs JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U77
adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the
FMC_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO
connection via a device or bypass jumper for the JTAG chain to be completed to the FPGA
U1.
The JTAG connectivity on the KC705 board allows a host computer to download bitstreams
to the FPGA using the Xilinx software. In addition, the JTAG connector allows debug tools or
a software debugger to access the FPGA. The Xilinx software tool can also indirectly
program the Linear BPI or the Quad SPI flash memory. To accomplish this, the software
X-Ref Target - Figure 1-9
UG810_c1_09_031214
JTAG_TDI
FMC_TDI_BUF
FPGA_TMS_BUF
FPGA_TDO
FPGA_TCK_BUF
FMC_LPC_TCK_BUF
FMC_HPC_TDO
FMC_LPC_TDO
FMC_TMS_BUF
LPC_PRSNT_M2C_B
HPC_PRSNT_M2C_B
JTAG_TMS
JTAG_TCK
JTAG_TDO
FMC_LPC_TMS_BUF
FMC_HPC_TCK_BUF
FMC_HPC_PRSNT_M2C_B
FMC_LPC_PRSNT_M2C_B
FMC HPC
Connector
TDI
TDO
J22
TMS
TCK
PRSNT_L
VCC3V3
FMC LPC
Connector
TDI
TDO
J2
TMS
TCK
PRSNT_L
Kintex-7
FPGA
TDI
TDO
U1
TMS
TCK
Digilent
USB-JTAG
Module
TMS
TDI
SN74AVC1T45
Voltage
Translator
U102
SN74AVC2T45
Voltage
Translator
U69
SN74LV541A
Voltage
Translator
U5
R381 15Ω
U59
R382 15Ω
R380 15Ω
TCK
TDO
TMS
TDI
J60
TCK
TDO
JTAG
Header
VCC2V5
VCC2V5
VCC3V3
VCC3V3
VCC3V3
VCC3V3
VCC3V3
U76
U77
Send Feedback
Chapter 1: KC705 Evaluation Board Features
configures the FPGA with a temporary design to access and program the BPI or Quad SPI
flash memory device. The JTAG circuit is shown in Figure 1-9.
Figure 1-9: JTAG Circuit
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Chapter 1: KC705 Evaluation Board Features
Send Feedback
Clock Generation
There are five clock sources available for the FPGA fabric on the KC705 board (refer to
Table 1-8).
Table 1-8: KC705 Board Clock Sources
Clock Name Reference Description
System Clock
User Clock
User SMA Clock
(differential pair)
GTX SMA REF Clock
(differential pair)
Jitter Attenuated
Clock
U6
U45
J11
J12
J16
J15
U70
SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time). See
System Clock Source, page 29.
Si570 3.3V LVDS I2C Programmable Oscillator
(Silicon Labs). Default power-on frequency 156.250 MHz. See
Programmable User Clock Source, page 29.
USER_SMA_CLOCK_P (net name).
See User SMA Clock Input, page 30.
USER_SMA_CLOCK_N (net name)
See User SMA Clock Input, page 30
SMA_MGT_REFCLK_P (net name).
See GTX SMA Clock Input, page 31.
SMA_MGT_REFCLK_N (net name).
See GTX SMA Clock Input, page 31.
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon
Labs).
See Jitter Attenuated Clock, page 32.
Table 1-9 lists the pin-to-pin connections from each clock source to the FPGA.
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Table 1-9: Clock Source to FPGA U1 Connections
Clock Source Pin Schematic Net Name I/O Standard U1 FPGA Pin
U6.5 SYSCLK_N LVDS AD11
U6.4 SYSCLK_P LVDS AD12
U45.5 USER_CLOCK_N LVDS_25 K29
U45.4 USER_CLOCK_P LVDS_25 K28
J12.1 USER_SMA_CLOCK_N LVDS_25 K25
J11.1 USER_SMA_CLOCK_P LVDS_25 L25
J15.1 SMA_MGT_REFCLK_N N/A (MGT REFCLK INPUT) J7
J16.1 SMA_MGT_REFCLK_P N/A (MGT REFCLK INPUT) J8
U70.29 Si5326_OUT_N N/A (MGT REFCLK INPUT) L7
U70.28 Si5326_OUT_P N/A (MGT REFCLK INPUT) L8
Chapter 1: KC705 Evaluation Board Features
Send Feedback
System Clock Source
[Figure 1-2, callout 7]
The KC705 board has a 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the
back side of the board and wired to an FPGA MRCC clock input on bank 33. This 200 MHz
signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins AD12
and AD11 respectively.
• Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
• PPM frequency jitter: 50 ppm
• Differential Output
The system clock circuit is shown in Figure 1-10.
X-Ref Target - Figure 1-10
VCC2V5
U6
SIT9102
200 MHz
1
2
3
Oscillator
OE
NC
GND
VCC
OUT_B
OUT
6
5
4
R459
100Ω 1%
SYSCLK_N
SYSCLK_P
C550
0.1 μF 10V
X5R
GND
UG810_c1_10_031214
Figure 1-10: System Clock Source
For more about the Si Time SiT9102 see [Ref 6].
Programmable User Clock Source
[Figure 1-2, callout 8]
The KC705 board has a programmable low-jitter 3.3V differential oscillator (U45) the FPGA
MRCC inputs of bank 15. This USER_CLOCK_P and USER_CLOCK_N clock signal pair are
connected to FPGA U1 pins K28 and K29 respectively. On power-up the user clock defaults
to an output frequency of 156.250 MHz. User applications can change the output frequency
within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the KC705
board reverts the user clock to its default frequency of 156.250 MHz.
• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)
• Differential Output
• I2C address 0x5D
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The user clock circuit is shown in Figure 1-11.
UG810_c1_11_031214
GND
VCC3V3
Si570
Programmable
Oscillator
NC
OE
GND
SCL
SDA
VDD
1
2
3
8
7
6
U45
R8
4.7KΩ 5%
USER CLOCK N
C77
0.01 μF 25V
X7R
CLK-
4
5
GND
VCC3V3
CLK+
USER CLOCK P
USER CLOCK SDA
USER CLOCK SCL
10 MHz - 810 MHz
50 PPM
To
I2C
Bus Switch
(U49)
Send Feedback
X-Ref Target - Figure 1-11
Figure 1-11: User Clock Source
Chapter 1: KC705 Evaluation Board Features
For more information about the Silicon Labs Si570 see [Ref 7].
Reference design files are available to demonstrate how to program the Si570
programmable oscillator. See these files and presentations:
• XTP186, KC705 Si570 Programming [Ref 8]
• RDF0175, KC705 Si570 Programming Design Files [Ref 9]
• XTP187, KC705 Si570 Fixed Frequencies [Ref 10]
• RDF0176, KC705 Si570 Fixed Frequencies Design Files [Ref 11]
User SMA Clock Input
[Figure 1-2, callout 9]
An external high-precision clock signal can be provided to the FPGA bank 15 by connecting
differential clock signals through the onboard 50Ω SMA connectors J11 (P) and J12 (N). The
differential clock has signal names are USER_SMA_CLOCK_P and USER_SMA_CLOCK_N,
which are connected to FPGA U1 pins L25 and K25, respectively. J11 (P) and J12 (N) are
connected directly to the noted FPGA pins (no series capacitors and no external parallel
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