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I2S
Product Manual
40 pgs644.99 Kb0

Xilinx I2S Product Manual

I2S Transmier and I2S Receiver v1.0
LogiCORE IP Product Guide
Vivado Design Suite
PG308 (v1.0) April 4, 2018
Table of Contents
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Chapter 1: IP Facts......................................................................................................... 4
Chapter 2: Overview......................................................................................................6
Chapter 3: Product Specification........................................................................... 8
Resource Use............................................................................................................................... 9
Port Descriptions.......................................................................................................................10
I2S Transmitter Register Space............................................................................................... 11
I2S Receiver Register Space..................................................................................................... 16
Chapter 4: Designing with the Core................................................................... 22
Chapter 5: Design Flow Steps.................................................................................27
Chapter 6: Example Design..................................................................................... 32
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I2S Transmitter and I2S Receiver 2
Simulating the Example Design.............................................................................................. 33
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Test Bench for Example Design...............................................................................................34
Appendix A: Debugging............................................................................................ 35
Appendix B: Additional Resources and Legal Notices............................. 38
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I2S Transmitter and I2S Receiver 3
IP Facts
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The Xilinx® LogiCORE™ IP I2S Transmier and LogiCORE™ Receiver cores are so Xilinx IP cores for use with the Xilinx Vivado® Design Suite, which makes it easy to implement inter-IC-sound (I2S) interface used to connect audio devices for transming and receiving PCM audio.
Features
• AXI4-Stream compliant
Chapter 1: IP Facts
Chapter 1
• Supports up to four I2S channels (upto eight Audio channels)
• 16/24 bit data
• Supports Master I2S mode
• Congurable FIFO depth
• Supports the AES channel status extracon/inseron
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported Device Family
Supported User Interfaces AXI4-Lite, AXI4-Stream, AXI4
Resources Performance and Resource Use web page for transmitter
Design Files System Verilog
Example Design System Verilog
Test Bench System Verilog
Constraints File Delivered at the time of IP generation
Simulation Model Source HDL
Supported S/W Driver
1
Provided with Core
2
UltraScale+™, UltraScale™, Zynq®-7000 SoC, 7 series, Zynq UltraScale+™ MPSoC.
and Performance and Resource Use web page for receiver.
Standalone
®
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I2S Transmitter and I2S Receiver 4
Chapter 1: IP Facts
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LogiCORE IP Facts Table
Tested Design Flows
Design Entry Vivado® Design Suite Vivado IP Integrator
Simulation For supported simulators, see the Xilinx Design Tools:
Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx® at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP catalog.
2. Standalone driver details can be found in the software development kit (SDK) directory (<install_directory>/SDK/ <release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the
Xilinx Wiki page.
3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
3
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I2S Transmitter and I2S Receiver 5
Overview
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The I2S Tramsmier and I2S Receiver cores provide an easy way to interface the I2S based audio DAC/ADC. These IPs require minimal register programming and also support any audio sampling rates. These IPs can be used along side HDMI, DisplayPort, and SDI for complete audio video
soluon.
Applications
Chapter 2: Overview
Chapter 2
Typical applicaons for I2S interfaces could be audio and video conferencing equipment, consumer mul-media devices, professional audio sources, and sinks. The I2S Tramsmier and I2S Receiver IPs can be used to develop audio soluon using I2S ADC/DACs. These IPs are typically used with video connecvity IPs such as HDMI and Display Port to play or insert the audio.
Unsupported Features
The following features of the standard are not supported in the core:
• Le and right jused I2S
• Data width of 20
• Slave mode
• Decode/encode user informaon bits
Licensing and Ordering
This Xilinx® LogiCORE™ IP module is provided at no addional cost with the Xilinx® Vivado under the terms of the Xilinx End User License.
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I2S Transmitter and I2S Receiver 6
®
Chapter 2: Overview
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Note: To verify that you need a license, check the License column of the IP Catalog. Included means that a license is included with the Vivado® Design Suite; Purchase means that you have to purchase a license to use the core.
For more informaon about this core, visit the I2S Tramsmier and I2S Receiver product web
page
Informaon about other Xilinx® LogiCORE™ IP modules is available at the Xilinx Intellectual
Property page. For informaon about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representave.
License Checkers
If the IP requires a license key, the key must be veried. The Vivado® design tools have several license checkpoints for gang licensed IP through the ow. If the license check succeeds, the IP can connue generaon. Otherwise, generaon halts with error. License checkpoints are enforced by the following tools:
• Vivado Synthesis
• Vivado Implementaon
• write_bitstream (Tcl command)
Note: IP license level is ignored at checkpoints. The test conrms a valid license exists. It does not check IP license level.
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I2S Transmitter and I2S Receiver 7
Product Specification
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The I2S Tramsmier and I2S Receiver IPs can be used to develop audio soluon using I2S ADC/ DACs. These IPs support any sampling rate and are very easy to congure with minimal register programming.
Figure 1: TX Audio Sampling
Chapter 3: Product Specification
Chapter 3
AXIS Audio (AES3)
s_axis_aud_aclk
aud_mclk
AXI4Lite
s_axi_ctrl_aclk
AES3 Audio
Decoder
Register
Interface
FIFO
I2S TX
I2S Timing
Gen
Sdata[3:0]
SCK LRCLK
X20717-042318
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I2S Transmitter and I2S Receiver 8
Figure 2: RX Audio Sampling
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Chapter 3: Product Specification
AXIS Audio (AES3)
m_axis_aud_aclk
s_axi_ctrl_aclk
AXI4Lite
aud_mclk
AES3 Audio
Encoder
Register
Interface
FIFO
I2S RX
I2S Timing
Gen
SData[3:0]
SCK LRCLK
X20720-042318
Performance
For full details about performance and resource use, visit the Performance and Resource Use web
page for transmier and Performance and Resource Use web page for receiver.
Resource Use
For full details about performance and resource use, visit the Performance and Resource Use web
page for transmier and Performance and Resource Use web page for receiver.
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I2S Transmitter and I2S Receiver 9
Chapter 3: Product Specification
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Port Descriptions
Port Names
Table 1: Port Names
Port Name I/O Clock Description
Transmitter Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4-Lite Interface
s_axi_ctrl_* s_axi_ctrl AXI4-Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs
aud_mrst I Reset Active-High reset for audio interface
s_axis_aud_aclk I Clock AXIS Audio streaming clock
s_axis_aud_resetn I Reset Active-Low AXIS audio reset
s_axis_aud_* Audio AXIS
Interface
Irq O Interrupt Active-High interrupt
lrclk_out O LRClk Output LR Clock. Available when core is configured
sclk_out O SCLK Output SCK Clock. Available when core is
lrclk_in I LRClk Input LR Clock. Available when core is configured
Sclk_in I SCLK Input SCK Clock. Available when core is configured
sdata_0_out O SDATA0 I2S Serial Data out
sdata_1_out O SDATA1 I2S Serial Data out. Available when number of
sdata_2_out O SDATA2 I2S Serial Data out. Available when number of
sdata_3_out O SDATA3 I2S Serial Data out. Available when number of
Receiver Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4Lite Interface
s_axi_ctrl_* s_axi_ctrl AXI4Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs
aud_mrst I Reset Active-High reset for audio interface
m_axis_aud_aclk I Clock AXIS Audio streaming clock
m_axis_aud_resetn I Reset Active-Low AXIS audio reset
m_axis_aud_* Audio AXIS
Interface
AXIS Audio Interface
as Master
configured as Master
as Slave
as Slave
audio channels is > 2
audio channels is > 4
audio channels is > 6
AXIS Audio Interface
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Chapter 3: Product Specification
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Table 1: Port Names (cont'd)
Port Name I/O Clock Description
Irq O Interrupt Active-High interrupt
lrclk_out O LRClk Output LR Clock. Available when core is configured
sclk_out O SCLK Output SCK Clock. Available when core is
lrclk_in I LRClk Input LR Clock. Available when core is configured
Sclk_in I SCLK Input SCK Clock. Available when core is configured
sdata_0_in I SDATA0 I2S Serial Data In
sdata_1_in I SDATA1 I2S Serial Data In. Available when number of audio
sdata_2_in I SDATA2 I2S Serial Data In. Available when number of audio
sdata_3_in I SDATA3 I2S Serial Data In. Available when number of audio
Notes:
as Master
configured as Master
as Slave
as Slave
channels is > 2
channels is > 4
channels is > 6
1. For more details on Audio AXIS interface, see Audio AXIS Interface.
I2S Transmitter Register Space
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.
Table 2: Register Address Space
Address (hex) Register Name
0x00 Core Version: Returns the core Major and Minor version
0x04 Core Configuration: Returns the core configuration details
0x08 Core Control: Register to enable/disable the core
0x10 Interrupt Control: Interrupt enable/disable register
0x14 Interrupt Status: Interrupt Status register
0x20 I2S Timing Control: Register to program the SCK divider
0x30 Channel 0/1 Control: Channel 0/1 control register
0x34 Channel 2/3 Control: Channel 2/3 control register
0x38 Channel 4/5 Control: Channel 4/5 control register
0x3C Channel 6/7 Control: Channel 6/7 control register
value
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Table 2: Register Address Space (cont'd)
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Address (hex) Register Name
0x50 AES Channel Status 0: Register that returns the LSB 32 bit of
0x54 AES Channel Status 1: Register that returns the next LSB 32
0x58 AES Channel Status 2: Register that returns the 32 bit of the
0x5C AES Channel Status 3: Register that returns the 32 bit of the
0x60 AES Channel Status 4: Register that returns the 32 bit of the
0x64 AES Channel Status 5: Register that returns the MSB 32 bit
Core Version (0x00)
Chapter 3: Product Specification
the AES Channel Status
bit of the AES Channel Status
AES Channel Status
AES Channel Status
AES Channel Status
of the AES Channel Status
This register returns the major and minor versions of the IP core.
Table 3: Transmitter Core Version (0x00)
Bit
31:16 0x1 RO Major Revision: This is the IP major revision value. For example if the IP version is
15:0 0x0 RO Minor Revision: This is the IP minor revision value. For example if the IP version
Default
Value
Access
Type
Description
1.2, then this will return a value of 1.
is 1.2, then this will return a value of 2.
Core Configuration (0x04)
This register returns the IP Conguraon.
Table 4: Transmitter Core Configuration (0x04)
Bit
31:17 0x1 Reserved
16 RO I2S Data Width: Indicates the I2S Data width of the core
15:12 Reserved
11:8 RO Number of Audio Channels: Indicates the number of audio channels supported.
7:1 Reserved
0 RO Is I2S Master: Indicates if the core has been generated as an I2S Master or Slave.
Default
Value
Access
Type
Description
1 = 24 bit 0 = 16 bit
Valid values are 2, 4, 6 and 8
1 = I2S Master
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