UNITRODE UCC18500, UCC18501, UCC18502, UCC18503, UCC28500 Technical data
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UCC18500
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
BiCMOS PFC/PWM Combination Controller
PRELIMINARY
FEATURES
•Combines PFC and 2nd Stage Down Converter Function
•Controls Boost PWM to Near-unity Power Factor
•Accurate Power Limiting
•Average Current Mode Control in PFC Stage
•Peak Current Mode Control in Second Stage
•Programmable Oscillator
•Leading Edge/Trailing Edge Modulation for Reduced Output Ripple Using SmartSync™
•Low Startup Supply Current
•Synchronized Second Stage Start-up, with Programmable Soft-start
•Programmable Second Stage Shut-down
DESCRIPTION
The UCC18500 family provides all of the functions necessary for an active power factor corrected preregulator and a second stage DC-to-DC converter. The controller achieves near-unity power factor by shaping the AC input line current waveform to correspond to the AC input line voltage using average current mode control. The DC-to-DC converter uses peak current mode control to perform the step down power conversion.
The PFC stage is leading edge modulated while the second stage is trailing edge synchronized to allow for minimum overlap between the boost and PWM switches. This reduces ripple current in the bulk output capacitor.
In order to operate with a three to one range of input line voltages, a line feedforward (VFF) in used to keep input power constant with varying input voltage. Generation of VFF is done using IAC in conjunction with an external single pole filter. This not only reduces external parts count, but avoids the use of high voltage components offering a lower cost solution. The multiplier then divides the line current by the square of VFF.
(continued)
BLOCK DIAGRAM
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VERR |
ISENSE2 |
SS2 |
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VCC |
GND |
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7 |
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8 |
13 |
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9 |
6 |
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SECOND STAGE |
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7.5V |
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20 |
VREF |
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SOFT START |
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REFERENCE |
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6.75V |
UVLO2 |
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UVLO |
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OVP/ENBL |
4 |
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VCC |
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1.5V |
– |
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ENABLE |
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16V/10 |
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+ |
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ILIMIT |
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1.5V |
1.3V |
R |
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10 |
GT2 |
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8.0V |
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PFCOVP |
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R |
Q |
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– |
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VAOUT |
1 |
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ZERO |
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PWM |
S |
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VOLTAGE |
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0.25V |
– |
POWER |
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CLK2 |
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ERROR AMP |
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+ |
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VSENSE |
3 |
– |
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X |
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VCC |
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+ |
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MULT |
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– |
CURRENT AMP |
– |
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X |
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+ |
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S |
Q |
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7.5V |
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PWM |
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PWM |
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)2 |
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12 |
GT1 |
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VFF |
19 |
(V |
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OSC |
LATCH |
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FF |
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R |
R |
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CLK1 |
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MIRROR |
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CLK2 |
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11 |
PWRGND |
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2:1 |
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CLK2 |
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CLK1 |
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ILIMIT |
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IAC |
18 |
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OSCILLATOR |
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– |
14 |
PKLMT |
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MOUT |
17 |
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+ |
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16 |
15 |
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2 |
5 |
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ISENSE1 |
CAOUT |
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RT |
CT |
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UDG-98189 |
SLUS419 - AUGUST 1999 |
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DESCRIPTION (cont.)
The UCC18500 PFC section incorporates a low offset voltage amplifier with 7.5V reference, a highly linear multiplier capable of a wide current range, a high bandwidth, low offset current amplifier, with a novel noise attenuation configuration, PWM comparator and latch and a high current output driver. Additional PFC features include over-voltage protection, zero power detection to turn-off the output when VAOUT is below 0.25V and peak current and power limiting.
The DC-to-DC section relies on an error signal generated on secondary-side and processes it by performing peak current mode control. The DC-to-DC section also features current limiting, a controlled soft-start, preset oper-
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
ating range with selectable options, and 50% maximum duty cycle.
The UCC38500 and UCC38502 have a wide PFC-UVLO threshold (16.5V/10V) for bootstrap bias supply operation. The UCC38501 and UCC38503 are designed with a narrow UVLO range (10.5V/10V) more suitable for fixed bias operation. The UCC38500 and UCC38501 have a narrow UVLO threshold for PWM stage (to allow operation down to 75% of nominal bulk voltage), while the UCC38502 and UCC38503 are configured for a much wider operation range for the PWM stage (down to 50% of bulk nominal voltage).
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Gate Drive Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2A
50% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Input Voltage
ISENSE1, ISENSE2 MOUT,VSENSE, OVP, ENBL, . . . . . . . . 11V
PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . 10mA
Maximum Negative Voltage, GT1, GT2,
PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND.
ORDERING INFORMATION
UCC 
850
PACKAGE INFORMATION
CONNECTION DIAGRAMS
DIL-20, SOIC-20 (TOP VIEW)
N, DW and J Packages
VAOUT |
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VREF |
1 |
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20 |
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VFF |
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RT |
2 |
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19 |
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VSENSE |
3 |
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18 |
IAC |
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OVP/ENA |
4 |
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17 |
MOUT |
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CT |
5 |
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16 |
ISENSE1 |
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GND |
6 |
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15 |
CAOUT |
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VERR |
7 |
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14 |
PKLMT |
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ISENSE2 |
8 |
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13 |
SS2 |
VCC |
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GT1 |
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9 |
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12 |
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GT2 |
10 |
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11 |
PWRGND |
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PRODUCT OPTION |
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TEMPERATURE RANGE |
UVLO |
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UVLO2 HYSTERESIS |
PACKAGE |
UCC18500 |
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16 |
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1.2 |
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UCC18501 |
–55° C to +125° C |
10.5 |
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1.2 |
J-CDIP |
UCC18502 |
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16 |
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3.0 |
N-PDIP |
UCC18503 |
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10.5 |
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3.0 |
DW-SOIC |
UCC28500 |
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16 |
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1.2 |
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UCC28501 |
–40° C to +85° C |
10.5 |
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1.2 |
N-PDIP |
UCC28502 |
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16 |
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3.0 |
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DW-SOIC |
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UCC28503 |
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10.5 |
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3.0 |
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UCC38500 |
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16 |
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1.2 |
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UCC38501 |
0° C to +70° C |
10.5 |
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1.2 |
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UCC38502 |
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16 |
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3.0 |
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UCC38503 |
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10.5 |
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3.0 |
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2
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications hold for TA=0°C to 70°C for the
UCC3850X, –40°C to +85°C for the UCC2850X, and –55°C to +125°C for the UCC1850X, T = T . VCC = 12V, RT = 22k, CT =
A J
330pF.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
Supply Current Section |
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Supply Current, Off |
VCC = 12V (VCC Turn-on Threshold –300mV) |
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150 |
300 |
A |
Supply Current, On |
VCC = 12V |
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4 |
6 |
mA |
UVLO Section |
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VCC Turn-On Threshold (UCCX8500/502) |
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15.4 |
16 |
16.6 |
V |
UVLO Hysteresis (UCCX8500/502) |
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5.4 |
6 |
6.2 |
V |
Shunt Voltage (UCCX8500/502) |
IVCC = 10mA |
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17 |
17.5 |
V |
VCC Turn-On Threshold (UCCX8501/503) |
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10.2 |
10.5 |
10.8 |
V |
UVLO Hysteresis (UCCX8501/503) |
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0.4 |
0.5 |
0.6 |
V |
Voltage Amplifier Section |
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Input Voltage |
TA = 0°C to 70°C |
7.388 |
7.500 |
7.613 |
V |
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TA = –40°C to 85°C |
7.369 |
7.500 |
7.631 |
V |
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TA = –55°C to125°C |
7.313 |
7.500 |
7.687 |
V |
VSENSE Bias Current |
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50 |
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nA |
Open Loop Gain |
VAOUT = 2V to 5V |
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80 |
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dB |
VOUT High |
ILOAD = –150 A |
5.4 |
5.5 |
5.6 |
V |
VOUT Low |
ILOAD = 150 A |
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0.05 |
0.10 |
V |
Over Voltage Protection and Enable Section |
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Over Voltage Reference |
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7.8 |
8.0 |
8.2 |
V |
Hysteresis |
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400 |
500 |
600 |
mV |
Enable Threshold |
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1 |
1.5 |
2 |
V |
Current Amplifier Section |
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Input Offset Voltage |
VCM = 0V, VCAOUT = 3V |
–5 |
0 |
5 |
mV |
Input Bias Current |
VCM = 0V, VCAOUT = 3V |
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–50 |
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nA |
Input Offset Current |
VCM = 0V, VCAOUT = 3V |
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25 |
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nA |
Open Loop Gain |
VCM = 0V, VCAOUT = 2V to 5V |
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90 |
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dB |
CMRR |
VCM = 0V to 1.5V, VCAOUT = 3V |
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80 |
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dB |
VOUT High |
ILOAD = –120 A |
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6.3 |
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V |
VOUT Low |
ILOAD = 1mA |
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0.2 |
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V |
Gain Bandwidth Product |
(Note 1) |
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2.5 |
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MHz |
Voltage Reference Section |
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Input Voltage |
TA = 0° C to 70° C |
7.388 |
7.500 |
7.613 |
V |
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TA = –40° C to 85° C |
7.369 |
7.500 |
7.631 |
V |
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TA = –55° C to 125° C |
7.313 |
7.500 |
7.687 |
V |
Load Regulation |
IREF = 1mA to 2mA |
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5 |
10 |
mV |
Line Regulation |
VCC = 12V to 16V |
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10 |
20 |
mV |
Short Circuit Current |
VREF = 0V |
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–25 |
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mA |
Oscillator Section |
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Initial Accuracy |
TA = 25°C |
85 |
100 |
115 |
kHz |
Voltage Stability |
VCC = 10.8V to 15V |
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1 |
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% |
Total Variation |
Line, Temp |
80 |
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120 |
kHz |
Ramp Peak Voltage |
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4.5 |
5 |
5.5 |
V |
Ramp Amplitude Voltage (peak to peak) |
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4 |
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V |
3
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