TEXAS INSTRUMENTS TMS320F28334 Technical data

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TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

Data Manual

Literature Number: SPRS439

June 2007

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Contents

1 TMS320F28335, TMS320F28334, TMS320F28332 DSCs ............................................................. 7

1.1 Features ....................................................................................................................... 7

1.2 Getting Started ............................................................................................................... 8

2 Introduction ......................................................................................................................... 9

2.1 Pin Assignments ............................................................................................................. 9

2.2 Signal Descriptions ......................................................................................................... 15

3 Functional Overview ........................................................................................................... 24

3.1 Memory Maps .............................................................................................................. 25

3.2 Brief Descriptions ........................................................................................................... 32

3.2.1 C28x CPU ....................................................................................................... 32

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 32

3.2.3 Peripheral Bus .................................................................................................. 32

3.2.4 Real-Time JTAG and Analysis ................................................................................ 32

3.2.5 External Interface (XINTF) ..................................................................................... 33

3.2.6 Flash .............................................................................................................. 33

3.2.7 M0, M1 SARAMs ............................................................................................... 33

3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 33

3.2.9 Boot ROM ........................................................................................................ 33

3.2.10 Security .......................................................................................................... 35

3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 35

3.2.12 External Interrupts (XINT1-XINT7, XNMI) .................................................................... 36

3.2.13 Oscillator and PLL .............................................................................................. 36

3.2.14 Watchdog ........................................................................................................ 36

3.2.15 Peripheral Clocking ............................................................................................. 36

3.2.16 Low-Power Modes .............................................................................................. 36

3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 37

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 37

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 37

3.2.20 Control Peripherals ............................................................................................. 38

3.2.21 Serial Port Peripherals ......................................................................................... 38

3.3 Register Map ................................................................................................................ 39

3.4 Device Emulation Registers ............................................................................................... 40

3.5 Interrupts .................................................................................................................... 41

3.5.1 External Interrupts .............................................................................................. 45

3.6 System Control ............................................................................................................. 45

3.6.1 OSC and PLL Block ............................................................................................ 47

3.6.2 Watchdog Block ................................................................................................. 50

3.7 Low-Power Modes Block .................................................................................................. 51

4 Peripherals ........................................................................................................................ 52

4.1 DMA Overview .............................................................................................................. 53

4.2 32-Bit CPU-Timers 0/1/2 .................................................................................................. 54

4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 56

4.4 High-Resolution PWM (HRPWM) ........................................................................................ 58

4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6) ............................................................................ 59

4.6 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 61

4.7 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 63

4.7.1 ADC Connections if the ADC Is Not Used ................................................................... 66

4.7.2 ADC Registers ................................................................................................... 66

4.8 Multichannel Buffered Serial Port (McBSP) Module ................................................................... 68

4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 71

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4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) ........................................... 76

4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ...................................................................... 80

4.12 Inter-Integrated Circuit (I2C) .............................................................................................. 83

4.13 GPIO MUX .................................................................................................................. 85

5 Device Support .................................................................................................................. 91

5.1 Device and Development Support Tool Nomenclature ................................................................ 91

5.2 Documentation Support ................................................................................................... 93

6 Electrical Specifications ...................................................................................................... 96

6.1 Absolute Maximum Ratings ............................................................................................... 96

6.2 Recommended Operating Conditions ................................................................................... 97

6.3 Electrical Characteristics ................................................................................................. 97

Contents 3

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TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

List of Figures

2-1 F28335, F28334, F28332 176-Pin PGF LQFP (Top View) .................................................................. 10

2-2 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .................... 11

2-3 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View) .................. 12

2-4 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .................... 13

2-5 F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Right Quadrant) (Bottom View) .................. 14

3-1 Functional Block Diagram ....................................................................................................... 24

3-2 F28335 Memory Map ............................................................................................................. 26

3-3 F28334 Memory Map ............................................................................................................. 27

3-4 F28332 Memory Map ............................................................................................................. 28

3-5 External and PIE Interrupt Sources ............................................................................................. 41

3-6 External Interrupts ................................................................................................................ 42

3-7 Multiplexing of Interrupts Using the PIE Block ................................................................................ 43

3-8 Clock and Reset Domains ....................................................................................................... 46

3-9 OSC and PLL Block Diagram ................................................................................................... 47

3-10 Using a 3.3-V External Oscillator ............................................................................................... 48

3-11 Using a 1.8-V External Oscillator ............................................................................................... 48

3-12 Using the Internal Oscillator ..................................................................................................... 48

3-13 Watchdog Module ................................................................................................................. 50

4-1 DMA Functional Block Diagram ................................................................................................. 53

4-2 CPU-Timers ........................................................................................................................ 54

4-3 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 54

4-4 Multiple PWM Modules in a 2833x System .................................................................................... 56

4-5 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 58

4-6 eCAP Functional Block Diagram ................................................................................................ 59

4-7 eQEP Functional Block Diagram ................................................................................................ 61

4-8 Block Diagram of the ADC Module ............................................................................................. 64

4-9 ADC Pin Connections With Internal Reference ............................................................................... 65

4-10 ADC Pin Connections With External Reference .............................................................................. 65

4-11 McBSP Module ................................................................................................................... 69

4-12 eCAN Block Diagram and Interface Circuit .................................................................................... 72

4-13 eCAN-A Memory Map ............................................................................................................ 73

4-14 eCAN-B Memory Map ............................................................................................................ 74

4-15 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 79

4-16 SPI Module Block Diagram (Slave Mode) ..................................................................................... 82

4-17 I2C Peripheral Module Interfaces ............................................................................................... 84

4-18 GPIO MUX Block Diagram ....................................................................................................... 85

4-19 Qualification Using Sampling Window .......................................................................................... 90

5-1 Example of 2833x Device Nomenclature ...................................................................................... 92

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List of Tables

2-1 Hardware Features ................................................................................................................ 9

2-2 Signal Descriptions ............................................................................................................... 15

3-1 Addresses of Flash Sectors in F28335 ......................................................................................... 29

3-2 Addresses of Flash Sectors in F28334 ......................................................................................... 29

3-3 Addresses of Flash Sectors in F28332 ......................................................................................... 29

3-4 Handling Security Code Locations .............................................................................................. 30

3-5 Wait-states ......................................................................................................................... 31

3-6 Boot Mode Selection .............................................................................................................. 34

3-7 Peripheral Frame 0 Registers ................................................................................................... 39

3-8 Peripheral Frame 1 Registers ................................................................................................... 39

3-9 Peripheral Frame 2 Registers ................................................................................................... 40

3-10 Peripheral Frame 3 Registers ................................................................................................... 40

3-11 Device Emulation Registers ..................................................................................................... 40

3-12 PIE Peripheral Interrupts ......................................................................................................... 43

3-13 PIE Configuration and Control Registers ...................................................................................... 44

3-14 External Interrupt Registers ...................................................................................................... 45

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 47

3-16 PLLCR Register Bit Definitions .................................................................................................. 49

3-17 CLKIN Divide Options ............................................................................................................ 49

3-18 Possible PLL Configuration Modes ............................................................................................. 49

3-19 Low-Power Modes ................................................................................................................ 51

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 55

4-2 ePWM Control and Status Registers ........................................................................................... 57

4-3 eCAP Control and Status Registers ............................................................................................ 60

4-4 eQEP Control and Status Registers ............................................................................................ 62

4-5 ADC Registers ..................................................................................................................... 66

4-6 McBSP Register Summary ...................................................................................................... 70

4-7 3.3-V eCAN Transceivers ....................................................................................................... 72

4-8 CAN Register Map ................................................................................................................ 75

4-9 SCI-A Registers ................................................................................................................... 77

4-10 SCI-B Registers ................................................................................................................... 77

4-11 SCI-C Registers ................................................................................................................... 78

4-12 SPI-A Registers ................................................................................................................... 81

4-13 I2C-A Registers .................................................................................................................... 84

4-14 GPIO Registers ................................................................................................................... 86

4-15 GPIO-A Mux Peripheral Selection Matrix ..................................................................................... 87

4-16 GPIO-B Mux Peripheral Selection Matrix ..................................................................................... 88

4-17 GPIO-C Mux Peripheral Selection Matrix ..................................................................................... 89

List of Tables 5

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1 TMS320F28335, TMS320F28334, TMS320F28332 DSCs

1.1 Features

• High-Performance Static CMOS Technology • Enhanced Control Peripherals

– Up to 150 MHz (6.67-ns Cycle Time) – Up to 18 PWM Outputs – 1.9-V Core, 3.3-V I/O Design – Up to 6 HRPWM Outputs With 150 ps MEP

• High-Performance 32-Bit CPU (TMS320C28x)

– IEEE-754 Single-Precision Floating-Point

Unit (FPU)

– 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC • Serial Port Peripherals – Harvard Bus Architecture – Up to 2 CAN Modules – Fast Interrupt Response and Processing – Up to 3 SCI (UART) Modules – Unified Memory Programming Model – Up to 2 McBSP/SPI Modules – Code-Efficient (in C/C++ and Assembly) – Dedicated SPI Module

• Six Channel DMA Controller (for ADC, McBSP,

XINTF, and SARAM)

• 16-bit or 32-bit External Memory Interface

(XINTF) – 2 x 8 Channel Input Multiplexer

• On-Chip Memory

– F28335: 256K x 16 Flash, 34K x 16 SARAM – F28334:128K x 16 Flash, 34K x 16 SARAM – F28332: 64K x 16 Flash, 26K x 16 SARAM • Up to 88 Individually Programmable, – 1K x 16 OTP ROM

• Boot ROM (8K x 16)

– With Software Boot Modes (via SCI, SPI,

CAN, I2C, McBSP, XINTF, and Parallel I/O)

– Standard Math Tables

• Clock and System Control

– Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• Any GPIO Pin Can Be Connected to One of the

Eight External Core Interrupts Software Libraries

• Peripheral Interrupt Expansion (PIE) Block • Low-Power Modes and Power Savings

That Supports All 58 Peripheral Interrupts

• 128-Bit Security Key/Lock

– Protects Flash/OTP/RAM Blocks – Prevents Firmware Reverse Engineering

• Three 32-Bit CPU Timers

Resolution – Up to 6 Event Capture Inputs – Up to 2 Quadrature Encoder Interfaces – Up to 6 32-bit/Six 16-bit Timers

– One Inter-Integrated-Circuit (I2C) Bus

• 12-Bit ADC, 16 Channels

– 80-ns Conversion Rate

– Two Sample-and-Hold – Single/Simultaneous Conversions – Internal or External Reference

Multiplexed GPIO Pins With Input Filtering

• JTAG Boundary Scan Support

• Advanced Emulation Features

– Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• Development Support Includes

– ANSI C/C++ Compiler/Assembler/Linker – Code Composer Studio™ IDE – DSP/BIOS™ – Digital Motor Control and Digital Power

– IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

• Package Options

– Lead-free Green Packaging – Thin Quad Flatpack (PGF) – MicroStar BGA™ (ZHH)

• Temperature Options:

– A: -40°C to 85°C – S: -40°C to 125°C

SPRS439 – JUNE 2007

(1)

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, C28x, TMS320C2000, TMS320C54x, TMS320C55x are trademarks of Texas Instruments.

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TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following:

• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

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Digital Signal Controllers (DSCs)

2 Introduction

The TMS320F28335, TMS320F28334, and TMS320F28332, devices, members of the TMS320C28x™ DSC generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, TMS320F28335, TMS320F28334, and TMS320F28332, are abbreviated as F28335, F28334, and F28332, respectively. Table 2-1 provides a summary of features for each device.

Table 2-1. Hardware Features

FEATURE F28335 (150 MHz) F28334 (150 MHz) F28332 (100 MHz)

Instruction cycle 6.67 ns 6.67 ns 10 ns Floating-point Unit Yes Yes Yes

3.3-V on-chip flash (16-bit word) 256K 128K 64K Single-access RAM (SARAM) (16-bit word) 34K 34K 26K Code security for on-chip flash/SARAM/OTP blocks Yes Yes Yes Boot ROM (8K X16) Yes Yes Yes One-time programmable (OTP) ROM

(16-bit word) 6-channel Direct Memory Access (DMA) Yes Yes Yes PWM outputs ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6

HRPWM channels ePWM1A/2A/3A/4A 32-bit Capture inputs or auxiliary PWM outputs 6 6 4

32-bit QEP channels (four inputs/channel) 2 2 2 Watchdog timer Yes Yes Yes

No. of channels 16 16 16

12-Bit ADC MSPS 12.5 12.5 12.5

Conversion time 80 ns 80 ns 80 ns 32-Bit CPU timers 3 3 3 Multichannel Buffered Serial Port (McBSP)/SPI 2 2 1 Serial Peripheral Interface (SPI) 1 1 1 Serial Communications Interface (SCI) 3 3 2 Enhanced Controller Area Network (eCAN) 2 2 2 Inter-Integrated Circuit (I2C) 1 1 1 Digital I/O pins (shared) 88 88 88 External interrupts 8 8 8

Packaging

Temperature options A: -40 ° C to 85 ° C (PGF, ZHH) (PGF, ZHH) (PGF, ZHH) Product status TMX TMX TMX

100-Pin PGF Yes Yes Yes

100-Ball ZHH Yes Yes Yes

ePWM1A/2A/3A/4A/5A/ ePWM1A/2A/3A/4A/5A/

1K 1K 1K

6A 6A

SPRS439 – JUNE 2007

2.1 Pin Assignments

The 176-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1 . The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5 . Table 2-2 describes the function(s) of each pin.

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88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

114

113

112

110

109

108

107

106

105

104

103

102

101

100

GPIO48/ECAP5/XD31 TCK EMU1 EMU0 V

DD3VFL

TEST2 TEST1 XRS TMS TRST TDO TDI GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO27/ECAP4/EQEP2S/MFSXB GPIO26/ECAP3/EQEP2I/MCLKXB V

DDIO

GPIO25/ECAP2/EQEP2B/MDRB GPIO24/ECAP1/EQEP2A/MDXB GPIO23/EQEP1I/MFSXA/SCIRXDB GPIO22/EQEP1S/MCLKXA/SCITXDB GPIO21/EQEP1B/MDRA/CANRXB GPIO20/EQEP1A/MDXA/CANTXB GPIO19/ /SCIRXDB/CANTXASPISTEA GPIO18/SPICLKA/SCITXDB/CANRXA V

DD2A18

SS2AGND

ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINB0 V

DDAIO

GPIO75/XD4

GPIO74/XD5

GPIO73/XD6

GPIO72/XD7

GPIO71/XD8

GPIO70/XD9

DDVSS

GPIO69/XD10

GPIO68/XD11

GPIO67/XD12

DDIOVSS

GPIO66/XD13

SSVDD

GPIO65/XD14

GPIO64/XD15

GPIO63/SCITXDC/XD16

GPIO62/SCIRXDC/XD17

GPIO61/MFSRB/XD18

GPIO60/MCLKRB/XD19

GPIO59/MFSRA/XD20

DDVSSVDDIOVSS

XCLKIN

GPIO58/MCLKRA/XD21

GPIO57/ /XD22SPISTEA

GPIO56/SPICLKA/XD23

GPIO55/SPISOMIA/XD24

GPIO54/SPISIMOA/XD25

GPIO53/EQEP1I/XD26

GPIO52/EQEP1S/XD27

DDIOVSS

GPIO51/EQEP1B/XD28

GPIO50/EQEP1A/XD29

GPIO49/ECAP6/XD30

GPIO30/CANRXA/XA18

GPIO29/SCITXDA/XA19

GPIO0/EPWM1A

GPIO1/EPWM1B/ECAP6/MFSRB

GPIO2/EPWM2A

DDIO

GPIO3/EPWM2B/ECAP5/MCLKRB

GPIO4/EPWM3A

GPIO5/EPWM3B/MFSRA/ECAP1

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO7/EPWM4B/MCLKRA/ECAP2

GPIO8/EPWM5A/CANTXB/

ADCSOCAO

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO10/EPWM6A/CANRXB/

ADCSOCBO

GPIO1

1/EPWM6B/SCIRXDB/ECAP4

GPIO12 /CANTXB/MDXB/TZ1

GPIO13/ /CANRXB/MDRBTZ2

GPIO14/ /XHOLD/ /

TZ3 SCITXDBMCLKXB

GPIO15/ /XHOLDATZ4 /SCIRXDB/MFSXB

GPIO16/SPISIMOA/CANTXB/TZ5

GPIO17/SPISOMIA/CANRXB/TZ6

DD1A18

SS1AGND

SSA2

DDA2

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

SSAIO

GPIO76/XD3

GPIO77/XD2

GPIO78/XD1

GPIO79/XD0

GPIO38/XWE0

XCLKOUT

GPIO28/SCIRXDA/XZCS6

GPIO34/ECAP1/XREADY

DDIO

GPIO36/SCIRXDA/XZCS0

GPIO35/SCITXDA/XR/W

XRD

GPIO37/ECAP2/XZCS7

GPIO40/XA0/XWE1

GPIO41/XA1 GPIO42/XA2

GPIO43/XA3 GPIO44/XA4 GPIO45/XA5

DDIO

GPIO46/XA6 GPIO47/XA7 GPIO80/XA8 GPIO81/XA9

GPIO82/XA10

GPIO83/XA11

GPIO84/XA12

DDIO

GPIO85/XA13 GPIO86/XA14 GPIO87/XA15 GPIO39/XA16

GPIO31/CANTXA/XA17

GPIO28/SCIRXDA/XZCS6

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

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Figure 2-1. F28335, F28334, F28332 176-Pin PGF LQFP (Top View)

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ADCINB0 ADCINB2 ADCINB6 ADCREFP

ADCINA1

ADCRESEXTADCINA2

ADCLO

ADCINA0 ADCINB4

SS1AGND

ADCINA4

ADCINA3 ADCINB3

ADCREFIN

P P

N N

M M

L LADCINA5

GPIO18/ SPICLKA/ SCITXDB/

CANRXA

SSA2

ADCINA7 ADCINB7

GPIO17/

SPISOMIA/

CANRXB/

TZ6

DD1A18

GPIO14/

SCITXDB/

MCLKXB

TZ3XHOLD/

GPIO13/

CANRXB/

MDRB

TZ2/

DDAIO

K K

J J

H H

1 2 3 4 5

6 7

GPIO20/

EQEP1A/

MDXA/

CANTXB

SS2AGND

GPIO21/

EQEP1B/

MDRA/

CANRXB

GPIO22/ EQEP1S/ MCLKXA/ SCITXDB

1 2

5 6

SSAIO

GPIO23/ EQEP1I/

MFSXA/

SCIRXDB

GPIO19/

SCIRXDB/

CANTXA

SPISTEA/

ADCINA6

GPIO16/

SPISIMOA/

CANTXB/

TZ5

GPIO15/

SCIRXDB/

MFSXB

TZ4XHOLDA/

DDA2

DD2A18

ADCREFMADCINB5ADCINB1

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 2-2. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View)

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GPIO50/

EQEP1A/

XD29

TMS TEST2

EMU1

GPIO51/

EQEP1B/

XD28

GPIO48/

ECAP5/

XD31

TCK

GPIO52/

EQEP1S/

XD27

GPIO27/

ECAP4/

EQEP2S/

MFSXB

XRS

EMU0

GPIO53/ EQEP1I/

XD26

GPIO55/

SPISOMIA/

XD24

GPIO56/

SPICLKA/

XD23

GPIO58/

MCLKRA/

XD21

GPIO33/

SCLA/

EPWMSYNCO/

ADCSOCBO

TRST

GPIO32/

SDAA/

EPWMSYNCI/

ADCSOCAO

DDIO

8 9

10 11 12 13 14

GPIO57/

XD22

SPISTEA

XCLKIN

GPIO59/ MFSRA/

XD20

GPIO25/

ECAP2/

EQEP2B/

MDRB

8 9 10

11 12

TEST1

DD3VFL

GPIO24/

ECAP1/

EQEP2A/

MDXB

GPIO26/

ECAP3/ EQEP2I/ MCLKXB

TDO

DDIO

GPIO54/

SPISIMOA/

XD25

TDI

DDIO

GPIO49/

ECAP6/

XD30

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 2-3. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)

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GPIO11

EPWM6B

SCIRXDB

ECAP4

/ /

GPIO12

CANTXB

MDXB

TZ1//

GPIO10 EPWM6A CANRXB

ADCSOCBO

/ /

GPIO9/ EPWM5B/ SCITXDB/

ECAP3

GPIO81/

XA9

GPIO8/

EPWM5A/

CANTXB/

ADCSOCAO

GPIO7/

EPWM4B/

MCLKRA/

ECAP2

GPIO84/

XA12

GPIO6/

EPWM4A/

EPWMSYNCI/

EPWMSYNCO

GPIO4/

EPWM3A

GPIO5/

EPWM3B/

MFSRA/

ECAP1

GPIO3/

EPWM2B/

ECAP5/

MCLKRB

DDIO

GPIO2/

EPWM2A

GPIO1/

EPWM1B/

ECAP6/ MFSRB

GPIO86/

XA14

GPIO83/

XA11

GPIO0/

EPWM1A

GPIO29/

SCITXDA/

XA19

GPIO85/

XA13

GPIO82/

XA10

GPIO30/

CANRXA/

XA18

GPIO39/

XA16

GPIO31/

CANTXA/

XA17

GPIO87/

XA15

DDIO

1 2 3 4 5 6 7

GPIO45/

XA5

GPIO80/

XA8

GPIO46/

XA6

GPIO43/

XA3

GPIO44/

XA4

GPIO47/

XA7

1 2 3 4 5

6 7

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 2-4. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View)

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GPIO60/

MCLKRB/

XD19

GPIO64/

XD15

GPIO63/

SCITXDC/

XD16

GPIO61/ MFSRB/

XD18

GPIO67/

XD12

GPIO65/

XD14

GPIO62/

SCIRXDC

XD17

GPIO78/

XD1

GPIO79/

XD0

GPIO66/

XD13

GPIO68/

XD11

GPIO37/

ECAP2/

XZCS7

GPIO34/

ECAP1/

XREADY

GPIO38/

XWE0

GPIO70/

XD9

GPIO40/

XA0/

XWE1

XCLKOUT

GPIO73/

XD6

GPIO42/

XA2

XRD

GPIO28/

SCIRXDA/

XZCS6

GPIO35/

SCITXDA/

XR/W

GPIO69/

XD10

DDIO

8 9 10 11 12 13 14

GPIO74/

XD5

GPIO76/

XD3

GPIO72/

XD7

GPIO75/

XD4

GPIO77/

XD2

GPIO41/

XA1

8 9

10 11 12 13 14

DDIO

GPIO36/

SCIRXDA/

XZCS0

GPIO71/

XD8

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 2-5. F28335, F28334, F28332 179-Ball ZHH MicroStar BGA™ (Lower Right Quadrant) (Bottom View)

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Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

2.2 Signal Descriptions

Table 2-2 describes the signals on the 2833x devices. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-2. Signal Descriptions

PIN NO.

NAME DESCRIPTION

TRST 78 M10

TCK 87 N12 JTAG test clock with internal pullup (I, ↑ ) TMS 79 P10

TDI 76 M9

TDO 77 K9

EMU0 85 L11 drive ↑ )

EMU1 86 P12 drive ↑ )

DD3VFL

TEST1 81 K10 Test Pin. Reserved for TI. Must be left unconnected. (I/O) TEST2 82 P11 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT 138 C11 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal

XCLKIN 105 J14 X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is used to

PGF ZHH

PIN # BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓ )

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑ )

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑ )

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA

FLASH

84 M11 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the feed clock to X1 pin), this pin must be tied to GND. (I)

(1)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

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PIN NO.

NAME DESCRIPTION

X1 104 J13 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

X2 102 J11

XRS 80 L10

ADCINA7 35 K4 ADC Group A, Channel 7 input (I) ADCINA6 36 J5 ADC Group A, Channel 6 input (I) ADCINA5 37 L1 ADC Group A, Channel 5 input (I) ADCINA4 38 L2 ADC Group A, Channel 4 input (I) ADCINA3 39 L3 ADC Group A, Channel 3 input (I) ADCINA2 40 M1 ADC Group A, Channel 2 input (I) ADCINA1 41 N1 ADC Group A, Channel 1 input (I) ADCINA0 42 M3 ADC Group A, Channel 0 input (I) ADCINB7 53 K5 ADC Group B, Channel 7 input (I) ADCINB6 52 P4 ADC Group B, Channel 6 input (I) ADCINB5 51 N4 ADC Group B, Channel 5 input (I) ADCINB4 50 M4 ADC Group B, Channel 4 input (I) ADCINB3 49 L4 ADC Group B, Channel 3 input (I) ADCINB2 48 P3 ADC Group B, Channel 2 input (I) ADCINB1 47 N3 ADC Group B, Channel 1 input (I) ADCINB0 46 P2 ADC Group B, Channel 0 input (I) ADCLO 43 M2 Low Reference (connect to analog ground) (I) ADCRESEXT 57 M5 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground. ADCREFIN 54 L5 External reference input (I)

ADCREFP 56 P5

ADCREFM 55 N5

DDA2

SSA2

DDAIO

SSAIO

DD1A18

SS1AGND

DD2A18

SS2AGND

PGF ZHH

PIN # BALL #

34 K2 ADC Analog Power Pin 33 K3 ADC Analog Ground Pin 45 N2 ADC Analog I/O Power Pin 44 P1 ADC Analog I/O Ground Pin 31 J4 ADC Analog Power Pin 32 K1 ADC Analog Ground Pin 59 M6 ADC Analog Power Pin 58 K6 ADC Analog Ground Pin

Table 2-2. Signal Descriptions (continued)

(1)

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑ ) The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.

ADC SIGNALS

Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 µ F to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 µ F to analog ground. (O)

CPU AND I/O POWER PINS

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

DDIO

PGF ZHH

PIN # BALL #

4 B1 15 B5 23 B11 29 C8 61 D13

101 E9 109 F3 CPU and Logic Digital Power Pins 117 F13 126 H1 139 H12 146 J2 154 K14 167 N6

9 A4 71 B10 93 E7

107 E12 121 F5

Digital I/O Power Pin

143 L8 159 H11 170 N14

3 A5

8 A10 14 A11 22 B4 30 C3 60 C7 70 C9 83 D1 92 D6

103 D14 106 E8 108 E14 118 F4

Digital Ground Pins

120 F12 125 G1 140 H10 144 H13 147 J3 155 J10 160 J12 166 M12 171 N10

N11

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Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

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PIN NO.

NAME DESCRIPTION

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O) ECAP6 Enhanced Capture 6 input/output (I/O) MFSRB McBSP-B receive frame synch (I/O)

GPIO2 General purpose input/output 2 (I/O/Z) EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O) ECAP5 Enhanced Capture 5 input/output (I/O) MCLKRB McBSP-B clock receive (I/O)

GPIO4 General purpose input/output 4 (I/O/Z) EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O) MFSRA McBSP-A receive frame synch (I/O) ECAP1 Enhanced Capture input/output 1 (I/O)

GPIO6 General purpose input/output 6 (I/O/Z) EPWM4A Enhanced PWM4 output A and HRPWM channel (O) EPWMSYNCI External ePWM sync pulse input (I) EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) EPWM4B Enhanced PWM4 output B (O) MCLKRA McBSP-A Clock Receive (I/O) ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General Purpose Input/Output 8 (I/O/Z) EPWM5A Enhanced PWM5 output A (O) CANTXB Enhanced CAN-B transmit (O) ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) EPWM5B Enhanced PWM5 output B (O) SCITXDB SCI-B transmit data(O) ECAP3 Enhanced capture input/output 3 (I/O)

GPIO10 General purpose input/output 10 (I/O/Z) EPWM6A Enhanced PWM6 output A (O) CANRXB Enhanced CAN-B receive (I) ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) EPWM6B Enhanced PWM6 output B (O) SCIRXDB SCI-B receive data (I) ECAP4 Enhanced CAP Input/Output 4 (I/O)

PGF ZHH

PIN # BALL #

5 C1

6 D3

7 D2

10 E4

11 E2

12 E3

13 E1

16 F2

17 F1

18 G5

19 G4

20 G2

Table 2-2. Signal Descriptions (continued)

P8 Digital Ground Pins

GPIOA AND PERIPHERAL SIGNALS

(1)

(2) (3)

(4)

(2) Some peripheral functions may not be available in all devices. See Table 2-1 for details. (3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO12 General purpose input/output 12 (I/O/Z) TZ1 Trip Zone input 1 (I) CANTXB Enhanced CAN-B transmit (O) MDXB McBSP-B transmit serial data (O)

GPIO13 General purpose input/output 13 (I/O/Z) TZ2 Trip Zone input 2 (I) CANRXB Enhanced CAN-B receive (I) MDRB McBSP-B receive serial data (I)

GPIO14 General purpose input/output 14 (I/O/Z)

TZ3/ XHOLD

SCITXDB SCI-B Transmit (I) MCLKXB McBSP-B clock transmit (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

TZ4/ XHOLDA

SCIRXDB SCI-B receive (I) MFSXB McBSP-B transmit frame synch (I/O)

GPIO16 General purpose input/output 16 (I/O/Z) SPISIMOA SPI slave in, master out (I/O) CANTXB Enhanced CAN-B transmit (O) TZ5 Trip Zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O) CANRXB Enhanced CAN-B receive (I) TZ6 Trip zone input 6 (I)

GPIO18 General purpose input/output 18 (I/O/Z) SPICLKA SPI-A clock input/output (I/O) SCITXDB SCI-B transmit (O) CANRXA Enhanced CAN-A receive (I)

GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/O) SCIRXDB SCI-B receive (I) CANTXA Enhanced CAN-A transmit (O)

GPIO20 General purpose input/output 20 (I/O/Z) EQEP1A Enhanced QEP1 input A (I) MDXA McBSP-A transmit serial data (O) CANTXB Enhanced CAN-B transmit (O)

GPIO21 General purpose input/output 21 (I/O/Z) EQEP1B Enhanced QEP1 input B (I) MDRA McBSP-A receive serial data (I) CANRXB Enhanced CAN-B receive (I)

GPIO22 General purpose input/output 22 (I/O/Z) EQEP1S Enhanced QEP1 strobe (I/O) MCLKXA McBSP-A clock transmit (I/O) SCITXDB SCI-B transmit (O)

GPIO23 General purpose input/output 23 (I/O/Z) EQEP1I Enhanced QEP1 index (I/O) MFSXA McBSP-A transmit frame synch (I/O) SCIRXDB SCI-B receive (I)

PGF ZHH

PIN # BALL #

21 G3

24 H3

Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external memory interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance

25 H2 state. The XINTF will release the bus when any current access is complete and there are no

pending accesses on the XINTF. (I)

Trip Zone input 4/External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state.

26 H4 XHOLDA is released when the XHOLD signal is released. External devices should only drive the

external bus when XHOLDA is active (low). (I)

27 H5

28 J1

62 L6

63 K7

64 L7

65 P7

66 N7

67 M7

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

(1)

(5)

(5) The pullups on GPIO12-GPIO34 are enabled upon reset.

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PIN NO.

NAME DESCRIPTION

GPIO24 General purpose input/output 24 (I/O/Z) ECAP1 Enhanced capture 1 (I/O) EQEP2A Enhanced QEP2 input A (I) MDXB McBSP-B transmit serial data (O)

GPIO25 General purpose input/output 25 (I/O/Z) ECAP2 Enhanced capture 2 (I/O) EQEP2B Enhanced QEP2 input B (I) MDRB McBSP-B receive serial data (I)

GPIO26 General purpose input/output 26 (I/O/Z) ECAP3 Enhanced capture 3 (I/O) EQEP2I Enhanced QEP2 index (I/O) MCLKXB McBSP-B clock transmit (O)

GPIO27 General purpose input/output 27 (I/O/Z) ECAP4 Enhanced capture 4 (I/O) EQEP2S Enhanced QEP2 strobe (I/O) MFSXB McBSP-B transmit frame synch (I/O)

GPIO28 General purpose input/output 28 (I/O/Z) SCIRXDA 141 E10 SCI receive data (I) XZCS6 External memory interface zone 6 chip select (O)

GPIO29 General purpose input/output 29. (I/O/Z) SCITXDA 2 C2 SCI transmit data (O) XA19 External Memory Interface Address Line 19 (O)

GPIO30 General purpose input/output 30 (I/O/Z) CANRXA 1 B2 Enhanced CAN-A receive (I) XA18 External Memory Interface Address Line 18 (O)

GPIO31 General purpose input/output 31 (I/O/Z) CANTXA 176 A2 Enhanced CAN-A transmit (O) XA17 External Memory Interface Address Line 17 (O)

GPIO32 General purpose input/output 32 (I/O/Z) SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I) ADCSOCAO ADC start-of-conversion A (O)

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion B (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z) ECAP1 142 D10 Enhanced Capture input/output 1 (I/O) XREADY External memory interface Ready signal

GPIO35 General-Purpose Input/Output 35 (I/O/Z) SCITXDA 148 A9 SCI-A transmit data (O) XR/ W External memory interface read, not write strobe

GPIO36 General-Purpose Input/Output 36 (I/O/Z) SCIRXDA 145 C10 SCI receive data (I) XZCS0 External memory interface zone 0 chip select (O)

GPIO37 General-Purpose Input/Output 37 (I/O/Z) ECAP2 150 D9 Enhanced Capture input/output 2 (I/O) XZCS7 External memory interface zone 7 chip select (O)

GPIO38 General-Purpose Input/Output 38 (I/O/Z)

- 137 D11 XWE0 External memory interface Write Enable 0 (O)

GPIO39 General-Purpose Input/Output 39 (I/O/Z)

- 175 B3 XA016 External Memory Interface Address Line 16 (O)

GPIO40 General-Purpose Input/Output 40 (I/O/Z)

- 151 D8 XA0/ XWE1 External Memory Interface Address Line 0/External memory interface Write Enable 1 (O)

PGF ZHH

PIN # BALL #

68 M8

69 N8

72 K8

73 L9

74 N9

75 P9

Table 2-2. Signal Descriptions (continued)

(1)

(5)

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO41 General-Purpose Input/Output 41 (I/O/Z)

- 152 A8 XA1 External Memory Interface Address Line 1 (O)

GPIO42 General-Purpose Input/Output 42 (I/O/Z)

- 153 B8 XA2 External Memory Interface Address Line 2 (O)

GPIO43 General-Purpose Input/Output 43 (I/O/Z)

- 156 B7 XA3 External Memory Interface Address Line 3 (O)

GPIO44 General-Purpose Input/Output 44 (I/O/Z)

- 157 A7 XA4 External Memory Interface Address Line 4 (O)

GPIO45 General-Purpose Input/Output 45 (I/O/Z)

- 158 D7 XA5 External Memory Interface Address Line 5 (O)

GPIO46 General-Purpose Input/Output 46 (I/O/Z)

- 161 B6 XA6 External Memory Interface Address Line 6 (O)

GPIO47 General-Purpose Input/Output 47 (I/O/Z)

- 162 A6 XA7 External Memory Interface Address Line 7 (O)

GPIO48 General-Purpose Input/Output 48 (I/O/Z) ECAP5 88 P13 Enhanced Capture input/output 5 (I/O) XD31 External Memory Interface Data Line 31 (O)

GPIO49 General-Purpose Input/Output 49 (I/O/Z) ECAP6 89 N13 Enhanced Capture input/output 6 (I/O) XD30 External Memory Interface Data Line 30 (O)

GPIO50 General-Purpose Input/Output 50 (I/O/Z) EQEP1A 90 P14 Enhanced QEP 1input A (I) XD29 External Memory Interface Data Line 29 (O)

GPIO51 General-Purpose Input/Output 51 (I/O/Z) EQEP1B 91 M13 Enhanced QEP 1input B (I) XD28 External Memory Interface Data Line 28 (O)

GPIO52 General-Purpose Input/Output 52 (I/O/Z) EQEP1S 94 M14 Enhanced QEP 1Strobe (I/O) XD27 External Memory Interface Data Line 27 (O)

GPIO53 General-Purpose Input/Output 53 (I/O/Z) EQEP1I 95 L12 Enhanced CAP1 lndex (I/O) XD26 External Memory Interface Data Line 26 (O)

GPIO54 General-Purpose Input/Output 54 (I/O/Z) SPISIMOA 96 L13 SPI-A slave in, master out (I/O) XD25 External Memory Interface Data Line 25 (O)

GPIO55 General-Purpose Input/Output 55 (I/O/Z) SPISOMIA 97 L14 SPI-A slave out, master in (I/O) XD24 External Memory Interface Data Line 24 (O)

GPIO56 General-Purpose Input/Output 56 (I/O/Z) SPICLKA 98 K11 SPI-A clock (I/O) XD23 External Memory Interface Data Line 23 (O)

GPIO57 General-Purpose Input/Output 57 (I/O/Z) SPISTEA 99 K13 SPI-A slave transmit enable (I/O) XD22 External Memory Interface Data Line 22 (O)

GPIO58 General-Purpose Input/Output 58 (I/O/Z) MCLKRA 100 K12 McBSP-A receive clock (I/O) XD21 External Memory Interface Data Line 21 (O)

GPIO59 General-Purpose Input/Output 59 (I/O/Z) MFSRA 110 H14 McBSP-A receive frame synch (I/O) XD20 External Memory Interface Data Line 20 (O)

PGF ZHH

PIN # BALL #

Digital Signal Controllers (DSCs)

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(1)

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PIN NO.

NAME DESCRIPTION

GPIO60 General-Purpose Input/Output 60 (I/O/Z) MCLKRB 111 G14 McBSP-B receive clock (I/O) XD19 External Memory Interface Data Line 19 (O)

GPIO61 General-Purpose Input/Output 61 (I/O/Z) MFSRB 112 G12 McBSP-B receive frame synch (I/O) XD18 External Memory Interface Data Line 18 (O)

GPIO62 General-Purpose Input/Output 62 (I/O/Z) SCIRXDC 113 G13 SCI-C receive data (I) XD17 External Memory Interface Data Line 17 (O)

GPIO63 General-Purpose Input/Output 63 (I/O/Z) SCITXDC 114 G11 SCI-C transmit data (O) XD16 External Memory Interface Data Line 16 (O)

GPIO64 General-Purpose Input/Output 64 (I/O/Z)

- 115 G10 XD15 External Memory Interface Data Line 15 (O)

GPIO65 General-Purpose Input/Output 65 (I/O/Z)

- 116 F14 XD14 External Memory Interface Data Line 14 (O)

GPIO66 General-Purpose Input/Output 66 (I/O/Z)

- 119 F11 XD13 External Memory Interface Data Line 13 (O)

GPIO67 General-Purpose Input/Output 67 (I/O/Z)

- 122 E13 XD12 External Memory Interface Data Line 12 (O)

GPIO68 General-Purpose Input/Output 68 (I/O/Z)

- 123 E11 XD11 External Memory Interface Data Line 11 (O)

GPIO69 General-Purpose Input/Output 69 (I/O/Z)

- 124 F10 XD10 External Memory Interface Data Line 10 (O)

GPIO70 General-Purpose Input/Output 70 (I/O/Z)

- 127 D12 XD9 External Memory Interface Data Line 9 (O)

GPIO71 General-Purpose Input/Output 71 (I/O/Z)

- 128 C14 XD8 External Memory Interface Data Line 8 (O)

GPIO72 General-Purpose Input/Output 72 (I/O/Z)

- 129 B14 XD7 External Memory Interface Data Line 7 (O)

GPIO73 General-Purpose Input/Output 73 (I/O/Z)

- 130 C12 XD6 External Memory Interface Data Line 6 (O)

GPIO74 General-Purpose Input/Output 74 (I/O/Z)

- 131 C13 XD5 External Memory Interface Data Line 5 (O)

GPIO75 General-Purpose Input/Output 75 (I/O/Z)

- 132 A14 XD4 External Memory Interface Data Line 4 (O)

GPIO76 General-Purpose Input/Output 76 (I/O/Z)

- 133 B13 XD3 External Memory Interface Data Line 3 (O)

GPIO77 General-Purpose Input/Output 77 (I/O/Z)

- 134 A13 XD2 External Memory Interface Data Line 2 (O)

GPIO78 General-Purpose Input/Output 78 (I/O/Z)

- 135 B12 XD1 External Memory Interface Data Line 1 (O)

PGF ZHH

PIN # BALL #

Table 2-2. Signal Descriptions (continued)

(1)

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

GPIO79 General-Purpose Input/Output 79 (I/O/Z)

- 136 A12 XD0 External Memory Interface Data Line 0 (O)

GPIO80 General-Purpose Input/Output 80 (I/O/Z)

- 163 C6 XA8 External Memory Interface Address Line 8 (O)

GPIO81 General-Purpose Input/Output 81 (I/O/Z)

- 164 E6 XA9 External Memory Interface Address Line 9 (O)

GPIO82 General-Purpose Input/Output 82 (I/O/Z)

- 165 C5 XA10 External Memory Interface Address Line 10 (O)

GPIO83 General-Purpose Input/Output 83 (I/O/Z)

- 168 D5 XA11 External Memory Interface Address Line 11 (O)

GPIO84

- 169 E5 XA12

GPIO85 General-Purpose Input/Output 85 (I/O/Z)

- 172 C4 XA13 External Memory Interface Address Line 13 (O)

GPIO86 General-Purpose Input/Output 86 (I/O/Z)

- 173 D4 XA14 External Memory Interface Address Line 14 (O)

GPIO87 General-Purpose Input/Output 87 (I/O/Z)

- 174 A3 XA15 External Memory Interface Address Line 15 (O)

XRD 149 B9 External memory interface Read Enable

PGF ZHH

PIN # BALL #

General-Purpose Input/Output 84 (I/O/Z) External Memory Interface Address Line 12 (O)

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

(1)

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PRODUCT PREVIEW

M0SARAM1Kx16

(0-Wait)

M1SARAM1Kx16

(0-Wait)

L0SARAM4Kx16

(0-Wait,DualMap)

L1SARAM4Kx16

(0-Wait,DualMap)

L2SARAM4Kx16

(0-Wait,DualMap)

L3SARAM4Kx16

(0-Wait,DualMap)

L4SARAM4Kx16

(0-WData,1-WProg)

L5SARAM4Kx16

(0-WData,1-WProg)

L6SARAM4Kx16

(0-WData,1-WProg)

L7SARAM4Kx16

(0-WData,1-WProg)

MemoryBus

BootROM

8Kx16

Code

Security

Module

DMA Bus

PSWD

OTP 2Kx16

Flash

256Kx16

8Sectors

Pump

Flash

Wrapper

TEST1

TEST2

XINTF

XA0/XWE1

XWE0

XZCS6

XZCS7

XZCS0

XR/W

XREADY

XHOLD

XHOLDA

XD31:0

XA19:1

GPIO

MUX

MemoryBus

XCLKOUT

XRD

GPIO

MUX

88GPIOs

8ExternalInterrupts

88GPIOs

12-Bit

ADC

2-S/H

A7:0

B7:0

CPUTimer0

CPUTimer1

CPUTimer2

OSC,

PLL,

LPM,

DMA

6Ch

PIE

(Interrupts)

CPU

(150MHZ@1.9V)

EMU1

EMU0

TRST

TDO

TMS

TDI

TCK

XRS

XCLKIN

FPU

REFIN

DMA Bus

MemoryBus

FIFO

(16Levels)

SCI-A/B/C

FIFO

(16Levels)

SPI-A

FIFO

(16Levels)

I2C

16-bitperipheralbus

SPISOMIx

SPISIMOx

SPICLKx

SPISTEx

SCIRXDx

SCITXDx

SDAx

SCLx

McBSP-A/B

MRXx

MDXx

MCLKXx

MCLKRx

MFSXx

MFSRx

32-bitperipheralbus

(DMA accessible)

EPWM-1/../6

HRPWM-1/../6

ECAP-1/../6

EQEP-1/2

EPWMxA

EPWMxB

ESYNCI

ESYNCO

TZxn

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

CAN-A/B

(32-mbox)

CANRXx

CANTXx

32-bitperipheralbus

GPIOMUX

88GPIOs

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

3 Functional Overview

Figure 3-1. Functional Block Diagram

24 Functional Overview Submit Documentation Feedback

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3.1 Memory Maps

In Figure 3-2 through Figure 3-4 , the following apply:

• Memory blocks are not to scale.

• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps

• Protected means the order of Write followed by Read operations is preserved rather than the pipeline

• Certain memory ranges are EALLOW protected against spurious writes after configuration.

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

are restricted to data memory only. A user program cannot access these memory maps in program space.

order.

Submit Documentation Feedback Functional Overview 25

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PRODUCT PREVIEW

Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

PeripheralFrame0

Reserved

L0SARAM(4Kx16,SecureZoneDualMapped)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(4Kx16,SecureZoneDualMapped)

FLASH(256Kx16,SecureZone)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x009000

0x0001-0000

0x300000

0x3FC000

0x3FE000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone6(1Mx16, )XZCS6

Reserved

XINTFVector-RAM(32x32)

(EnableifVMAP =1,ENPIR=0)

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps*M0vector,PIEvector,BROMvector,XINTFvector*shouldbeenabledatatime.

LEGEND:

L2SARAM(4Kx16,SecureZone,DualMapped)

L3SARAM(4Kx16,SecureZone,DualMapped)

L4SARAM(4Kx16,DMA Accessilbe)

L5SARAM(4Kx16,DMA Accessible)

L6SARAM(4Kx16,DMA Accessible)

L7SARAM(4Kx16,DMA Accessiible)

0x0000-A000

0x0000-B000

0x0000-C000

0x0000-D000

0x0000-E000

0x0000-F000

Reserved

0x100000

0x200000

XINTFZone0(4Kx16, )

(Protected,DMA Accessible)

XZCS0

0x004000

0x005000

0x300000

Low64K

(24x/240xEquivalentDataSpace)

High64K

(24x/240xEquivalent

ProgramSpace)

0x005000

XINTFZone7(1Mx16, )XZCS7

PeripheralFrame3(Protected,DMA Accessable)

128-bitPassword0x33FFF8

0x340000

L0SARAM(4Kx16,SecureZoneDualMapped)

OTP (IKx16,SecureZone)

0x3F8000

Reserved

0x380400

L1SARAM(4Kx16,SecureZoneDualMapped)

0x3F9000

L2SARAM(4Kx16,SecureZoneDualMapped)

0x3F A000

L3SARAM(4Kx16,SecureZoneDualMapped)

0x3FB000

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 3-2. F28335 Memory Map

Functional Overview26 Submit Documentation Feedback

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Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

PeripheralFrame0

Reserved

L0SARAM(4Kx16,SecureZoneDualMapped)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(4Kx16,SecureZoneDualMapped)

FLASH(128Kx16,SecureZone)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x009000

0x0001-0000

0x320000

0x3FC000

0x3FE000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone0(4Kx16, )

(Protected,DMA Accessible)

XZCS0

XINTFZone6(1Mx16, )XZCS6

Reserved

XINTFVector-RAM(32x32)

(EnableifVMAP =1,ENPIR=0)

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps*M0vector,PIEvector,BROMvector,XINTFvector*shouldbeenabledatatime.

LEGEND:

L2SARAM(4Kx16,SecureZone,DualMapped)

L3SARAM(4Kx16,SecureZone,DualMapped)

L4SARAM(4Kx16,DMA Accessilbe)

L5SARAM(4Kx16,DMA Accessible)

L6SARAM(4Kx16,DMA Accessible)

L7SARAM(4Kx16,DMA Accessiible)

0x0000-A000

0x0000-B000

0x0000-C000

0x0000-D000

0x0000-E000

0x0000-F000

Reserved

0x004000

0x100000

0x200000

0x005000

0x300000

Low64K

(24x/240xEquivalentDataSpace)

High64K

(24x/240xEquivalent

ProgramSpace)

0x005000

XINTFZone7(1Mx16, )XZCS7

PeripheralFrame3(Protected,DMA Accessable)

128-bitPassword0x33FFF8

0x340000

L0SARAM(4Kx16,SecureZoneDualMapped)

OTP (IKx16,SecureZone)

0x3F8000

Reserved

0x380400

L1SARAM(4Kx16,SecureZoneDualMapped)

0x3F9000

L2SARAM(4Kx16,SecureZoneDualMapped)

0x3F A000

L3SARAM(4Kx16,SecureZoneDualMapped)

0x3FB000

XINTFZone7(16Kx15, )

(EnableifMP/ =1)

XZCS6AND7

PeripheralFrame0

TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Figure 3-3. F28334 Memory Map

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PRODUCT PREVIEW

Block

Start Address

0x000000

M0Vector-RAM(32x32)

(EnableifVMAP =0)

DataSpace

ProgSpace

M0SARAM(1Kx16)

M1SARAM(1Kx16)

PeripheralFrame0

0x000040

0x000400

0x000800

PIEVector-RAM

(256x16)

(Enabledif

VMAP =1, ENPIE=1)

Reserved

L0SARAM(4Kx16,SecureZoneDualMapped)

PeripheralFrame1

(Protected)

Reserved

PeripheralFrame2

(Protected)

L1SARAM(4Kx16,SecureZoneDualMapped)

FLASH(64Kx16,SecureZone)

Reserved

BootROM(8Kx16)

BROMVector-ROM(32x32)

(EnableifVMAP =1,ENPIE=0)

0x000D00

0x000E00

0x002000

0x006000

0x007000

0x008000

0x009000

0x330000

0x3FC000

0x3FE000

0x3FFFC0

DataSpace

ProgSpace

Reserved

XINTFZone0(4Kx16, )

(Protected,DMA Accessible)

XZCS0

XINTFZone6(1Mx16, )XZCS6

Reserved

XINTFVector-RAM(32x32)

(EnableifVMAP =1,ENPIR=0)

On-ChipMemory ExternalMemoryXINTF

Onlyoneofthesevectormaps*M0vector,PIEvector,BROMvector,XINTFvector*shouldbeenabledatatime.

LEGEND:

L2SARAM(4Kx16,SecureZone,DualMapped)

L3SARAM(4Kx16,SecureZone,DualMapped)

L4SARAM(4Kx16,DMA Accessilbe)

L5SARAM(4Kx16,DMA Accessible)

0x0000-A000

0x0000-B000

0x0000-C000

0x0000-D000

0x0000-E000

Reserved

0x004000

0x100000

0x200000

0x005000

0x300000

Low64K

(24x/240xEquivalentDataSpace)

High64K

(24x/240xEquivalent

ProgramSpace)

0x005000

XINTFZone7(1Mx16, )XZCS7

PeripheralFrame3(Protected,DMA Accessable)

128-bitPassword0x33FFF8

0x340000

L0SARAM(4Kx16,SecureZoneDualMapped)

OTP (IKx16,SecureZone)

0x3F8000

Reserved

0x380400

L1SARAM(4Kx16,SecureZoneDualMapped)

0x3F9000

L2SARAM(4Kx16,SecureZoneDualMapped)

0x3F A000

L3SARAM(4Kx16,SecureZoneDualMapped)

0x3FB000

XINTFZone7(16Kx15, )

(EnableifMP/ =1)

XZCS6AND7

PeripheralFrame0

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

Functional Overview28 Submit Documentation Feedback

Figure 3-4. F28332 Memory Map

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TMS320F28335, TMS320F28334, TMS320F28332

Digital Signal Controllers (DSCs)

Table 3-1. Addresses of Flash Sectors in F28335

ADDRESS RANGE PROGRAM AND DATA SPACE

0x30 0000 - 0x30 7FFF Sector H (32K x 16) 0x30 8000 - 0x30 FFFF Sector G (32K x 16) 0x31 0000 - 0x31 7FFF Sector F (32K x 16) 0x31 8000 - 0x31 FFFF Sector E (32K x 16) 0x32 0000 - 0x32 7FFF Sector D (32K x 16) 0x32 8000 - 0x32 FFFF Sector C (32K x 16) 0x33 0000 - 0x33 7FFF Sector B (32K x 16) 0x33 8000 - 0x33 FFFF Sector A (32K x 16)

0x33 FF80 - 0x33 FFF5

0x33 FFF6 - 0x33 FFF7

0x33 FFF8 - 0x33 FFFF

Table 3-2. Addresses of Flash Sectors in F28334

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password

(128-Bit) (Do Not Program to all zeros)

SPRS439 – JUNE 2007

ADDRESS RANGE PROGRAM AND DATA SPACE

0x32 0000 - 0x32 3FFF Sector H (16K x 16) 0x32 4000 - 0x32 7FFF Sector G (16K x 16) 0x32 8000 - 0x32 BFFF Sector F (16K x 16)

0x32 C000 - 0x32 FFFF Sector E (16K x 16)

0x33 0000 - 0x33 3FFF Sector D (16K x 16)

0x33 4000 - 0x33 7FFFF Sector C (16K x 16)

0x33 8000 - 0x33 BFFF Sector B (16K x 16)

0x33 C000 - 0x33 FFFF Sector A (16K x 16)

0x33 FF80 - 0x33 FFF5 Program to 0x0000 when using the

0x33 FFF6 - 0x33 FFF7 Boot-to-Flash Entry Point

0x33 FFF8 - 0x33 FFFF Security Password (128-Bit)

Code Security Module

(program branch instruction here)

(Do Not Program to all zeros)

Table 3-3. Addresses of Flash Sectors in F28332

ADDRESS RANGE PROGRAM AND DATA SPACE

0x33 0000 - 0x33 3FFF Sector D (16K x 16)

0x33 4000 - 0x33 7FFFF Sector C (16K x 16)

0x33 8000 - 0x33 BFFF Sector B (16K x 16)

0x33 C000 - 0x33 FFFF Sector A (16K x 16)

0x33 FF80 - 0x33 FFF5 Program to 0x0000 when using the Code Security

0x33 FFF6 - 0x33 FFF7 Boot-to-Flash Entry Point (program branch

0x33 FFF8 - 0x33 FFFF Security Password (128-Bit) (Do Not Program to all

Module

instruction here)

zeros)

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PRODUCT PREVIEW

TMS320F28335, TMS320F28334, TMS320F28332 Digital Signal Controllers (DSCs)

SPRS439 – JUNE 2007

ADDRESS FLASH

0x33FF80 - 0x33FFEF Application code and data 0x33FFF0 - 0x33FFF5 Reserved for data only

Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

NOTE

• When the code-security passwords are programmed, all addresses between 0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and should not contain program code. .

Table 3-4 shows how to handle these memory locations.

Table 3-4. Handling Security Code Locations

Code security enabled Code security disabled

Fill with 0x0000

The wait-states for the various spaces in the memory map area are listed in Table 3-5 .

30 Functional Overview Submit Documentation Feedback

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TEXAS INSTRUMENTS TMS320F28334 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual