Texas instruments TMS320F2810, TMS320C2810, TMS320F2812, TMS320C2811, TMS320C2812 Data Manual

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

Digital Signal Processors

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS174S

April 2001–Revised March 2011

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Contents

1 TMS320F281x, TMS320C281x DSPs ..................................................................................... 11

1.1 Features .................................................................................................................... 11

1.2 Getting Started ............................................................................................................. 12

2 Introduction ...................................................................................................................... 13

2.1 Description ................................................................................................................. 13

2.2 Device Summary .......................................................................................................... 14

2.3 Pin Assignments ........................................................................................................... 15

2.3.1 Terminal Assignments for the GHH/ZHH Packages ....................................................... 15

2.3.2 Pin Assignments for the PGF Package ...................................................................... 16

2.3.3 Pin Assignments for the PBK Package ...................................................................... 17

2.4 Signal Descriptions ........................................................................................................ 18

3 Functional Overview .......................................................................................................... 27

3.1 Memory Map ............................................................................................................... 28

3.2 Brief Descriptions .......................................................................................................... 33

3.2.1 C28x CPU ....................................................................................................... 33

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 33

3.2.3 Peripheral Bus .................................................................................................. 33

3.2.4 Real-Time JTAG and Analysis ................................................................................ 33

3.2.5 External Interface (XINTF) (2812 Only) ...................................................................... 34

3.2.6 Flash (F281x Only) ............................................................................................. 34

3.2.7 ROM (C281x Only) ............................................................................................. 34

3.2.8 M0, M1 SARAMs ............................................................................................... 34

3.2.9 L0, L1, H0 SARAMs ............................................................................................ 35

3.2.10 Boot ROM ....................................................................................................... 35

3.2.11 Security .......................................................................................................... 35

3.2.12 Peripheral Interrupt Expansion (PIE) Block ................................................................. 36

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................ 36

3.2.14 Oscillator and PLL .............................................................................................. 37

3.2.15 Watchdog ........................................................................................................ 37

3.2.16 Peripheral Clocking ............................................................................................. 37

3.2.17 Low-Power Modes .............................................................................................. 37

3.2.18 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 37

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 38

3.2.20 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 38

3.2.21 Control Peripherals ............................................................................................. 38

3.2.22 Serial Port Peripherals ......................................................................................... 38

3.3 Register Map ............................................................................................................... 39

3.4 Device Emulation Registers .............................................................................................. 41

3.5 External Interface, XINTF (2812 Only) ................................................................................. 42

3.5.1 Timing Registers ................................................................................................ 43

3.5.2 XREVISION Register ........................................................................................... 43

3.6 Interrupts .................................................................................................................... 44

3.6.1 External Interrupts .............................................................................................. 47

3.7 System Control ............................................................................................................ 48

3.8 OSC and PLL Block ....................................................................................................... 50

2 Contents Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3.8.1 Loss of Input Clock ............................................................................................. 51

3.9 PLL-Based Clock Module ................................................................................................ 52

3.10 External Reference Oscillator Clock Option ........................................................................... 52

3.11 Watchdog Block ........................................................................................................... 53

3.12 Low-Power Modes Block ................................................................................................. 54

SPRS174S–APRIL 2001–REVISED MARCH 2011

4 Peripherals ....................................................................................................................... 55

4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 55

4.2 Event Manager Modules (EVA, EVB) ................................................................................... 58

4.2.1 General-Purpose (GP) Timers ................................................................................ 61

4.2.2 Full-Compare Units ............................................................................................. 61

4.2.3 Programmable Deadband Generator ........................................................................ 61

4.2.4 PWM Waveform Generation .................................................................................. 61

4.2.5 Double Update PWM Mode ................................................................................... 61

4.2.6 PWM Characteristics ........................................................................................... 62

4.2.7 Capture Unit ..................................................................................................... 62

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 62

4.2.9 External ADC Start-of-Conversion ........................................................................... 62

4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 63

4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 68

4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 73

4.6 Serial Communications Interface (SCI) Module ....................................................................... 77

4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 80

4.8 GPIO MUX ................................................................................................................. 83

5 Development Support ........................................................................................................ 86

5.1 Device and Development Support Tool Nomenclature ............................................................... 86

5.2 Documentation Support ................................................................................................... 87

5.3 Community Resources .................................................................................................... 89

6 Electrical Specifications ..................................................................................................... 90

6.1 Absolute Maximum Ratings .............................................................................................. 90

6.2 Recommended Operating Conditions .................................................................................. 90

6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) .............. 91

6.4 Current Consumption ..................................................................................................... 92

6.5 Current Consumption Graphs ............................................................................................ 94

6.6 Reducing Current Consumption ......................................................................................... 96

6.7 Emulator Connection Without Signal Buffering for the DSP ......................................................... 96

6.8 Power Sequencing Requirements ....................................................................................... 97

6.9 Signal Transition Levels .................................................................................................. 99

6.10 Timing Parameter Symbology .......................................................................................... 100

6.11 General Notes on Timing Parameters ................................................................................. 100

6.12 Test Load Circuit ......................................................................................................... 100

6.13 Device Clock Table ...................................................................................................... 101

6.14 Clock Requirements and Characteristics ............................................................................. 102

6.14.1 Input Clock Requirements ................................................................................... 102

6.14.2 Output Clock Characteristics ................................................................................ 103

6.15 Reset Timing .............................................................................................................. 103

6.16 Low-Power Mode Wakeup Timing ..................................................................................... 107

Copyright © 2001–2011, Texas Instruments Incorporated Contents 3

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.17 Event Manager Interface ................................................................................................ 111

6.17.1 PWM Timing ................................................................................................... 111

6.17.2 Interrupt Timing ................................................................................................ 113

6.18 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 114

6.19 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 115

6.20 Serial Peripheral Interface (SPI) Master Mode Timing .............................................................. 116

6.21 Serial Peripheral Interface (SPI) Slave Mode Timing ............................................................... 121

6.22 External Interface (XINTF) Timing ..................................................................................... 125

6.23 XINTF Signal Alignment to XCLKOUT ................................................................................ 129

6.24 External Interface Read Timing ........................................................................................ 130

6.25 External Interface Write Timing ........................................................................................ 132

6.26 External Interface Ready-on-Read Timing With One External Wait State ....................................... 133

6.27 External Interface Ready-on-Write Timing With One External Wait State ........................................ 136

6.28 XHOLD and XHOLDA ................................................................................................... 139

6.29 XHOLD/XHOLDA Timing ............................................................................................... 140

6.30 On-Chip Analog-to-Digital Converter .................................................................................. 142

6.30.1 ADC Absolute Maximum Ratings ........................................................................... 142

6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 143

6.30.3 Current Consumption for Different ADC Configurations ................................................. 144

6.30.4 ADC Power-Up Control Bit Timing .......................................................................... 145

6.30.5 Detailed Description .......................................................................................... 145

6.30.5.1 Reference Voltage ................................................................................ 145

6.30.5.2 Analog Inputs ..................................................................................... 145

6.30.5.3 Converter .......................................................................................... 145

6.30.5.4 Conversion Modes ............................................................................... 145

6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 146

6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 147

6.30.8 Definitions of Specifications and Terminology ............................................................. 148

6.31 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 149

6.31.1 McBSP Transmit and Receive Timing ...................................................................... 149

6.31.2 McBSP as SPI Master or Slave Timing .................................................................... 152

6.32 Flash Timing (F281x Only) ............................................................................................. 156

6.33 ROM Timing (C281x only) .............................................................................................. 158

6.34 Migrating From F281x Devices to C281x Devices .................................................................. 159

www.ti.com

7 Revision History .............................................................................................................. 160

8 Mechanical Data .............................................................................................................. 161

4 Contents Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

List of Figures

2-1 TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)............................. 15

2-2 TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) ..................................................... 16

2-3 TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View).............. 17

3-1 Functional Block Diagram....................................................................................................... 28

3-2 F2812/C2812 Memory Map..................................................................................................... 29

3-3 F2811/C2811 Memory Map..................................................................................................... 30

3-4 F2810/C2810 Memory Map..................................................................................................... 30

3-5 External Interface Block Diagram .............................................................................................. 42

3-6 Interrupt Sources ................................................................................................................. 44

3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 45

3-8 Clock and Reset Domains ...................................................................................................... 48

3-9 OSC and PLL Block.............................................................................................................. 50

3-10 Recommended Crystal/Clock Connection .................................................................................... 52

3-11 Watchdog Module................................................................................................................ 53

4-1 CPU-Timers....................................................................................................................... 55

4-2 CPU-Timer Interrupts Signals and Output Signal............................................................................ 56

4-3 Event Manager A Functional Block Diagram ................................................................................. 61

4-4 Block Diagram of the F281x and C281x ADC Module ...................................................................... 64

4-5 ADC Pin Connections With Internal Reference .............................................................................. 65

4-6 ADC Pin Connections With External Reference ............................................................................. 66

4-7 eCAN Block Diagram and Interface Circuit................................................................................... 69

4-8 eCAN Memory Map .............................................................................................................. 71

4-9 McBSP Module With FIFO...................................................................................................... 74

4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 79

4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 82

4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 85

5-1 TMS320x281x Device Nomenclature.......................................................................................... 87

6-1 F2812/F2811/F2810 Typical Current Consumption Over Frequency ..................................................... 94

6-2 F2812/F2811/F2810 Typical Power Consumption Over Frequency....................................................... 95

6-3 C2812/C2811/C2810 Typical Current Consumption Over Frequency .................................................... 95

6-4 C2812/C2811/C2810 Typical Power Consumption Over Frequency...................................................... 96

6-5 Emulator Connection Without Signal Buffering for the DSP................................................................ 97

6-6 F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2 ....................................... 98

6-7 Output Levels ..................................................................................................................... 99

6-8 Input Levels ....................................................................................................................... 99

6-9 3.3-V Test Load Circuit......................................................................................................... 100

6-10 Clock Timing..................................................................................................................... 103

6-11 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)................................................. 105

6-12 Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................. 106

6-13 Warm Reset in Microcomputer Mode ........................................................................................ 106

6-14 Effect of Writing Into PLLCR Register ....................................................................................... 106

6-15 IDLE Entry and Exit Timing.................................................................................................... 107

6-16 STANDBY Entry and Exit Timing............................................................................................. 109

6-17 HALT Wakeup Using XNMI ................................................................................................... 110

6-18 PWM Output Timing............................................................................................................ 111

6-19 TDIRx Timing.................................................................................................................... 112

6-20 EVASOC Timing................................................................................................................ 112

Copyright © 2001–2011, Texas Instruments Incorporated List of Figures 5

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6-21 EVBSOC Timing................................................................................................................ 112

6-22 External Interrupt Timing....................................................................................................... 113

6-23 General-Purpose Output Timing.............................................................................................. 114

6-24 GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 115

6-25 General-Purpose Input Timing................................................................................................ 116

6-26 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 118

6-27 SPI Master External Timing (Clock Phase = 1)............................................................................. 120

6-28 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 122

6-29 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 124

6-30 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 128

6-31 Example Read Access......................................................................................................... 131

6-32 Example Write Access......................................................................................................... 132

6-33 Example Read With Synchronous XREADY Access ...................................................................... 134

6-34 Example Read With Asynchronous XREADY Access..................................................................... 135

6-35 Write With Synchronous XREADY Access.................................................................................. 137

6-36 Write With Asynchronous XREADY Access ................................................................................ 138

6-37 External Interface Hold Waveform............................................................................................ 140

6-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 141

6-39 ADC Analog Input Impedance Model ........................................................................................ 145

6-40 ADC Power-Up Control Bit Timing ........................................................................................... 145

6-41 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 146

6-42 Simultaneous Sampling Mode Timing ....................................................................................... 147

6-43 McBSP Receive Timing........................................................................................................ 151

6-44 McBSP Transmit Timing....................................................................................................... 151

6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 152

6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 153

6-47 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 154

6-48 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 155

www.ti.com

6 List of Figures Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

List of Tables

2-1 Hardware Features............................................................................................................... 14

2-2 Signal Descriptions............................................................................................................... 18

3-1 Addresses of Flash Sectors in F2812 and F2811 ........................................................................... 31

3-2 Addresses of Flash Sectors in F2810 ......................................................................................... 31

3-3 Wait States ........................................................................................................................ 32

3-4 Boot Mode Selection............................................................................................................. 35

3-5 Impact of Using the Code Security Module................................................................................... 36

3-6 Peripheral Frame 0 Registers .................................................................................................. 39

3-7 Peripheral Frame 1 Registers .................................................................................................. 39

3-8 Peripheral Frame 2 Registers .................................................................................................. 40

3-9 Device Emulation Registers..................................................................................................... 41

3-10 XINTF Configuration and Control Register Mappings....................................................................... 43

3-11 XREVISION Register Bit Definitions........................................................................................... 43

3-12 PIE Peripheral Interrupts........................................................................................................ 45

3-13 PIE Configuration and Control Registers...................................................................................... 46

3-14 External Interrupts Registers ................................................................................................... 47

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 49

3-16 PLLCR Register Bit Definitions................................................................................................. 51

3-17 Possible PLL Configuration Modes ............................................................................................ 52

3-18 F281x and C281x Low-Power Modes ......................................................................................... 54

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 57

4-2 Module and Signal Names for EVA and EVB ................................................................................ 58

4-3 EVA Registers .................................................................................................................... 59

4-4 ADC Registers.................................................................................................................... 67

4-5 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs ............................................ 70

4-6 CAN Registers.................................................................................................................... 72

4-7 McBSP Registers................................................................................................................. 75

4-8 SCI-A Registers .................................................................................................................. 78

4-9 SCI-B Registers .................................................................................................................. 78

4-10 SPI Registers ..................................................................................................................... 81

4-11 GPIO Mux Registers............................................................................................................. 83

4-12 GPIO Data Registers ............................................................................................................ 84

5-1 TMS320x281x Peripheral Selection Guide ................................................................................... 87

6-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 92

6-2 TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 93

6-3 Typical Current Consumption by Various Peripherals (at 150 MHz) ...................................................... 96

6-4 Recommended “Low-Dropout Regulators”.................................................................................... 97

6-5 TMS320F281x and TMS320C281x Clock Table and Nomenclature .................................................... 101

6-6 Input Clock Frequency ......................................................................................................... 102

6-7 XCLKIN Timing Requirements – PLL Bypassed or Enabled ............................................................. 102

6-8 XCLKIN Timing Requirements – PLL Disabled ............................................................................ 102

6-9 Possible PLL Configuration Modes........................................................................................... 102

6-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 103

6-11 Reset (XRS) Timing Requirements .......................................................................................... 103

6-12 IDLE Mode Timing Requirements ........................................................................................... 107

Copyright © 2001–2011, Texas Instruments Incorporated List of Tables 7

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6-13 IDLE Mode Switching Characteristics ....................................................................................... 107

6-14 STANDBY Mode Timing Requirements ..................................................................................... 108

6-15 STANDBY Mode Switching Characteristics ................................................................................ 108

6-16 HALT Mode Timing Requirements ........................................................................................... 110

6-17 HALT Mode Switching Characteristics ...................................................................................... 110

6-18 PWM Switching Characteristics .............................................................................................. 111

6-19 Timer and Capture Unit Timing Requirements ............................................................................. 111

6-20 External ADC Start-of-Conversion – EVA – Switching Characteristics ................................................. 112

6-21 External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 112

6-22 Interrupt Switching Characteristics .......................................................................................... 113

6-23 Interrupt Timing Requirements ............................................................................................... 113

6-24 General-Purpose Output Switching Characteristics ....................................................................... 114

6-25 General-Purpose Input Timing Requirements .............................................................................. 116

6-26 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 117

6-27 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 119

6-28 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 121

6-29 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 123

6-30 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 125

6-31 XINTF Clock Configurations................................................................................................... 128

6-32 External Memory Interface Read Switching Characteristics ............................................................. 130

6-33 External Memory Interface Read Timing Requirements .................................................................. 130

6-34 External Memory Interface Write Switching Characteristics .............................................................. 132

6-35 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 133

6-36 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 133

6-37 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 133

6-38 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 133

6-39 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 136

6-40 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 136

6-41 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 136

6-42 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 140

6-43 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 141

6-44 DC Specifications .............................................................................................................. 143

6-45 AC Specifications............................................................................................................... 144

6-46 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ........................................ 144

6-47 ADC Power-Up Delays......................................................................................................... 145

6-48 Sequential Sampling Mode Timing ........................................................................................... 146

6-49 Simultaneous Sampling Mode Timing ....................................................................................... 147

6-50 McBSP Timing Requirements ................................................................................................ 149

6-51 McBSP Switching Characteristics ........................................................................................... 150

6-52 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 152

6-53 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 152

6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 153

6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 153

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 154

6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 154

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 155

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 155

6-60 Flash Endurance for A and S Temperature Material....................................................................... 156

www.ti.com

8 List of Tables Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

6-61 Flash Endurance for Q Temperature Material .............................................................................. 156

6-62 Flash Parameters at 150-MHz SYSCLKOUT............................................................................... 156

6-63 Flash/OTP Access Timing..................................................................................................... 157

6-64 Minimum Required Flash Wait States at Different Frequencies (F281x devices)...................................... 157

6-65 ROM Access Timing............................................................................................................ 158

6-66 Minimum Required ROM Wait States at Different Frequencies (C281x devices)...................................... 158

8-1 Thermal Resistance Characteristics for 179-Ball GHH.................................................................... 161

8-2 Thermal Resistance Characteristics for 179-Ball ZHH..................................................................... 161

8-3 Thermal Resistance Characteristics for 176-Pin PGF ..................................................................... 161

8-4 Thermal Resistance Characteristics for 128-Pin PBK ..................................................................... 161

SPRS174S–APRIL 2001–REVISED MARCH 2011

Copyright © 2001–2011, Texas Instruments Incorporated List of Tables 9

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

10 List of Tables Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Digital Signal Processors

Check for Samples: TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812

1 TMS320F281x, TMS320C281x DSPs

1.1 Features

1234

• High-Performance Static CMOS Technology • Clock and System Control

– 150 MHz (6.67-ns Cycle Time) – Dynamic PLL Ratio Changes Supported
– Low-Power (1.8-V Core @135 MHz, – On-Chip Oscillator

1.9-V Core @150 MHz, 3.3-V I/O) Design

• JTAG Boundary Scan Support

(1)

• High-Performance 32-Bit CPU ( TMS320C28x™)

– 16 x 16 and 32 x 32 MAC Operations Supports 45 Peripheral Interrupts
– 16 x 16 Dual MAC • Three 32-Bit CPU-Timers
– Harvard Bus Architecture • 128-Bit Security Key/Lock
– Atomic Operations – Protects Flash/ROM/OTP and L0/L1 SARAM
– Fast Interrupt Response and Processing – Prevents Firmware Reverse-Engineering
– Unified Memory Programming Model • Motor Control Peripherals
– 4M Linear Program/Data Address Reach – Two Event Managers (EVA, EVB)
– Code-Efficient (in C/C++ and Assembly) – Compatible to 240xA Devices
– TMS320F24x/LF240x Processor Source Code • Serial Port Peripherals

Compatible

• On-Chip Memory

– Flash Devices: Up to 128K x 16 Flash (SCIs), Standard UART

(Four 8K x 16 and Six 16K x 16 Sectors)
– ROM Devices: Up to 128K x 16 ROM
– 1K x 16 OTP ROM
– L0 and L1: 2 Blocks of 4K x 16 Each

Single-Access RAM (SARAM)
– H0: 1 Block of 8K x 16 SARAM
– M0 and M1: 2 Blocks of 1K x 16 Each

SARAM

• Boot ROM (4K x 16)
– With Software Boot Modes
– Standard Math Tables

• External Interface (2812)
– Over 1M x 16 Total Memory
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Three Individual Chip Selects

– Watchdog Timer Module

• Three External Interrupts

• Peripheral Interrupt Expansion (PIE) Block That

– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces

– Enhanced Controller Area Network (eCAN)
– Multichannel Buffered Serial Port (McBSP)

• 12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Fast Conversion Rate: 80 ns/12.5 MSPS

• Up to 56 General-Purpose I/O (GPIO) Pins

• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware

• Development Tools Include
– ANSI C/C++ Compiler/Assembler/Linker
– Code Composer Studio™ IDE
– DSP/BIOS™
– JTAG Scan Controllers

(1)

• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks

(1) IEEE Standard 1149.1-1990 IEEE Standard Test Access Port

and Boundary-Scan Architecture

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MicroStar BGA, TMS320C28x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TI, TMS320C54x, TMS320C55x, TMS320 are

trademarks of Texas Instruments.

3eZdsp is a trademark of Spectrum Digital Incorporated.
4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2001–2011, Texas Instruments Incorporated

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

• Package Options • Temperature Options
– 179-Ball MicroStar BGA™ With External – A: –40°C to 85°C (GHH, ZHH, PGF, PBK)

Memory Interface (GHH, ZHH) (2812)

– 176-Pin Low-Profile Quad Flatpack (LQFP)

With External Memory Interface (PGF) (2812)

– S: –40°C to 125°C (GHH, ZHH, PGF, PBK)
– Q: –40°C to 125°C (PGF, PBK)

[Q100 Qualification]

– 128-Pin LQFP Without External Memory

Interface (PBK) (2810, 2811)

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x™ device. For
more detail on each of these steps, see the following:

• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0)

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

• TMS320F28x DSC Development and Experimenter’s Kits (http://www.ti.com/f28xkits)

www.ti.com

12 TMS320F281x, TMS320C281x DSPs Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

2 Introduction

This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.

2.1 Description

The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812
devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance
solutions for demanding control applications. The functional blocks and the memory maps are described in

Section 3, Functional Overview.

Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810,
F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811,
and TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three
ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811
devices; and 2812 denotes both F2812 and C2812 devices.

SPRS174S–APRIL 2001–REVISED MARCH 2011

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 13

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

2.2 Device Summary

Table 2-1 provides a summary of each device’s features.

Table 2-1. Hardware Features

FEATURE TYPE

Instruction Cycle (at 150 MHz) – 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns
Single-Access RAM (SARAM) (16-bit word) – 18K 18K 18K 18K 18K 18K

3.3-V On-Chip Flash (16-bit word) – 64K 128K 128K – – –
On-Chip ROM (16-bit word) – – – – 64K 128K 128K
Code Security for On-Chip

Flash/SARAM/OTP/ROM
Boot ROM – Yes Yes Yes Yes Yes Yes
OTP ROM (1K x 16) – Yes Yes Yes Yes
External Memory Interface 0 – – Yes – – Yes

Event Managers A and B (EVA and EVB) –

● General-Purpose (GP) Timers – 4 4 4 4 4 4

● Compare (CMP)/PWM 0 16 16 16 16 16 16

● Capture (CAP)/QEP Channels 0 6/2 6/2 6/2 6/2 6/2 6/2

Watchdog Timer – Yes Yes Yes Yes Yes Yes
12-Bit ADC Yes Yes Yes Yes Yes Yes

● Channels 16 16 16 16 16 16
32-Bit CPU Timers – 3 3 3 3 3 3
Serial Peripheral Interface (SPI) 0 Yes Yes Yes Yes Yes Yes
Serial Communications Interfaces A and B SCIA, SCIA, SCIA, SCIA, SCIA, SCIA,

(SCIA and SCIB) SCIB SCIB SCIB SCIB SCIB SCIB
Controller Area Network (CAN) 0 Yes Yes Yes Yes Yes Yes
Multichannel Buffered Serial Port (McBSP) 0 Yes Yes Yes Yes Yes Yes
Digital I/O Pins (Shared) – 56 56 56 56 56 56
External Interrupts – 3 3 3 3 3 3
Supply Voltage – 1.8-V Core (135 MHz), 1.9-V Core (150 MHz), 3.3-V I/O

128-pin PBK Yes Yes – Yes Yes –

Packaging –

Temperature Options

Product Status

(1) The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature

number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed.

(2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the

TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.
(3) On C281x devices, OTP is replaced by a 1K x 16 block of ROM.
(4) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

(4)

176-pin PGF – – Yes – – Yes
179-ball GHH – – Yes – – Yes
179-ball ZHH – – Yes – – Yes
A: –40°C to 85°C – Yes Yes Yes Yes Yes Yes
S: –40°C to 125°C – Yes Yes Yes Yes Yes Yes
Q: –40°C to 125°C

(Q100 Qualification)

(2)

F2810 F2811 F2812 C2810 C2811 C2812

– Yes Yes Yes Yes Yes Yes

EVA, EVA, EVA, EVA, EVA, EVA,

EVB EVB EVB EVB EVB EVB

0

0

– Yes Yes PGF only Yes Yes PGF only
– TMS TMS TMS TMS TMS TMS

(1)

(3)

Yes

(3)

Yes

(3)

14 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

1412 1310 118 95 63 41 2 7

XA[14]

V

SSAIO

ADCINA0 ADCINA4

V

DDA2VDD1

SCIRXDA

XA[16] XD[15]

TESTSEL

XA[11]

ADCINB2

V

DDAIO

ADCLO ADCINA3 ADCINA7 XREADY

XA[17] XA[15] XD[14]

TRST

XZCS6AND7

ADCINB3 ADCINB0 ADCINB1 ADCINA2

V

SS1

SCITXDA

EMU1

XA[12] XA[10]

TDI

ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6

XRS

XA[18]

EMU0

TDO

TMS

XA[9]

P

M

L

J

H

K

N

G

E

F

D

C

A

B

ADC­REFP

XINT2_

ADCSOC

AVDDREFBG

AVSSREFBG

ADC-

REFM

ADCINA5

ADC-

BGREFIN

XHOLD

XNMI_

XINT13

XA[13]

C2TRIP

XA[8]

C1TRIP

ADC-

RESEXT

V

SSA1

V

SSA2

V

DDA1

ADCINB7

C3TRIP

XCLKOUT

XA[7]

TCLKINA TDIRA

MDXA MDRA

XD[0] XA[0] XA[6]

MCLKRA

XD[1]

MFSXA

XD[2]

CAP1_

QEP1

CAP2_

QEP2

CAP3_

QEPI1

XA[5]

T1CTRIP_

PDPINTA

MCLKXA

MFSRA

XD[3]

XD[5]

XD[13]

T1PWM_

T1CMP

XA[4]

T2PWM_

T2CMP

SPICLKA

XD[4]

SPISTEA

T3PWM_

T3CMP

C6TRIP

TCLKINB

X1/

XCLKIN

XHOLDA

PWM5

PWM6

XD[6]

PWM11

XD[7]

C5TRIP

TDIRB

XD[10]

PWM3

PWM4

XD[12]

SPISIMOA

XA[1]

XRD

PWM12

CAP4_

QEP3

CAP5_

QEP4

TEST1

XD[9]

X2

XA[3]

PWM1

SCIRXDB

PWM2

SPISOMIA

PWM9

T4PWM_

T4CMP

C4TRIP

V

DD3VFL

XD[11] XA[2]

XWE

CANTXA CANRXA

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

XZCS0AND1

PWM10

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

CAP6_

QEPI2

XD[8]

T3CTRIP_

PDPINTB

T4CTRIP/
EVBSOC

XINT1_

XBIO

XF_

XPLLDIS

XMP/MC

T2CTRIP/

EVASOC

XR/W

XZCS2

SCITXDB

TCK

PWM7

TEST2

PWM8

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.3 Pin Assignments

Figure 2-1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2-2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and
Figure 2-3 shows the pin assignments for the 128-pin PBK LQFP. Table 2-2 describes the function(s) of

each pin.

2.3.1 Terminal Assignments for the GHH/ZHH Packages

See Table 2-2 for a description of each terminal’s function(s).

Figure 2-1. TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 15

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

1

2

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

ADCRESEXT

XA[0]

XA[1]

XD[0]

XD[1]

XD[2]

XD[3]

XD[4]

XD[6]

SPISIMOA

SPISOMIA

XRD

XZCS0AND1

C3TRIP

C2TRIP

C1TRIP

XD[5]

SPICLKA

SPISTEA

MDRA

MDXA

MCLKRA

MCLKXA

MFSXA

MFSRA

AV

DDREFBG

AV

SSREFBG

V

DDIO

V

DDIO

V

DDA1

V

SSA1

V

DDAIO

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

133

176

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

XR/W

T3PWM_T3CMP

XD[7]

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

XD[8]

TEST2

TEST1

XD[9]

V

DD3VFL

TDIRB

TCLKINB

XD[10]

XD[11]

X2

X1/XCLKIN

T3CTRIP_PDPINTB

XA[2]

V

DDIO

V

DDIO

XHOLDA

T4CTRIPEVBSOC/

XWE

XA[3]

CANTXA

XZCS2

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175

88

45

132 89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

XA[11]

XA[10]

XA[9]

XA[8]

XA[7]

XA[6]

XD[13]

XD[12]

XA[5]

XA[4]

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

CAP3_QEPI1

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

T1PWM_T1CMP

XCLKOUT

TCLKINA

TDIR

TDI

TDO

TMS

44

XZCS6AND7

TESTSEL

TRST

TCK

EMU0
XA[12]
XD[14]

XA[13]

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

XA[14]

V

DDIO

EMU1
XD[15]
XA[15]

XNMI_XINT13

XINT2_ADCSOC

XA[16]

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

V

DD1

V

SS1

ADCBGREFIN

V

SSA2

V

DDA2

ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2

ADCINA1

ADCINA0

ADCLO

V

SSAIO

XF_XPLLDIS

XMP/MC

T1CTRIP_PDPINTA

T2CTRIP/EVASOC

XINT1_XBIO

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.3.2 Pin Assignments for the PGF Package

The TMS320F2812 and TMS320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments
are shown in Figure 2-2. See Table 2-2 for a description of each pin’s function(s).

www.ti.com

Figure 2-2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)

16 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

1

2

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

ADCRESEXT

MDRA

MDXA

MCLKRA

MCLKXA

MFSXA

MFSRA

SPICLKA

SPISTEA

SPISIMOA

SPISOMIA

AVSSREFBG

AVDDREFBG

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

TDI

TDO

TMS

XCLKOUT

TCLKINA

TDIRA

CAP3_QEPI1

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

T1PWM_T1CMP

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

T1CTRIP_PDPINTA

T2CTRIPEVASOC/

C3TRIP

C2TRIP

C1TRIP

97

96 65

32

128

64

33

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

T3PWM_T3CMP

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

TEST2

TEST1

V

DD3VFL

TDIRB

TCLKINB

X2

X1/XCLKIN

T3CTRIP_PDPINTB

CANTXA

34

35

36

37

38

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

39

63

T4CTRIPEVBSOC/

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

122

98

TESTSEL

TRST

TCK

EMU0

XF_XPLLDIS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDIO

V

DDIO

V

DDIO

V

DDIO

EMU1

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

SCITXDA
SCIRXDA

XRS
V

DD1

V

SS1

ADCBGREFIN

V

SSA2

V

SSA1

V

DDA1

V

DDA2

ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2

ADCINA1

ADCINA0

ADCLO

V

SSAIO

V

DDAIO

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

2.3.3 Pin Assignments for the PBK Package

The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad
flatpack (LQFP) pin assignments are shown in Figure 2-3. See Table 2-2 for a description of each pin’s
function(s).

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 2-3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View)

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 17

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.4 Signal Descriptions

Table 2-2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All

outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is
used.

PU/PD

(1)

(3)

16-bit XINTF Data Bus

DESCRIPTION

Table 2-2. Signal Descriptions

PIN NO.

NAME I/O/Z

XA[18] D7 158 – O/Z –
XA[17] B7 156 – O/Z –
XA[16] A8 152 – O/Z –
XA[15] B9 148 – O/Z –
XA[14] A10 144 – O/Z –
XA[13] E10 141 – O/Z –
XA[12] C11 138 – O/Z –
XA[11] A14 132 – O/Z –
XA[10] C12 130 – O/Z –
XA[9] D14 125 – O/Z – 19-bit XINTF Address Bus
XA[8] E12 121 – O/Z –
XA[7] F12 118 – O/Z –
XA[6] G14 111 – O/Z –
XA[5] H13 108 – O/Z –
XA[4] J12 103 – O/Z –
XA[3] M11 85 – O/Z –
XA[2] N10 80 – O/Z –
XA[1] M2 43 – O/Z –
XA[0] G5 18 – O/Z –
XD[15] A9 147 – I/O/Z PU
XD[14] B11 139 – I/O/Z PU
XD[13] J10 97 – I/O/Z PU
XD[12] L14 96 – I/O/Z PU
XD[11] N9 74 – I/O/Z PU
XD[10] L9 73 – I/O/Z PU
XD[9] M8 68 – I/O/Z PU
XD[8] P7 65 – I/O/Z PU
XD[7] L5 54 – I/O/Z PU
XD[6] L3 39 – I/O/Z PU
XD[5] J5 36 – I/O/Z PU
XD[4] K3 33 – I/O/Z PU
XD[3] J3 30 – I/O/Z PU
XD[2] H5 27 – I/O/Z PU
XD[1] H3 24 – I/O/Z PU
XD[0] G3 21 – I/O/Z PU

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

XINTF SIGNALS (2812 ONLY)

(2)

www.ti.com

(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are

8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3, Electrical Characteristics

Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode.
18 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

XMP/MC F1 17 – I PD

XHOLD E7 159 – I PU into a high-impedance state. The XINTF will

XHOLDA K10 82 – O/Z –

XZCS0AND1 P1 44 – O/Z – XZCS0AND1 is active (low) when an access

XZCS2 P13 88 – O/Z – (low) when an access to the XINTF Zone 2 is

XZCS6AND7 B13 133 – O/Z – XZCS6AND7 is active (low) when an access

XWE N11 84 – O/Z –

XRD M3 42 – O/Z – basis, by the Lead, Active, and Trail periods in

XR/W N4 51 – O/Z –

XREADY B6 161 – I PU XREADY can be configured to be a

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

(2)

PU/PD

(3)

Microprocessor/Microcomputer Mode Select.
Switches between microprocessor and
microcomputer mode. When high, Zone 7 is
enabled on the external interface. When low,
Zone 7 is disabled from the external interface,
and on-chip boot ROM may be accessed
instead. This signal is latched into the
XINTCNF2 register on a reset and the user
can modify this bit in software. The state of the
XMP/MC pin is ignored after reset.

External Hold Request. XHOLD, when active
(low), requests the XINTF to release the
external bus and place all buses and strobes

release the bus when any current access is
complete and there are no pending accesses
on the XINTF.

External Hold Acknowledge. XHOLDA is
driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses
and strobe signals will be in a high-impedance
state. XHOLDA is released when the XHOLD
signal is released. External devices should
only drive the external bus when XHOLDA is
active (low).

XINTF Zone 0 and Zone 1 Chip Select.
to the XINTF Zone 0 or Zone 1 is performed.

XINTF Zone 2 Chip Select. XZCS2 is active
performed.

XINTF Zone 6 and Zone 7 Chip Select.
to the XINTF Zone 6 or Zone 7 is performed.

Write Enable. Active-low write strobe. The
write strobe waveform is specified, per zone
basis, by the Lead, Active, and Trail periods in
the XTIMINGx registers.

Read Enable. Active-low read strobe. The
read strobe waveform is specified, per zone

the XTIMINGx registers. NOTE: The XRD and
XWE signals are mutually exclusive.

Read Not Write Strobe. Normally held high.
When low, XR/W indicates write cycle is
active; when high, XR/W indicates read cycle
is active.

Ready Signal. Indicates peripheral is ready to
complete the access when asserted to 1.

synchronous or an asynchronous input. See
the timing diagrams for more details.

DESCRIPTION

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 19

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

X1/XCLKIN K9 77 58 I – X1/XCLKIN pin is referenced to the 1.8-V (or

X2 M9 76 57 O – Oscillator Output

XCLKOUT F11 119 87 O – XCLKOUT = SYSCLKOUT/4. The XCLKOUT

TESTSEL A13 134 97 I PD

XRS D6 160 113 I/O PU when a watchdog reset occurs. During

TEST1 M7 67 51 I/O – devices, this pin is a “no connect (NC)”

TEST2 N7 66 50 I/O – devices, this pin is a “no connect (NC)”

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

JTAG AND MISCELLANEOUS SIGNALS

(2)

PU/PD

(3)

Oscillator Input – input to the internal
oscillator. This pin is also used to feed an
external clock. The 28x can be operated with
an external clock source, provided that the
proper voltage levels be driven on the
X1/XCLKIN pin. It should be noted that the

1.9-V) core digital power supply (VDD), rather
than the 3.3-V I/O supply (V
diode may be used to clamp a buffered clock
signal to ensure that the logic-high level does
not exceed VDD(1.8 V or 1.9 V) or a 1.8-V
oscillator may be used.

Output clock derived from SYSCLKOUT to be
used for external wait-state generation and as
a general-purpose clock source. XCLKOUT is
either the same frequency, 1/2 the frequency,
or 1/4 the frequency of SYSCLKOUT. At reset,

signal can be turned off by setting bit 3
(CLKOFF) of the XINTCNF2 register to 1.
Unlike other GPIO pins, the XCLKOUT pin is
not placed in a high-impedance state during
reset.

Test Pin. Reserved for TI. Must be connected
to ground.

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to

terminate execution. The PC will point to the
address contained at the location 0x3FFFC0.
When XRS is brought to a high level,
execution begins at the location pointed to by
the PC. This pin is driven low by the DSP

watchdog reset, the XRS pin will be driven low
for the watchdog reset duration of
512 XCLKIN cycles.

The output buffer of this pin is an open-drain
with an internal pullup (100 µA, typical). It is
recommended that this pin be driven by an
open-drain device.

Test Pin. Reserved for TI. On F281x devices,
TEST1 must be left unconnected. On C281x

(i.e., this pin is not connected to any circuitry
internal to the device).

Test Pin. Reserved for TI. On F281x devices,
TEST2 must be left unconnected. On C281x

(i.e., this pin is not connected to any circuitry
internal to the device).

DESCRIPTION

DDIO

). A clamping

20 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

TRST B12 135 98 I PD

TCK A12 136 99 I PU JTAG test clock with internal pullup

TMS D13 126 92 I PU pullup. This serial control input is clocked into

TDI C13 131 96 I PU TDI is clocked into the selected register

TDO D12 127 93 O/Z –

EMU0 D11 137 100 I/O/Z PU

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

JTAG

(2)

PU/PD

(3)

JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system
control of the operations of the device. If this
signal is not connected or driven low, the
device operates in its functional mode, and the
test reset signals are ignored.

NOTE: Do not use pullup resistors on TRST; it
has an internal pulldown device. TRST is an
active-high test pin and must be maintained
low at all times during normal device
operation. In a low-noise environment, TRST
may be left floating. In other instances, an
external pulldown resistor is highly
recommended. The value of this resistor
should be based on drive strength of the
debugger pods applicable to the design. A

2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.

JTAG test-mode select (TMS) with internal
the TAP controller on the rising edge of TCK.

JTAG test data input (TDI) with internal pullup.
(instruction or data) on a rising edge of TCK.

JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge
of TCK.

Emulator pin 0. When TRST is driven high,
this pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used
to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and
the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device
into boundary-scan mode.

NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength
of the debugger pods applicable to the design.
A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.

DESCRIPTION

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 21

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

EMU1 C9 146 105 I/O/Z PU

ADC ANALOG INPUT SIGNALS

ADCINA7 B5 167 119 I –
ADCINA6 D5 168 120 I –
ADCINA5 E5 169 121 I –
ADCINA4 A4 170 122 I –
ADCINA3 B4 171 123 I –
ADCINA2 C4 172 124 I –
ADCINA1 D4 173 125 I –
ADCINA0 A3 174 126 I –
ADCINB7 F5 9 9 I –
ADCINB6 D1 8 8 I –
ADCINB5 D2 7 7 I –
ADCINB4 D3 6 6 I –
ADCINB3 C1 5 5 I –
ADCINB2 B1 4 4 I –
ADCINB1 C3 3 3 I –
ADCINB0 C2 2 2 I –

ADCREFP E2 11 11 I/O –

ADCREFM E4 10 10 I/O –

(2)

PU/PD

(3)

DESCRIPTION

Emulator pin 1. When TRST is driven high,
this pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used
to put the device into boundary-scan mode.
With the EMU0 pin at a logic-high state and
the EMU1 pin at a logic-low state, a rising
edge on the TRST pin would latch the device
into boundary-scan mode.

NOTE: An external pullup resistor is
recommended on this pin. The value of this
resistor should be based on the drive strength
of the debugger pods applicable to the design.
A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it
is recommended that each target board be
validated for proper operation of the debugger
and the application.

8-channel analog inputs for
Sample-and-Hold A. The ADC pins should not
be driven before the V
pins have been fully powered up.

DDA1

, V

DDA2

, and V

8-channel analog inputs for
Sample-and-Hold B. The ADC pins should not
be driven before the V
pins have been fully powered up.

DDA1

, V

DDA2

, and V

ADC Voltage Reference Output (2 V).
Requires a low ESR (under 1.5 Ω) ceramic
bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (2 V) if
the software bit is enabled for this mode.
1–10 µF low ESR capacitor can be used in the
external reference mode.]
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data
sheet that is used in the system.

ADC Voltage Reference Output (1 V).
Requires a low ESR (under 1.5 Ω) ceramic
bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (1 V) if
the software bit is enabled for this mode.
1–10 µF low ESR capacitor can be used in the
external reference mode.]
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data
sheet that is used in the system.

www.ti.com

DDAIO

DDAIO

22 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

ADCRESEXT F2 16 16 O –

ADCBGREFIN E6 164 116 – –
AVSSREFBG E3 12 12 – – ADC Analog GND

AVDDREFBG E1 13 13 – – ADC Analog Power (3.3-V)
ADCLO B3 175 127 – –
V

SSA1

V

SSA2

V

DDA1

V

DDA2

V

SS1

V

DD1

V

DDAIO

V

SSAIO

F3 15 15 – – ADC Analog GND
C5 165 117 – – ADC Analog GND
F4 14 14 – – ADC Analog 3.3-V Supply
A5 166 118 – – ADC Analog 3.3-V Supply
C6 163 115 – – ADC Digital GND
A6 162 114 – – ADC Digital 1.8-V (or 1.9-V) Supply
B2 1 1 – – 3.3-V Analog I/O Power Pin
A2 176 128 – – Analog I/O Ground Pin

POWER SIGNALS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

H1 23 20 – –

L1 37 29 – –
P5 56 42 – –
P9 75 56 – –

P12 – 63 – –
K12 100 74 – –
G12 112 82 – –
C14 128 94 – –
B10 143 102 – –

C8 154 110 – –
G4 19 17 – –
K1 32 26 – –

L2 38 30 – –
P4 52 39 – –
K6 58 – – –
P8 70 53 – –

M10 78 59 – –

L11 86 62 – –

K13 99 73 – –

J14 105 – – –
G13 113 – – –
E14 120 88 – –
B14 129 95 – –
D10 142 – – –
C10 – 103 – –

B8 153 109 – –

(2)

PU/PD

(3)

DESCRIPTION

ADC External Current Bias Resistor.
Use 24.9 kΩ ± 5% for ADC clock range

1–18.75 MHz; use 20 kΩ ± 5% for ADC clock
range 18.75 MHz–25 MHz.

Test Pin. Reserved for TI. Must be left
unconnected.

Common Low Side Analog Input. Connect to
analog ground.

1.8-V or 1.9-V Core Digital Power Pins. See

Section 6.2, Recommended Operating

Conditions, for voltage requirements.

Core and Digital I/O Ground Pins

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 23

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DDIO

V

DD3VFL

J4 31 25 – –
L7 64 49 – –

L10 81 – – –
N14 – – – –
G11 114 83 – –

E9 145 104 – –

N8 69 52 – –

GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS

GPIOA0 - PWM1 (O) M12 92 68 I/O PU GPIO or PWM Output Pin #1
GPIOA1 - PWM2 (O) M14 93 69 I/O PU GPIO or PWM Output Pin #2
GPIOA2 - PWM3 (O) L12 94 70 I/O PU GPIO or PWM Output Pin #3
GPIOA3 - PWM4 (O) L13 95 71 I/O PU GPIO or PWM Output Pin #4
GPIOA4 - PWM5 (O) K11 98 72 I/O PU GPIO or PWM Output Pin #5
GPIOA5 - PWM6 (O) K14 101 75 I/O PU GPIO or PWM Output Pin #6
GPIOA6 -

T1PWM_T1CMP (I)
GPIOA7 -

T2PWM_T2CMP (I)

J11 102 76 I/O PU GPIO or Timer 1 Output

J13 104 77 I/O PU GPIO or Timer 2 Output

GPIOA8 - CAP1_QEP1 (I) H10 106 78 I/O PU GPIO or Capture Input #1
GPIOA9 - CAP2_QEP2 (I) H11 107 79 I/O PU GPIO or Capture Input #2
GPIOA10 - CAP3_QEPI1 (I) H12 109 80 I/O PU GPIO or Capture Input #3
GPIOA11 - TDIRA (I) F14 116 85 I/O PU GPIO or Timer Direction
GPIOA12 - TCLKINA (I) F13 117 86 I/O PU GPIO or Timer Clock Input
GPIOA13 - C1TRIP (I) E13 122 89 I/O PU GPIO or Compare 1 Output Trip
GPIOA14 - C2TRIP (I) E11 123 90 I/O PU GPIO or Compare 2 Output Trip
GPIOA15 - C3TRIP (I) F10 124 91 I/O PU GPIO or Compare 3 Output Trip

GPIOB OR EVB SIGNALS

GPIOB0 - PWM7 (O) N2 45 33 I/O PU GPIO or PWM Output Pin #7
GPIOB1 - PWM8 (O) P2 46 34 I/O PU GPIO or PWM Output Pin #8
GPIOB2 - PWM9 (O) N3 47 35 I/O PU GPIO or PWM Output Pin #9
GPIOB3 - PWM10 (O) P3 48 36 I/O PU GPIO or PWM Output Pin #10
GPIOB4 - PWM11 (O) L4 49 37 I/O PU GPIO or PWM Output Pin #11
GPIOB5 - PWM12 (O) M4 50 38 I/O PU GPIO or PWM Output Pin #12
GPIOB6 -

T3PWM_T3CMP (I)
GPIOB7 -

T4PWM_T4CMP (I)

K5 53 40 I/O PU GPIO or Timer 3 Output

N5 55 41 I/O PU GPIO or Timer 4 Output

GPIOB8 - CAP4_QEP3 (I) M5 57 43 I/O PU GPIO or Capture Input #4
GPIOB9 - CAP5_QEP4 (I) M6 59 44 I/O PU GPIO or Capture Input #5
GPIOB10 - CAP6_QEPI2 (I) P6 60 45 I/O PU GPIO or Capture Input #6
GPIOB11 - TDIRB (I) L8 71 54 I/O PU GPIO or Timer Direction
GPIOB12 - TCLKINB (I) K8 72 55 I/O PU GPIO or Timer Clock Input

(2)

PU/PD

(3)

DESCRIPTION

3 3-V I/O Digital Power Pins

3.3-V Flash Core Power Pin. This pin should
be connected to 3.3 V at all times after
power-up sequence requirements have been
met. This pin is used as V
and must be connected to 3.3 V in ROM parts

DDIO

as well.

www.ti.com

in ROM parts

24 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

GPIOB13 - C4TRIP (I) N6 61 46 I/O PU GPIO or Compare 4 Output Trip
GPIOB14 - C5TRIP (I) L6 62 47 I/O PU GPIO or Compare 5 Output Trip
GPIOB15 - C6TRIP (I) K7 63 48 I/O PU GPIO or Compare 6 Output Trip

GPIOD0 ­T1CTRIP_PDPINTA (I)

GPIOD1 - GPIO or Timer 2 Compare Output Trip or
T2CTRIP/EVASOC (I) External ADC Start-of-Conversion EV-A

GPIOD5 ­T3CTRIP_PDPINTB (I)

GPIOD6 - GPIO or Timer 4 Compare Output Trip or
T4CTRIP/EVBSOC (I) External ADC Start-of-Conversion EV-B

GPIOE0 - XINT1_XBIO (I) D9 149 106 I/O/Z – GPIO or XINT1 or XBIO input
GPIOE1 -

XINT2_ADCSOC (I)
GPIOE2 - XNMI_XINT13 (I) E8 150 107 I/O PU GPIO or XNMI or XINT13

GPIOF0 - SPISIMOA (O) M1 40 31 I/O/Z – GPIO or SPI slave in, master out
GPIOF1 - SPISOMIA (I) N1 41 32 I/O/Z – GPIO or SPI slave out, master in
GPIOF2 - SPICLKA (I/O) K2 34 27 I/O/Z – GPIO or SPI clock
GPIOF3 - SPISTEA (I/O) K4 35 28 I/O/Z – GPIO or SPI slave transmit enable

GPIOF4 - SCITXDA (O) C7 155 111 I/O PU GPIO or SCI asynchronous serial port TX data
GPIOF5 - SCIRXDA (I) A7 157 112 I/O PU GPIO or SCI asynchronous serial port RX data

GPIOF6 - CANTXA (O) N12 87 64 I/O PU GPIO or eCAN transmit data
GPIOF7 - CANRXA (I) N13 89 65 I/O PU GPIO or eCAN receive data

GPIOF8 - MCLKXA (I/O) J1 28 23 I/O PU GPIO or McBSP transmit clock
GPIOF9 - MCLKRA (I/O) H2 25 21 I/O PU GPIO or McBSP receive clock
GPIOF10 - MFSXA (I/O) H4 26 22 I/O PU GPIO or McBSP transmit frame synch
GPIOF11 - MFSRA (I/O) J2 29 24 I/O PU GPIO or McBSP receive frame synch
GPIOF12 - MDXA (O) G1 22 19 I/O – GPIO or McBSP transmitted serial data
GPIOF13 - MDRA (I) G2 20 18 I/O PU GPIO or McBSP received serial data

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

GPIOD OR EVA SIGNALS

H14 110 81 I/O PU GPIO or Timer 1 Compare Output Trip

G10 115 84 I/O PU

GPIOD OR EVB SIGNALS

P10 79 60 I/O PU GPIO or Timer 3 Compare Output Trip

P11 83 61 I/O PU

GPIOE OR INTERRUPT SIGNALS

D8 151 108 I/O/Z – GPIO or XINT2 or ADC start-of-conversion

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

(2)

PU/PD

(3)

DESCRIPTION

Copyright © 2001–2011, Texas Instruments Incorporated Introduction 25

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

GPIOF14 ­XF_XPLLDIS (O)

GPIOG4 - SCITXDB (O) P14 90 66 I/O/Z –

GPIOG5 - SCIRXDB (I) M13 91 67 I/O/Z –

179-BALL 176-PIN 128-PIN
GHH/ZHH PGF PBK

GPIOF OR XF CPU OUTPUT SIGNAL

A11 140 101 I/O PU

GPIOG OR SCI-B SIGNALS

(2)

PU/PD

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along
with the 3.3-V supply.

(3)

This pin has three functions:

1. XF – General-purpose output pin.

2. XPLLDIS – This pin is sampled during
reset to check whether the PLL must be
disabled. The PLL will be disabled if this
pin is sensed low. HALT and STANDBY
modes cannot be used when the PLL is
disabled.

3. GPIO – GPIO function

GPIO or SCI asynchronous serial port transmit
data

GPIO or SCI asynchronous serial port receive
data

DESCRIPTION

www.ti.com

26 Introduction Copyright © 2001–2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

INT[12:1]

CLKIN

Real-Time JTAG

Peripheral Bus

C28x CPU

INT14

NMI

INT13

Memory Bus

Flash
128K x 16 (F2812)
128K x 16 (F2811)

64K x 16 (F2810)

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

OTP

1K x 16

(C)

McBSP

System Control

(Oscillator and PLL

+

Peripheral Clocking

+

Low-Power Modes

+

Watchdog)

FIFO

FIFO

PIE

(96 Interrupts)

(A)

RS

SPI

FIFO

TINT0

TINT1

TINT2

CPU-Timer 0

CPU-Timer 1

CPU-Timer 2

16 Channels

GPIO Pins

XRS

X1/XCLKIN

X2

XF_XPLLDIS

Protected by the code-security module.

XINT13

G

P

I

O

M
U

X

XNMI

ROM

128K x 16 (C2812)
128K x 16 (C2811)

64K x 16 (C2810)

Control

Address (19)

Data (16)

External

Interface

(XINTF)

(B)

L0 SARAM

4K x 16

L1 SARAM

4K x 16

M1 SARAM

1K x 16

M0 SARAM

1K x 16

H0 SARAM

8K x 16

Boot ROM

4K x 16

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3 Functional Overview

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. 45 of the possible 96 interrupts are used on the devices.
B. XINTF is available on the F2812 and C2812 devices only.
C. On C281x devices, the OTP is replaced with a 1K x 16 block of ROM.

Figure 3-1. Functional Block Diagram

Copyright © 2001–2011, Texas Instruments Incorporated Functional Overview 27

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

×

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

×

XINTF Vector - RAM (32 x 32)

(Enabled if VMAP = 1, MP/ = 1, ENPIE = 0)MC

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

×

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

×

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (128K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8
0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

Data Space

Prog Space

XINTF Zone 0 (8K x 16, )XZCS0AND1

XINTF Zone 1 (8K x 16, ) (Protected)XZCS0AND1

×

XINTF Zone 2 (0.5M x 16, )XZCS2

×

XINTF Zone 6 (0.5M x 16, )XZCS6AND7

XINTF Zone 7 (16K x 16, )

(Enabled if MP/ = 1)

XZCS6AND7

MC

×

On-Chip Memory External Memory XINTF

Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.

LEGEND:

0x08 0000

0x00 4000

0x10 0000

0x18 0000

0x3F C000

0x00 2000

0x3D 8000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved (1K)

Reserved

Reserved

Reserved

Reserved

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.1 Memory Map

www.ti.com

A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

28 Functional Overview Copyright © 2001–2011, Texas Instruments Incorporated

User program cannot access these memory maps in program space.

Figure 3-2. F2812/C2812 Memory Map

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

LEGEND:

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

×

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

×

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

×

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

×

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (128K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

On-Chip Memory

0x3D 8000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved (1K)

Reserved

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Copyright © 2001–2011, Texas Instruments Incorporated Functional Overview 29

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-3. F2811/C2811 Memory Map

Submit Documentation Feedback

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

LEGEND:

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

×

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

×

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

×

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

×

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (64K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

On-Chip Memory

0x3E 8000

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

30 Functional Overview Copyright © 2001–2011, Texas Instruments Incorporated

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-4. F2810/C2810 Memory Map

Submit Documentation Feedback