Texas instruments TMS320F2810, TMS320C2810, TMS320F2812, TMS320C2811, TMS320C2812 Data Manual

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

Digital Signal Processors

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS174S

April 2001–Revised March 2011

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Contents

1 TMS320F281x, TMS320C281x DSPs ..................................................................................... 11

1.1 Features .................................................................................................................... 11

1.2 Getting Started ............................................................................................................. 12

2 Introduction ...................................................................................................................... 13

2.1 Description ................................................................................................................. 13

2.2 Device Summary .......................................................................................................... 14

2.3 Pin Assignments ........................................................................................................... 15

2.3.1 Terminal Assignments for the GHH/ZHH Packages ....................................................... 15

2.3.2 Pin Assignments for the PGF Package ...................................................................... 16

2.3.3 Pin Assignments for the PBK Package ...................................................................... 17

2.4 Signal Descriptions ........................................................................................................ 18

3 Functional Overview .......................................................................................................... 27

3.1 Memory Map ............................................................................................................... 28

3.2 Brief Descriptions .......................................................................................................... 33

3.2.1 C28x CPU ....................................................................................................... 33

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 33

3.2.3 Peripheral Bus .................................................................................................. 33

3.2.4 Real-Time JTAG and Analysis ................................................................................ 33

3.2.5 External Interface (XINTF) (2812 Only) ...................................................................... 34

3.2.6 Flash (F281x Only) ............................................................................................. 34

3.2.7 ROM (C281x Only) ............................................................................................. 34

3.2.8 M0, M1 SARAMs ............................................................................................... 34

3.2.9 L0, L1, H0 SARAMs ............................................................................................ 35

3.2.10 Boot ROM ....................................................................................................... 35

3.2.11 Security .......................................................................................................... 35

3.2.12 Peripheral Interrupt Expansion (PIE) Block ................................................................. 36

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI) ........................................................ 36

3.2.14 Oscillator and PLL .............................................................................................. 37

3.2.15 Watchdog ........................................................................................................ 37

3.2.16 Peripheral Clocking ............................................................................................. 37

3.2.17 Low-Power Modes .............................................................................................. 37

3.2.18 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 37

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 38

3.2.20 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 38

3.2.21 Control Peripherals ............................................................................................. 38

3.2.22 Serial Port Peripherals ......................................................................................... 38

3.3 Register Map ............................................................................................................... 39

3.4 Device Emulation Registers .............................................................................................. 41

3.5 External Interface, XINTF (2812 Only) ................................................................................. 42

3.5.1 Timing Registers ................................................................................................ 43

3.5.2 XREVISION Register ........................................................................................... 43

3.6 Interrupts .................................................................................................................... 44

3.6.1 External Interrupts .............................................................................................. 47

3.7 System Control ............................................................................................................ 48

3.8 OSC and PLL Block ....................................................................................................... 50

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3.8.1 Loss of Input Clock ............................................................................................. 51

3.9 PLL-Based Clock Module ................................................................................................ 52

3.10 External Reference Oscillator Clock Option ........................................................................... 52

3.11 Watchdog Block ........................................................................................................... 53

3.12 Low-Power Modes Block ................................................................................................. 54

SPRS174S–APRIL 2001–REVISED MARCH 2011

4 Peripherals ....................................................................................................................... 55

4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 55

4.2 Event Manager Modules (EVA, EVB) ................................................................................... 58

4.2.1 General-Purpose (GP) Timers ................................................................................ 61

4.2.2 Full-Compare Units ............................................................................................. 61

4.2.3 Programmable Deadband Generator ........................................................................ 61

4.2.4 PWM Waveform Generation .................................................................................. 61

4.2.5 Double Update PWM Mode ................................................................................... 61

4.2.6 PWM Characteristics ........................................................................................... 62

4.2.7 Capture Unit ..................................................................................................... 62

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 62

4.2.9 External ADC Start-of-Conversion ........................................................................... 62

4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 63

4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 68

4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 73

4.6 Serial Communications Interface (SCI) Module ....................................................................... 77

4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 80

4.8 GPIO MUX ................................................................................................................. 83

5 Development Support ........................................................................................................ 86

5.1 Device and Development Support Tool Nomenclature ............................................................... 86

5.2 Documentation Support ................................................................................................... 87

5.3 Community Resources .................................................................................................... 89

6 Electrical Specifications ..................................................................................................... 90

6.1 Absolute Maximum Ratings .............................................................................................. 90

6.2 Recommended Operating Conditions .................................................................................. 90

6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) .............. 91

6.4 Current Consumption ..................................................................................................... 92

6.5 Current Consumption Graphs ............................................................................................ 94

6.6 Reducing Current Consumption ......................................................................................... 96

6.7 Emulator Connection Without Signal Buffering for the DSP ......................................................... 96

6.8 Power Sequencing Requirements ....................................................................................... 97

6.9 Signal Transition Levels .................................................................................................. 99

6.10 Timing Parameter Symbology .......................................................................................... 100

6.11 General Notes on Timing Parameters ................................................................................. 100

6.12 Test Load Circuit ......................................................................................................... 100

6.13 Device Clock Table ...................................................................................................... 101

6.14 Clock Requirements and Characteristics ............................................................................. 102

6.14.1 Input Clock Requirements ................................................................................... 102

6.14.2 Output Clock Characteristics ................................................................................ 103

6.15 Reset Timing .............................................................................................................. 103

6.16 Low-Power Mode Wakeup Timing ..................................................................................... 107

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.17 Event Manager Interface ................................................................................................ 111

6.17.1 PWM Timing ................................................................................................... 111

6.17.2 Interrupt Timing ................................................................................................ 113

6.18 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 114

6.19 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 115

6.20 Serial Peripheral Interface (SPI) Master Mode Timing .............................................................. 116

6.21 Serial Peripheral Interface (SPI) Slave Mode Timing ............................................................... 121

6.22 External Interface (XINTF) Timing ..................................................................................... 125

6.23 XINTF Signal Alignment to XCLKOUT ................................................................................ 129

6.24 External Interface Read Timing ........................................................................................ 130

6.25 External Interface Write Timing ........................................................................................ 132

6.26 External Interface Ready-on-Read Timing With One External Wait State ....................................... 133

6.27 External Interface Ready-on-Write Timing With One External Wait State ........................................ 136

6.28 XHOLD and XHOLDA ................................................................................................... 139

6.29 XHOLD/XHOLDA Timing ............................................................................................... 140

6.30 On-Chip Analog-to-Digital Converter .................................................................................. 142

6.30.1 ADC Absolute Maximum Ratings ........................................................................... 142

6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions ........................... 143

6.30.3 Current Consumption for Different ADC Configurations ................................................. 144

6.30.4 ADC Power-Up Control Bit Timing .......................................................................... 145

6.30.5 Detailed Description .......................................................................................... 145

6.30.5.1 Reference Voltage ................................................................................ 145

6.30.5.2 Analog Inputs ..................................................................................... 145

6.30.5.3 Converter .......................................................................................... 145

6.30.5.4 Conversion Modes ............................................................................... 145

6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 146

6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 147

6.30.8 Definitions of Specifications and Terminology ............................................................. 148

6.31 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 149

6.31.1 McBSP Transmit and Receive Timing ...................................................................... 149

6.31.2 McBSP as SPI Master or Slave Timing .................................................................... 152

6.32 Flash Timing (F281x Only) ............................................................................................. 156

6.33 ROM Timing (C281x only) .............................................................................................. 158

6.34 Migrating From F281x Devices to C281x Devices .................................................................. 159

www.ti.com

7 Revision History .............................................................................................................. 160

8 Mechanical Data .............................................................................................................. 161

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

List of Figures

2-1 TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)............................. 15

2-2 TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View) ..................................................... 16

2-3 TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP (Top View).............. 17

3-1 Functional Block Diagram....................................................................................................... 28

3-2 F2812/C2812 Memory Map..................................................................................................... 29

3-3 F2811/C2811 Memory Map..................................................................................................... 30

3-4 F2810/C2810 Memory Map..................................................................................................... 30

3-5 External Interface Block Diagram .............................................................................................. 42

3-6 Interrupt Sources ................................................................................................................. 44

3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 45

3-8 Clock and Reset Domains ...................................................................................................... 48

3-9 OSC and PLL Block.............................................................................................................. 50

3-10 Recommended Crystal/Clock Connection .................................................................................... 52

3-11 Watchdog Module................................................................................................................ 53

4-1 CPU-Timers....................................................................................................................... 55

4-2 CPU-Timer Interrupts Signals and Output Signal............................................................................ 56

4-3 Event Manager A Functional Block Diagram ................................................................................. 61

4-4 Block Diagram of the F281x and C281x ADC Module ...................................................................... 64

4-5 ADC Pin Connections With Internal Reference .............................................................................. 65

4-6 ADC Pin Connections With External Reference ............................................................................. 66

4-7 eCAN Block Diagram and Interface Circuit................................................................................... 69

4-8 eCAN Memory Map .............................................................................................................. 71

4-9 McBSP Module With FIFO...................................................................................................... 74

4-10 Serial Communications Interface (SCI) Module Block Diagram............................................................ 79

4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode).......................................................... 82

4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 85

5-1 TMS320x281x Device Nomenclature.......................................................................................... 87

6-1 F2812/F2811/F2810 Typical Current Consumption Over Frequency ..................................................... 94

6-2 F2812/F2811/F2810 Typical Power Consumption Over Frequency....................................................... 95

6-3 C2812/C2811/C2810 Typical Current Consumption Over Frequency .................................................... 95

6-4 C2812/C2811/C2810 Typical Power Consumption Over Frequency...................................................... 96

6-5 Emulator Connection Without Signal Buffering for the DSP................................................................ 97

6-6 F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2 ....................................... 98

6-7 Output Levels ..................................................................................................................... 99

6-8 Input Levels ....................................................................................................................... 99

6-9 3.3-V Test Load Circuit......................................................................................................... 100

6-10 Clock Timing..................................................................................................................... 103

6-11 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note D)................................................. 105

6-12 Power-on Reset in Microprocessor Mode (XMP/MC = 1)................................................................. 106

6-13 Warm Reset in Microcomputer Mode ........................................................................................ 106

6-14 Effect of Writing Into PLLCR Register ....................................................................................... 106

6-15 IDLE Entry and Exit Timing.................................................................................................... 107

6-16 STANDBY Entry and Exit Timing............................................................................................. 109

6-17 HALT Wakeup Using XNMI ................................................................................................... 110

6-18 PWM Output Timing............................................................................................................ 111

6-19 TDIRx Timing.................................................................................................................... 112

6-20 EVASOC Timing................................................................................................................ 112

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6-21 EVBSOC Timing................................................................................................................ 112

6-22 External Interrupt Timing....................................................................................................... 113

6-23 General-Purpose Output Timing.............................................................................................. 114

6-24 GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 115

6-25 General-Purpose Input Timing................................................................................................ 116

6-26 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 118

6-27 SPI Master External Timing (Clock Phase = 1)............................................................................. 120

6-28 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 122

6-29 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 124

6-30 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 128

6-31 Example Read Access......................................................................................................... 131

6-32 Example Write Access......................................................................................................... 132

6-33 Example Read With Synchronous XREADY Access ...................................................................... 134

6-34 Example Read With Asynchronous XREADY Access..................................................................... 135

6-35 Write With Synchronous XREADY Access.................................................................................. 137

6-36 Write With Asynchronous XREADY Access ................................................................................ 138

6-37 External Interface Hold Waveform............................................................................................ 140

6-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 141

6-39 ADC Analog Input Impedance Model ........................................................................................ 145

6-40 ADC Power-Up Control Bit Timing ........................................................................................... 145

6-41 Sequential Sampling Mode (Single-Channel) Timing...................................................................... 146

6-42 Simultaneous Sampling Mode Timing ....................................................................................... 147

6-43 McBSP Receive Timing........................................................................................................ 151

6-44 McBSP Transmit Timing....................................................................................................... 151

6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 152

6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0................................................... 153

6-47 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1................................................... 154

6-48 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1................................................... 155

www.ti.com

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

List of Tables

2-1 Hardware Features............................................................................................................... 14

2-2 Signal Descriptions............................................................................................................... 18

3-1 Addresses of Flash Sectors in F2812 and F2811 ........................................................................... 31

3-2 Addresses of Flash Sectors in F2810 ......................................................................................... 31

3-3 Wait States ........................................................................................................................ 32

3-4 Boot Mode Selection............................................................................................................. 35

3-5 Impact of Using the Code Security Module................................................................................... 36

3-6 Peripheral Frame 0 Registers .................................................................................................. 39

3-7 Peripheral Frame 1 Registers .................................................................................................. 39

3-8 Peripheral Frame 2 Registers .................................................................................................. 40

3-9 Device Emulation Registers..................................................................................................... 41

3-10 XINTF Configuration and Control Register Mappings....................................................................... 43

3-11 XREVISION Register Bit Definitions........................................................................................... 43

3-12 PIE Peripheral Interrupts........................................................................................................ 45

3-13 PIE Configuration and Control Registers...................................................................................... 46

3-14 External Interrupts Registers ................................................................................................... 47

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 49

3-16 PLLCR Register Bit Definitions................................................................................................. 51

3-17 Possible PLL Configuration Modes ............................................................................................ 52

3-18 F281x and C281x Low-Power Modes ......................................................................................... 54

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 57

4-2 Module and Signal Names for EVA and EVB ................................................................................ 58

4-3 EVA Registers .................................................................................................................... 59

4-4 ADC Registers.................................................................................................................... 67

4-5 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs ............................................ 70

4-6 CAN Registers.................................................................................................................... 72

4-7 McBSP Registers................................................................................................................. 75

4-8 SCI-A Registers .................................................................................................................. 78

4-9 SCI-B Registers .................................................................................................................. 78

4-10 SPI Registers ..................................................................................................................... 81

4-11 GPIO Mux Registers............................................................................................................. 83

4-12 GPIO Data Registers ............................................................................................................ 84

5-1 TMS320x281x Peripheral Selection Guide ................................................................................... 87

6-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 92

6-2 TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During

Low-Power Modes at 150-MHz SYSCLKOUT ............................................................................... 93

6-3 Typical Current Consumption by Various Peripherals (at 150 MHz) ...................................................... 96

6-4 Recommended “Low-Dropout Regulators”.................................................................................... 97

6-5 TMS320F281x and TMS320C281x Clock Table and Nomenclature .................................................... 101

6-6 Input Clock Frequency ......................................................................................................... 102

6-7 XCLKIN Timing Requirements – PLL Bypassed or Enabled ............................................................. 102

6-8 XCLKIN Timing Requirements – PLL Disabled ............................................................................ 102

6-9 Possible PLL Configuration Modes........................................................................................... 102

6-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 103

6-11 Reset (XRS) Timing Requirements .......................................................................................... 103

6-12 IDLE Mode Timing Requirements ........................................................................................... 107

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6-13 IDLE Mode Switching Characteristics ....................................................................................... 107

6-14 STANDBY Mode Timing Requirements ..................................................................................... 108

6-15 STANDBY Mode Switching Characteristics ................................................................................ 108

6-16 HALT Mode Timing Requirements ........................................................................................... 110

6-17 HALT Mode Switching Characteristics ...................................................................................... 110

6-18 PWM Switching Characteristics .............................................................................................. 111

6-19 Timer and Capture Unit Timing Requirements ............................................................................. 111

6-20 External ADC Start-of-Conversion – EVA – Switching Characteristics ................................................. 112

6-21 External ADC Start-of-Conversion – EVB – Switching Characteristics ................................................. 112

6-22 Interrupt Switching Characteristics .......................................................................................... 113

6-23 Interrupt Timing Requirements ............................................................................................... 113

6-24 General-Purpose Output Switching Characteristics ....................................................................... 114

6-25 General-Purpose Input Timing Requirements .............................................................................. 116

6-26 SPI Master Mode External Timing (Clock Phase = 0) .................................................................... 117

6-27 SPI Master Mode External Timing (Clock Phase = 1) .................................................................... 119

6-28 SPI Slave Mode External Timing (Clock Phase = 0) ...................................................................... 121

6-29 SPI Slave Mode External Timing (Clock Phase = 1) ...................................................................... 123

6-30 Relationship Between Parameters Configured in XTIMING and Duration of Pulse ................................... 125

6-31 XINTF Clock Configurations................................................................................................... 128

6-32 External Memory Interface Read Switching Characteristics ............................................................. 130

6-33 External Memory Interface Read Timing Requirements .................................................................. 130

6-34 External Memory Interface Write Switching Characteristics .............................................................. 132

6-35 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ....................... 133

6-36 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ............................ 133

6-37 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ....................................... 133

6-38 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ...................................... 133

6-39 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ........................ 136

6-40 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ....................................... 136

6-41 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ...................................... 136

6-42 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ...................................................... 140

6-43 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ................................................. 141

6-44 DC Specifications .............................................................................................................. 143

6-45 AC Specifications............................................................................................................... 144

6-46 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ........................................ 144

6-47 ADC Power-Up Delays......................................................................................................... 145

6-48 Sequential Sampling Mode Timing ........................................................................................... 146

6-49 Simultaneous Sampling Mode Timing ....................................................................................... 147

6-50 McBSP Timing Requirements ................................................................................................ 149

6-51 McBSP Switching Characteristics ........................................................................................... 150

6-52 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ............................... 152

6-53 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) ........................... 152

6-54 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ............................... 153

6-55 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) ........................... 153

6-56 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ............................... 154

6-57 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) ........................... 154

6-58 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ............................... 155

6-59 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ........................... 155

6-60 Flash Endurance for A and S Temperature Material....................................................................... 156

www.ti.com

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

6-61 Flash Endurance for Q Temperature Material .............................................................................. 156

6-62 Flash Parameters at 150-MHz SYSCLKOUT............................................................................... 156

6-63 Flash/OTP Access Timing..................................................................................................... 157

6-64 Minimum Required Flash Wait States at Different Frequencies (F281x devices)...................................... 157

6-65 ROM Access Timing............................................................................................................ 158

6-66 Minimum Required ROM Wait States at Different Frequencies (C281x devices)...................................... 158

8-1 Thermal Resistance Characteristics for 179-Ball GHH.................................................................... 161

8-2 Thermal Resistance Characteristics for 179-Ball ZHH..................................................................... 161

8-3 Thermal Resistance Characteristics for 176-Pin PGF ..................................................................... 161

8-4 Thermal Resistance Characteristics for 128-Pin PBK ..................................................................... 161

SPRS174S–APRIL 2001–REVISED MARCH 2011

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Digital Signal Processors

Check for Samples: TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812

1 TMS320F281x, TMS320C281x DSPs

1.1 Features

1234

• High-Performance Static CMOS Technology • Clock and System Control

– 150 MHz (6.67-ns Cycle Time) – Dynamic PLL Ratio Changes Supported – Low-Power (1.8-V Core @135 MHz, – On-Chip Oscillator

1.9-V Core @150 MHz, 3.3-V I/O) Design

• JTAG Boundary Scan Support

(1)

• High-Performance 32-Bit CPU ( TMS320C28x™)

– 16 x 16 and 32 x 32 MAC Operations Supports 45 Peripheral Interrupts – 16 x 16 Dual MAC • Three 32-Bit CPU-Timers – Harvard Bus Architecture • 128-Bit Security Key/Lock – Atomic Operations – Protects Flash/ROM/OTP and L0/L1 SARAM – Fast Interrupt Response and Processing – Prevents Firmware Reverse-Engineering – Unified Memory Programming Model • Motor Control Peripherals – 4M Linear Program/Data Address Reach – Two Event Managers (EVA, EVB) – Code-Efficient (in C/C++ and Assembly) – Compatible to 240xA Devices – TMS320F24x/LF240x Processor Source Code • Serial Port Peripherals

Compatible

• On-Chip Memory

– Flash Devices: Up to 128K x 16 Flash (SCIs), Standard UART

(Four 8K x 16 and Six 16K x 16 Sectors) – ROM Devices: Up to 128K x 16 ROM – 1K x 16 OTP ROM – L0 and L1: 2 Blocks of 4K x 16 Each

Single-Access RAM (SARAM) – H0: 1 Block of 8K x 16 SARAM – M0 and M1: 2 Blocks of 1K x 16 Each

SARAM

• Boot ROM (4K x 16) – With Software Boot Modes – Standard Math Tables

• External Interface (2812) – Over 1M x 16 Total Memory – Programmable Wait States – Programmable Read/Write Strobe Timing – Three Individual Chip Selects

– Watchdog Timer Module

• Three External Interrupts

• Peripheral Interrupt Expansion (PIE) Block That

– Serial Peripheral Interface (SPI) – Two Serial Communications Interfaces

– Enhanced Controller Area Network (eCAN) – Multichannel Buffered Serial Port (McBSP)

• 12-Bit ADC, 16 Channels – 2 x 8 Channel Input Multiplexer – Two Sample-and-Hold – Single/Simultaneous Conversions – Fast Conversion Rate: 80 ns/12.5 MSPS

• Up to 56 General-Purpose I/O (GPIO) Pins

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• Development Tools Include – ANSI C/C++ Compiler/Assembler/Linker – Code Composer Studio™ IDE – DSP/BIOS™ – JTAG Scan Controllers

(1)

• Low-Power Modes and Power Savings – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

(1) IEEE Standard 1149.1-1990 IEEE Standard Test Access Port

and Boundary-Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MicroStar BGA, TMS320C28x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TI, TMS320C54x, TMS320C55x, TMS320 are

trademarks of Texas Instruments.

3eZdsp is a trademark of Spectrum Digital Incorporated. 4All other trademarks are the property of their respective owners.

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

• Package Options • Temperature Options – 179-Ball MicroStar BGA™ With External – A: –40°C to 85°C (GHH, ZHH, PGF, PBK)

Memory Interface (GHH, ZHH) (2812)

– 176-Pin Low-Profile Quad Flatpack (LQFP)

With External Memory Interface (PGF) (2812)

– S: –40°C to 125°C (GHH, ZHH, PGF, PBK) – Q: –40°C to 125°C (PGF, PBK)

[Q100 Qualification]

– 128-Pin LQFP Without External Memory

Interface (PBK) (2810, 2811)

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x™ device. For more detail on each of these steps, see the following:

• Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0)

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

• TMS320F28x DSC Development and Experimenter’s Kits (http://www.ti.com/f28xkits)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

2 Introduction

This section provides a summary of each device’s features, lists the pin assignments, and describes the function of each pin. This document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

2.1 Description

The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812 devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in

Section 3, Functional Overview.

Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812 are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. TMS320C2810, TMS320C2811, and TMS320C2812 are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices.

SPRS174S–APRIL 2001–REVISED MARCH 2011

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

2.2 Device Summary

Table 2-1 provides a summary of each device’s features.

Table 2-1. Hardware Features

FEATURE TYPE

Instruction Cycle (at 150 MHz) – 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns Single-Access RAM (SARAM) (16-bit word) – 18K 18K 18K 18K 18K 18K

3.3-V On-Chip Flash (16-bit word) – 64K 128K 128K – – – On-Chip ROM (16-bit word) – – – – 64K 128K 128K Code Security for On-Chip

Flash/SARAM/OTP/ROM Boot ROM – Yes Yes Yes Yes Yes Yes OTP ROM (1K x 16) – Yes Yes Yes Yes External Memory Interface 0 – – Yes – – Yes

Event Managers A and B (EVA and EVB) –

● General-Purpose (GP) Timers – 4 4 4 4 4 4

● Compare (CMP)/PWM 0 16 16 16 16 16 16

● Capture (CAP)/QEP Channels 0 6/2 6/2 6/2 6/2 6/2 6/2

Watchdog Timer – Yes Yes Yes Yes Yes Yes 12-Bit ADC Yes Yes Yes Yes Yes Yes

● Channels 16 16 16 16 16 16 32-Bit CPU Timers – 3 3 3 3 3 3 Serial Peripheral Interface (SPI) 0 Yes Yes Yes Yes Yes Yes Serial Communications Interfaces A and B SCIA, SCIA, SCIA, SCIA, SCIA, SCIA,

(SCIA and SCIB) SCIB SCIB SCIB SCIB SCIB SCIB Controller Area Network (CAN) 0 Yes Yes Yes Yes Yes Yes Multichannel Buffered Serial Port (McBSP) 0 Yes Yes Yes Yes Yes Yes Digital I/O Pins (Shared) – 56 56 56 56 56 56 External Interrupts – 3 3 3 3 3 3 Supply Voltage – 1.8-V Core (135 MHz), 1.9-V Core (150 MHz), 3.3-V I/O

128-pin PBK Yes Yes – Yes Yes –

Packaging –

Temperature Options

Product Status

(1) The TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature

number SPRZ193) has been posted on the Texas Instruments (TI) website. It will be updated as needed.

(2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the

TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. (3) On C281x devices, OTP is replaced by a 1K x 16 block of ROM. (4) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

(4)

176-pin PGF – – Yes – – Yes 179-ball GHH – – Yes – – Yes 179-ball ZHH – – Yes – – Yes A: –40°C to 85°C – Yes Yes Yes Yes Yes Yes S: –40°C to 125°C – Yes Yes Yes Yes Yes Yes Q: –40°C to 125°C

(Q100 Qualification)

(2)

F2810 F2811 F2812 C2810 C2811 C2812

– Yes Yes Yes Yes Yes Yes

EVA, EVA, EVA, EVA, EVA, EVA,

EVB EVB EVB EVB EVB EVB

– Yes Yes PGF only Yes Yes PGF only – TMS TMS TMS TMS TMS TMS

(1)

(3)

Yes

(3)

Yes

(3)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

1412 1310 118 95 63 41 2 7

XA[14]

SSAIO

ADCINA0 ADCINA4

DDA2VDD1

SCIRXDA

XA[16] XD[15]

TESTSEL

XA[11]

ADCINB2

DDAIO

ADCLO ADCINA3 ADCINA7 XREADY

XA[17] XA[15] XD[14]

TRST

XZCS6AND7

ADCINB3 ADCINB0 ADCINB1 ADCINA2

SS1

SCITXDA

EMU1

XA[12] XA[10]

TDI

ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6

XRS

XA[18]

EMU0

TDO

TMS

XA[9]

ADCREFP

XINT2_

ADCSOC

AVDDREFBG

AVSSREFBG

ADC-

REFM

ADCINA5

ADC-

BGREFIN

XHOLD

XNMI_

XINT13

XA[13]

C2TRIP

XA[8]

C1TRIP

ADC-

RESEXT

SSA1

SSA2

DDA1

ADCINB7

C3TRIP

XCLKOUT

XA[7]

TCLKINA TDIRA

MDXA MDRA

XD[0] XA[0] XA[6]

MCLKRA

XD[1]

MFSXA

XD[2]

CAP1_

QEP1

CAP2_

QEP2

CAP3_

QEPI1

XA[5]

T1CTRIP_

PDPINTA

MCLKXA

MFSRA

XD[3]

XD[5]

XD[13]

T1PWM_

T1CMP

XA[4]

T2PWM_

T2CMP

SPICLKA

XD[4]

SPISTEA

T3PWM_

T3CMP

C6TRIP

TCLKINB

X1/

XCLKIN

XHOLDA

PWM5

PWM6

XD[6]

PWM11

XD[7]

C5TRIP

TDIRB

XD[10]

PWM3

PWM4

XD[12]

SPISIMOA

XA[1]

XRD

PWM12

CAP4_

QEP3

CAP5_

QEP4

TEST1

XD[9]

XA[3]

PWM1

SCIRXDB

PWM2

SPISOMIA

PWM9

T4PWM_

T4CMP

C4TRIP

DD3VFL

XD[11] XA[2]

XWE

CANTXA CANRXA

DDIO

XZCS0AND1

PWM10

CAP6_

QEPI2

XD[8]

T3CTRIP_

PDPINTB

T4CTRIP/ EVBSOC

XINT1_

XBIO

XF_

XPLLDIS

XMP/MC

T2CTRIP/

EVASOC

XR/W

XZCS2

SCITXDB

TCK

PWM7

TEST2

PWM8

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.3 Pin Assignments

Figure 2-1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages. Figure 2-2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2-3 shows the pin assignments for the 128-pin PBK LQFP. Table 2-2 describes the function(s) of

each pin.

2.3.1 Terminal Assignments for the GHH/ZHH Packages

See Table 2-2 for a description of each terminal’s function(s).

Figure 2-1. TMS320F2812 and TMS320C2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

ADCRESEXT

XA[0]

XA[1]

XD[0]

XD[1]

XD[2]

XD[3]

XD[4]

XD[6]

SPISIMOA

SPISOMIA

XRD

XZCS0AND1

C3TRIP

C2TRIP

C1TRIP

XD[5]

SPICLKA

SPISTEA

MDRA

MDXA

MCLKRA

MCLKXA

MFSXA

MFSRA

DDREFBG

SSREFBG

DDIO

DDA1

SSA1

DDAIO

133

176

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

XR/W

T3PWM_T3CMP

XD[7]

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

XD[8]

TEST2

TEST1

XD[9]

DD3VFL

TDIRB

TCLKINB

XD[10]

XD[11]

X1/XCLKIN

T3CTRIP_PDPINTB

XA[2]

DDIO

XHOLDA

T4CTRIPEVBSOC/

XWE

XA[3]

CANTXA

XZCS2

134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175

132 89

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

XA[11]

XA[10]

XA[9]

XA[8]

XA[7]

XA[6]

XD[13]

XD[12]

XA[5]

XA[4]

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

CAP3_QEPI1

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

T1PWM_T1CMP

XCLKOUT

TCLKINA

TDIR

TDI

TDO

TMS

XZCS6AND7

TESTSEL

TRST

TCK

EMU0 XA[12] XD[14]

XA[13]

XA[14]

DDIO

EMU1 XD[15] XA[15]

XNMI_XINT13

XINT2_ADCSOC

XA[16]

SCITXDA

XA[17]

SCIRXDA

XA[18]

XHOLD

XRS

XREADY

DD1

SS1

ADCBGREFIN

SSA2

DDA2

ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2

ADCINA1

ADCINA0

ADCLO

SSAIO

XF_XPLLDIS

XMP/MC

T1CTRIP_PDPINTA

T2CTRIP/EVASOC

XINT1_XBIO

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.3.2 Pin Assignments for the PGF Package

The TMS320F2812 and TMS320C2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-2. See Table 2-2 for a description of each pin’s function(s).

www.ti.com

Figure 2-2. TMS320F2812 and TMS320C2812 176-Pin PGF LQFP (Top View)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFM

ADCREFP

ADCRESEXT

MDRA

MDXA

MCLKRA

MCLKXA

MFSXA

MFSRA

SPICLKA

SPISTEA

SPISIMOA

SPISOMIA

AVSSREFBG

AVDDREFBG

TDI

TDO

TMS

XCLKOUT

TCLKINA

TDIRA

CAP3_QEPI1

CAP2_QEP2

CAP1_QEP1

T2PWM_T2CMP

T1PWM_T1CMP

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

SCIRXDB

SCITXDB

CANRXA

T1CTRIP_PDPINTA

T2CTRIPEVASOC/

C3TRIP

C2TRIP

C1TRIP

96 65

128

PWM7

PWM8

PWM9

PWM10

PWM11

PWM12

T3PWM_T3CMP

T4PWM_T4CMP

CAP4_QEP3

CAP5_QEP4

CAP6_QEPI2

C4TRIP

C5TRIP

C6TRIP

TEST2

TEST1

DD3VFL

TDIRB

TCLKINB

X1/XCLKIN

T3CTRIP_PDPINTB

CANTXA

T4CTRIPEVBSOC/

127

126

125

124

123

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

122

TESTSEL

TRST

TCK

EMU0

XF_XPLLDIS

DDIO

EMU1

XINT1_XBIO

XNMI_XINT13

XINT2_ADCSOC

SCITXDA SCIRXDA

XRS V

DD1

SS1

ADCBGREFIN

SSA2

SSA1

DDA1

DDA2

ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2

ADCINA1

ADCINA0

ADCLO

SSAIO

DDAIO

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

2.3.3 Pin Assignments for the PBK Package

The TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-3. See Table 2-2 for a description of each pin’s function(s).

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 2-3. TMS320F2810, TMS320F2811, TMS320C2810, and TMS320C2811 128-Pin PBK LQFP

(Top View)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

2.4 Signal Descriptions

Table 2-2 specifies the signals on the F281x and C281x devices. All digital inputs are TTL-compatible. All

outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.

PU/PD

(1)

(3)

16-bit XINTF Data Bus

DESCRIPTION

Table 2-2. Signal Descriptions

PIN NO.

NAME I/O/Z

XA[18] D7 158 – O/Z – XA[17] B7 156 – O/Z – XA[16] A8 152 – O/Z – XA[15] B9 148 – O/Z – XA[14] A10 144 – O/Z – XA[13] E10 141 – O/Z – XA[12] C11 138 – O/Z – XA[11] A14 132 – O/Z – XA[10] C12 130 – O/Z – XA[9] D14 125 – O/Z – 19-bit XINTF Address Bus XA[8] E12 121 – O/Z – XA[7] F12 118 – O/Z – XA[6] G14 111 – O/Z – XA[5] H13 108 – O/Z – XA[4] J12 103 – O/Z – XA[3] M11 85 – O/Z – XA[2] N10 80 – O/Z – XA[1] M2 43 – O/Z – XA[0] G5 18 – O/Z – XD[15] A9 147 – I/O/Z PU XD[14] B11 139 – I/O/Z PU XD[13] J10 97 – I/O/Z PU XD[12] L14 96 – I/O/Z PU XD[11] N9 74 – I/O/Z PU XD[10] L9 73 – I/O/Z PU XD[9] M8 68 – I/O/Z PU XD[8] P7 65 – I/O/Z PU XD[7] L5 54 – I/O/Z PU XD[6] L3 39 – I/O/Z PU XD[5] J5 36 – I/O/Z PU XD[4] K3 33 – I/O/Z PU XD[3] J3 30 – I/O/Z PU XD[2] H5 27 – I/O/Z PU XD[1] H3 24 – I/O/Z PU XD[0] G3 21 – I/O/Z PU

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

XINTF SIGNALS (2812 ONLY)

(2)

www.ti.com

(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are

8 mA. (2) I = Input, O = Output, Z = High impedance (3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 6.3, Electrical Characteristics

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

XMP/MC F1 17 – I PD

XHOLD E7 159 – I PU into a high-impedance state. The XINTF will

XHOLDA K10 82 – O/Z –

XZCS0AND1 P1 44 – O/Z – XZCS0AND1 is active (low) when an access

XZCS2 P13 88 – O/Z – (low) when an access to the XINTF Zone 2 is

XZCS6AND7 B13 133 – O/Z – XZCS6AND7 is active (low) when an access

XWE N11 84 – O/Z –

XRD M3 42 – O/Z – basis, by the Lead, Active, and Trail periods in

XR/W N4 51 – O/Z –

XREADY B6 161 – I PU XREADY can be configured to be a

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

(2)

PU/PD

(3)

Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface. When low, Zone 7 is disabled from the external interface, and on-chip boot ROM may be accessed instead. This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software. The state of the XMP/MC pin is ignored after reset.

External Hold Request. XHOLD, when active (low), requests the XINTF to release the external bus and place all buses and strobes

release the bus when any current access is complete and there are no pending accesses on the XINTF.

External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has granted a XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low).

XINTF Zone 0 and Zone 1 Chip Select. to the XINTF Zone 0 or Zone 1 is performed.

XINTF Zone 2 Chip Select. XZCS2 is active performed.

XINTF Zone 6 and Zone 7 Chip Select. to the XINTF Zone 6 or Zone 7 is performed.

Write Enable. Active-low write strobe. The write strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.

Read Enable. Active-low read strobe. The read strobe waveform is specified, per zone

the XTIMINGx registers. NOTE: The XRD and XWE signals are mutually exclusive.

Read Not Write Strobe. Normally held high. When low, XR/W indicates write cycle is active; when high, XR/W indicates read cycle is active.

Ready Signal. Indicates peripheral is ready to complete the access when asserted to 1.

synchronous or an asynchronous input. See the timing diagrams for more details.

DESCRIPTION

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

X1/XCLKIN K9 77 58 I – X1/XCLKIN pin is referenced to the 1.8-V (or

X2 M9 76 57 O – Oscillator Output

XCLKOUT F11 119 87 O – XCLKOUT = SYSCLKOUT/4. The XCLKOUT

TESTSEL A13 134 97 I PD

XRS D6 160 113 I/O PU when a watchdog reset occurs. During

TEST1 M7 67 51 I/O – devices, this pin is a “no connect (NC)”

TEST2 N7 66 50 I/O – devices, this pin is a “no connect (NC)”

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

JTAG AND MISCELLANEOUS SIGNALS

(2)

PU/PD

(3)

Oscillator Input – input to the internal oscillator. This pin is also used to feed an external clock. The 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the

1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (V diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD(1.8 V or 1.9 V) or a 1.8-V oscillator may be used.

Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At reset,

signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in a high-impedance state during reset.

Test Pin. Reserved for TI. Must be connected to ground.

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to

terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP

watchdog reset, the XRS pin will be driven low for the watchdog reset duration of 512 XCLKIN cycles.

The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is recommended that this pin be driven by an open-drain device.

Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected. On C281x

(i.e., this pin is not connected to any circuitry internal to the device).

Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected. On C281x

(i.e., this pin is not connected to any circuitry internal to the device).

DESCRIPTION

DDIO

). A clamping

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

TRST B12 135 98 I PD

TCK A12 136 99 I PU JTAG test clock with internal pullup

TMS D13 126 92 I PU pullup. This serial control input is clocked into

TDI C13 131 96 I PU TDI is clocked into the selected register

TDO D12 127 93 O/Z –

EMU0 D11 137 100 I/O/Z PU

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

JTAG

(2)

PU/PD

(3)

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. TRST is an active-high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A

2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

JTAG test-mode select (TMS) with internal the TAP controller on the rising edge of TCK.

JTAG test data input (TDI) with internal pullup. (instruction or data) on a rising edge of TCK.

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK.

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

DESCRIPTION

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

EMU1 C9 146 105 I/O/Z PU

ADC ANALOG INPUT SIGNALS

ADCINA7 B5 167 119 I – ADCINA6 D5 168 120 I – ADCINA5 E5 169 121 I – ADCINA4 A4 170 122 I – ADCINA3 B4 171 123 I – ADCINA2 C4 172 124 I – ADCINA1 D4 173 125 I – ADCINA0 A3 174 126 I – ADCINB7 F5 9 9 I – ADCINB6 D1 8 8 I – ADCINB5 D2 7 7 I – ADCINB4 D3 6 6 I – ADCINB3 C1 5 5 I – ADCINB2 B1 4 4 I – ADCINB1 C3 3 3 I – ADCINB0 C2 2 2 I –

ADCREFP E2 11 11 I/O –

ADCREFM E4 10 10 I/O –

(2)

PU/PD

(3)

DESCRIPTION

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

8-channel analog inputs for Sample-and-Hold A. The ADC pins should not be driven before the V pins have been fully powered up.

DDA1

, V

DDA2

, and V

8-channel analog inputs for Sample-and-Hold B. The ADC pins should not be driven before the V pins have been fully powered up.

DDA1

, V

DDA2

, and V

ADC Voltage Reference Output (2 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. [Can accept external reference input (2 V) if the software bit is enabled for this mode. 1–10 µF low ESR capacitor can be used in the external reference mode.] NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.

ADC Voltage Reference Output (1 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground. [Can accept external reference input (1 V) if the software bit is enabled for this mode. 1–10 µF low ESR capacitor can be used in the external reference mode.] NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.

www.ti.com

DDAIO

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

ADCRESEXT F2 16 16 O –

ADCBGREFIN E6 164 116 – – AVSSREFBG E3 12 12 – – ADC Analog GND

AVDDREFBG E1 13 13 – – ADC Analog Power (3.3-V) ADCLO B3 175 127 – – V

SSA1

SSA2

DDA1

DDA2

SS1

DD1

DDAIO

SSAIO

F3 15 15 – – ADC Analog GND C5 165 117 – – ADC Analog GND F4 14 14 – – ADC Analog 3.3-V Supply A5 166 118 – – ADC Analog 3.3-V Supply C6 163 115 – – ADC Digital GND A6 162 114 – – ADC Digital 1.8-V (or 1.9-V) Supply B2 1 1 – – 3.3-V Analog I/O Power Pin A2 176 128 – – Analog I/O Ground Pin

POWER SIGNALS

H1 23 20 – –

L1 37 29 – – P5 56 42 – – P9 75 56 – –

P12 – 63 – – K12 100 74 – – G12 112 82 – – C14 128 94 – – B10 143 102 – –

C8 154 110 – – G4 19 17 – – K1 32 26 – –

L2 38 30 – – P4 52 39 – – K6 58 – – – P8 70 53 – –

M10 78 59 – –

L11 86 62 – –

K13 99 73 – –

J14 105 – – – G13 113 – – – E14 120 88 – – B14 129 95 – – D10 142 – – – C10 – 103 – –

B8 153 109 – –

(2)

PU/PD

(3)

DESCRIPTION

ADC External Current Bias Resistor. Use 24.9 kΩ ± 5% for ADC clock range

1–18.75 MHz; use 20 kΩ ± 5% for ADC clock range 18.75 MHz–25 MHz.

Test Pin. Reserved for TI. Must be left unconnected.

Common Low Side Analog Input. Connect to analog ground.

1.8-V or 1.9-V Core Digital Power Pins. See

Section 6.2, Recommended Operating

Conditions, for voltage requirements.

Core and Digital I/O Ground Pins

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

DDIO

DD3VFL

J4 31 25 – – L7 64 49 – –

L10 81 – – – N14 – – – – G11 114 83 – –

E9 145 104 – –

N8 69 52 – –

GPIO OR PERIPHERAL SIGNALS

GPIOA OR EVA SIGNALS

GPIOA0 - PWM1 (O) M12 92 68 I/O PU GPIO or PWM Output Pin #1 GPIOA1 - PWM2 (O) M14 93 69 I/O PU GPIO or PWM Output Pin #2 GPIOA2 - PWM3 (O) L12 94 70 I/O PU GPIO or PWM Output Pin #3 GPIOA3 - PWM4 (O) L13 95 71 I/O PU GPIO or PWM Output Pin #4 GPIOA4 - PWM5 (O) K11 98 72 I/O PU GPIO or PWM Output Pin #5 GPIOA5 - PWM6 (O) K14 101 75 I/O PU GPIO or PWM Output Pin #6 GPIOA6 -

T1PWM_T1CMP (I) GPIOA7 -

T2PWM_T2CMP (I)

J11 102 76 I/O PU GPIO or Timer 1 Output

J13 104 77 I/O PU GPIO or Timer 2 Output

GPIOA8 - CAP1_QEP1 (I) H10 106 78 I/O PU GPIO or Capture Input #1 GPIOA9 - CAP2_QEP2 (I) H11 107 79 I/O PU GPIO or Capture Input #2 GPIOA10 - CAP3_QEPI1 (I) H12 109 80 I/O PU GPIO or Capture Input #3 GPIOA11 - TDIRA (I) F14 116 85 I/O PU GPIO or Timer Direction GPIOA12 - TCLKINA (I) F13 117 86 I/O PU GPIO or Timer Clock Input GPIOA13 - C1TRIP (I) E13 122 89 I/O PU GPIO or Compare 1 Output Trip GPIOA14 - C2TRIP (I) E11 123 90 I/O PU GPIO or Compare 2 Output Trip GPIOA15 - C3TRIP (I) F10 124 91 I/O PU GPIO or Compare 3 Output Trip

GPIOB OR EVB SIGNALS

GPIOB0 - PWM7 (O) N2 45 33 I/O PU GPIO or PWM Output Pin #7 GPIOB1 - PWM8 (O) P2 46 34 I/O PU GPIO or PWM Output Pin #8 GPIOB2 - PWM9 (O) N3 47 35 I/O PU GPIO or PWM Output Pin #9 GPIOB3 - PWM10 (O) P3 48 36 I/O PU GPIO or PWM Output Pin #10 GPIOB4 - PWM11 (O) L4 49 37 I/O PU GPIO or PWM Output Pin #11 GPIOB5 - PWM12 (O) M4 50 38 I/O PU GPIO or PWM Output Pin #12 GPIOB6 -

T3PWM_T3CMP (I) GPIOB7 -

T4PWM_T4CMP (I)

K5 53 40 I/O PU GPIO or Timer 3 Output

N5 55 41 I/O PU GPIO or Timer 4 Output

GPIOB8 - CAP4_QEP3 (I) M5 57 43 I/O PU GPIO or Capture Input #4 GPIOB9 - CAP5_QEP4 (I) M6 59 44 I/O PU GPIO or Capture Input #5 GPIOB10 - CAP6_QEPI2 (I) P6 60 45 I/O PU GPIO or Capture Input #6 GPIOB11 - TDIRB (I) L8 71 54 I/O PU GPIO or Timer Direction GPIOB12 - TCLKINB (I) K8 72 55 I/O PU GPIO or Timer Clock Input

(2)

PU/PD

(3)

DESCRIPTION

3 3-V I/O Digital Power Pins

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met. This pin is used as V and must be connected to 3.3 V in ROM parts

DDIO

as well.

www.ti.com

in ROM parts

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

GPIOB13 - C4TRIP (I) N6 61 46 I/O PU GPIO or Compare 4 Output Trip GPIOB14 - C5TRIP (I) L6 62 47 I/O PU GPIO or Compare 5 Output Trip GPIOB15 - C6TRIP (I) K7 63 48 I/O PU GPIO or Compare 6 Output Trip

GPIOD0 T1CTRIP_PDPINTA (I)

GPIOD1 - GPIO or Timer 2 Compare Output Trip or T2CTRIP/EVASOC (I) External ADC Start-of-Conversion EV-A

GPIOD5 T3CTRIP_PDPINTB (I)

GPIOD6 - GPIO or Timer 4 Compare Output Trip or T4CTRIP/EVBSOC (I) External ADC Start-of-Conversion EV-B

GPIOE0 - XINT1_XBIO (I) D9 149 106 I/O/Z – GPIO or XINT1 or XBIO input GPIOE1 -

XINT2_ADCSOC (I) GPIOE2 - XNMI_XINT13 (I) E8 150 107 I/O PU GPIO or XNMI or XINT13

GPIOF0 - SPISIMOA (O) M1 40 31 I/O/Z – GPIO or SPI slave in, master out GPIOF1 - SPISOMIA (I) N1 41 32 I/O/Z – GPIO or SPI slave out, master in GPIOF2 - SPICLKA (I/O) K2 34 27 I/O/Z – GPIO or SPI clock GPIOF3 - SPISTEA (I/O) K4 35 28 I/O/Z – GPIO or SPI slave transmit enable

GPIOF4 - SCITXDA (O) C7 155 111 I/O PU GPIO or SCI asynchronous serial port TX data GPIOF5 - SCIRXDA (I) A7 157 112 I/O PU GPIO or SCI asynchronous serial port RX data

GPIOF6 - CANTXA (O) N12 87 64 I/O PU GPIO or eCAN transmit data GPIOF7 - CANRXA (I) N13 89 65 I/O PU GPIO or eCAN receive data

GPIOF8 - MCLKXA (I/O) J1 28 23 I/O PU GPIO or McBSP transmit clock GPIOF9 - MCLKRA (I/O) H2 25 21 I/O PU GPIO or McBSP receive clock GPIOF10 - MFSXA (I/O) H4 26 22 I/O PU GPIO or McBSP transmit frame synch GPIOF11 - MFSRA (I/O) J2 29 24 I/O PU GPIO or McBSP receive frame synch GPIOF12 - MDXA (O) G1 22 19 I/O – GPIO or McBSP transmitted serial data GPIOF13 - MDRA (I) G2 20 18 I/O PU GPIO or McBSP received serial data

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

GPIOD OR EVA SIGNALS

H14 110 81 I/O PU GPIO or Timer 1 Compare Output Trip

G10 115 84 I/O PU

GPIOD OR EVB SIGNALS

P10 79 60 I/O PU GPIO or Timer 3 Compare Output Trip

P11 83 61 I/O PU

GPIOE OR INTERRUPT SIGNALS

D8 151 108 I/O/Z – GPIO or XINT2 or ADC start-of-conversion

GPIOF OR SPI SIGNALS

GPIOF OR SCI-A SIGNALS

GPIOF OR CAN SIGNALS

GPIOF OR McBSP SIGNALS

(2)

PU/PD

(3)

DESCRIPTION

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME I/O/Z

GPIOF14 XF_XPLLDIS (O)

GPIOG4 - SCITXDB (O) P14 90 66 I/O/Z –

GPIOG5 - SCIRXDB (I) M13 91 67 I/O/Z –

179-BALL 176-PIN 128-PIN GHH/ZHH PGF PBK

GPIOF OR XF CPU OUTPUT SIGNAL

A11 140 101 I/O PU

GPIOG OR SCI-B SIGNALS

(2)

PU/PD

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with the 3.3-V supply.

(3)

This pin has three functions:

1. XF – General-purpose output pin.

2. XPLLDIS – This pin is sampled during reset to check whether the PLL must be disabled. The PLL will be disabled if this pin is sensed low. HALT and STANDBY modes cannot be used when the PLL is disabled.

3. GPIO – GPIO function

GPIO or SCI asynchronous serial port transmit data

GPIO or SCI asynchronous serial port receive data

DESCRIPTION

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

INT[12:1]

CLKIN

Real-Time JTAG

Peripheral Bus

C28x CPU

INT14

NMI

INT13

Memory Bus

Flash 128K x 16 (F2812) 128K x 16 (F2811)

64K x 16 (F2810)

eCAN

SCIA/SCIB

12-Bit ADC

External Interrupt

Control

(XINT1/2/13, XNMI)

EVA/EVB

Memory Bus

OTP

1K x 16

(C)

McBSP

System Control

(Oscillator and PLL

Peripheral Clocking

Low-Power Modes

Watchdog)

FIFO

PIE

(96 Interrupts)

(A)

SPI

FIFO

TINT0

TINT1

TINT2

CPU-Timer 0

CPU-Timer 1

CPU-Timer 2

16 Channels

GPIO Pins

XRS

X1/XCLKIN

XF_XPLLDIS

Protected by the code-security module.

XINT13

M U

XNMI

ROM

128K x 16 (C2812) 128K x 16 (C2811)

64K x 16 (C2810)

Control

Address (19)

Data (16)

External

Interface

(XINTF)

(B)

L0 SARAM

4K x 16

L1 SARAM

4K x 16

M1 SARAM

1K x 16

M0 SARAM

1K x 16

H0 SARAM

8K x 16

Boot ROM

4K x 16

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3 Functional Overview

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. 45 of the possible 96 interrupts are used on the devices. B. XINTF is available on the F2812 and C2812 devices only. C. On C281x devices, the OTP is replaced with a 1K x 16 block of ROM.

Figure 3-1. Functional Block Diagram

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

XINTF Vector - RAM (32 x 32)

(Enabled if VMAP = 1, MP/ = 1, ENPIE = 0)MC

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (128K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8 0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

Data Space

Prog Space

XINTF Zone 0 (8K x 16, )XZCS0AND1

XINTF Zone 1 (8K x 16, ) (Protected)XZCS0AND1

XINTF Zone 2 (0.5M x 16, )XZCS2

XINTF Zone 6 (0.5M x 16, )XZCS6AND7

XINTF Zone 7 (16K x 16, )

(Enabled if MP/ = 1)

XZCS6AND7

On-Chip Memory External Memory XINTF

Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.

LEGEND:

0x08 0000

0x00 4000

0x10 0000

0x18 0000

0x3F C000

0x00 2000

0x3D 8000

Reserved

Reserved (1K)

Reserved

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.1 Memory Map

www.ti.com

A. Memory blocks are not to scale. B. Reserved locations are reserved for future expansion. Application should not access these areas. C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both. D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order. F. Certain memory ranges are EALLOW protected against spurious writes after configuration. G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

User program cannot access these memory maps in program space.

Figure 3-2. F2812/C2812 Memory Map

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

LEGEND:

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (128K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

On-Chip Memory

0x3D 8000

Reserved

Reserved (1K)

Reserved

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. Memory blocks are not to scale. B. Reserved locations are reserved for future expansion. Application should not access these areas. C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space. D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order. E. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-3. F2811/C2811 Memory Map

Submit Documentation Feedback

Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.

LEGEND:

Block

Start Address

Low 64K

(24x/240x Equivalent Data Space)

High 64K

(24x/240x Equivalent

Program Space)

0x00 0000

M0 Vector - RAM (32 x 32)

(Enabled if VMAP = 0)

BROM Vector - ROM (32 x 32)

(Enabled if VMAP = 1, MP/ = 0, ENPIE = 0)MC

Data Space

Prog Space

M0 SARAM (1K x 16)

M1 SARAM (1K x 16)

Peripheral Frame 0

0x00 0040

0x00 0400

0x00 0800

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

L0 SARAM (4K x 16, Secure Block)

Peripheral Frame 1

(Protected)

Peripheral Frame 2

(Protected)

L1 SARAM (4K x 16, Secure Block)

OTP (or ROM) (1K x 16, Secure Block)

Flash (or ROM) (64K x 16, Secure Block)

128-Bit Password

H0 SARAM (8K x 16)

Boot ROM (4K x 16)

(Enabled if MP/ = 0)MC

0x00 0D00

0x00 0E00

0x00 2000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

On-Chip Memory

0x3E 8000

Reserved

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-4. F2810/C2810 Memory Map

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 3-1. Addresses of Flash Sectors in F2812 and F2811

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000 0x3D 9FFF

0x3D A000

0x3D BFFF

0x3D C000

0x3D FFFF

0x3E 0000 0x3E 3FFF

0x3E 4000 0x3E 7FFF

0x3E 8000

0x3E BFFF

0x3E C000 0x3E FFFF

0x3F 0000 0x3F 3FFF

0x3F 4000 0x3F 5FFF

0x3F 6000 Sector A, 8K x 16 0x3F 7F80 Program to 0x0000 when using the

0x3F 7FF5 Code Security Module 0x3F 7FF6 Boot-to-Flash (or ROM) Entry Point

0x3F 7FF7 (program branch instruction here) 0x3F 7FF8 Security Password (128-Bit)

0x3F 7FFF (Do not program to all zeros)

Sector J, 8K x 16

Sector I, 8K x 16

Sector H, 16K x 16

Sector G, 16K x 16

Sector F, 16K x 16

Sector E, 16K x 16

Sector D, 16K x 16

Sector C, 16K x 16

Sector B, 8K x 16

Table 3-2. Addresses of Flash Sectors in F2810

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3E 8000

0x3E BFFF

0x3E C000 0x3E FFFF

0x3F 0000 0x3F 3FFF

0x3F 4000 0x3F 5FFF

0x3F 6000 Sector A, 8K x 16 0x3F 7F80 Program to 0x0000 when using the

0x3F 7FF5 Code Security Module 0x3F 7FF6 Boot-to-Flash (or ROM) Entry Point

0x3F 7FF7 (program branch instruction here) 0x3F 7FF8 Security Password (128-Bit)

0x3F 7FFF (Do not program to all zeros)

Sector E, 16K x 16

Sector D, 16K x 16

Sector C, 16K x 16

Sector B, 8K x 16

The “Low 64K” of the memory address range maps into the data space of the 240x. The “High 64K” of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will execute only from the “High 64K”memory area. Hence, the top 32K of Flash/ROM and H0 SARAM block can be used to run 24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7 (if MP/MC mode is high).

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.

The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select (XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected to make sure that operations occur as written (the penalty is extra cycles that are added to align the operations). This mode is programmable and, by default, it will protect the selected zones.

On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/MC.

www.ti.com

NOTE

I/O space is not supported on the 2812 XINTF. The wait states for the various spaces in the memory map area are listed in Table 3-3.

Table 3-3. Wait States

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed Peripheral Frame 1 Fixed

Peripheral Frame 2 Fixed

L0 and L1 SARAMs 0-wait Fixed

OTP (or ROM) reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more

Flash (or ROM) reduced CPU frequency. The CSM password locations are hardwired for

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

XINTF Cycles can be extended by external memory or peripheral.

0-wait (writes) 2-wait (reads)

Programmable,

1-wait minimum

Programmable,

0-wait minimum

Programmable,

1-wait minimum

Programmed via the Flash registers. 1-wait-state operation is possible at a information.

Programmed via the Flash registers. 0-wait-state operation is possible at 16 wait states. See Section 3.2.6, Flash (F281x Only), for more information.

Programmed via the XINTF registers. 0-wait operation is not possible.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software investment. Additionally, the C28x is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be summarized as follows:

SPRS174S–APRIL 2001–REVISED MARCH 2011

Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments ( TI™) DSP family of devices, the F281x and C281x adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the F281x and C281x. One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

3.2.4 Real-Time JTAG and Analysis

The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F281x and C281x support real-time mode of operation whereby the contents of memory, peripheral, and register locations can be modified while the processor is running and executing code and servicing interrupts. The

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F281x and C281x implement the real-time mode in hardware within the CPU. This is a unique feature to the F281x and C281x, no software monitor is required. Additionally, special analysis hardware is provided that allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs.

3.2.5 External Interface (XINTF) (2812 Only)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals.

3.2.6 Flash (F281x Only)

The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four 8K x 16 sectors, and six 16K x 16 sectors. The F2810 has 64K x 16 of embedded flash, segregated into two 8K x 16 sectors, and three 16K x 16 sectors. All three devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800–0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information.

www.ti.com

The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).

3.2.7 ROM (C281x Only)

The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In addition to this, there is a 1K x 16 ROM block that replaces the OTP memory available in flash devices. For information on how to submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide (literature number SPRU430).

3.2.8 M0, M1 SARAMs

All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks and hence the mapping of data variables on the 240x devices can remain at the same physical address on C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages.

NOTE

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.2.9 L0, L1, H0 SARAMs

The F281x and C281x contain an additional 16K x 16 of single-access RAM, divided into three blocks (4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both program and data space.

3.2.10 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can select to execute code already present in the internal Flash or download new software to internal RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-4 shows the details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide (literature number SPRU095), for more information.

Table 3-4. Boot Mode Selection

BOOT MODE SELECTED

GPIO PU status Jump to Flash/ROM address 0x3F 7FF6.

A branch instruction must have been programmed here prior to 1 x x x reset to re-direct code execution as desired.

Call SPI_Boot to load from an external serial SPI EEPROM 0 1 x x Call SCI_Boot to load from SCI-A 0 0 1 1 Jump to H0 SARAM address 0x3F 8000 0 0 1 0 Jump to OTP address 0x3D 7800 0 0 0 1 Call Parallel_Boot to load from GPIO Port B 0 0 0 0

(1) Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic. (2) If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader. (3) PU = pin has an internal pullup. No PU = pin does not have an internal pullup.

(3)

GPIOF4 GPIOF12 GPIOF3 GPIOF2

(SCITXDA) (MDXA) (SPISTEA) (SPICLK)

PU No PU No PU No PU

(1)(2)

3.2.11 Security

The F281x and C281x support high levels of security to protect the user firmware from being reverse-engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/ROM/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which matches the value stored in the password locations within the Flash/ROM.

NOTE

• When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data.

• On ROM devices, addresses 0x3F 7FF2–0x3F 7FF5 and 0x3D 7BFC–0x3D 7BFF are reserved for TI, irrespective of whether code security has been used or not. User application should not use these locations in any way.

• The 128-bit password (at 0x3F 7FF8–0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Table 3-5. Impact of Using the Code Security Module

ADDRESS

0x3F 7F80 – 0x3F 7FEF 0x3F 7FF0 – 0x3F 7FF5

0x3D 7BFC – 0x3D 7BFF Application code and data

(1) See the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature

number SPRZ193) for some restrictions.

Code Security Enabled Code Security Disabled

Fill with 0x0000 Application code and data

CODE SECURITY STATUS

(1)

Disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANT ABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

3.2.12 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F281x and C281x, 45 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI)

The F281x and C281x support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free-running up-counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the interrupt.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3.2.14 Oscillator and PLL

The F281x and C281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to Section 6, Electrical Specifications, for timing details. The PLL block can be set in bypass mode.

3.2.15 Watchdog

The F281x and C281x support a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be disabled if necessary.

3.2.16 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.17 Low-Power Modes

The F281x and C281x devices are fully static CMOS devices. Three low-power modes are provided:

SPRS174S–APRIL 2001–REVISED MARCH 2011

IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only

those peripherals that must function during IDLE are left operating. An enabled interrupt from an active peripheral will wake the processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event.

HALT: Turns off the internal oscillator. This mode basically shuts down the device and places it

in the lowest possible power consumption mode. Only a reset or XNMI can wake the device from this mode.

3.2.18 Peripheral Frames 0, 1, 2 (PFn)

The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0: XINTF: External Interface Configuration Registers (2812 only)

PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Control, Programming, Erase, Verify Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers

PF1: eCAN: eCAN Mailbox and Control Registers PF2: SYS: System Control Registers

GPIO: GPIO Mux Configuration and Control Registers EV: Event Manager (EVA/EVB) Control Registers McBSP: McBSP Control and TX/RX Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Peripheral Interface (SPI) Control and RX/TX Registers ADC: 12-Bit ADC Registers

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.

3.2.20 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.21 Control Peripherals

The F281x and C281x support the following peripherals that are used for embedded control and communication:

EV: The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. The event managers on the F281x and C281x are compatible to the event managers on the 240x devices (with some minor enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

www.ti.com

3.2.22 Serial Port Peripherals

The F281x and C281x support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality

codecs for modem applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported by a 16-level FIFO that significantly reduces the overhead for servicing this peripheral.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the F281x and C281x, the port supports a 16-level, receive-and-transmit FIFO for reducing servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the F281x and C281x, the port supports a 16-level, receive-and-transmit FIFO for reducing servicing overhead.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.3 Register Map

The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 3-6.

Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus.

See Table 3-7.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus.

See Table 3-8.

Table 3-6. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Device Emulation Registers 0x00 0880 – 0x00 09FF 384 EALLOW protected Reserved 0x00 0A00 – 0x00 0A7F 128

FLASH Registers Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 EALLOW protected

Reserved 0x00 0AF0 – 0x00 0B1F 48 XINTF Registers 0x00 0B20 – 0x00 0B3F 32 Not EALLOW protected Reserved 0x00 0B40 – 0x00 0BFF 192 CPU-TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 Not EALLOW protected Reserved 0x00 0C40 – 0x00 0CDF 160 PIE Registers 0x00 0CE0 – 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 EALLOW protected Reserved 0x00 0E00 – 0x00 0FFF 512

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS

instruction disables writes. This prevents stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

(3)

0x00 0A80 – 0x00 0ADF 96

(1)

(2)

EALLOW protected CSM Protected

Table 3-7. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

eCAN Registers 0x00 6000 – 0x00 60FF

eCAN Mailbox RAM 0x00 6100 – 0x00 61FF Not EALLOW-protected Reserved 0x00 6200 – 0x00 6FFF 3584

(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

256 Some eCAN control registers (and selected bits in

(128 x 32) other eCAN control registers) are EALLOW-protected.

256

(128 x 32)

(1)

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 3-8. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Reserved 0x00 7000 – 0x00 700F 16 System Control Registers 0x00 7010 – 0x00 702F 32 EALLOW Protected Reserved 0x00 7030 – 0x00 703F 16 SPI-A Registers 0x00 7040 – 0x00 704F 16 Not EALLOW Protected SCI-A Registers 0x00 7050 – 0x00 705F 16 Not EALLOW Protected Reserved 0x00 7060 – 0x00 706F 16 External Interrupt Registers 0x00 7070 – 0x00 707F 16 Not EALLOW Protected Reserved 0x00 7080 – 0x00 70BF 64 GPIO Mux Registers 0x00 70C0 – 0x00 70DF 32 EALLOW Protected GPIO Data Registers 0x00 70E0 – 0x00 70FF 32 Not EALLOW Protected ADC Registers 0x00 7100 – 0x00 711F 32 Not EALLOW Protected Reserved 0x00 7120 – 0x00 73FF 736 EV-A Registers 0x00 7400 – 0x00 743F 64 Not EALLOW Protected Reserved 0x00 7440 – 0x00 74FF 192 EV-B Registers 0x00 7500 – 0x00 753F 64 Not EALLOW Protected Reserved 0x00 7540 – 0x00 774F 528 SCI-B Registers 0x00 7750 – 0x00 775F 16 Not EALLOW Protected Reserved 0x00 7760 – 0x00 77FF 160 McBSP Registers 0x00 7800 – 0x00 783F 64 Not EALLOW Protected Reserved 0x00 7840 – 0x00 7FFF 1984

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).

(1)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-9.

Table 3-9. Device Emulation Registers

NAME ADDRESS RANGE DESCRIPTION

DEVICECNF 0x00 0880 – 0x00 0881 2 Device Configuration Register PARTID 0x00 0882 1 Part ID Register

REVID 0x00 0883 1 Revision ID Register 0x0004 – Reserved

PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protection Range Address Register Reserved 0x00 0886 – 0x00 09FF 378

SIZE (x16)

0x0001 or 0x0002 – F281x 0x0003 – C281x

0x0001 – Silicon Revision A 0x0002 – Silicon Revision B 0x0003 – Silicon Revisions C, D

0x0005 – Silicon Revision E 0x0006 – Silicon Revision F 0x0007 – Silicon Revision G

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

XD[15:0]

XA[18:0]

XZCS6

XZCS7

XZCS6AND7

XZCS2

XWE

XR/W

XREADY

XMP/MC

XHOLD

XHOLDA

XCLKOUT

(E)

XRD

XINTF Zone 0

(8K x 16)

XINTF Zone 1

(8K x 16)

XINTF Zone 2

(512K x 16)

XINTF Zone 6

(512K x 16)

XINTF Zone 7

(16K x 16)

(mapped here if MP/ = 1)MC

0x40 0000

0x3F C000

0x18 0000

0x10 0000

0x00 6000

0x00 4000

0x00 2000

0x00 0000

Data Space

Prog Space

0x08 0000

XZCS0AND1

XZCS0 XZCS1

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.5 External Interface, XINTF (2812 Only)

This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 devices.

The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The external interface on the 2812 is mapped into five fixed zones shown in Figure 3-5.

Figure 3-5 shows the 2812 XINTF signals.

www.ti.com

A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of

XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled.

B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip

selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals.

C. The chip selects for Zone 0 and Zone 1 are ANDed internally together to form one chip select (XZCS0AND1). Any

external memory that is connected to XZCS0AND1 is dually mapped to both Zone 0 and Zone 1.

D. The chip selects for Zone 6 and Zone 7 are ANDed internally together to form one chip select (XZCS6AND7). Any

external memory that is connected to XZCS6AND7 is dually mapped to both Zone 6 and Zone 7. This means that if Zone 7 is disabled (via the MP/MC mode), then any external memory is still accessible via Zone 6 address space.

E. XCLKOUT is also pinned out on the 2810 and 2811.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-5. External Interface Block Diagram

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

The operation and timing of the external interface, can be controlled by the registers listed in Table 3-10.

Table 3-10. XINTF Configuration and Control Register Mappings

NAME ADDRESS DESCRIPTION

XTIMING0 0x00 0B20 2 XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register. XTIMING1 0x00 0B22 2 XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register. XTIMING2 0x00 0B24 2 XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register. XTIMING6 0x00 0B2C 2 XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register. XTIMING7 0x00 0B2E 2 XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register. XINTCNF2 0x00 0B34 2 XINTF Configuration Register can access as two 16-bit registers or one 32-bit register. XBANK 0x00 0B38 1 XINTF Bank Control Register XREVISION 0x00 0B3A 1 XINTF Revision Register

SIZE

(x16)

3.5.1 Timing Registers

XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. The XINTF timing parameters can be configured individually for each zone based on the requirements of the memory or peripheral accessed by that particular zone. This allows the programmer to maximize the efficiency of the bus on a per-zone basis. All XINTF timing values are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6-30.

For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x DSP External Interface (XINTF) Reference Guide (literature number SPRU067).

3.5.2 XREVISION Register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the product. For the 2812, this register will be configured as described in Table 3-11.

Table 3-11. XREVISION Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

15–0 REVISION R 0x0004

Current XINTF Revision. For internal use/reference. Test purposes only. Subject to change.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

PIE

96 Interrupts

(A)

TIMER 2

(Reserved for DSP/BIOS)

TIMER 0

Watchdog

Peripherals

(SPI, SCI, McBSP, CAN, EV, ADC)

(41 Interrupts)

TINT0

Interrupt Control

XNMICR[15:0]

XINT1

Interrupt Control

XINT1CR[15:0]

XINT2

Interrupt Control

XINT2CR[15:0]

GPIO

MUX

WDINT

C28x CPU

INT1

INT12

INT13

INT14

NMI

XINT1CTR[15:0]

XINT2CTR[15:0]

XNMICTR[15:0]

TIMER 1

TINT2

Low-Power Modes

LPMINT

WAKEINT

XNMI_XINT13

MUX

TINT1

enable

select

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.6 Interrupts

Figure 3-6 shows how the various interrupt sources are multiplexed within the F281x and C281x devices.

www.ti.com

A. Out of a possible 96 interrupts, 45 are currently used by peripherals.

Figure 3-6. Interrupt Sources

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F281x and C281x, 45 of these are used by peripherals as shown in Table 3-12.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx[8:1] PIEIFRx[8:1]

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals

External

Interrupts

(Enable) (Flag)

IER[12:1]IFR[12:1]

Global

Enable

INTM

PIEACKx

(Enable/Flag)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 3-7. Multiplexing of Interrupts Using the PIE Block

Table 3-12. PIE Peripheral Interrupts

CPU

INTERRUPTS

INT1 XINT2 XINT1 Reserved

INT2 Reserved

INT3 Reserved

INT4 Reserved

INT5 Reserved

INT6 Reserved Reserved Reserved Reserved INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT9 Reserved Reserved

INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

(1) Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

• No peripheral within the group is asserting interrupts.

• No peripheral interrupts are assigned to the group (example PIE group 12).

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT PDPINTB PDPINTA (LPM/WD) (TIMER 0) (ADC) (EV-B) (EV-A)

T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT

(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)

CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT

(EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A) (EV-A)

T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT

(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)

CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT

(EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B) (EV-B)

MXINT MRINT SPITXINTA SPIRXINTA

(McBSP) (McBSP) (SPI) (SPI)

ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN) (CAN) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

Submit Documentation Feedback

PIE INTERRUPTS

(1)

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 3-13. PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

PIECTRL 0x0000 0CE0 1 PIE, Control Register PIEACK 0x0000 0CE1 1 PIE, Acknowledge Register PIEIER1 0x0000 0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0000 0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0000 0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0000 0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0000 0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0000 0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0000 0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0000 0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0000 0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0000 0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0000 0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0000 0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0000 0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0000 0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0000 0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0000 0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0000 0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0000 0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0000 0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0000 0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0000 0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0000 0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0000 0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0000 0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0000 0CFA – 0x0000 0CFF 6 Reserved

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.

(1)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.6.1 External Interrupts

Table 3-14. External Interrupts Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XINT1CR 0x00 7070 1 XINT1 control register XINT2CR 0x00 7071 1 XINT2 control register Reserved 0x00 7072 – 0x00 7076 5 XNMICR 0x00 7077 1 XNMI control register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register Reserved 0x00 707A – 0x00 707E 5 XNMICTR 0x00 707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

HSPCLK

PLL

X1/XCLKIN

Power

Modes

Control

Watchdog

Block

C28x CPU

High-Speed Peripherals

EV-A/B

High-Speed Prescaler

Low-Speed Prescaler

Clock Enables

System Control

Registers

Peripheral

Registers

XF_XPLLDIS

ADC

Registers

12-Bit ADC

16 ADC Inputs

HSPCLK

LSPCLK

Peripheral Reset

SYSCLKOUT

XRS

Reset

Peripheral Bus

GPIO

MUX

GPIOs

I/O

OSC

CLKIN

(A)

Low-Speed Peripherals

SCI-A/B, SPI, McBSP

Peripheral

Registers

eCAN

Peripheral

Registers

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.7 System Control

This section describes the F281x and C281x oscillator, PLL and clocking mechanisms, the watchdog function and the low-power modes. Figure 3-8 shows the various clock and reset domains in the F281x and C281x devices that will be discussed.

www.ti.com

A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 3-8. Clock and Reset Domains

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15.

Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

Reserved 0x00 7010 – 0x00 7017 8 Reserved 0x00 7018 1 Reserved 0x00 7019 1

HISPCP 0x00 701A 1

LOSPCP 0x00 701B 1 PCLKCR 0x00 701C 1 Peripheral Clock Control Register

Reserved 0x00 701D 1 LPMCR0 0x00 701E 1 Low-Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low-Power Mode Control Register 1 Reserved 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register Reserved 0x00 7024 1 WDKEY 0x00 7025 1 Watchdog Reset Key Register Reserved 0x00 7026 – 0x00 7028 3 WDCR 0x00 7029 1 Watchdog Control Register Reserved 0x00 702A – 0x00 702F 6

(1) All of the above registers can only be accessed by executing the EALLOW instruction. (2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)

will not reset PLLCR.

High-Speed Peripheral Clock Prescaler Register for HSPCLK clock

Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock

(2)

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

X1/XCLKIN

On-Chip

Oscillator

(OSC)

PLL

Bypass

XF_XPLLDIS

OSCCLK (PLL Disabled)

Latch

XPLLDIS

XRS

PLL

4-Bit PLL Select

SYSCLKOUT

CLKIN

CPU

4-Bit PLL Select

XCLKIN

PLL Block

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.8 OSC and PLL Block

Figure 3-9 shows the OSC and PLL block on the F281x and C281x.

www.ti.com

Figure 3-9. OSC and PLL Block

The on-chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the X1/XCLKIN and X2 pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and the X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0] set the clocking ratio.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 3-16. PLLCR Register Bit Definitions

BIT(S) NAME TYPE DESCRIPTION

15:4 Reserved R = 0 0:0

3:0 DIV R/W 0,0,0,0

(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is

not changed.

XRS

RESET

(1)

SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.

Bit Value n SYSCLKOUT

0000 PLL Bypassed XCLKIN/2 0001 1 XCLKIN/2 0010 2 XCLKIN 0011 3 XCLKIN * 1.5 0100 4 XCLKIN * 2 0101 5 XCLKIN * 2.5 0110 6 XCLKIN * 3 0111 7 XCLKIN * 3.5 1000 8 XCLKIN * 4 1001 9 XCLKIN * 4.5 1010 10 XCLKIN * 5 1011 11 Reserved 1100 12 Reserved 1101 13 Reserved 1110 14 Reserved 1111 15 Reserved

3.8.1 Loss of Input Clock

In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical frequency of 1–4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to work.

Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing (i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

Applications in which the correct CPU operating frequency is absolutely critical must implement a mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the V

DD3VFL

NOTE

rail.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

(A)

X1/XCLKIN

Crystal

(a) (b)

External Clock Signal

(Toggling 0-V )

X1/XCLKIN

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

3.9 PLL-Based Clock Module

The F281x and C281x have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 XCLKIN cycles.

The PLL-based clock module provides two modes of operation:

• Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation: This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1/XCLKIN pin.

A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the

DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range.

Figure 3-10. Recommended Crystal/Clock Connection

www.ti.com

Table 3-17. Possible PLL Configuration Modes

PLL MODE REMARKS SYSCLKOUT

PLL Disabled Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the XCLKIN

PLL Bypassed bypassed. However, the /2 module in the PLL block divides the clock input at the XCLKIN/2

PLL Enabled (XCLKIN * n) / 2

Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled. X1/XCLKIN pin.

Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is X1/XCLKIN pin by two before feeding it to the CPU.

Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the PLL block now divides the output of the PLL by two before feeding it to the CPU.

3.10 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:

• Fundamental mode, parallel resonant

• CL(load capacitance) = 12 pF

• CL1= CL2= 24 pF

• C

• ESR range = 25 to 40 Ω

shunt

= 6 pF

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

/512

OSCCLK

WDCR (WDPS[2:0])

WDCLK

WDCNTR[7:0]

WDKEY[7:0]

Good Key

Bad Key

WDCR (WDCHK[2:0])

Bad

WDCHK

Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

3.11 Watchdog Block

The watchdog block on the F281x and C281x is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. TheWDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-11. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See

Section 3.12, Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so is the WATCHDOG.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

3.12 Low-Power Modes Block

The low-power modes on the F281x and C281x are similar to the 240x devices. Table 3-18 summarizes the various modes.

Table 3-18. F281x and C281x Low-Power Modes

XRS,

WDINT,

XNMI,

Debugger

XRS,

WDINT,

XINT1,

XNMI,

SCIRXDA, SCIRXDB,

CANRX,

Debugger

(1)

(3)

MODE LPM[1:0] OSCCLK CLKIN SYSCLKOUT EXIT

Normal X,X on on on –

IDLE 0,0 on on on

STANDBY 0,1 off off

HALT 1,X (oscillator and PLL turned off, off off XNMI,

(1) The Exit column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals, will

exit the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode will not be exited and the device will go back into the indicated low-power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is

still functional; while on the 24x/240x, the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

(watchdog still running) C1/2/3/4/5/6TRIP,

watchdog not functional) Debugger

on T1/2/3/4CTRIP,

off XRS,

(2)

Any Enabled Interrupt,

The various low-power modes operate as follows:

IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized

by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode All other signals (including XNMI) will wake the device from STANDBY

mode if selected by the LPMCR1 register. The user will need to select which signal(s) will wake the device. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode Only the XRS and XNMI external signals can wake the device from HALT

mode. The XNMI input to the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them when the IDLE instruction was executed.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

4 Peripherals

The integrated peripherals of the F281x and C281x are described in the following subsections:

• Three 32-bit CPU-Timers

• Two event-manager modules (EVA, EVB)

• Enhanced analog-to-digital converter (ADC) module

• Enhanced controller area network (eCAN) module

• Multichannel buffered serial port (McBSP) module

• Serial communications interface modules (SCI-A, SCI-B)

• Serial peripheral interface (SPI) module

• Digital I/O and shared pin functions

4.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F281x and C281x devices (CPU-TIMER0/1/2). Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.

These timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB).

If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

SPRS174S–APRIL 2001–REVISED MARCH 2011

NOTE

Figure 4-1. CPU-Timers

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

INT1

INT12

INT14

C28x

CPU

TINT2

TINT0

PIE

CPU-TIMER 2 (Reserved for

DSP/BIOS)

INT13

TINT1

XINT13

CPU-TIMER 0

CPU-TIMER 1

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

In the F281x and C281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-2.

A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-2. CPU-Timer Interrupts Signals and Output Signal

www.ti.com

The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x00 0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x00 0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x00 0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x00 0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x00 0C04 1 CPU-Timer 0, Control Register Reserved 0x00 0C05 1 TIMER0TPR 0x00 0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x00 0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x00 0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x00 0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x00 0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x00 0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x00 0C0C 1 CPU-Timer 1, Control Register Reserved 0x00 0C0D 1 TIMER1TPR 0x00 0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x00 0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x00 0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x00 0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x00 0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x00 0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x00 0C14 1 CPU-Timer 2, Control Register Reserved 0x00 0C15 1 TIMER2TPR 0x00 0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x00 0C17 1 CPU-Timer 2, Prescale Register High Reserved 0x00 0C18 – 0x00 0C3F 40

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

4.2 Event Manager Modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 4-2 shows the module and signal names used. Table 4-2 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.

Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ. Table 4-3 lists the EVA registers. For more information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number

SPRU065).

Table 4-2. Module and Signal Names for EVA and EVB

EVENT MANAGER

MODULES

GP Timers

Compare Units Compare 2 PWM3/4 Compare 5 PWM9/10

Capture Units Capture 2 CAP2 Capture 5 CAP5

QEP Channels QEP2 QEP4

External Clock Inputs

External Trip Inputs Compare C2TRIP Compare C5TRIP

External Trip Inputs

(1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as

PDPINTB.

MODULE SIGNAL MODULE SIGNAL

GP Timer 1 T1PWM/T1CMP GP Timer 3 T3PWM/T3CMP GP Timer 2 T2PWM/T2CMP GP Timer 4 T4PWM/T4CMP

Compare 1 PWM1/2 Compare 4 PWM7/8 Compare 3 PWM5/6 Compare 6 PWM11/12

Capture 1 CAP1 Capture 4 CAP4 Capture 3 CAP3 Capture 6 CAP6

QEP1 QEP3

QEPI1 QEPI2

Direction TDIRA Direction TDIRB

External Clock TCLKINA External Clock TCLKINB

EVA EVB

QEP1 QEP3 QEP2 QEP4

C1TRIP C4TRIP C3TRIP C6TRIP

T1CTRIP_PDPINTA

T2CTRIP/EVASOC T4CTRIP/EVBSOC

(1)

T3CTRIP_PDPINTB

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

Table 4-3. EVA Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPTCONA 0x00 7400 1 GP Timer Control Register A T1CNT 0x00 7401 1 GP Timer 1 Counter Register T1CMPR 0x00 7402 1 GP Timer 1 Compare Register T1PR 0x00 7403 1 GP Timer 1 Period Register T1CON 0x00 7404 1 GP Timer 1 Control Register T2CNT 0x00 7405 1 GP Timer 2 Counter Register T2CMPR 0x00 7406 1 GP Timer 2 Compare Register T2PR 0x00 7407 1 GP Timer 2 Period Register T2CON 0x00 7408 1 GP Timer 2 Control Register EXTCONA COMCONA 0x00 7411 1 Compare Control Register A ACTRA 0x00 7413 1 Compare Action Control Register A DBTCONA 0x00 7415 1 Dead-Band Timer Control Register A CMPR1 0x00 7417 1 Compare Register 1 CMPR2 0x00 7418 1 Compare Register 2 CMPR3 0x00 7419 1 Compare Register 3 CAPCONA 0x00 7420 1 Capture Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two-Level-Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two-Level-Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two-Level-Deep Capture FIFO Stack 3 CAP1FBOT 0x00 7427 1 Bottom Register of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Register of Capture FIFO Stack 3 EVAIMRA 0x00 742C 1 Interrupt Mask Register A EVAIMRB 0x00 742D 1 Interrupt Mask Register B EVAIMRC 0x00 742E 1 Interrupt Mask Register C EVAIFRA 0x00 742F 1 Interrupt Flag Register A EVAIFRB 0x00 7430 1 Interrupt Flag Register B EVAIFRC 0x00 7431 1 Interrupt Flag Register C

(1) The EV-B register set is identical except the address range is from 0x00 7500 to 0x00 753F. The above registers are mapped to Zone 2. (2) New register compared to 24x/240x

(2)

This space allows only 16-bit accesses. 32-bit accesses produce undefined results.

0x00 7409 1 GP Extension Control Register A

(1)

SPRS174S–APRIL 2001–REVISED MARCH 2011

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

GPTCONA[12:4], CAPCONA[8], EXTCONA[0]

EVATO ADC (Internal)

Timer 1 Compare

Output

Logic

T1PWM_T1CMP

GPTCONA[1,0]

T1CON[1]

GP Timer 1

TCLKINA

Prescaler

HSPCLK

T1CON[10:8]

T1CON[5,4]

clock

T1CON[15:11,6,3,2]

TDIRA

dir

Timer 2 Compare

GP Timer 2

Capture Units

COMCONA[15:5,2:0]

T1CTRIP PDPINTA T2CTRIP C1TRIP C2TRIP C3TRIP/ , , , ,

Output

Logic

T2PWM_T2CMP

GPTCONA[3,2]

T2CON[1]

T2CON[15:11,7,6,3,2,0]

ACTRA[15:12],

COMCONA[12],

T1CON[13:11]

CAPCONA[10,9]

DBTCONA[15:0]

ACTRA[11:0]

TCLKINA

Prescaler

HSPCLK

T2CON[10:8]

T2CON[5,4]

clock dir

CAPCONA[15:12,7:0]

CAP1_QEP1

CAP2_QEP2

CAP3_QEPI1

QEP

Logic

QEPCLK

QEPDIR

reset

EVAENCLK

Control Logic

TDIRA

Index Qual

Peripheral Bus

EXTCONA[1:2]

EVASOC ADC (External)

Full Compare 1

Full Compare 2

Full Compare 3

SVPWM

State

Machine

Dead-Band

Logic

Output

Logic

PWM1 PWM2 PWM3

PWM4 PWM5 PWM6

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

A. The EVB module is similar to the EVA module.

Figure 4-3. Event Manager A Functional Block Diagram

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

4.2.1 General-Purpose (GP) Timers

There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

• A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

• A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes

• A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes

• A 16-bit timer-control register, TxCON, for reads or writes

• Selectable internal or external input clocks

• A programmable prescaler for internal or external clock inputs

• Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period

interrupts

• A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is selected)

The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.2.2 Full-Compare Units

There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.

4.2.3 Programmable Deadband Generator

Deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTRx register.

4.2.4 PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.

4.2.5 Double Update PWM Mode

The F281x and C281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM operation mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently modifiable in each PWM period. To support this mode, the compare register that determines the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning of a PWM period and another time in the middle of a PWM period. The compare registers in F281x and C281x Event Managers are all buffered and support three compare value reload/update (value in buffer becoming active) modes. These modes have earlier been documented as compare value reload conditions. The reload condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for compare value reload.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.2.6 PWM Characteristics

Characteristics of the PWMs are as follows:

• 16-bit registers

• Wide range of programmable deadband for the PWM output pairs

• Change of the PWM carrier frequency for PWM frequency wobbling as needed

• Change of the PWM pulse widths within and after each PWM period as needed

• External-maskable power and drive-protection interrupts

• Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms

• Minimized CPU overhead using auto-reload of the compare and period registers

• The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.

– PDPINTA pin status is reflected in bit 8 of COMCONA register. – PDPINTB pin status is reflected in bit 8 of COMCONB register.

• EXTCON register bits provide options to individually trip control for each PWM pair of signals

4.2.7 Capture Unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.

www.ti.com

Capture units include the following features:

• One 16-bit capture control register, CAPCONx (R/W)

• One 16-bit capture FIFO status register, CAPFIFOx

• Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

• Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

• Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]

• User-specified transition (rising edge, falling edge, or both edges) detection

• Three maskable interrupt flags, one for each capture unit

• The capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture function.

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse).

With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.

4.2.9 External ADC Start-of-Conversion

EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

0,ValueDigital =

V0inputwhen £

4095,ValueDigital =

V3inputwhen ³

V3inputV0when <<

ADCLOVoltageAnalogInput

4096ValueDigital

´=

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

4.3 Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 4-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (voltages above 3.0 V produce full-scale conversion results)

• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input channels

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)

• Sixteen result registers (individually addressable) to store conversion values – The digital value of the input analog voltage is derived by:

SPRS174S–APRIL 2001–REVISED MARCH 2011

• Multiple triggers as sources for the start-of-conversion (SOC) sequence – S/W – software immediate start – EVA – Event manager A (multiple event sources within EVA) – EVB – Event manager B (multiple event sources within EVB)

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

• Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conversions

• EVA and EVB triggers can operate independently in dual-sequencer mode

• Sample-and-hold (S/H) acquisition time window has separate prescale control

The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-4 shows the block diagram of the F281x and C281x ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Result Registers

EVB

S/W

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

12-Bit

ADC

Module

Analog

MUX

EVA

S/W

ADCINA0

ADCINA7

ADCINB0

ADCINB7

ADCSOC

System

Control Block

High-Speed

Prescaler

HSPCLK

C28x

SYSCLKOUT

S/H

ADCENCLK

Sequencer 2Sequencer 1

SOCSOC

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Figure 4-4. Block Diagram of the F281x and C281x ADC Module

To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (V from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected

DDA1/VDDA2

, AVDDREFBG)

to analog ground.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCBGREFIN

(A)

Test Pin

ADC External Current Bias Resistor

ADCRESEXT

ADCREFP

DDA1

DDA2

SSA1

SSA2

AVDDREFBG

AVSSREFBG

DDAIO

SSAIO

DD1

SS1

ADC Reference Positive Output

ADCREFM

ADC Reference Medium Output

ADC Analog Power

ADC Reference Power

ADC Analog I/O Power

ADC Digital Power

Analog input 0-3 V with respect to ADCLO

Connect to Analog Ground

Analog 3.3 V

Analog Ground

1.8 V

ADCREFP and ADCREFM should not be loaded by external circuitry

can use the same 1.8-V (or 1.9-V) supply as the digital core but separate the two with a ferrite bead or a filter

Digital Ground

ADC 16-Channel Analog Inputs

10 Fμ

(C)

10 Fμ

(C)

24.9 k /20 k

(B)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

Figure 4-5 shows the ADC pin-biasing for internal reference and Figure 4-6 shows the ADC pin-biasing for

external reference.

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. Provide access to this pin in PCB layouts. Intended for test purposes only. B. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz. C. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor D. External decoupling capacitors are recommended on all power pins. E. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

Figure 4-5. ADC Pin Connections With Internal Reference

NOTE

The temperature rating of any recommended component must match the rating of the end product.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCBGREFIN

ADC External Current Bias Resistor

ADCRESEXT

ADCREFP

DDA1

DDA2

SSA1

SSA2

AVDDREFBG

AVSSREFBG

DDAIO

SSAIO

DD1

SS1

Test Pin

ADC Reference Positive Input

ADCREFM

ADC Reference Medium Input

ADC Analog Power

ADC Reference Power

ADC Analog I/O Power

ADC Digital Power

Analog Input 0-3 V With Respect to ADCLO

Connect to Analog Ground

Analog 3.3 V Analog 3.3 V

Analog 3.3 V

Analog 3.3 V Analog Ground

1.8 V can use the same 1.8-V (or 1.9-V) supply as the digital core but separate the two with a ferrite bead or a filter

Digital Ground

ADC 16-Channel Analog Inputs

2 V

1 V

(D)

1 F -μ 10 Fμ

24.9 k /20 k

(C)

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

A. External decoupling capacitors are recommended on all power pins. B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. C. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz. D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP –

ADCREFM) = 1 V ± 0.1% or better. External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP – ADCREFM will determine the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more information.

Figure 4-6. ADC Pin Connections With External Reference

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4.

Table 4-4. ADC Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

ADCTRL1 0x00 7100 1 ADC Control Register 1 ADCTRL2 0x00 7101 1 ADC Control Register 2 ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x00 7107 1 ADC Auto-Sequence Status Register ADCRESULT0 0x00 7108 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9 ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x00 7113 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x00 7114 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15 ADCTRL3 0x00 7118 1 ADC Control Register 3 ADCST 0x00 7119 1 ADC Status Register Reserved 0x00 711C – 0x00 711F 4

(1) The above registers are Peripheral Frame 2 Registers.

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.4 Enhanced Controller Area Network (eCAN) Module

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)

• Self-test mode – Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

www.ti.com

NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.

The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for details.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 x 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and

Message Objects Control

Message Controller

32 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

Controls

Address Data

eCAN1INTeCAN0INT

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 4-7. eCAN Block Diagram and Interface Circuit

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

Table 4-5. 3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs

PART SUPPLY LOW-POWER SLOPE

NUMBER VOLTAGE MODE CONTROL

SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C

SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C

SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C

SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C

SN65HVD232 3.3 V None None None – –40°C to 85°C

SN65HVD232Q 3.3 V None None None – –40°C to 125°C

SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C

Standby

SN65HVD234 3.3 V and Adjustable None – –40°C to 125°C

Sleep

SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C

ISO1050 3–5.5 V None None None Thermal Shutdown –55°C to 105°C

VREF OTHER T

Built-in Isolation Low Prop Delay

Failsafe Operation

Dominant Time-out

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

Master Control - CANMC

Bit-Timing Configuration - CANBTC

Error and Status - CANES

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Global Interrupt Flag 1 - CANGIF1

Time-Out Control - CANTOC

Time-Out Status - CANTOS

Reserved

eCAN Control and Status Registers

Message Identifier - MSGID

61E8h-61E9h

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h

603Fh

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

6040h

607Fh 6080h

60BFh 60C0h

60FFh

eCAN Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Mailbox 06100h-6107h

Mailbox 1

6108h-610Fh

Mailbox 2

6110h-6117h

Mailbox 3

6118h-611Fh

eCAN Memory RAM (512 Bytes)

Mailbox 4

6120h-6127h

Mailbox 28

61E0h-61E7h

Mailbox 2961E8h-61EFh

Mailbox 3061F0h-61F7h

Mailbox 31

61F8h-61FFh

61EAh-61EBh

61ECh-61EDh

61EEh-61EFh

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

Figure 4-8. eCAN Memory Map

NOTE

SPRS174S–APRIL 2001–REVISED MARCH 2011

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

The CAN registers listed in Table 4-6 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Table 4-6. CAN Registers

NAME ADDRESS SIZE (x32) DESCRIPTION

CANME 0x00 6000 1 Mailbox enable CANMD 0x00 6002 1 Mailbox direction CANTRS 0x00 6004 1 Transmit request set CANTRR 0x00 6006 1 Transmit request reset CANTA 0x00 6008 1 Transmission acknowledge CANAA 0x00 600A 1 Abort acknowledge CANRMP 0x00 600C 1 Receive message pending CANRML 0x00 600E 1 Receive message lost CANRFP 0x00 6010 1 Remote frame pending CANGAM 0x00 6012 1 Global acceptance mask CANMC 0x00 6014 1 Master control CANBTC 0x00 6016 1 Bit-timing configuration CANES 0x00 6018 1 Error and status CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIF0 0x00 601E 1 Global interrupt flag 0 CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1 CANMIM 0x00 6024 1 Mailbox interrupt mask CANMIL 0x00 6026 1 Mailbox interrupt level CANOPC 0x00 6028 1 Overwrite protection control CANTIOC 0x00 602A 1 TX I/O control CANRIOC 0x00 602C 1 RX I/O control CANTSC 0x00 602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x00 6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x00 6032 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

(1)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.5 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices, except the DMA features

• Full-duplex communication

• Double-buffered data registers which allow a continuous data stream

• Independent framing and clocking for receive and transmit

• External shift clock generation or an internal programmable frequency shift clock

• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits

• 8-bit data transfers with LSB or MSB first

• Programmable polarity for both frame synchronization and data clocks

• Highly programmable internal clock and frame generation

• Support A-bis mode

• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices

• Works with SPI-compatible devices

• Two 16 x 16-level FIFO for Transmit channel

• Two 16 x 16-level FIFO for Receive channel

The following application interfaces can be supported on the McBSP:

• T1/E1 framers

• MVIP switching-compatible and ST-BUS-compliant devices including: – MVIP framers – H.100 framers – SCSA framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) – IIS-compliant devices

• McBSP clock rate = CLKG = CLKSRG/(1 + CLKGDIV) , where CLKSRG source could be LSPCLK, CLKX, or CLKR.

(2) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is

less than the I/O buffer speed limit—20-MHz maximum.

(2)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

McBSP Receive

Interrupt Select Logic

Expand Logic

RX FIFO

Interrupt

DRR2 Receive Buffer

RX FIFO Registers

RBR1 Register

RBR2 Register

McBSP Registers

and

Control Logic

CLKX

FSX

CLKR

FSR

Compand Logic

DXR2 Transmit Buffer

RSR1

XSR2

XSR1

Peripheral Read Bus

RSR2

DXR1 Transmit Buffer

LSPCLK

MRINT

To CPU

McBSP

RX Interrupt Logic

RX FIFO _15

RX FIFO _1

RX FIFO _0

RX FIFO _15

RX FIFO _1

RX FIFO _0

McBSP Transmit

Interrupt Select Logic

TX FIFO

Interrupt

TX FIFO Registers

MXINT

To CPU

TX Interrupt Logic

TX FIFO _15

TX FIFO _1

TX FIFO _0

TX FIFO _15

TX FIFO _1

TX FIFO _0

Peripheral Write Bus

DRR1 Receive Buffer

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x and C281x

version of Peripheral Frame 2.

www.ti.com

Figure 4-9. McBSP Module With FIFO

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 4-7 provides a summary of the McBSP registers.

Table 4-7. McBSP Registers

NAME DESCRIPTION

– – – 0x0000 McBSP Receive Buffer Register – – – 0x0000 McBSP Receive Shift Register – – – 0x0000 McBSP Transmit Shift Register

DRR2 00 R 0x0000

DRR1 01 R 0x0000

DXR2 02 W 0x0000

DXR1 03 W 0x0000

SPCR2 04 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 05 R/W 0x0000 McBSP Serial Port Control Register 1

RCR2 06 R/W 0x0000 McBSP Receive Control Register 2 RCR1 07 R/W 0x0000 McBSP Receive Control Register 1 XCR2 08 R/W 0x0000 McBSP Transmit Control Register 2

XCR1 09 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0B R/W 0x0000 McBSP Sample Rate Generator Register 1

MCR2 0C R/W 0x0000 McBSP Multichannel Register 2

MCR1 0D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B

PCR 12 R/W 0x0000 McBSP Pin Control Register RCERC 13 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 14 R/W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 15 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 16 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E

XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H

ADDRESS TYPE RESET VALUE

0x00 78xxh (R/W) (HEX)

DATA REGISTERS, RECEIVE, TRANSMIT

McBSP CONTROL REGISTERS

MULTICHANNEL CONTROL REGISTERS

(1)

McBSP Data Receive Register 2

• Read First if the word size is greater than 16 bits, else ignore DRR2

McBSP Data Receive Register 1

• Read Second if the word size is greater than 16 bits, else read DRR1 only

McBSP Data Transmit Register 2

• Write First if the word size is greater than 16 bits, else ignore DXR2

McBSP Data Transmit Register 1

• Write Second if the word size is greater than 16 bits, else write to DXR1 only

(1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 4-7. McBSP Registers (continued)

NAME DESCRIPTION

DRR2 00 R 0x0000

DRR1 01 R 0x0000

DXR2 02 W 0x0000

DXR1 03 W 0x0000

MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register

MFFRX 21 R/W 0x201F McBSP Receive FIFO Register

MFFCT 22 R/W 0x0000 McBSP FIFO Control Register

MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register

MFFST 24 R/W 0x0000 McBSP FIFO Status Register

(2) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

ADDRESS TYPE RESET VALUE

0x00 78xxh (R/W) (HEX)

FIFO MODE REGISTERS (applicable only in FIFO mode)

FIFO Data Registers

FIFO Control Registers

(2)

McBSP Data Receive Register 2 – Top of receive FIFO

• Read First FIFO pointers will not advance

McBSP Data Receive Register 1 – Top of receive FIFO

• Read Second for FIFO pointers to advance

McBSP Data Transmit Register 2 – Top of transmit FIFO

• Write First FIFO pointers will not advance

McBSP Data Transmit Register 1 – Top of transmit FIFO

• Write Second for FIFO pointers to advance

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

rateBaud

8*1)(BRR

LSPCLK

0BRRwhen ¹

LSPCLK

0BRRwhen =

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

4.6 Serial Communications Interface (SCI) Module

The F281x and C281x devices include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

• Baud rate programmable to 64K different rates

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

• Max bit rate = 75 MHz/16 = 4.688 x 106b/s

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

(3)

SPRS174S–APRIL 2001–REVISED MARCH 2011

Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

(3) Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is

less than the I/O buffer speed limit—20 MHz maximum.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.

Table 4-8. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x00 7050 1 SCI-A Communications Control Register SCICTL1A 0x00 7051 1 SCI-A Control Register 1 SCIHBAUDA 0x00 7052 1 SCI-A Baud Register, High Bits SCILBAUDA 0x00 7053 1 SCI-A Baud Register, Low Bits SCICTL2A 0x00 7054 1 SCI-A Control Register 2 SCIRXSTA 0x00 7055 1 SCI-A Receive Status Register SCIRXEMUA 0x00 7056 1 SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x00 7057 1 SCI-A Receive Data Buffer Register SCITXBUFA 0x00 7059 1 SCI-A Transmit Data Buffer Register SCIFFTXA SCIFFRXA SCIFFCTA SCIPRIA 0x00 705F 1 SCI-A Priority Control Register

(1) These registers are new registers for the FIFO mode.

(1)

0x00 705A 1 SCI-A FIFO Transmit Register 0x00 705B 1 SCI-A FIFO Receive Register 0x00 705C 1 SCI-A FIFO Control Register

Table 4-9. SCI-B Registers

(1)

www.ti.com

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRB 0x00 7750 1 SCI-B Communications Control Register SCICTL1B 0x00 7751 1 SCI-B Control Register 1 SCIHBAUDB 0x00 7752 1 SCI-B Baud Register, High Bits SCILBAUDB 0x00 7753 1 SCI-B Baud Register, Low Bits SCICTL2B 0x00 7754 1 SCI-B Control Register 2 SCIRXSTB 0x00 7755 1 SCI-B Receive Status Register SCIRXEMUB 0x00 7756 1 SCI-B Receive Emulation Data Buffer Register SCIRXBUFB 0x00 7757 1 SCI-B Receive Data Buffer Register SCITXBUFB 0x00 7759 1 SCI-B Transmit Data Buffer Register SCIFFTXB SCIFFRXB SCIFFCTB SCIPRIB 0x00 775F 1 SCI-B Priority Control Register

(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce (2) These registers are new registers for the FIFO mode.

(2)

undefined results.

0x00 775A 1 SCI-B FIFO Transmit Register 0x00 775B 1 SCI-B FIFO Receive Register 0x00 775C 1 SCI-B FIFO Control Register

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

LSPCLK

Frame Format and Mode

Even/Odd

Enable

Parity

SCIRXD

SCIRXST.1

TXENA

RXWAKE

SCITXD

SCICCR.6 SCICCR.5

RXSHF Register

SCITXD

TXSHF

WUT

SCICTL1.3

TXWAKE

Baud Rate

MSbyte

Baud Rate

LSbyte

SCIHBAUD. 15 - 8

SCILBAUD. 7 - 0

FIFO

Interrupts

RXENA

SCICTL1.0

FIFO

Interrupts

SCICTL1.1

SCIRXD

RX ERR INT ENA

SCICTL1.6

RX Error

PEFE OE

RX Error

SCIRXST.7 SCIRXST.4 - 2

SCITXBUF.7-0

TX FIFO Registers

Transmitter-Data

Buffer Register

SCIFFENA

TX FIFO _15

- - - - -

TX FIFO _1

TX FIFO _0

SCIFFTX.14

SCIRXBUF.7-0

RX FIFO Registers

Receive-Data

Buffer Register

SCIRXBUF.7-0

SCIFFRX.15

RXFFOVF

RX FIFO _0

- - - - -

RX FIFO _1

RX FIFO _15

SCI TX Interrupt Select Logic

TX EMPTY

SCICTL2.6

TXINT

TXRDY

SCICTL2.0

TX INT ENA

SCICTL2.7

To CPU

AutoBaud Detect Logic

TX Interrupt Logic

RX Interrupt Logic

SCI RX Interrupt Select Logic

RXRDY

SCIRXST.6

BRKDT

SCIRXST.5

RX/BK INT ENA

SCICTL2.1

RXINT

To CPU

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

Figure 4-10 shows the SCI module block diagram.

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

rateBaud

1)(SPIBRR

LSPCLK

0SPIBRRwhen ¹

LSPCLK

32,1,0,SPIBRRwhen =

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.7 Serial Peripheral Interface (SPI) Module

The F281x and C281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave

• Baud rate: 125 different programmable rates

www.ti.com

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• 16-level transmit/receive FIFO

• Delayed transmit control

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

The SPI port operation is configured and controlled by the registers listed in Table 4-10.

Table 4-10. SPI Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SPICCR 0x00 7040 1 SPI Configuration Control Register SPICTL 0x00 7041 1 SPI Operation Control Register SPISTS 0x00 7042 1 SPI Status Register SPIBRR 0x00 7044 1 SPI Baud Rate Register SPIRXEMU 0x00 7046 1 SPI Receive Emulation Buffer Register SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register SPIDAT 0x00 7049 1 SPI Serial Data Register SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register SPIFFRX 0x00 704B 1 SPI FIFO Receive Register SPIFFCT 0x00 704C 1 SPI FIFO Control Register SPIPRI 0x00 704F 1 SPI Priority Control Register

(1) These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

(1)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

LSPCLK

456 123 0

0123

SPI Bit Rate

State Control

SPICCR.3 - 0

SPIBRR.6 - 0

Clock

Polarity

SPICCR.6

Clock

Phase

SPICTL.3

Talk

SPICTL.1

Master/Slave

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

SW3

To CPU

SW1

SPIDAT.15 - 0

SPITXINT

FIFO

Interrupt

FIFO

Interrupt

SPISTE

(A)

RX FIFO Registers

SPIRXBUF

SPIFFTX.14

SPIFFENA

RX FIFO _15

- - - - -

RX FIFO _1

RX FIFO _0

TX FIFO Registers

SPITXBUF

- - - - -

TX FIFO _15

TX FIFO _0

TX FIFO _1

SPITXBUF Buffer Register

SPIRXBUF Buffer Register

SPICTL.0

SPI

INT ENA

SPI

INT FLAG

SPISTS.6

Receiver

Overrun Flag

Overrun

INT ENA

SPISTS.7

SPICTL.4

SPIINT/SPIRXINT

RX Interrupt

Logic

TX Interrupt

Logic

SPIFFOVF

FLAG

SPIFFRX.15

SPIDAT Data Register

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

Figure 4-11 is a block diagram of the SPI in slave mode.

www.ti.com

A. SPISTEis driven low by the master for a slave device.

Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

4.8 GPIO MUX

The GPIO Mux registers are used to select the operation of shared pins on the F281x and C281x devices. The pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX registers). If selected for “Digital I/O”mode, registers are provided to configure the pin direction (via the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers). Table 4-11 lists the GPIO Mux Registers.

Table 4-11. GPIO Mux Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPAMUX 0x00 70C0 1 GPIO A Mux Control Register GPADIR 0x00 70C1 1 GPIO A Direction Control Register GPAQUAL 0x00 70C2 1 GPIO A Input Qualification Control Register Reserved 0x00 70C3 1 GPBMUX 0x00 70C4 1 GPIO B Mux Control Register GPBDIR 0x00 70C5 1 GPIO B Direction Control Register GPBQUAL 0x00 70C6 1 GPIO B Input Qualification Control Register Reserved 0x00 70C7 1 Reserved 0x00 70C8 1 Reserved 0x00 70C9 1 Reserved 0x00 70CA 1 Reserved 0x00 70CB 1 GPDMUX 0x00 70CC 1 GPIO D Mux Control Register GPDDIR 0x00 70CD 1 GPIO D Direction Control Register GPDQUAL 0x00 70CE 1 GPIO D Input Qualification Control Register Reserved 0x00 70CF 1 GPEMUX 0x00 70D0 1 GPIO E Mux Control Register GPEDIR 0x00 70D1 1 GPIO E Direction Control Register GPEQUAL 0x00 70D2 1 GPIO E Input Qualification Control Register Reserved 0x00 70D3 1 GPFMUX 0x00 70D4 1 GPIO F Mux Control Register GPFDIR 0x00 70D5 1 GPIO F Direction Control Register Reserved 0x00 70D6 1 Reserved 0x00 70D7 1 GPGMUX 0x00 70D8 1 GPIO G Mux Control Register GPGDIR 0x00 70D9 1 GPIO G Direction Control Register Reserved 0x00 70DA 1 Reserved 0x00 70DB 1 Reserved 0x00 70DC – 0x00 70DF 4

(1) Reserved locations return undefined values and writes are ignored. (2) Not all inputs support input signal qualification. (3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.

(1)(2)(3)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

If configured for ”Digital I/O” mode, additional registers are provided for setting individual I/O signals (via the GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT registers). Table 4-12 lists the GPIO Data Registers. For more information, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).

Table 4-12. GPIO Data Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPADAT 0x00 70E0 1 GPIO A Data Register GPASET 0x00 70E1 1 GPIO A Set Register GPACLEAR 0x00 70E2 1 GPIO A Clear Register GPATOGGLE 0x00 70E3 1 GPIO A Toggle Register GPBDAT 0x00 70E4 1 GPIO B Data Register GPBSET 0x00 70E5 1 GPIO B Set Register GPBCLEAR 0x00 70E6 1 GPIO B Clear Register GPBTOGGLE 0x00 70E7 1 GPIO B Toggle Register Reserved 0x00 70E8 1 Reserved 0x00 70E9 1 Reserved 0x00 70EA 1 Reserved 0x00 70EB 1 GPDDAT 0x00 70EC 1 GPIO D Data Register GPDSET 0x00 70ED 1 GPIO D Set Register GPDCLEAR 0x00 70EE 1 GPIO D Clear Register GPDTOGGLE 0x00 70EF 1 GPIO D Toggle Register GPEDAT 0x00 70F0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register GPECLEAR 0x00 70F2 1 GPIO E Clear Register GPETOGGLE 0x00 70F3 1 GPIO E Toggle Register GPFDAT 0x00 70F4 1 GPIO F Data Register GPFSET 0x00 70F5 1 GPIO F Set Register GPFCLEAR 0x00 70F6 1 GPIO F Clear Register GPFTOGGLE 0x00 70F7 1 GPIO F Toggle Register GPGDAT 0x00 70F8 1 GPIO G Data Register GPGSET 0x00 70F9 1 GPIO G Set Register GPGCLEAR 0x00 70FA 1 GPIO G Clear Register GPGTOGGLE 0x00 70FB 1 GPIO G Toggle Register Reserved 0x00 70FC – 0x00 70FF 4

(1) Reserved locations will return undefined values and writes will be ignored. (2) These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.

(1)(2)

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Peripheral I/O

MUX

0 1

MUX

Internal (Pullup or Pulldown)

Digital I/O

XRS

High-Impedance Enable (1)

High-

Impedance

Control

GPxDIR

GPxMUX

GPxQUAL

GPxDAT/SET/CLEAR/TOGGLE

Input Qualification

SYSCLKOUT

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

Figure 4-12 shows how the various register bits select the various modes of operation for GPIO function.

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only

gives the value written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the corresponding direction bit is zero (input mode).

B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification

sampling period. The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0's or all 1's). This feature removes unwanted spikes from the input signal.

Figure 4-12. GPIO/Peripheral Pin Multiplexing

The input function of the GPIO pin and the input path to the peripheral are always enabled. It is the output function of the GPIO pin that is multiplexed with the output path of the primary (peripheral) function. Since the output buffer of a pin connects back to the input buffer, any GPIO signal present at the pin will be propagated to the peripheral module as well. Therefore, when a pin is configured for GPIO operation, the corresponding peripheral functionality (and interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.

NOTE

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

5 Development Support

Texas Instruments ( TI™) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of F281x- and C281x-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• 2812 eZdsp

• JTAG-based emulators – SPI515, XDS510PP, XDS510PP Plus, XDS510 USB

• Universal 5-V dc power supply

• Documentation and cables

www.ti.com

5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F2812GHH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

TMX Experimental device that is not necessarily representative of the final device’s electrical

specifications

TMP Final silicon die that conforms to the device’s electrical specifications but has not

completed quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

PREFIX

TMS

320

2810

PBK

experimental device prototype device qualified device

TMX = TMP = TMS =

DEVICE FAMILY

320 = TMS320 DSP Family

TECHNOLOGY

PACKAGE TYPE

(A)

= 179-ball MicroStar BGA = 179-ball MicroStar BGA (lead-free) = 176-pin LQFP = 128-pin LQFP

GHH ZHH PGF PBK

= Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O) = ROM (1.8-V/1.9-V Core/3.3-V I/O)

F C

DEVICE

2810

2811

2812

= Ball Grid Array = Low-Profile Quad Flatpack

BGA LQFP

TEMPERATURE RANGE

= −40 °

−40°C to 125°C

= −40°C to 125°C (Q100 qualification)

°C to 85 C

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend for reading the complete device name for any TMS320x281x family member.

SPRS174S–APRIL 2001–REVISED MARCH 2011

5.2 Documentation Support

Extensive documentation supports all of the TMS320™ DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications.

Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.

See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more information on types of peripherals.

TMS320x281x DSP System Control and Interrupts SPRU078 – x x TMS320x281x DSP External Interface (XINTF) SPRU067 0 x TMS320x281x Enhanced Controller Area Network (eCAN) SPRU074 0 x x TMS320x281x DSP Event Manager (EV) SPRU065 0 x x TMS320x281x DSP Analog-to-Digital Converter (ADC) SPRU060 0 x x TMS320x281x DSP Multichannel Buffered Serial Port (McBSP) SPRU061 0 x x TMS320x281x Serial Communications Interface (SCI) SPRU051 0 x x TMS320x281x Serial Peripheral Interface SPRU059 0 x x TMS320x281x DSP Boot ROM SPRU095 – x x

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices which do not affect the basic functionality of the module. These device-specific differences are listed in the peripheral reference guides.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 5-1. TMS320x281x Device Nomenclature

Table 5-1. TMS320x281x Peripheral Selection Guide

PERIPHERAL LIT. NO. TYPE

Submit Documentation Feedback

(1)

2812

2811,

2810

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

The following documents are available on the TI website (http://www.ti.com):

SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing

unit (CPU) and the assembly language instructions of the TMS320C28x™ fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.

SPRU060 TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide describes the

ADC module. The module is a 12-bit pipelined ADC. The analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits, referred to as the wrapper in this document, include programmable conversion sequencer, result registers, interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules.

SPRU095 TMS320x281x DSP Boot ROM Reference Guide describes the purpose and features of the

bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.

SPRU065 TMS320x281x DSP Event Manager (EV) Reference Guide describes the EV modules that

provide a broad range of functions and features that are particularly useful in motion control and motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits.

SPRU067 TMS320x281x DSP External Interface (XINTF) Reference Guide describes the external

interface (XINTF) of the 281x digital signal processors (DSPs).

www.ti.com

SPRU061 TMS320x281x DSP Multichannel Buffered Serial Port (McBSP) Reference Guide

describes the McBSP available on the 281x devices. The McBSPs allow direct interface between a DSP and other devices in a system.

SPRU078 TMS320x281x DSP System Control and Interrupts Reference Guide describes the

various interrupts and system control features of the 281x digital signal processors (DSPs).

SPRU074 TMS320x281x Enhanced Controller Area Network (eCAN) Reference Guide describes

the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x DSP is compatible with the CAN 2.0B standard (active).

SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference

guides of the 28x digital signal processors (DSPs).

SPRU051 TMS320x281x Serial Communications Interface (SCI) Reference Guide describes the

SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

SPRU059 TMS320x281x Serial Peripheral Interface Reference Guide describes the SPI—a

high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is used for communications between the DSP controller and external peripherals or another controller.

SPRA550 3.3V DSP for Digital Motor Control Application Report. The application report first

describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V/5-V interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed. Guidelines for component layout and printed circuit board (PCB) design that can reduce

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

SPRU625 TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide

SPRU513 TMS320C28x Assembly Language Tools v5.0 User’s Guide describes the assembly

SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0 User’s Guide describes the

SPRA876 Programming Examples for the TMS320F281x eCAN Application Report contains

SPRA989 F2810, F2811, and F2812 ADC Calibration Application Report describes a method for

SPRS174S–APRIL 2001–REVISED MARCH 2011

system noise and EMI effects are summarized in the last section.

available within the Code Composer Studio for TMS320C2000™ IDE, that simulates the instruction set of the C28x core.

describes development using DSP/BIOS™.

language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x™ device.

TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320™ DSP assembly language source code for the TMS320C28x device.

several programming examples to illustrate how the eCAN module is set up for different modes of operation. The objective is to help you come up to speed quickly in programming the eCAN. All programs have been extensively commented to aid easy understanding. The CANalyzer tool from Vector CANtech, Inc. was used to monitor and control the bus operation. All projects and CANalyzer configuration files are included in the spra876.zip file.

improving the absolute accuracy of the 12-bit analog-to-digital converter (ADC) found on the F2810/F2811/F2812 devices. Due to inherent gain and offset errors, the absolute accuracy of the ADC is impacted. The methods described in this application note can improve the absolute accuracy of the ADC to achieve levels better than 0.5%. This application note is accompanied by an example program (ADCcalibration, spra989.zip) that executes from RAM on the F2812 eZdsp.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320™ DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320™ DSP customers on product information.

Updated information on the TMS320™ DSP controllers can be found on the worldwide web at:

http://www.ti.com.

To send comments regarding this TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811,TMS320C2812 Digital Signal Processors Data Manual (literature number SPRS174), click on the Submit Documentation Feedback link at the bottom of the page. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

5.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320F281x and TMS320C281x DSPs.

6.1 Absolute Maximum Ratings

Supply voltage range (V Supply voltage range (VDD, V Input voltage range, V Output voltage range, V Input clamp current, IIK(VIN< 0 or VIN> V Output clamp current, IOK(VO< 0 or VO> V Operating ambient temperature ranges, T

Junction temperature range, T Storage temperature range, T

(1) Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. Stresses beyond those

listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2, Recommended Operating Conditions, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are

with respect to VSS. (2) Continuous clamp current per pin is ±2 mA (3) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see the IC Package Thermal Metrics Application Report (literature number SPRA953) and the Reliability

Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).

DDIO

, V

DD3VFL

) –0.5 V to 2.5 V

DD1

(3)

stg

(1)

, V

DDA1

DDA2

(2)

)

DDIO

) ±20 mA

DDIO

, and AVDDREFBG) –0.3 V to 4.6 V

DDAIO

A version (GHH, ZHH, PGF, PBK) S version (GHH, ZHH, PGF, PBK) Q version (PGF, PBK)

(3)

(3) (3)

–0.3 V to 4.6 V –0.3 V to 4.6 V

±20 mA

–40°C to 85°C –40°C to 125°C –40°C to 125°C –40°C to 150°C –65°C to 150°C

6.2 Recommended Operating Conditions

(1)

MIN NOM MAX UNIT

DDIO

VDD, V

DD1

, V

DDA1

AVDDREFBG, V

V f

DDA2

DDAIO DD3VFL

SYSCLKOUT

Device supply voltage, I/O 3.14 3.3 3.47 V

Device supply voltage, CPU V

1.8 V (135 MHz) 1.71 1.8 1.89

1.9 V (150 MHz) 1.81 1.9 2

Supply ground 0 V

, ADC supply voltage 3.14 3.3 3.47 V

Flash programming supply voltage 3.14 3.3 3.47 V Device clock frequency VDD= 1.9 V ± 5% 2 150

(system clock)

VDD= 1.8 V ± 5% 2 135

High-level input voltage All inputs except X1/XCLKIN 2 V

X1/XCLKIN (@ 50 µA max) 0.7V

Low-level input voltage All inputs except X1/XCLKIN 0.8 V

X1/XCLKIN (@ 50 µA max) 0.3V

High-level output source current, All I/Os except Group 2 –4 mA VOH= 2.4 V

Group 2

(2)

Low-level output sink current, All I/Os except Group 2 4 VOL= VOLMAX

Group 2

(2)

Ambient temperature A version –40 85

S version –40 125 °C Q version –40 125

(1) See Section 6.8 for power sequencing of V (2) Group 2 pins are as follows: XINTF pins, T1CTRIP_PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.

DDIO

, V

DDAIO

, VDD, V

DDA1/VDDA2

/AVDDREFBG, and V

DD3VFL

MHz

DDIO

–8

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V I

C C

(1) Applicable to C281x devices (2) Applicable to F281x devices (3) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5. (4) The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.

High-level output voltage IOH= IOHMAX 2.4 V

IOH= 50 µA V

Low-level output voltage IOL= IOLMAX 0.4 V

(1)

Input current With pullup V (low level)

(2)

Input current With pullup V

With pulldown V

(low level) VIN= 0 V XRS) except EVB

= 3.3 V, VIN= 0 V –80 –140 –190 µA

DDIO

= 3.3 V, VIN= 0 V ±2

DDIO

= 3.3 V, All I/Os

DDIO

(3)

(including –80 –140 –190 µA

DDIO

– 0.2

GPIOB/EVB –13 –25 –35

With pulldown V

Input current With pullup V (high level)

With pulldown

(4)

Leakage current (for pins without internal VO= V PU/PD), high-impedance state (off-state)

Input capacitance 2 pF

Output capacitance 3 pF

= 3.3 V, VIN= 0 V ±2

DDIO

= 3.3 V, VIN= V

DDIO

= 3.3 V, VIN= V

DDIO

or 0 V ±2 µA

DD DD

28 50 80

±2 µA

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

6.4 Current Consumption

Table 6-1. TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating

Conditions During Low-Power Modes at 150-MHz SYSCLKOUT

MODE TEST CONDITIONS

TYP MAX

(3)

TYP MAX

DDIO

(1)

(3)

DD3VFL

TYP MAX

(3)

TYP MAX

All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz.

Operational the SCIA, SCIB, and CAN ports. The 195 mA

Data is continuously transmitted out of

(4)

230 mA 15 mA 30 mA 40 mA 45 mA 40 mA 50 mA hardware multiplier is exercised. Code is running out of flash with 5 wait-states.

• Flash is powered down

IDLE 125 mA 150 mA 5 mA 10 mA 2 µA 4 µA 1 µA 20 µA

• XCLKOUT is turned off

• All peripheral clocks are on,

except ADC

• Flash is powered down

STANDBY 5 mA 10 mA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA

• Peripheral clocks are turned off

• Pins without an internal PU/PD are

tied high/low

• Flash is powered down

• Peripheral clocks are turned off

HALT 70 µA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA

• Pins without an internal PU/PD are

tied high/low

• Input clock is disabled

(1) I (2) I (3) MAX numbers are at 125°C, and MAX voltage (VDD= 1.89 V; V (4) IDDrepresents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by V

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA

DDA1

, V

, AVDDREFBG, and V

DDA2

DDAIO

DDIO

pins.

, V

DD3VFL

, V

DDA

= 3.47 V).

DD1

DDA

(2)

(3)

NOTE

HALT and STANDBY modes cannot be used when the PLL is disabled.

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

Table 6-2. TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating

Conditions During Low-Power Modes at 150-MHz SYSCLKOUT

MODE TEST CONDITIONS

TYP MAX

(3)

TYP MAX

DDIO

(1)

(3)

TYP MAX

All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz.

Operational 210 mA

Data is continuously transmitted out of the SCIA, SCIB, and CAN ports. The hardware

(4)

260 mA 20 mA 30 mA 40 mA 50 mA

multiplier is exercised. Code is running out of ROM with 5 wait-states.

IDLE 140 mA 165 mA 20 mA 30 mA 5 µA 10 µA

• XCLKOUT is turned off

• All peripheral clocks are on, except ADC

• Peripheral clocks are turned off

STANDBY 5 mA 10 mA 5 µA 20 µA 5 µA 10 µA

• Pins without an internal PU/PD are tied high/low

• Peripheral clocks are turned off

HALT 70 µA 5 µA 10 µA 1 µA

• Pins without an internal PU/PD are tied high/low

• Input clock is disabled

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA

DDA1

, V

, AVDDREFBG, and V

DDA2

DDAIO

DDIO

pins.

, V

DD3VFL

, V

DDA

= 3.47 V).

DDA

DD1

(2)

(3)

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

100

150

200

250

0 20 40 60 80 100 120 140 160

SYSCLKOUT (MHz)

Current (mA)

IDD IDDIO

IDD3VFL

IDDA

Total 3.3-V current

100

200

300

400

500

600

700

0 20 40 60 80 100 120 140 160

SYSCLKOUT (MHz)

Power (mW)

Total Power

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.5 Current Consumption Graphs

A. Test conditions are as defined in Table 6-1 for operational currents. B. IDDrepresents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn

by V

. C. I D. Total 3.3-V current is the sum of I

DD1

represents the current drawn by V

DDA

by V

DDAIO

DDIO

DDA1

, I

and V

DD3VFL

DDA2

, and I

rails.

. It includes a small amount of current (<1 mA) drawn

DDA

Figure 6-1. F2812/F2811/F2810 Typical Current Consumption Over Frequency

www.ti.com

Figure 6-2. F2812/F2811/F2810 Typical Power Consumption Over Frequency

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

100

150

200

250

0 20 40 60 80 100 120 140 160

SYSCLKOUT (MHz)

Current (mA)

IDD IDDIO IDDA

Total 3.3-V current

100

200

300

400

500

600

0 20 40 60 80 100 120 140 160

Total Power

SYSCLKOUT (MHz)

Power (mW)

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174S–APRIL 2001–REVISED MARCH 2011

A. Test conditions are as defined in Table 6-2 for operational currents. B. IDDrepresents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn

by V

. C. I D. Total 3.3-V current is the sum of I

DD1

represents the current drawn by V

DDA

DDIO

DDA1

and I

and V

DDA

rails.

DDA2

. It includes a small amount of current (<1 mA) drawn by V

Figure 6-3. C2812/C2811/C2810 Typical Current Consumption Over Frequency

DDAIO

Figure 6-4. C2812/C2811/C2810 Typical Power Consumption Over Frequency

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

6 inches or less

EMU0

GND

EMU1 EMU1

TMS TMS

TDI TDI

DSP

JTAG Header

TDO TDO

TCK TCK

TCK_RET

TRST

DDIO

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.6 Reducing Current Consumption

28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 6-3 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals.

Table 6-3. Typical Current Consumption by Various Peripherals (at 150 MHz)

PERIPHERAL MODULE IDDCURRENT REDUCTION (mA)

eCAN 12

EVA 6 EVB 6 ADC 8

SCI 4

SPI 5

McBSP 13

(1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible

only after the peripheral clocks are turned on.

(2) This number represents the current drawn by the digital portion of the ADC module. Turning off the

clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

DDA

) as well.

www.ti.com

(1)

(2)

6.7 Emulator Connection Without Signal Buffering for the DSP

Figure 6-5 shows the connection between the DSP and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-5 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Figure 6-5. Emulator Connection Without Signal Buffering for the DSP

Submit Documentation Feedback

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

6.8 Power Sequencing Requirements

TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. The current F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp board) suggests two options for the power sequencing circuit.

Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp together. C281x can also be used on boards that have F281x power sequencing implemented; however, if the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least 1 V.

• Option 1: In this approach, an external power sequencing circuit enables V (1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (V (V

DDA1/VDDA2

requirement. Option 2 is the recommended approach.

• Option 2: Enable power to all 3.3-V supply pins (V ramp 1.8 V (or 1.9 V) (VDD/V

1.8 V or 1.9 V (VDD/V signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device. See Figure 6-11 for power-on reset timing.

• Power-Down Sequencing: During power-down, the device reset should be asserted low (8 µs, minimum) before the VDDsupply reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the V ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.

/AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the

) supply pins.

DD1

) should not reach 0.3 V until V

DD1

DDIO

, V

DD3VFL

SPRS174S–APRIL 2001–REVISED MARCH 2011

first, then VDDand V

DDIO

) and ADC

DD3VFL

, V

DDA1/VDDA2/VDDAIO

has reached 2.5 V. This ensures the reset

DDIO

/AVDDREFBG) and then

DDIO/VDD

power supplies

DD1

Table 6-4. Recommended “Low-Dropout Regulators”

SUPPLIER PART NUMBER

Texas Instruments TPS767D301

NOTE

The GPIO pins are undefined until VDD= 1 V and V

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

DDIO

= 2.5 V.

DD_3.3V

(A)

2.5 V

(C)

3.3 V

DD_1.8V

(B)

XRS

1.8 V (or 1.9 V)

XRS

1.5 V

3.3 V

<10 ms

>1 ms

(D)

Power-Up Sequence Power-Down Sequence

(E)

>8 sμ

(F)

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

www.ti.com

A. V B. V

DD_3.3V DD_1.8V

– V

DDIO

– VDD, V

, V

DD1

DD3VFL

, V

DDAIO

, V

DDA1

, V

DDA2

, AVDDREFBG

C. 1.8-V (or 1.9-V) supply should ramp after the 3.3-V supply reaches at least 2.5 V. D. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 6-11, Power-on Reset in

Microcomputer Mode (XMP/MC = 0), for minimum requirements.

E. Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this

occurs a few milliseconds before the 1.8-V (or 1.9-V) supply reaches 1.5 V.

F. Keeping reset low (XRS) at least 8 µs prior to the 1.8-V (or 1.9-V) supply reaching 1.5 V will keep the flash module in

complete reset before the supplies ramp down.

G. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9-V) supply reaches at least 1 V, this supply should be

ramped as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).

H. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.

Figure 6-6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

0.4 V (V )

2.4 V (V )

0.8 V (V )

2.0 V (V )

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

6.9 Signal Transition Levels

Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of

0.4 V.

Figure 6-7 shows output levels.

Output transition times are specified as follows:

• For a high-to-low transition, the level at which the output is said to be no longer high is below V and the level at which the output is said to be low is V

• For a low-to-high transition, the level at which the output is said to be no longer low is above V and the level at which the output is said to be high is V

Figure 6-8 shows the input levels.

Figure 6-7. Output Levels

OL(MAX)

OH(MIN)

SPRS174S–APRIL 2001–REVISED MARCH 2011

OH(MIN)

and lower.

OL(MAX)

and higher.

Figure 6-8. Input Levels

Input transition times are specified as follows:

• For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is below V

and the level at which the input is said to be low is V

IH(MIN)

IL(MAX)

and lower.

• For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is above V

and the level at which the input is said to be high is V

IL(MAX)

IH(MIN)

and higher.

NOTE

See the individual timing diagrams for levels used for testing timing parameters.

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

Transmission Line

4.0 pF 1.85 pF

Z0 = 50

(A)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output Under Test

3.5 nH

Device Pin

(A)

TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812

SPRS174S–APRIL 2001–REVISED MARCH 2011

6.10 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their meanings: Letters and symbols and their meanings:

a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width)

6.11 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

www.ti.com

6.12 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 6-9. 3.3-V Test Load Circuit

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

Submit Documentation Feedback

Texas instruments TMS320F2810, TMS320C2810, TMS320F2812, TMS320C2811, TMS320C2812 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 TMS320F281x, TMS320C281x DSPs

1.1 Features

1.2 Getting Started

2 Introduction

2.1 Description

2.2 Device Summary

2.3 Pin Assignments

2.3.1 Terminal Assignments for the GHH/ZHH Packages

2.3.2 Pin Assignments for the PGF Package

2.3.3 Pin Assignments for the PBK Package

2.4 Signal Descriptions

3 Functional Overview

3.1 Memory Map

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 External Interface (XINTF) (2812 Only)

3.2.6 Flash (F281x Only)

3.2.7 ROM (C281x Only)

3.2.8 M0, M1 SARAMs

3.2.9 L0, L1, H0 SARAMs

3.2.10 Boot ROM

3.2.11 Security

3.2.12 Peripheral Interrupt Expansion (PIE) Block

3.2.13 External Interrupts (XINT1, XINT2, XINT13, XNMI)

3.2.14 Oscillator and PLL

3.2.15 Watchdog

3.2.16 Peripheral Clocking

3.2.17 Low-Power Modes

3.2.18 Peripheral Frames 0, 1, 2 (PFn)

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer

3.2.20 32-Bit CPU-Timers (0, 1, 2)

3.2.21 Control Peripherals

3.2.22 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 External Interface, XINTF (2812 Only)

3.5.1 Timing Registers

3.5.2 XREVISION Register

3.6 Interrupts

3.6.1 External Interrupts

3.7 System Control

3.8 OSC and PLL Block

3.8.1 Loss of Input Clock

3.9 PLL-Based Clock Module

3.10 External Reference Oscillator Clock Option

3.11 Watchdog Block

3.12 Low-Power Modes Block

4 Peripherals

4.1 32-Bit CPU-Timers 0/1/2

4.2 Event Manager Modules (EVA, EVB)

4.2.1 General-Purpose (GP) Timers

4.2.2 Full-Compare Units

4.2.3 Programmable Deadband Generator

4.2.4 PWM Waveform Generation

4.2.5 Double Update PWM Mode

4.2.6 PWM Characteristics

4.2.7 Capture Unit

4.2.8 Quadrature-Encoder Pulse (QEP) Circuit

4.2.9 External ADC Start-of-Conversion

4.3 Enhanced Analog-to-Digital Converter (ADC) Module

4.4 Enhanced Controller Area Network (eCAN) Module

4.5 Multichannel Buffered Serial Port (McBSP) Module

4.6 Serial Communications Interface (SCI) Module

4.7 Serial Peripheral Interface (SPI) Module

4.8 GPIO MUX

5 Development Support

5.1 Device and Development Support Tool Nomenclature

5.2 Documentation Support

5.3 Community Resources

6 Electrical Specifications

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)