TEXAS INSTRUMENTS TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801 Technical data

...

Download

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

Data Manual

Literature Number: SPRS230J

October 2003 – Revised September 2007

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Contents

Revision History ........................................................................................................................... 9

1 F280x, F2801x, C280x DSPs ................................................................................................. 11

1.1 Features ..................................................................................................................... 11

1.2 Getting Started .............................................................................................................. 12

2 Introduction ....................................................................................................................... 13

2.1 Pin Assignments ............................................................................................................ 15

2.2 Signal Descriptions ......................................................................................................... 21

3 Functional Overview ........................................................................................................... 27

3.1 Memory Maps ............................................................................................................... 28

3.2 Brief Descriptions ........................................................................................................... 36

3.2.1 C28x CPU ....................................................................................................... 36

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 36

3.2.3 Peripheral Bus .................................................................................................. 36

3.2.4 Real-Time JTAG and Analysis ................................................................................ 36

3.2.5 Flash .............................................................................................................. 37

3.2.6 ROM ............................................................................................................... 37

3.2.7 M0, M1 SARAMs ............................................................................................... 37

3.2.8 L0, L1, H0 SARAMs ............................................................................................ 37

3.2.9 Boot ROM ........................................................................................................ 37

3.2.10 Security .......................................................................................................... 39

3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 40

3.2.12 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 40

3.2.13 Oscillator and PLL .............................................................................................. 40

3.2.14 Watchdog ........................................................................................................ 40

3.2.15 Peripheral Clocking ............................................................................................. 40

3.2.16 Low-Power Modes .............................................................................................. 40

3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 41

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 41

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 41

3.2.20 Control Peripherals ............................................................................................. 41

3.2.21 Serial Port Peripherals ......................................................................................... 42

3.3 Register Map ................................................................................................................ 42

3.4 Device Emulation Registers ............................................................................................... 44

3.5 Interrupts .................................................................................................................... 44

3.5.1 External Interrupts .............................................................................................. 47

3.6 System Control ............................................................................................................. 48

3.6.1 OSC and PLL Block ............................................................................................ 49

3.6.2 Watchdog Block ................................................................................................. 52

3.7 Low-Power Modes Block .................................................................................................. 53

4 Peripherals ........................................................................................................................ 54

4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 54

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 56

4.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 58

4.4 Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 58

4.5 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 61

4.6 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 63

4.6.1 ADC Connections if the ADC Is Not Used ................................................................... 66

4.6.2 ADC Registers ................................................................................................... 67

4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 68

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 73

Contents 2 Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) ........................................... 76

4.10 Inter-Integrated Circuit (I2C) .............................................................................................. 80

4.11 GPIO MUX .................................................................................................................. 82

5 Device Support .................................................................................................................. 86

5.1 Device and Development Support Tool Nomenclature ................................................................ 86

5.2 Documentation Support ................................................................................................... 88

6 Electrical Specifications ...................................................................................................... 91

6.1 Absolute Maximum Ratings ............................................................................................... 91

6.2 Recommended Operating Conditions ................................................................................... 92

6.3 Electrical Characteristics ................................................................................................. 92

6.4 Current Consumption ..................................................................................................... 93

6.4.1 Reducing Current Consumption .............................................................................. 97

6.4.2 Current Consumption Graphs .................................................................................. 98

6.5 Emulator Connection Without Signal Buffering for the DSP .......................................................... 99

6.6 Timing Parameter Symbology ........................................................................................... 100

6.6.1 General Notes on Timing Parameters ....................................................................... 100

6.6.2 Test Load Circuit .............................................................................................. 101

6.6.3 Device Clock Table ........................................................................................... 101

6.7 Clock Requirements and Characteristics ............................................................................. 103

6.8 Power Sequencing ........................................................................................................ 104

6.8.1 Power Management and Supervisory Circuit Solutions ................................................... 104

6.9 General-Purpose Input/Output (GPIO) ................................................................................. 107

6.9.1 GPIO - Output Timing ......................................................................................... 107

6.9.2 GPIO - Input Timing ........................................................................................... 108

6.9.3 Sampling Window Width for Input Signals .................................................................. 109

6.9.4 Low-Power Mode Wakeup Timing ........................................................................... 110

6.10 Enhanced Control Peripherals .......................................................................................... 113

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ........................................................ 113

6.10.2 Trip-Zone Input Timing ........................................................................................ 113

6.10.3 External Interrupt Timing ...................................................................................... 115

6.10.4 I2C Electrical Specification and Timing ..................................................................... 116

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing .................................................... 116

6.10.6 SPI Slave Mode Timing ....................................................................................... 120

6.10.7 On-Chip Analog-to-Digital Converter ........................................................................ 123

6.11 Detailed Descriptions .................................................................................................... 128

6.12 Flash Timing ............................................................................................................... 129

6.13 ROM Timing (C280x only) ............................................................................................... 130

7 Migrating From F280x Devices to C280x Devices .................................................................. 131

7.1 Migration Issues ........................................................................................................... 131

8 Mechanical Data ............................................................................................................... 132

Contents 3

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

List of Figures

2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................. 16

2-2 TMS320F2806 100-Pin PZ LQFP (Top View) ................................................................................. 17

2-3 TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP

(Top View) ......................................................................................................................... 18

2-4 TMS320F2801x 100-Pin PZ LQFP

(Top View) ......................................................................................................................... 19

2-5 TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801

100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 20

3-1 Functional Block Diagram ........................................................................................................ 27

3-2 F2809 Memory Map .............................................................................................................. 28

3-3 F2808 Memory Map .............................................................................................................. 29

3-4 F2806 Memory Map .............................................................................................................. 30

3-5 F2802, C2802 Memory Map ..................................................................................................... 31

3-6 F2801, F28015, F28016, C2801 Memory Map ............................................................................... 32

3-7 External and PIE Interrupt Sources ............................................................................................. 45

3-8 Multiplexing of Interrupts Using the PIE Block ................................................................................ 46

3-9 Clock and Reset Domains ....................................................................................................... 48

3-10 OSC and PLL Block Diagram ................................................................................................... 49

3-11 Using a 3.3-V External Oscillator ............................................................................................... 50

3-12 Using a 1.8-V External Oscillator ............................................................................................... 50

3-13 Using the Internal Oscillator ..................................................................................................... 50

3-14 Watchdog Module ................................................................................................................. 52

4-1 CPU-Timers ........................................................................................................................ 54

4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 55

4-3 Multiple PWM Modules in a 280x System ..................................................................................... 56

4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 58

4-5 eCAP Functional Block Diagram ................................................................................................ 59

4-6 eQEP Functional Block Diagram ................................................................................................ 61

4-7 Block Diagram of the ADC Module ............................................................................................. 64

4-8 ADC Pin Connections With Internal Reference ............................................................................... 65

4-9 ADC Pin Connections With External Reference .............................................................................. 66

4-10 eCAN Block Diagram and Interface Circuit .................................................................................... 69

4-11 eCAN-A Memory Map ............................................................................................................ 70

4-12 eCAN-B Memory Map ............................................................................................................ 71

4-13 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 75

4-14 SPI Module Block Diagram (Slave Mode) ..................................................................................... 79

4-15 I2C Peripheral Module Interfaces ............................................................................................... 81

4-16 GPIO MUX Block Diagram ....................................................................................................... 82

4-17 Qualification Using Sampling Window .......................................................................................... 85

5-1 Example of TMS320x280x Device Nomenclature ............................................................................ 87

List of Figures4 Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-1 Typical Operational Current Versus Frequency (F2808) .................................................................... 98

6-2 Typical Operational Power Versus Frequency (F2808) ...................................................................... 98

6-3 Emulator Connection Without Signal Buffering for the DSP ................................................................. 99

6-4 3.3-V Test Load Circuit ......................................................................................................... 101

6-5 Clock Timing ..................................................................................................................... 104

6-6 Power-on Reset .................................................................................................................. 105

6-7 Warm Reset ...................................................................................................................... 106

6-8 Example of Effect of Writing Into PLLCR Register .......................................................................... 107

6-9 General-Purpose Output Timing ............................................................................................... 107

6-10 Sampling Mode .................................................................................................................. 108

6-11 General-Purpose Input Timing ................................................................................................. 109

6-12 IDLE Entry and Exit Timing .................................................................................................... 110

6-13 STANDBY Entry and Exit Timing Diagram ................................................................................... 111

6-14 HALT Wake-Up Using GPIOn ................................................................................................. 112

6-15 PWM Hi-Z Characteristics ...................................................................................................... 113

6-16 ADCSOCAO or ADCSOCBO Timing ......................................................................................... 115

6-17 External Interrupt Timing ....................................................................................................... 115

6-18 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 118

6-19 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 120

6-20 SPI Slave Mode External Timing (Clock Phase = 0) ........................................................................ 121

6-21 SPI Slave Mode External Timing (Clock Phase = 1) ........................................................................ 122

6-22 ADC Power-Up Control Bit Timing ............................................................................................ 124

6-23 ADC Analog Input Impedance Model ......................................................................................... 125

6-24 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 126

6-25 Simultaneous Sampling Mode Timing ........................................................................................ 127

List of Figures 5

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

List of Tables

2-1 Hardware Features (100-MHz Devices) ........................................................................................ 14

2-2 Hardware Features (60-MHz Devices) ......................................................................................... 15

2-3 Signal Descriptions ............................................................................................................... 21

3-1 Addresses of Flash Sectors in F2809 .......................................................................................... 33

3-2 Addresses of Flash Sectors in F2808 .......................................................................................... 33

3-3 Addresses of Flash Sectors in F2806, F2802 ................................................................................. 33

3-4 Addresses of Flash Sectors in F2801, F28015, F28016 ..................................................................... 34

3-5 Impact of Using the Code Security Module .................................................................................... 34

3-6 Wait-states ......................................................................................................................... 35

3-7 Boot Mode Selection .............................................................................................................. 38

3-8 Peripheral Frame 0 Registers .................................................................................................. 43

3-9 Peripheral Frame 1 Registers .................................................................................................. 43

3-10 Peripheral Frame 2 Registers .................................................................................................. 44

3-11 Device Emulation Registers ..................................................................................................... 44

3-12 PIE Peripheral Interrupts ........................................................................................................ 46

3-13 PIE Configuration and Control Registers ...................................................................................... 47

3-14 External Interrupt Registers ...................................................................................................... 47

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 49

3-16 PLLCR Register Bit Definitions .................................................................................................. 51

3-17 Possible PLL Configuration Modes ............................................................................................. 51

3-18 Low-Power Modes ................................................................................................................ 53

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 55

4-2 ePWM Control and Status Registers ........................................................................................... 57

4-3 eCAP Control and Status Registers ............................................................................................ 59

4-4 eQEP Control and Status Registers ............................................................................................ 62

4-5 ADC Registers ..................................................................................................................... 67

4-6 3.3-V eCAN Transceivers ....................................................................................................... 69

4-7 CAN Register Map ............................................................................................................... 72

4-8 SCI-A Registers .................................................................................................................. 74

4-9 SCI-B Registers .................................................................................................................. 74

4-10 SPI-A Registers ................................................................................................................... 77

4-11 SPI-B Registers ................................................................................................................... 77

4-12 SPI-C Registers ................................................................................................................... 78

4-13 SPI-D Registers ................................................................................................................... 78

4-14 I2C-A Registers .................................................................................................................... 81

4-15 GPIO Registers ................................................................................................................... 83

4-16 F2808 GPIO MUX Table ......................................................................................................... 84

6-1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............ 93

6-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .............................. 94

List of Tables6 Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............ 95

6-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ........... 96

6-5 Typical Current Consumption by Various Peripherals (at 100 MHz) ...................................................... 97

6-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices) ...................................................... 101

6-7 TMS320x280x Clock Table and Nomenclature (60-MHz Devices) ....................................................... 102

6-8 Input Clock Frequency .......................................................................................................... 103

6-9 XCLKIN Timing Requirements - PLL Enabled ............................................................................... 103

6-10 XCLKIN Timing Requirements - PLL Disabled .............................................................................. 103

6-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 103

6-12 Power Management and Supervisory Circuit Solutions .................................................................... 104

6-13 Reset ( XRS) Timing Requirements ........................................................................................... 106

6-14 General-Purpose Output Switching Characteristics ......................................................................... 107

6-15 General-Purpose Input Timing Requirements ............................................................................... 108

6-16 IDLE Mode Timing Requirements ............................................................................................. 110

6-17 IDLE Mode Switching Characteristics ......................................................................................... 110

6-18 STANDBY Mode Timing Requirements ...................................................................................... 110

6-19 STANDBY Mode Switching Characteristics ................................................................................. 111

6-20 HALT Mode Timing Requirements ............................................................................................ 111

6-21 HALT Mode Switching Characteristics ....................................................................................... 112

6-22 ePWM Timing Requirements................................................................................................... 113

6-23 ePWM Switching Characteristics .............................................................................................. 113

6-24 Trip-Zone input Timing Requirements ........................................................................................ 113

6-25 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) .............................................. 114

6-26 Enhanced Capture (eCAP) Timing Requirement ............................................................................ 114

6-27 eCAP Switching Characteristics ............................................................................................... 114

6-28 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................... 114

6-29 eQEP Switching Characteristics ............................................................................................... 114

6-30 External ADC Start-of-Conversion Switching Characteristics .............................................................. 114

6-31 External Interrupt Timing Requirements ...................................................................................... 115

6-32 External Interrupt Switching Characteristics ................................................................................. 115

6-33 I2C Timing ....................................................................................................................... 116

6-34 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 117

6-35 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 119

6-36 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 120

6-37 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 121

6-38 ADC Electrical Characteristics (over recommended operating conditions) .............................................. 123

6-39 ADC Power-Up Delays .......................................................................................................... 124

6-40 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) ....................................... 124

6-41 Sequential Sampling Mode Timing ............................................................................................ 126

6-42 Simultaneous Sampling Mode Timing ........................................................................................ 127

6-43 Flash Endurance ................................................................................................................. 129

List of Tables 7

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6-44 Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 129

6-45 Flash/OTP Access Timing ...................................................................................................... 129

6-46 Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 130

6-47 ROM/OTP Access Timing ...................................................................................................... 130

6-48 ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies ..................................... 130

8-1 F280x Thermal Model 100-pin GGM Results ................................................................................ 132

8-2 F280x Thermal Model 100-pin PZ Results ................................................................................... 132

8-3 C280x Thermal Model 100-pin GGM Results ................................................................................ 132

8-4 C280x Thermal Model 100-pin PZ Results ................................................................................... 132

8-5 F2809 Thermal Model 100-pin GGM Results ............................................................................... 132

8-6 F2809 Thermal Model 100-pin PZ Results .................................................................................. 133

List of Tables8 Submit Documentation Feedback

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual was revised from SPRS230I to SPRS230J. This document has been reviewed for technical accuracy; the technical content is up to date as of the

specified release date with the following changes:

Technical Changes Made for Revision J

Location Additions, Deletions, Changes

Section 2.1 Modified first paragraph in section on pin assignments Figure 2-3 Modified the TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP

Figure 2-5 Added 2801x devices to title of pinmap for GGM and ZGM packages Table 2-3 Changed description of EPWM5A and EPWM6A Figure 3-5 Added a note to the 2802 memory map Figure 3-6 Added a note to the 2801, 2801x memory map Table 3-6 Modified Wait-states table Table 3-6 Modified section on ROM Section 3.2.10 Deleted part of note in section on security Section 3.2.19 Modified section on 32-bit CPU timers Figure 3-7 Modified External and PIE Interrupt Sources figure and added two paragraphs following figure Figure 4-2 Modified figure Section 4.3 Deleted note in HRPWM section

pinmap

Revision History 9

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Revision History10 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

1 F280x, F2801x, C280x DSPs

1.1 Features

• High-Performance Static CMOS Technology • Enhanced Control Peripherals

– 100 MHz (10-ns Cycle Time) – Up to 16 PWM Outputs – 60 MHz (16.67-ns Cycle Time) – Up to 6 HRPWM Outputs With 150 ps MEP – Low-Power (1.8-V Core, 3.3-V I/O) Design

• JTAG Boundary Scan Support

(1)

• High-Performance 32-Bit CPU (TMS320C28x)

– 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly)

• On-Chip Memory

– F2809: 128K X 16 Flash, 18K X 16 SARAM

F2808: 64K X 16 Flash, 18K X 16 SARAM F2806: 32K X 16 Flash, 10K X 16 SARAM F2802: 32K X 16 Flash, 6K X 16 SARAM F2801: 16K X 16 Flash, 6K X 16 SARAM

F2801x: 16K X 16 Flash, 6K X 16 SARAM – 1K x 16 OTP ROM (Flash Devices Only) – C2802: 32K X 16 ROM, 6K X 16 SARAM

C2801: 16K X 16 ROM, 6K X 16 SARAM

• Boot ROM (4K x 16)

– With Software Boot Modes (via SCI, SPI,

CAN, I2C, and Parallel I/O) – Standard Math Tables

• Clock and System Control

– Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module

• Any GPIO A Pin Can Be Connected to One of

the Three External Core Interrupts

• Peripheral Interrupt Expansion (PIE) Block

That Supports All 43 Peripheral Interrupts

• 128-Bit Security Key/Lock

– Protects Flash/OTP/L0/L1 Blocks – Prevents Firmware Reverse Engineering

• Three 32-Bit CPU Timers

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

Resolution – Up to Four Capture Inputs – Up to Two Quadrature Encoder Interfaces – Up to Six 32-bit/Six 16-bit Timers

• Serial Port Peripherals

– Up to 4 SPI Modules – Up to 2 SCI (UART) Modules – Up to 2 CAN Modules – One Inter-Integrated-Circuit (I2C) Bus

• 12-Bit ADC, 16 Channels

– 2 x 8 Channel Input Multiplexer – Two Sample-and-Hold – Single/Simultaneous Conversions – Fast Conversion Rate:

80 ns - 12.5 MSPS (F2809 only)

160 ns - 6.25 MSPS (280x)

267 ns - 3.75 MSPS (F2801x) – Internal or External Reference

• Up to 35 Individually Programmable,

Multiplexed GPIO Pins With Input Filtering

• Advanced Emulation Features

– Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• Development Support Includes

– ANSI C/C++ Compiler/Assembler/Linker – Code Composer Studio™ IDE – DSP/BIOS™ – Digital Motor Control and Digital Power

Software Libraries

• Low-Power Modes and Power Savings

– IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks

• Package Options

– Thin Quad Flatpack (PZ) – MicroStar BGA™ (GGM, ZGM)

• Temperature Options:

– A: -40C to 85C (PZ, GGM, ZGM) – S: -40C to 125C (PZ, GGM, ZGM)

– Q: -40C to 125C (PZ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, C28x, TMS320C2000 are trademarks of Texas Instruments. eZdsp is a trademark of Spectrum Digital.

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following:

• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

Step 1. Acquire the appropriate development tools

The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial development, which, in one package, includes:

• On-board JTAG emulation via USB or parallel port

• Appropriate emulation driver

• Code Composer Studio™ IDE for eZdsp

Once you have become familiar with the device and begin developing on your own hardware, purchase Code Composer Studio™ IDE separately for software development and a JTAG emulation tool to get started on your project.

Step 2. Download starter software

To simplify programming for C28x devices, it is recommended that users download and use the C/C++ Header Files and Example(s) to begin developing software for the C28x devices and their various peripherals.

After downloading the appropriate header file package for your device, refer to the following resources for step-by-step instructions on how to run the peripheral examples and use the header file structure for your own software

• The Quick Start Readme in the /doc directory to run your first application.

• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report

(literature number SPRAA85 )

Step 3. Download flash programming software

Many C28x devices include on-chip flash memory and tools that allow you to program the flash with your software IP.

• Flash Tools: C28x Flash Tools

• TMS320F281x Flash Programming Solutions (literature number SPRB169 )

• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature

number SPRA958 )

Step 4. Move on to more advanced topics

For more application software and other advanced topics, visit the TI website at

http://www.ti.com or http://www.ti.com/c2000getstarted .

12 F280x, F2801x, C280x DSPs Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

2 Introduction

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015, TMS320F28016, TMS320C2802, and TMS320C2801, devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS32028016 are abbreviated as F2809, F2808, F2806, F2802, F2801, F28015, F28016, C2802, and C2801, respectively. TMS320F28015 and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for each device.

Submit Documentation Feedback Introduction 13

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-1. Hardware Features (100-MHz Devices)

FEATURE F2809 F2808 F2806 F2802 F2801 C2802 C2801

Instruction cycle (at 100 MHz) 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

Single-access RAM (SARAM) (16-bit word) (L0, L1, M0, M1, (L0, L1, M0, M1,

3.3-V on-chip flash (16-bit word) 128K 64K 32K 32K 16K – – On-chip ROM (16-bit word) – – – – – 32K 16K Code security for on-chip flash/SARAM/OTP blocks Yes Yes Yes Yes Yes Yes Yes Boot ROM (4K X16) Yes Yes Yes Yes Yes Yes Yes One-time programmable (OTP) ROM

(16-bit word) PWM outputs ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3

HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A 32-bit CAPTURE inputs or auxiliary PWM outputs eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2

32-bit QEP channels (four inputs/channel) eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1 Watchdog timer Yes Yes Yes Yes Yes Yes Yes 12-Bit, 16-channel ADC conversion time 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns 32-Bit CPU timers 3 3 3 3 3 3 3 Serial Peripheral Interface (SPI) SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B Serial Communications Interface (SCI) SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A Enhanced Controller Area Network (eCAN) eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A Digital I/O pins (shared) 35 35 35 35 35 35 35 External interrupts 3 3 3 3 3 3 3 Supply voltage 1.8-V Core, 3.3-V I/O Yes Yes Yes Yes Yes Yes Yes

Packaging

Temperature options S: -40 ° C to 125 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Product status

(1)

100-Pin PZ Yes Yes Yes Yes Yes Yes Yes 100-Ball GGM, ZGM Yes Yes Yes Yes Yes Yes Yes A: -40 ° C to 85 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: -40 ° C to 125 ° C (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ)

18K 18K

H0) H0)

1K 1K 1K 1K 1K – –

ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/

4A/5A/6A 3A/4A 3A/4A

TMS TMS TMS TMS TMS TMS TMS

10K 6K 6K 6K 6K

(L0, L1, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

14 Introduction Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-2. Hardware Features (60-MHz Devices)

FEATURE F2802-60 F2801-60 F28016 F28015

Instruction cycle (at 60 MHz) 16.67 ns 16.67 ns 16.67 ns 16.67 ns Single-access RAM (SARAM) (16-bit word)

3.3-V on-chip flash (16-bit word) 32K 16K 16K 16K On-chip ROM (16-bit word) – – – – Code security for on-chip flash/SARAM/OTP

blocks Boot ROM (4K X16) Yes Yes Yes Yes One-time programmable (OTP) ROM

(16-bit word) PWM outputs ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4 HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A 32-bit CAPTURE inputs or auxiliary PWM

outputs 32-bit QEP channels (four inputs/channel) eQEP1 eQEP1 - Watchdog timer Yes Yes Yes Yes

No. of channels 16 16 16 16

12-Bit ADC MSPS 3.75 3.75 3.75 3.75

Conversion time 267 ns 267 ns 267 ns 267 ns 32-Bit CPU timers 3 3 3 3 Serial Peripheral Interface (SPI) SPI-A/B SPI-A/B SPI-A SPI-A Serial Communications Interface (SCI) SCI-A SCI-A SCI-A SCI-A Enhanced Controller Area Network (eCAN) eCAN-A eCAN-A eCAN-A Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A Digital I/O pins (shared) 35 35 35 35 External interrupts 3 3 3 3

Supply voltage

Packaging

Temperature options S: -40 ° C to 125 ° C (PZ GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Product status

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

(1)

100-Pin PZ Yes Yes Yes Yes

100-Ball GGM, ZGM Yes Yes Yes Yes

A: -40 ° C to 85 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: -40 ° C to 125 ° C (PZ) (PZ) (PZ) (PZ)

6K 6K 6K 6K

(L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

Yes Yes Yes Yes

1K 1K 1K 1K

eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2

1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,

3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O

TMS TMS TMS TMS

2.1 Pin Assignments

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1 , Figure 2-2 , Figure 2-3 , and Figure 2-4 . The 100-ball GGM and ZGM ball grid array (BGA) terminal assignments are shown in Figure 2-5 . Table 2-3 describes the function(s) of each pin.

Submit Documentation Feedback Introduction 15

www.ti.com

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

GPIO0/EPWM1A

TCK

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

GPIO22/EQEP1S/SPICLKC/SCITXDB

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO21/EQEP1B/SPISOMIC/CANRXB

XCLKOUT

GPIO20/EQEP1A/SPISIMOC/CANTXB

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO18/SPICLKA/SCITXDB

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO4/EPWM3A

XRS

TRST

DDIO

GPIO10/EPWM6A/CANRXB/ADCSOCBO

GPIO8/EPWM5A/CANTXB/ADCSOCAO

GPIO17/SPISOMIA/CANRXB/TZ6

DDIO

GPIO16/SPISIMOA/CANTXB/TZ5

DD2A18

SS2AGND

DDAIO

GPIO12/TZ1/CANTXB/SPISIMOB

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3/SCITXDB/SPICLKB

DD1A18

SS1AGND

SSA2

DDA2

GPIO15/TZ4/SCIRXDB/SPISTEB

SSAIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO13/TZ2/CANRXB/SPISOMIB

DD3VFL

GPIO28/SCIRXDA/TZ5

DDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

EMU1

EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B/SPISIMOD

GPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)

Introduction 16 Submit Documentation Feedback

www.ti.com

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

100

GPIO3/EPWM2B/SPISOMID GPIO0/EPWM1A

GPIO2/EPWM2A GPIO1/EPWM1B/SPISIMOD

GPIO34

ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINB0

TCK

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

GPIO22/EQEP1S/SPICLKC/SCITXDB

XCLKOUT

GPIO20/EQEP1A/SPISIMOC

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO18/SPICLKA/SCITXDB

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO4/EPWM3A

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

XRS

TRST

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO21/EQEP1B/SPISOMIC

DDIO

GPIO16/SPISIMOA/TZ5

DD2A18

SS2AGND

DDAIO

DDIO

GPIO10/EPWM6A/ADCSOCBO

GPIO8/EPWM5A/ADCSOCAO

GPIO17/SPISOMIA/TZ6

DD3VFL

GPIO28/SCIRXDA/TZ5

DDIO

GPIO13/TZ2/SPISOMIB

GPIO12/TZ1/SPISIMOB

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3/SCITXDB/SPICLKB

DD1A18

SS1AGND

SSA2

DDA2

GPIO15/TZ4/SCIRXDB/SPISTEB

SSAIO

DDIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

GPIO24/ECAP1/EQEP2A/SPISIMOB

EMU1

EMU0

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)

Submit Documentation Feedback Introduction 17

www.ti.com

100

101112

GPIO0/EPWM1A

GPIO2/EPWM2A GPIO1/EPWM1B

GPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFIN ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3 ADCINB2

ADCINB1

ADCINB0

TCK

TMS

TDI

CLKOUT

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCL

XRS

TRST

SPISIMOB/GPIO12/TZ1

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

DD1A18

SS1AGND

SSA2

DDA2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

SPISOMIB/GPIO13/TZ2

DD3VFL

(A)

GPIO28/SCIRXDA/TZ5

GPIO21/EQEP1B

SSVDD

GPIO23/EQEP1I

GPIO22/EQEP1S

DDIO

GPIO10/ADC

SOCBO

GPIO20/EQEP1A

GPIO9

GPIO8/ADCSOCAO

GPIO7/ECAP2

GPIO19/SPISTEA

GPIO6/EPWMSYNCI/EPWMSYNCO

GPIO1

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

DDIO

GPIO16/SPISIMOA/TZ5

GPIO3/EPWM2B

DD2A18

SS2AGND

DDAIO

SPICLKB/GPIO14/TZ3

SPISTEB/GPIO15/TZ4

SPISTEB/GPIO27

DDIO

SPISIMOB/GPIO24/ECAP1

SSAIO

GPIO25/ECAP2/SPISOMIB

SPICLKB/GPIO26

TEST2

TEST1

XCLKIN

EMU1

EMU0

TDO

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. On the C280x devices, the V

Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP

pin is V

DD3VFL

DDIO

(Top View)

Introduction 18 Submit Documentation Feedback

www.ti.com

100

101112

GPIO0/EPWM1A

GPIO2/EPWM2A GPIO1/EPWM1B

GPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFIN ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3 ADCINB2

ADCINB1

ADCINB0

TCK

TMS

TDI

CLKOUT

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCL

XRS

TRST

GPIO12/TZ1

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3

DD1A18

SS1AGND

SSA2

DDA2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

GPIO13/TZ2

DD3VFL

(A)

GPIO28/SCIRXDA/TZ5

GPIO21

GPIO23

GPIO22

DDIO

GPIO10/ADC

SOCBO

GPIO20

GPIO9

GPIO8/ADCSOCAO

GPIO7/EPWM4B/ECAP2

GPIO19/SPISTEA

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO11

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

DDIO

GPIO16/SPISIMOA/TZ5

GPIO3/EPWM2B

DD2A18

SS2AGND

DDAIO

GPIO15/TZ4

GPIO27

DDIO

GPIO24/ECAP1

SSAIO

GPIO25/ECAP2

GPIO26

TEST2

TEST1

XCLKIN

EMU1

EMU0

TDO

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.

Submit Documentation Feedback Introduction 19

Figure 2-4. TMS320F2801x 100-Pin PZ LQFP

(Top View)

www.ti.com

21 3

5 76 98 10

Bottom View

TRST TCK

TDI

TDO TMS

EMU0

EMU1

DD3VFL

TEST1

TEST2

XCLKOUT

XCLKIN

XRS

GPIO0

GPIO1

GPIO2 GPIO3 GPIO4

GPIO5

GPIO6GPIO7

GPIO9 GPIO8

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23GPIO24GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

DDA2

DD1A18

SS1AGND

DDIO

VSSAIO

DDAIO

VSSA2

ADCINA7

SS2AGND

DD2A18

DDIO

VSS

ADCINB2

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCINB7

ADCINB1

ADCINB0

ADCLO

ADCRESEXT

ADCREFIN

ADCREFP

ADCREFM

ADCINB3

ADCINB5

ADCINB4

ADCINB6

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801

100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

20 Introduction Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

2.2 Signal Descriptions

Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-3. Signal Descriptions

PIN NO.

NAME DESCRIPTION

PIN #

TRST 84 A6

TCK 75 A10 JTAG test clock with internal pullup (I, ↑ ) TMS 74 B10

TDI 73 C9

TDO 76 B9

EMU0 80 A8 (I/O/Z, 8 mA drive ↑ )

EMU1 81 B7 (I/O/Z, 8 mA drive ↑ )

DD3VFL

TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O) TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal

XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is

96 C4

GGM/

ZGM

BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓ )

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑ )

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑ )

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM parts (C280x), this pin should be connected to V

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, used to feed clock to X1 pin), this pin must be tied to GND. (I)

DDIO

(1)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

Submit Documentation Feedback Introduction 21

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

X2 86 C6

XRS 78 B8

ADCINA7 16 F3 ADC Group A, Channel 7 input (I) ADCINA6 17 F4 ADC Group A, Channel 6 input (I) ADCINA5 18 G4 ADC Group A, Channel 5 input (I) ADCINA4 19 G1 ADC Group A, Channel 4 input (I) ADCINA3 20 G2 ADC Group A, Channel 3 input (I) ADCINA2 21 G3 ADC Group A, Channel 2 input (I) ADCINA1 22 H1 ADC Group A, Channel 1 input (I) ADCINA0 23 H2 ADC Group A, Channel 0 input (I) ADCINB7 34 K5 ADC Group B, Channel 7 input (I) ADCINB6 33 H4 ADC Group B, Channel 6 input (I) ADCINB5 32 K4 ADC Group B, Channel 5 input (I) ADCINB4 31 J4 ADC Group B, Channel 4 input (I) ADCINB3 30 K3 ADC Group B, Channel 3 input (I) ADCINB2 29 H3 ADC Group B, Channel 2 input (I) ADCINB1 28 J3 ADC Group B, Channel 1 input (I) ADCINB0 27 K2 ADC Group B, Channel 0 input (I) ADCLO 24 J1 Low Reference (connect to analog ground) (I) ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground. ADCREFIN 35 J5 External reference input (I)

ADCREFP 37 G5

ADCREFM 36 H5

DDA2

SSA2

DDAIO

SSAIO

DD1A18

SS1AGND

DD2A18

SS2AGND

GGM/

15 F2 ADC Analog Power Pin (3.3 V) 14 F1 ADC Analog Ground Pin 26 J2 ADC Analog I/O Power Pin (3.3 V) 25 K1 ADC Analog I/O Ground Pin 12 E4 ADC Analog Power Pin (1.8 V) 13 E5 ADC Analog Ground Pin 40 J6 ADC Analog Power Pin (1.8 V) 39 K6 ADC Analog Ground Pin

ZGM

BALL #

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑ ) The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.

ADC SIGNALS

Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 μ F to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 μ F to analog ground. (O)

CPU AND I/O POWER PINS

(1)

Introduction 22 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

DDIO

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM1B Enhanced PWM1 Output B (O) SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801, 2802)

- GPIO2 General purpose input/output 2 (I/O/Z)

EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM2B Enhanced PWM2 Output B (O) SPISOMID SPI-D slave out, master in (I/O) (not available on 2801, 2802)

- GPIO4 General purpose input/output 4 (I/O/Z)

EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM3B Enhanced PWM3 output B (O) SPICLKD SPI-D clock (I/O) (not available on 2801, 2802) ECAP1 Enhanced capture input/output 1 (I/O)

GGM/

ZGM

BALL #

10 E2 42 G6 59 F10 68 D7

CPU and Logic Digital Power Pins (1.8 V)

85 B6 93 D4

3 C2 46 H7 65 E9

Digital I/O Power Pin (3.3 V)

82 A7

2 B1 11 E3 41 H6 49 K9 55 H10 62 F7 Digital Ground Pins 69 D10 77 A9 87 D6 89 A5 94 A4

GPIOA AND PERIPHERAL SIGNALS

47 K8

44 K7

45 J7

48 J8

51 J9

53 H9

(2) (3)

(4)

TMS320F2802, TMS320F2801

(1)

(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details. (3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

Submit Documentation Feedback Introduction 23

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO6 General purpose input/output 6 (I/O/Z) EPWM4A Enhanced PWM4 output A and HRPWM channel (not available on 2801, 2802) (O) EPWMSYNCI External ePWM sync pulse input (I)

56 G9

GGM/

ZGM

BALL #

(4)

EPWMSYNCO External ePWM sync pulse output (O) GPIO7 General purpose input/output 7 (I/O/Z)

EPWM4B Enhanced PWM4 output B (not available on 2801, 2802) (O) SPISTED SPI-D slave transmit enable (not available on 2801, 2802) (I/O)

58 G8

(4)

ECAP2 Enhanced capture input/output 2 (I/O) GPIO8 General purpose input/output 8 (I/O/Z)

EPWM5A Enhanced PWM5 output A and HRPWM channel (not available on 2801, 2802) (O) CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)

60 F9

(4)

ADCSOCAO ADC start-of-conversion A (O) GPIO9 General purpose input/output 9 (I/O/Z)

EPWM5B Enhanced PWM5 output B (not available on 2801, 2802) (O) SCITXDB SCI-B transmit data (not available on 2801, 2802) (O)

61 F8

(4)

ECAP3 Enhanced capture input/output 3 (not available on 2801, 2802) (I/O) GPIO10 General purpose input/output 10 (I/O/Z)

EPWM6A Enhanced PWM6 output A and HRPWM channel (not available on 2801, 2802) (O) CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)

64 E10

(4)

ADCSOCBO ADC start-of-conversion B (O) GPIO11 General purpose input/output 11 (I/O/Z)

EPWM6B Enhanced PWM6 output B (not available on 2801, 2802) (O) SCIRXDB SCI-B receive data (not available on 2801, 2802) (I)

70 D9

(4)

ECAP4 Enhanced CAP Input/Output 4 (not available on 2801, 2802) (I/O) GPIO12 General purpose input/output 12 (I/O/Z)

TZ1 Trip Zone input 1 (I) CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)

1 B2

(5)

SPISIMOB SPI-B Slave in, Master out (I/O) GPIO13 General purpose input/output 13 (I/O/Z)

TZ2 Trip zone input 2 (I) CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)

95 B4

(5)

SPISOMIB SPI-B slave out, master in (I/O) GPIO14 General purpose input/output 14 (I/O/Z)

TZ3 Trip zone input 3 (I) SCITXDB SCI-B transmit (not available on 2801, 2802) (O)

8 D3

(5)

SPICLKB SPI-B clock input/output (I/O) GPIO15 General purpose input/output 15 (I/O/Z)

TZ4 Trip zone input (I) SCIRXDB SCI-B receive (not available on 2801, 2802) (I)

9 E1

(5)

SPISTEB SPI-B slave transmit enable (I/O) GPIO16 General purpose input/output 16 (I/O/Z)

SPISIMOA SPI-A slave in, master out (I/O) CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)

50 K10

(5)

TZ5 Trip zone input 5 (I) GPIO17 General purpose input/output 17 (I/O/Z)

SPISOMIA SPI-A slave out, master in (I/O) CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)

52 J10

(5)

TZ6 Trip zone input 6(I) GPIO18 General purpose input/output 18 (I/O/Z)

(5)

SPICLKA SPI-A clock input/output (I/O) SCITXDB 54 H8 SCI-B transmit (not available on 2801, 2802) (O)

- -

- GPIO19 General purpose input/output 19 (I/O/Z)

(5)

SPISTEA SPI-A slave transmit enable input/output (I/O) SCIRXDB 57 G10 SCI-B receive (not available on 2801, 2802) (I)

- -

(1)

(5) The pullups on GPIO12-GPIO34 are enabled upon reset.

Introduction 24 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO20 General purpose input/output 20 (I/O/Z) EQEP1A Enhanced QEP1 input A (I) SPISIMOC SPI-C slave in, master out (not available on 2801, 2802) (I/O)

63 F6

GGM/

ZGM

BALL #

(5)

CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O) GPIO21 General purpose input/output 21 (I/O/Z)

EQEP1B Enhanced QEP1 input A (I) SPISOMIC SPI-C master in, slave out (not available on 2801, 2802) (I/O)

67 E7

(5)

CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I) GPIO22 General purpose input/output 22 (I/O/Z)

EQEP1S Enhanced QEP1 strobe (I/O) SPICLKC SPI-C clock (not available on 2801, 2802) (I/O)

71 D8

(5)

SCITXDB SCI-B transmit (not available on 2801, 2802) (O) GPIO23 General purpose input/output 23 (I/O/Z)

EQEP1I Enhanced QEP1 index (I/O) SPISTEC SPI-C slave transmit enable (not available on 2801, 2802) (I/O)

72 C10

(5)

SCIRXDB SCI-B receive (I) (not available on 2801, 2802) GPIO24 General purpose input/output 24 (I/O/Z)

ECAP1 Enhanced capture 1 (I/O) EQEP2A Enhanced QEP2 input A (I) (not available on 2801, 2802)

83 C7

(5)

SPISIMOB SPI-B slave in, master out (I/O) GPIO25 General purpose input/output 25 (I/O/Z)

ECAP2 Enhanced capture 2 (I/O) EQEP2B Enhanced QEP2 input B (I) (not available on 2801, 2802)

91 C5

(5)

SPISOMIB SPI-B master in, slave out (I/O) GPIO26 General purpose input/output 26 (I/O/Z)

ECAP3 Enhanced capture 3 (I/O) (not available on 2801, 2802) EQEP2I Enhanced QEP2 index (I/O) (not available on 2801, 2802)

99 A2

(5)

SPICLKB SPI-B clock (I/O) GPIO27 General purpose input/output 27 (I/O/Z)

ECAP4 Enhanced capture 4 (I/O) (not available on 2801, 2802) EQEP2S Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)

79 C8

(5)

SPISTEB SPI-B slave transmit enable (I/O) GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCIRXDA SCI receive data (I)

- -

92 D5

TZ5 Trip zone input 5 (I) GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCITXDA SCI transmit data (O)

- -

4 C3

TZ6 Trip zone 6 input (I) GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)

CANRXA Enhanced CAN-A receive data (I)

- -

6 D2

- GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)

CANTXA Enhanced CAN-A transmit data (O)

- -

7 D1

- GPIO32 General purpose input/output 32 (I/O/Z)

SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I)

100 A1

(5)

ADCSOCAO ADC start-of-conversion (O)

(1)

(5)

Submit Documentation Feedback Introduction 25

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z)

- -

(1) The pullups on GPIO12-GPIO34 are enabled upon reset.

GGM/

43 G7

ZGM

BALL #

5 C1

NOTE

Some peripheral functions may not be available in TMS320F2801x devices. See

Table 2-2 for details.

(1)

26 Introduction Submit Documentation Feedback

www.ti.com

3 Functional Overview

INT[12:1]

Real-TimeJTAG

(TDI,TDO,TRST

,TCK,

TMS,EMU0,EMU1)

C28xCPU

(100MHz)

NMI,INT13

MemoryBus

BootROM

4K 16

(1-waitstate)

FLASH

128Kx16(F2809)

64Kx16(F2808) 32Kx16(F2806) 32Kx16(F2802) 16Kx16(F2801)

16Kx16(F2801x)

H0SARAM

(C)

8K 16

(0-wait)

L1SARAM

(B)

4K 16 (0-wait)

L0SARAM

4K 16

(0-wait)

M0SARAM

1K 16

M1SARAM

1K 16

INT14

32-bitCPUTIMER0

32-bitCPUTIMER1

32-bitCPUTIMER2

SYSCLKOUT

CLKIN

12-BitADC

ADCSOCA/B

SOCA/B

16Channels

XCLKOUT

XRS

XCLKIN

X1 X2

SystemControl

(Oscillator,PLL,

PeripheralClocking,

LowPowerModes,

WatchDog)

ePWM1/2/3/4/5/6

(12PWMoutputs,

6tripzones,

6timers16-bit)

eCAP1/2/3/4

(4timers32-bit)

eQEP1/2

eCAN-A/B(32mbox)

ExternalInterrupt

Control

PIE

(96Interrupts)

(A)

FIFO

SCI-A/B

SPI-A/B/C/D

I2C-A

GPIOMUX

GPIOs

(35)

TINT0

TINT1

TINT2

OTP

(D)

1K 16

PeripheralBus

Protected bythecode-securitymodule.

ROM 32K x16(C2802) 16Kx16(C2801)

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. 43 of the possible 96 interrupts are used on the devices. B. Not available in F2802, F2801, C2802, and C2801. C. Not available in F2806, F2802, F2801, C2802, and C2801. D. The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.

Submit Documentation Feedback Functional Overview 27

Figure 3-1. Functional Block Diagram

www.ti.com

0x00 0000

Block Start

Address

Data Space

Prog Space

M0 SARAM (1 K y 16)

M1 SARAM (1 K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x00 A000

0x00 C000

OTP

(1 k y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(128 k y 16, Secure Zone)

0x3D 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x3F A000

0x3F F000

Boot ROM (4 k y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

Reserved

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.1 Memory Maps

A. Memory blocks are not to scale. B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space. C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Functional Overview28 Submit Documentation Feedback

Figure 3-2. F2809 Memory Map

www.ti.com

0x00 0000

Block Start

Address

Data Space

Prog Space

M0 SARAM (1 K y 16)

M1 SARAM (1 K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x00 A000

0x00 C000

OTP

(1 k y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(64 k y 16, Secure Zone)

0x3E 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x3F A000

0x3F F000

Boot ROM (4 k y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

Reserved

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. Memory blocks are not to scale. B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

Submit Documentation Feedback Functional Overview 29

Figure 3-3. F2808 Memory Map

www.ti.com

0x00 0000

Block Start

Address

Data Space

M0 SARAM (1K y 16)

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8 0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP

(1 K y 16, Secure Zone)

FLASH

(32 K y 16, Secure Zone)

Boot ROM (4 K y 16)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

Reserved

M1 SARAM (1K y 16)

L0 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L0 SARAM (0-wait) (4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k y 16, Secure Zone, Dual Mapped)

128-bit Password

0x3F 0000

Prog Space

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. Memory blocks are not to scale. B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Functional Overview30 Submit Documentation Feedback

User program cannot access these memory maps in program space.

Figure 3-4. F2806 Memory Map

www.ti.com

0x00 0000

Block Start

Address

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x3D 7800

0x3F 0000

0x3F 7FF8 0x3F 8000

0x3F 9000

0x3F F000

0x3F FFC0

OTP (F2802 Only)

(A)

(1K y 16, Secure Zone)

FLASH (F2802) or ROM (C2802)

(32K y 16, Secure Zone)

L0 (0-wait)

(4K y 16, Secure Zone, Dual Mapped)

Boot ROM (4 K y 16)

Reserved

128-bit Password

Data Space Prog Space

0x3D 7C00

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual Mapped)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802. B. Memory blocks are not to scale. C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space. D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. E. Certain memory ranges are EALLOW protected against spurious writes after configuration. F. Some locations in ROM are reserved for TI. See Table 3-5 for more information.

Submit Documentation Feedback Functional Overview 31

Figure 3-5. F2802, C2802 Memory Map

www.ti.com

0x00 0000

Block Start

Address

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x3D 7800

0x3F 4000

0x3F 7FF8 0x3F 8000

0x3F 9000

0x3F F000

0x3F FFC0

OTP (F2801/F2801x Only)

(A)

(1K y 16, Secure Zone)

FLASH (F2801) or ROM (C2801)

(16K y 16, Secure Zone)

L0 (0-wait)

(4K y 16, Secure Zone, Dual Mapped)

Boot ROM (4K y 16)

Reserved

128-bit Password

Data Space Prog Space

0x3D 7C00

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

M0 SARAM (1K y 16)

M1 SARAM (1K y 16)

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

L0 SARAM (0-wait)

(4K y 16, Secure Zone, Dual Mapped)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801. B. Memory blocks are not to scale. C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

Functional Overview32 Submit Documentation Feedback

Figure 3-6. F2801, F28015, F28016, C2801 Memory Map

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-1. Addresses of Flash Sectors in F2809

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000 - 0x3D BFFF Sector H (16K x 16) 0x3D C000 - 0x3D FFFF Sector G (16K x 16)

0x3E 0000 - 0x3E 3FFF Sector F (16K x 16)

0x3E 4000 - 0x3E 7FFF Sector E (16K x 16) 0x3E 8000 - 0x3E BFFF Sector D (16K x 16) 0x3E C000 - 0x3E FFFF Sector C (16K x 16)

0x3F 0000 - 0x3F 3FFF Sector B (16K x 16)

0x3F 4000 - 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 - 0x3F 7FF5

0x3F 7FF6 - 0x3F 7FF7

0x3F 7FF8 - 0x3F 7FFF

Table 3-2. Addresses of Flash Sectors in F2808

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3E 8000 - 0x3E BFFF Sector D (16K x 16) 0x3E C000 - 0x3E FFFF Sector C (16K x 16)

0x3F 0000 - 0x3F 3FFF Sector B (16K x 16)

0x3F 4000 - 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 - 0x3F 7FF5

0x3F 7FF6 - 0x3F 7FF7

0x3F 7FF8 - 0x3F 7FFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 3-3. Addresses of Flash Sectors in F2806, F2802

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3F 0000 - 0x3F 1FFF Sector D (8K x 16)

0x3F 2000 - 0x3F 3FFF Sector C (8K x 16)

0x3F 4000 - 0x3F 5FFF Sector B (8K x 16)

0x3F 6000 - 0x3F 7F7F Sector A (8K x 16)

0x3F 7F80 - 0x3F 7FF5

0x3F 7FF6 - 0x3F 7FF7

0x3F 7FF8 - 0x3F 7FFF

Submit Documentation Feedback Functional Overview 33

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-4. Addresses of Flash Sectors in F2801, F28015, F28016

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3F 4000 - 0x3F 4FFF Sector D (4K x 16)

0x3F 5000 - 0x3F 5FFF Sector C (4K x 16)

0x3F 6000 - 0x3F 6FFF Sector B (4K x 16)

0x3F 7000 - 0x3F 7F7F Sector A (4K x 16)

0x3F 7F80 - 0x3F 7FF5 Program to 0x0000 when using the

0x3F 7FF6 - 0x3F 7FF7 Boot-to-Flash Entry Point

0x3F 7FF8 - 0x3F 7FFF Security Password (128-Bit)

• When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and should not contain program code. .

• On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are reserved for TI, irrespective of whether code security has been used or not. User application should not use these locations in any way.

Table 3-5 shows how to handle these memory locations.

Code Security Module

(program branch instruction here)

(Do not program to all zeros)

NOTE

Table 3-5. Impact of Using the Code Security Module

ADDRESS FLASH ROM

Code security enabled Code security disabled Code security enabled Code security disabled

0x3F7F80 - 0x3F7FEF Application code and data Fill with 0x0000 Application code and data 0x3F7FF0 - 0x3F7FF5 Reserved for data only

0x3D7BFC – 0x3D7BFF Application code and data

Fill with 0x0000

Reserved for TI. Do not use.

Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-6 .

34 Functional Overview Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-6. Wait-states

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed Peripheral Frame 1

Peripheral Frame 2 Fixed

L0 & L1 SARAMs 0-wait

OTP is possible at a reduced CPU frequency. See Section 3.2.5

Flash

H0 SARAM 0-wait Fixed

Boot-ROM 1-wait Fixed

0-wait (writes) Fixed. The eCAN peripheral can extend a cycle as needed. 2-wait (reads) Back-to-back writes will introduce a 1-cycle delay.

0-wait (writes) 2-wait (reads)

Programmable, 1-wait minimum

Programmable, is possible at reduced CPU frequency. The CSM password 0-wait minimum locations are hardwired for 16 wait-states. See

Programmed via the Flash registers. 1-wait-state operation for more information.

Programmed via the Flash registers. 0-wait-state operation

Section 3.2.5 for more information.

TMS320F2802, TMS320F2801

Submit Documentation Feedback Functional Overview 35

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.2 Brief Descriptions

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a very efficient C/C++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)

3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the 280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

3.2.4 Real-Time JTAG and Analysis

The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the 280x, no software monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user-selectable break events when a match occurs.

Functional Overview36 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.2.5 Flash

The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K X 16 sectors. The F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. The F2806 and F2802 have 32K X 16 of embedded flash, segregated into four 8K X 16 sectors. The F2801 device contains 16K X 16 of embedded flash, segregated into four 4K X 16 sectors. All five devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables and should not contain program code.

NOTE

The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x280x System Control and Interrupts Reference Guide (literature number

SPRU712 ).

3.2.6 ROM

The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.

3.2.7 M0, M1 SARAMs

All 280x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages.

3.2.8 L0, L1, H0 SARAMs

The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into 3 blocks (L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16 of single-access RAM (L0-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to both program and data space.

3.2.9 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.

Submit Documentation Feedback Functional Overview 37

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-7. Boot Mode Selection

MODE DESCRIPTION SPICLKA GPIO34

GPIO18

SCITXDB

Boot to Flash/ROM Jump to Flash/ROM address 0x3F 7FF6 1 1 1

You must have programmed a branch instruction here prior

to reset to redirect code execution as desired. SCI-A Boot Load a data stream from SCI-A 1 1 0 SPI-A Boot Load from an external serial SPI EEPROM on SPI-A 1 0 1 I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 0

the I2C bus eCAN-A Boot Call CAN_Boot to load from eCAN-A mailbox 1. 0 1 1 Boot to M0 SARAM Jump to M0 SARAM address 0x00 0000. 0 1 0 Boot to OTP Jump to OTP address 0x3D 7800 0 0 1 Parallel I/O Boot Load data from GPIO0 - GPIO15 0 0 0

GPIO29

SCITXDA

Functional Overview38 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.2.10 Security

The 280x devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which matches the value stored in the password locations within the Flash.

NOTE

The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device.

disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

Submit Documentation Feedback Functional Overview 39

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.2.11 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.12 External Interrupts (XINT1, XINT2, XNMI)

The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be configured to trigger any external interrupt.

3.2.13 Oscillator and PLL

The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.14 Watchdog

The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be disabled if necessary.

3.2.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.16 Low-Power Modes

The 280x devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.

HALT: Turns off the internal oscillator. This mode basically shuts down the device and places it in

those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode.

An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event

the lowest possible power consumption mode. A reset or external signal can wake the device from this mode.

Functional Overview40 Submit Documentation Feedback

www.ti.com

3.2.17 Peripheral Frames 0, 1, 2 (PFn)

The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Control, Programming, Erase, Verify Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers (dual-mapped)

PF1: eCAN: eCAN Mailbox and Control Registers

GPIO: GPIO MUX Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Result Register I2C: Inter-Integrated Circuit Module and Registers

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes.

3.2.19 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.20 Control Peripherals

The 280x devices support the following peripherals which are used for embedded control and communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation,

adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM features.

eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal.

Submit Documentation Feedback Functional Overview 41

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed

measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals.

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

3.2.21 Serial Port Peripherals

The 280x devices support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time

stamping of messages, and is CAN 2.0B-compliant.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

I2C: The inter-integrated circuit (I2C) module provides an interface between a DSP and other

devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version

2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module. On the 280x, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

3.3 Register Map

The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:

Functional Overview42 Submit Documentation Feedback

Peripheral These are peripherals that are mapped directly to the CPU memory bus. Frame 0: See Table 3-8

Peripheral These are peripherals that are mapped to the 32-bit peripheral bus. Frame 1 See Table 3-9

Peripheral These are peripherals that are mapped to the 16-bit peripheral bus. Frame 2: See Table 3-10

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-8. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Device Emulation Registers 0x0880 - 0x09FF 384 EALLOW protected FLASH Registers Code Security Module Registers 0x0AE0 - 0x0AEF 16 EALLOW protected

ADC Result Registers (dual-mapped) 0x0B00 - 0x0B0F 16 Not EALLOW protected CPU-TIMER0/1/2 Registers 0x0C00 - 0x0C3F 64 Not EALLOW protected PIE Registers 0x0CE0 - 0x0CFF 32 Not EALLOW protected PIE Vector Table 0x0D00 - 0x0DFF 256 EALLOW protected

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) Missing segments of memory space are reserved and should not be used in applications. (3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(4) The Flash Registers are also protected by the Code Security Module (CSM).

(4)

0x0A80 - 0x0ADF 96

(1) (2)

EALLOW protected CSM Protected

(3)

Table 3-9. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

eCANA Registers 0x6000 - 0x60FF 256 bits in other eCAN control registers) are

eCANA Mailbox RAM 0x6100 - 0x61FF 256 Not EALLOW-protected

eCANB Registers 0x6200 - 0x62FF 256 bits in other eCAN control registers) are

eCANB Mailbox RAM 0x6300 - 0x63FF 256 Not EALLOW-protected ePWM1 Registers 0x6800 - 0x683F 64 ePWM2 Registers 0x6840 - 0x687F 64 ePWM3 Registers 0x6880 - 0x68BF 64 ePWM4 Registers 0x68C0 - 0x68FF 64 ePWM5 Registers 0x6900 - 0x693F 64 ePWM6 Registers 0x6940 - 0x697F 64 eCAP1 Registers 0x6A00 - 0x6A1F 32 eCAP2 Registers 0x6A20 - 0x6A3F 32 eCAP3 Registers 0x6A40 - 0x6A5F 32 eCAP4 Registers 0x6A60 - 0x6A7F 32 eQEP1 Registers 0x6B00 - 0x6B3F 64 eQEP2 Registers 0x6B40 - 0x6B7F 64 GPIO Control Registers 0x6F80 - 0x6FBF 128 EALLOW protected GPIO Data Registers 0x6FC0 - 0x6FDF 32 Not EALLOW protected GPIO Interrupt and LPM Select Registers 0x6FE0 - 0x6FFF 32 EALLOW protected

(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries. (2) Missing segments of memory space are reserved and should not be used in applications.

(1) (2)

Some eCAN control registers (and selected EALLOW-protected.

Some ePWM registers are EALLOW protected. See Table 4-2

Not EALLOW protected

Submit Documentation Feedback Functional Overview 43

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-10. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

System Control Registers 0x7010 - 0x702F 32 EALLOW Protected SPI-A Registers 0x7040 - 0x704F 16 SCI-A Registers 0x7050 - 0x705F 16 External Interrupt Registers 0x7070 - 0x707F 16 ADC Registers 0x7100 - 0x711F 32 SPI-B Registers 0x7740 - 0x774F 16 Not EALLOW Protected SCI-B Registers 0x7750 - 0x775F 16 SPI-C Registers 0x7760 - 0x776F 16 SPI-D Registers 0x7780 - 0x778F 16 I2C Registers 0x7900 - 0x792F 48

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written). (2) Missing segments of memory space are reserved and should not be used in applications.

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-11 .

(1) (2)

Table 3-11. Device Emulation Registers

NAME SIZE (x16) DESCRIPTION

DEVICECNF 2 Device Configuration Register PARTID 0x0882 1 Part ID Register 0x002C

REVID 0x0883 1 Revision ID Register 0x0000 - Silicon Rev. 0 - TMX

PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register

(1) The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.

ADDRESS

RANGE

0x0880 0x0881

(1)

0x0024 - F2802 0x0034 - F2806 0x003C - F2808 0x00FE - F2809 0x0014 - F28016 0x001C - F28015 0xFF2C - C2801 0xFF24 - C2802

0x0001 - Silicon Rev. A - TMX 0x0002 - Silicon Rev. B - TMS 0x0003 - Silicon Rev. C - TMS

Revision ID Register 0x0000 - Silicon rev. 0 - TMS (F2809 only)

- F2801

3.5 Interrupts

Figure 3-7 shows how the various interrupt sources are multiplexed within the 280x devices.

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as shown in Table 3-12 .

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

Functional Overview44 Submit Documentation Feedback

www.ti.com

XINT2

C28

CPU

CPUTIMER2

(ReservedforDSP/BIOS)

CPUTIMER0

Watchdog

Peripherals

(SPI,SCI,I2C,eCAN,ePWM,eCAP,eQEP,ADC)

TINT0

InterruptControl

XNMICR(15:0)

XINT1

InterruptControl

XINT1

XINT1CR(15:0)

InterruptControl

XINT2

XINT2CR(15:0)

GPIO

MUX

WDINT

INT1to

INT12

INT13

INT14

NMI

XINT1CTR(15:0)

XINT2CTR(15:0)

XNMICTR(15:0)

CPUTIMER1

TINT2

LowPowerModes

LPMINT

WAKEINT

TINT1

int13_select

XNMI_XINT13

GPIO0.int

GPIO31.int

ADC

XINT2SOC

GPIOXINT1SEL(4:0)

GPIOXINT2SEL(4:0)

GPIOXNMISEL(4:0)

nmi_select

MUX

PIE

96Interrupts

MUX

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.

Submit Documentation Feedback Functional Overview 45

Figure 3-7. External and PIE Interrupt Sources

www.ti.com

INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx(8:1) PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals or

External

Interrupts

(Enable) (Flag)

IER(12:1)IFR(12:1)

Global

Enable

INTM

PIEACKx

(Enable/Flag)

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 3-8. Multiplexing of Interrupts Using the PIE Block

Table 3-12. PIE Peripheral Interrupts

CPU

INTERRUPTS

INT1 XINT2 XINT1 reserved

INT2 reserved reserved

INT3 reserved reserved

INT4 reserved reserved reserved reserved

INT5 reserved reserved reserved reserved reserved reserved

INT6 INT7 reserved reserved reserved reserved reserved reserved reserved reserved INT8 reserved reserved reserved reserved reserved reserved

INT9

INT10 reserved reserved reserved reserved reserved reserved reserved reserved INT11 reserved reserved reserved reserved reserved reserved reserved reserved INT12 reserved reserved reserved reserved reserved reserved reserved reserved

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT SEQ2INT SEQ1INT (LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)

EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

(ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA

(SPI-D) (SPI-D) (SPI-C) (SPI-C) (SPI-B) (SPI-B) (SPI-A) (SPI-A)

ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

(CAN-B) (CAN-B) (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)

(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

1) No peripheral within the group is asserting interrupts.

2) No peripheral interrupts are assigned to the group (example PIE group 12).

PIE INTERRUPTS

ECAP4_INT ECAP3_INT ECAP2_INT ECAP1_INT

(eCAP4) (eCAP3) (eCAP2) (eCAP1)

(1)

EQEP2_INT EQEP1_INT

(eQEP2) (eQEP1)

I2CINT2A I2CINT1A

(I2C-A) (I2C-A)

Functional Overview46 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-13. PIE Configuration and Control Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA 6 Reserved

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

(1)

3.5.1 External Interrupts

Table 3-14. External Interrupt Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XINT1CR 0x7070 1 XINT1 control register XINT2CR 0x7071 1 XINT2 control register reserved 0x7072 - 0x7076 5 XNMICR 0x7077 1 XNMI control register XINT1CTR 0x7078 1 XINT1 counter register XINT2CTR 0x7079 1 XINT2 counter register reserved 0x707A - 0x707E 5 XNMICTR 0x707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x280x System Control and Interrupts Reference

Guide (literature number SPRU712).

Submit Documentation Feedback Functional Overview 47

www.ti.com

PLL

Power Modes Control

Watchdog

Block

28x CPU

Peripheral Bus

Low-Speed Peripherals

SCI-A/B, SPI-A/B/C/D

Peripheral

Registers

High-Speed Prescaler

Low-Speed Prescaler

Clock Enables

GPIO MUX

System Control

Registers

XCLKIN

ADC

Registers

12-Bit ADC

16 ADC inputs

LSPCLK

I/O

Peripheral Reset

SYSCLKOUT

(A)

XRS

Reset

GPIOs

Peripheral

Registers

I/O

OSC

CLKIN

(A)

HSPCLK

eCAN-A/B

I2C-A

Peripheral

Registers

I/O

ePWM 1/2/3/4/5/6

eCAP 1/2/3/4 eQEP 1/2

Peripheral

Registers

CPU

Timers

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

3.6 System Control

This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-9 shows the various clock and reset domains in the 280x devices that will be discussed.

A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT).

Figure 3-9. Clock and Reset Domains

Functional Overview48 Submit Documentation Feedback

www.ti.com

XCLKIN

(3.3-V clock input)

On chip

oscillator

xor

PLLSTS[OSCOFF]

OSCCLK

PLL

VCOCLK

4-bit PLL Select (PLLCR)

OSCCLK or

VCOCLK

CLKIN

OSCCLK

PLLSTS[PLLOFF]

n ≠ 0

PLLSTS[CLKINDIV]

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15 .

Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XCLK 0x7010 1 XCLKOUT Pin Control, X1 and XCLKIN Status Register PLLSTS 0x7011 1 PLL Status Register reserved 0x7012 - 0x7019 8 HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler Register (for HSPCLK) LOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler Register (for LSPCLK) PCLKCR0 0x701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x701D 1 Peripheral Clock Control Register 1 LPMCR0 0x701E 1 Low Power Mode Control Register 0 reserved 0x701F - 0x7020 1 PLLCR 0x7021 1 PLL Control Register SCSR 0x7022 1 System Control and Status Register WDCNTR 0x7023 1 Watchdog Counter Register reserved 0x7024 1 WDKEY 0x7025 1 Watchdog Reset Key Register reserved 0x7026 - 0x7028 3 WDCR 0x7029 1 Watchdog Control Register reserved 0x702A - 0x702F 6

(1) All of the registers in this table are EALLOW protected.

3.6.1 OSC and PLL Block

(1)

Figure 3-10 shows the OSC and PLL block on the 280x.

Figure 3-10. OSC and PLL Block Diagram

The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following configurations:

DDIO

1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V

2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V

The three possible input-clock configurations are shown in Figure 3-11 through Figure 3-13

Submit Documentation Feedback Functional Overview 49

www.ti.com

External Clock Signal

(Toggling 0−V

DDIO

)

XCLKIN

External Clock Signal

(Toggling 0−VDD)

XCLKIN

X2X1

Crystal

XCLKIN

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 3-11. Using a 3.3-V External Oscillator

Figure 3-12. Using a 1.8-V External Oscillator

Figure 3-13. Using the Internal Oscillator

3.6.1.1 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:

• Fundamental mode, parallel resonant

• C

(load capacitance) = 12 pF

• C

= C

L1 shunt

= 24 pF

= 6 pF

• ESR range = 30 to 60 Ω

TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range.

3.6.1.2 PLL-Based Clock Module

The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK cycles.

50 Functional Overview Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 3-16. PLLCR Register Bit Definitions

PLLCR[DIV]

0000 (PLL bypass) OSCCLK/n

1011-1111 reserved

(1) This register is EALLOW protected. (2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output

clock from the CPU. The frequency of SYSCLKOUT is the same as CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.

(1)

0001 (OSCCLK*1)/n 0010 (OSCCLK*2)/n 0011 (OSCCLK*3)/n 0100 (OSCCLK*4)/n 0101 (OSCCLK*5)/n 0110 (OSCCLK*6)/n 0111 (OSCCLK*7)/n 1000 (OSCCLK*8)/n 1001 (OSCCLK*9)/n 1010 (OSCCLK*10)/n

SYSCLKOUT

(CLKIN)

TMS320F2802, TMS320F2801

(2)

NOTE

PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to the core. This bit must be 0 before writing to the PLLCR and must only be set after PLLSTS[PLLLOCKS] = 1.

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin.

Table 3-17. Possible PLL Configuration Modes

PLL MODE REMARKS PLLSTS[CLKINDIV]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block 0 OSCCLK/2

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

PLL Bypass

PLL Enable 0 OSCCLK*n/2

is disabled in this mode. This can be useful to reduce system noise and for low before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external 0 OSCCLK/2

reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks.

3.6.1.3 Loss of Input Clock

SYSCLKOUT

(CLKIN)

1 OSCCLK

In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or absent.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog

Submit Documentation Feedback Functional Overview 51

www.ti.com

/512

OSCCLK

WDCR (WDPS(2:0))

WDCLK

WDCNTR(7:0)

WDKEY(7:0)

Good Key

1 0 1

WDCR (WDCHK(2:0))

Bad WDCHK Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory and the V

3.6.2 Watchdog Block

The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-14 shows the various functional blocks within the watchdog module.

NOTE

rail.

DD3VFL

A. The WDRST signal is driven low for 512 OSCCLK cycles.

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

Functional Overview52 Submit Documentation Feedback

Figure 3-14. Watchdog Module

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7 , Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

3.7 Low-Power Modes Block

The low-power modes on the 280x are similar to the 240x devices. Table 3-18 summarizes the various modes.

Table 3-18. Low-Power Modes

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

IDLE 00 On On On

STANDBY 01 Off Off

HALT 1X (oscillator and PLL turned off, Off Off

(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will

exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(watchdog still running) signal, debugger

watchdog not functional)

On XRS, Watchdog interrupt, GPIO Port A

Off

(2)

XRS, Watchdog interrupt, any enabled interrupt, XNMI

XRS, GPIO Port A signal, XNMI, debugger

(3)

(1)

(3)

, XNMI

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by

the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device

from HALT mode. The user selects the signal in the GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x System Control and Interrupts Reference Guide (literature number SPRU712) for more details.

Submit Documentation Feedback Functional Overview 53

www.ti.com

Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4 Peripherals

The integrated peripherals of the 280x are described in the following subsections:

• Three 32-bit CPU-Timers

• Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)

• Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)

• Up to two enhanced QEP modules (eQEP1, eQEP2)

• Enhanced analog-to-digital converter (ADC) module

• Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)

• Up to two serial communications interface modules (SCI-A, SCI-B)

• Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)

• Inter-integrated circuit module (I2C)

• Digital I/O and shared pin functions

4.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2). CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS™.

These timers are different from the timers that are present in the ePWM modules.

NOTE

NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

Figure 4-1. CPU-Timers

In the 280x devices, the timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in

Figure 4-2 .

Peripherals 54 Submit Documentation Feedback

www.ti.com

INT1

INT12

INT14

C28x

TINT2

TINT0

PIE

CPU-TIMER0

CPU-TIMER2 (Reservedfor

DSP/BIOS)

INT13

TINT1

CPU-TIMER1

XINT13

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.

Figure 4-2. CPU-Timer Interrupt Signals and Output Signal

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x System Control and Interrupts Reference Guide (literature number SPRU712).

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register reserved 0x0C15 1 TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High

Submit Documentation Feedback Peripherals 55

www.ti.com

PIE

TZ1

to TZ6

Peripheral Bus

ePWM1 module

ePWM2 module

ePWMx module

EPWM1SYNCI

EPWM2SYNCI

EPWM2SYNCO

EPWMxSYNCI

EPWMxSYNCO

ADC

GPIO

MUX

EPWM1SYNCI

EPWM1SYNCO

ADCSOCx0

EPWMxA

EPWMxB

EPWM2A

EPWM2B

EPWM1A

EPWM1B

EPWM1INT

EPWM1SOC

EPWM2INT

EPWM2SOC

EPWMxINT

EPWMxSOC

to eCAP1

module

(sync in)

TZ1 to TZ6

EPWM1SYNCO

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

reserved 40

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)

The 280x device contains up to six enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRU791) for more details.

0x0C18 0x0C3F

Figure 4-3. Multiple PWM Modules in a 280x System

Table 4-2 shows the complete ePWM register set per module.

56 Peripherals Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-2. ePWM Control and Status Registers

NAME EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 DESCRIPTION

TBCTL 0x6800 0x6840 0x6880 0x68C0 0x6900 0x6940 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1 / 0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 N/A N/A 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 / 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 / 0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 N/A N/A 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 0x690B 0x694B 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 0x690E 0x694E 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 0x690F 0x694F 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 0x6910 0x6950 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 0x6911 0x6951 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 / 0 Trip Zone Select Register TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1 / 0 Trip Zone Control Register TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1 / 0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1 / 0 Trip Zone Clear Register TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1 / 0 Trip Zone Force Register ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1 / 0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 0x691E 0x695E 1 / 0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 0x6920

(2)

0x6960

SIZE (x16) /

#SHADOW

1 / 0 HRPWM Configuration Register

(1)

(1) Registers that are EALLOW protected. (2) Applicable to F2809 only

Submit Documentation Feedback Peripherals 57

www.ti.com

CTR=PRD

TBPRD shadow (16)

TBPRD active (16)

Counter

up/down

(16 bit) TBCNT

active (16)

TBCTL[CNTLDE]

TBCTL[SWFSYNC] (software forced sync)

EPWMxSYNCI

CTR=ZERO

CTR_Dir

CTR=CMPB

Disabled

Sync in/out select

Mux

TBCTL[SYNCOSEL]

EPWMxSYNCO

TBPHS active (24)

TBPHSHR (8)

Phase control

Time−base (TB)

CTR=CMPA

CMPA active (24)

CMPA shadow (24)

Action

qualifier

(AQ)

Counter compare (CC)

CMPB active (16)

CTR=CMPB

CMPB shadow (16)

CMPAHR (8)

EPWMA

EPWMB

Dead band

(DB) (PC)

chopper

PWM

zone

(TZ)

Trip

CTR = ZERO

EPWMxAO

EPWMxBO EPWMxTZINT TZ1 to TZ6

HiRes PWM (HRPWM)

CTR = PRD

CTR = ZERO

CTR = CMPB

CTR = CMPA

CTR_Dir

Event

trigger

and

interrupt

(ET)

EPWMxINT EPWMxSOCA EPWMxSOCB

CTR=ZERO

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.3 Hi-Resolution PWM (HRPWM)

4.4 Enhanced CAP Modules (eCAP1/2/3/4)

Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM

• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies

greater than ~200 KHz when using a CPU/System clock of 100 MHz.

• This capability can be utilized in both duty cycle and phase-shift control methods.

• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and

Phase registers of the ePWM module.

• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functional block diagram of a module. See the TMS320x280x Enhanced Capture (eCAP) Module Reference Guide (literature number SPRU807) for more details.

The eCAP modules are clocked at the SYSCLKOUT rate.

Peripherals 58 Submit Documentation Feedback

www.ti.com

TSCTR

(counter−32 bit)

RST

CAP1

(APRD active)

CAP2

(ACMP active)

CAP3

(APRD shadow)

CAP4

(ACMP shadow)

Continuous /

Oneshot

Capture Control

LD1

LD2

LD3

LD4

PRD [0−31]

CMP [0−31]

CTR [0−31]

eCAPx

Interrupt

Trigger

and

Flag

control

to PIE

CTR=CMP

ACMP

shadow

Event

Pre-scale

CTRPHS

(phase register−32 bit)

SYNCOut

SYNCIn

Event

qualifier

Polarity

select

Polarity

select

Polarity

select

Polarity

select

CTR=PRD

CTR_OVF

PWM

compare

logic

CTR [0−31] PRD [0−31]

CMP [0−31]

CTR=CMP

CTR=PRD

CTR_OVF

OVF

APWM mode

Delta−mode

SYNC

Capture events

CEVT[1:4]

APRD

shadow

MODE SELECT

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.

NAME ECAP1 ECAP2 ECAP3 ECAP4 DESCRIPTION

TSCTR 0x6A00 0x6A20 0x6A40 0x6A60 2 Time-Stamp Counter

Submit Documentation Feedback Peripherals 59

Figure 4-5. eCAP Functional Block Diagram

Table 4-3. eCAP Control and Status Registers

SIZE

(x16)

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-3. eCAP Control and Status Registers (continued)

NAME ECAP1 ECAP2 ECAP3 ECAP4 DESCRIPTION

CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 2 Counter Phase Offset Value Register

CAP1 0x6A04 0x6A24 0x6A44 0x6A64 2 Capture 1 Register CAP2 0x6A06 0x6A26 0x6A46 0x6A66 2 Capture 2 Register CAP3 0x6A08 0x6A28 0x6A48 0x6A68 2 Capture 3 Register CAP4 0x6A0A 0x6A2A 0x6A4A 0x6A6A 2 Capture 4 Register

Reserved 0x6A0C- 0x6A2C- 0x6A4C- 0x6A6C- 8

0x6A12 0x6A32 0x6A52 0x6A72 ECCTL1 0x6A14 0x6A34 0x6A54 0x6A74 1 Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 0x6A75 1 Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 Capture Interrupt Enable Register

ECFLG 0x6A17 0x6A37 0x6A57 0x6A77 1 Capture Interrupt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 Capture Interrupt Clear Register ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 1 Capture Interrupt Force Register

Reserved 0x6A1A- 0x6A3A- 0x6A5A- 0x6A7A- 6

0x6A1F 0x6A3F 0x6A5F 0x6A7F

SIZE

(x16)

Peripherals 60 Submit Documentation Feedback

www.ti.com

4.5 Enhanced QEP Modules (eQEP1/2)

QWDTMR

QWDPRD

QWDOGUTIME

QUPRD

QUTMR

UTOUT

WDTOUT

Quadrature

capture unit

(QCAP)

QCPRDLAT

QCTMRLAT

QFLG

QEPSTS

QEPCTL

Registers

used by

multiple units

QCLK

QDIR

PHE

PCSOUT

Quadrature

decoder

(QDU)

QDECCTL

Position counter/

control unit

(PCCU)

QPOSLAT

QPOSSLAT

QPOSILAT

EQEPxAIN EQEPxBIN

EQEPxIIN

EQEPxIOUT

EQEPxIOE EQEPxSIN

EQEPxSOUT

EQEPxSOE

GPIO

MUX

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxS

EQEPxI

QPOSCMP

QEINT

QFRC

QCLR

QPOSCTL

1632

QPOSCNT

QPOSMAX

QPOSINIT

PIE

EQEPxINT

Enhanced QEP (eQEP) peripheral

System

control registers

QCTMR

QCPRD

1616

QCAPCTL

EQEPxENCLK

SYSCLKOUT

Data bus

To CPU

The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the TMS320x280x Enhanced Quadrature Encoder (eQEP) Module Reference Guide (literature number SPRU790) for more details.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 4-6. eQEP Functional Block Diagram

Submit Documentation Feedback Peripherals 61

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-4. eQEP Control and Status Registers

NAME SIZE(x16)/ REGISTER DESCRIPTION

QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position Counter QPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compare QPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit Timer QUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period Register QWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 0x6B55 1/0 eQEP Control Register QCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control Register QEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status Register QCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture Timer QCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period Latch Reserved 0x6B21- 0x6B61- 31/0

EQEP1 EQEP2

ADDRESS ADDRESS

0x6B3F 0x6B7F

EQEP1

#SHADOW

Peripherals 62 Submit Documentation Feedback

www.ti.com

4.6 Enhanced Analog-to-Digital Converter (ADC) Module

Digital Value + 0,

Digital Value + 4096

Input Analog Voltage * ADCLO

when input ≤ 0 V

when 0 V < input < 3 V

when input ≥ 3 VDigital V alue + 4095,

A simplified functional block diagram of the ADC module is shown in Figure 4-7 . The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)

• Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion

can be programmed to select any 1 of 16 input channels

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)

• Sixteen result registers (individually addressable) to store conversion values – The digital value of the input analog voltage is derived by:

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. All fractional values are truncated.

• Multiple triggers as sources for the start-of-conversion (SOC) sequence – S/W - software immediate start – ePWM start of conversion – XINT2 ADC start of conversion

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.

• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to

synchronize conversions.

• SOCA and SOCB triggers can operate independently in dual-sequencer mode.

• Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-7 shows the block diagram of the ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

Submit Documentation Feedback Peripherals 63

www.ti.com

Result Registers

EPWMSOCB

S/W

GPIO/XINT2

_ADCSOC

EPWMSOCA

S/W

Sequencer 2

Sequencer 1

SOCSOC

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

Module

ADC

12-Bit

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

Control Block

High-Speed

Prescaler

HSPCLK

ADCENCLK

DSP

SYSCLKOUT

S/H

HALT

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 4-7. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V V

, V

DD2A18

, V

DDA2

DDAIO

) from the digital supply.Figure 4-8 shows the ADC pin connections for the 280x

devices.

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

– ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the

clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module, however, will be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

– HALT: This mode only affects the analog module. It does not affect the registers.

In this mode, the ADC module goes into low-power mode. This mode also will stop the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.

NOTE

DD1A18

Peripherals 64 Submit Documentation Feedback

www.ti.com

ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADC Reference Positive Output

ADCREFMADC Reference Medium Output

ADC Power

ADC Analog and Reference I/O Power

Analog input 0−3 V with respect to ADCLO

Connect to analog ground

22 kW

2.2 mF

(A)

2.2 mF

(A)

ADC Analog Power Pin (1.8 V) ADC Analog Power Pin (1.8 V)

ADC Analog Power Pin (3.3 V)

ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V)

ADCREFP and ADCREFM should not be loaded by external circuitry

ADC Analog Ground Pin

ADC 16-Channel Analog Inputs

Float or ground if internal reference is used

ADC Analog Ground Pin ADC Analog Ground Pin

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 4-8 shows the ADC pin-biasing for internal reference and Figure 4-9 shows the ADC pin-biasing for

external reference.

Figure 4-8. ADC Pin Connections With Internal Reference

Submit Documentation Feedback Peripherals 65

www.ti.com

ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADC Reference Positive Output

ADCREFMADC Reference Medium Output

ADC Analog Power

ADC Analog and Reference I/O Power

Analog input 0−3 V with respect to ADCLO

Connect to Analog Ground

22 kW

2.2 mF

(A)

2.2 mF

(A)

ADCREFP and ADCREFM should not

be loaded by external circuitry

ADC 16-Channel Analog Inputs

Connect to 1.500, 1.024, or 2.048-V precision source

(D)

ADC Analog Power Pin (1.8 V) ADC Analog Power Pin (1.8 V)

ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V) ADC Analog Ground Pin

ADC Analog Ground Pin ADC Analog Ground Pin

ADC Analog Power Pin (3.3 V)

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. TAIYO YUDEN LMK212BJ225MG-T or equivalent B. External decoupling capacitors are recommended on all power pins. C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on

the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy of this voltage source.

Figure 4-9. ADC Pin Connections With External Reference

The temperature rating of any recommended component must match the rating of the end product.

4.6.1 ADC Connections if the ADC Is Not Used

It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application:

• V

• ADCLO – Connect to V

• ADCREFIN – Connect to V

• ADCREFP/ADCREFM – Connect a 100-nF cap to V

• ADCRESEXT – Connect a 20-k Ω resistor (very loose tolerance) to V

• ADCINAn, ADCINBn - Connect to V

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.

When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (V

Peripherals 66 Submit Documentation Feedback

DD1A18

, V

DDA2 SS1AGND

DDAIO

SS1AGND

DD2A18

– Connect to V

SS2AGND

– Connect to V

SS2AGND

, V

SSA2

NOTE

DDIO

, V

)

– Connect to V

SSAIO

www.ti.com

4.6.2 ADC Registers

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5 .

Table 4-5. ADC Registers

NAME ADDRESS

ADCTRL1 0x7100 1 ADC Control Register 1 ADCTRL2 0x7101 1 ADC Control Register 2

ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x7107 1 ADC Auto-Sequence Status Register ADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9

ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x7115 0x0B0D 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x7116 0x0B0E 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x7117 0x0B0F 1 ADC Conversion Result Buffer Register 15

ADCTRL3 0x7118 1 ADC Control Register 3

ADCST 0x7119 1 ADC Status Register

Reserved 2

ADCREFSEL 0x711C 1 ADC Reference Select Register

ADCOFFTRIM 0x711D 1 ADC Offset Trim Register

Reserved 2 ADC Status Register

(1) The registers in this column are Peripheral Frame 2 Registers. (2) The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and left

justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

(1)

ADDRESS

0x711A 0x711B

0x711E 0x711F

(2)

SIZE (x16) DESCRIPTION

(1)

Submit Documentation Feedback Peripherals 67

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

The CAN module has the following features:

• Fully compliant with CAN protocol, version 2.0B

• Supports data rates up to 1 Mbps

• Thirty-two mailboxes, each with the following properties:

– Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out

• Low-power mode

• Programmable wake-up on bus activity

• Automatic reply to a remote request message

• Automatic retransmission of a frame in case of loss of arbitration or error

• 32-bit local network time counter synchronized by a specific message (communication in conjunction

with mailbox 16)

• Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

NOTE

For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps. For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.

Peripherals 68 Submit Documentation Feedback

www.ti.com

Mailbox RAM

(512 Bytes)

32-Message Mailbox

of 4 × 32-Bit Words

Memory Management

Unit

CPU Interface,

Receive Control Unit,

Timer Management Unit

eCAN Memory

(512 Bytes)

Registers and Message

Objects Control

32 32

Message Controller

32 3232 3232 32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

Enhanced CAN Controller

Controls

Address Data

eCAN1INTeCAN0INT

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

PART NUMBER VREF OTHER T

SN65HVD230 3.3 V Standby Adjustable Yes – -40 ° C to 85 ° C

SN65HVD230Q 3.3 V Standby Adjustable Yes – -40 ° C to 125 ° C

SN65HVD231 3.3 V Sleep Adjustable Yes – -40 ° C to 85 ° C

SN65HVD231Q 3.3 V Sleep Adjustable Yes – -40 ° C to 125 ° C

SN65HVD232 3.3 V None None None – -40 ° C to 85 ° C

SN65HVD232Q 3.3 V None None None – -40 ° C to 125 ° C

SN65HVD233 3.3 V Standby Adjustable None Diagnostic -40 ° C to 125 ° C

SN65HVD234 3.3 V Standby & Sleep Adjustable None – -40 ° C to 125 ° C SN65HVD235 3.3 V Standby Adjustable None Autobaud -40 ° C to 125 ° C

Figure 4-10. eCAN Block Diagram and Interface Circuit

SUPPLY LOW-POWER SLOPE

VOLTAGE MODE CONTROL

Table 4-6. 3.3-V eCAN Transceivers

Loopback

Submit Documentation Feedback Peripherals 69

www.ti.com

Mailbox Enable − CANME

Mailbox Direction − CANMD

Transmission Request Set − CANTRS

Transmission Request Reset − CANTRR

Transmission Acknowledge − CANTA

Abort Acknowledge − CANAA

Received Message Pending − CANRMP

Received Message Lost − CANRML Remote Frame Pending − CANRFP

Global Acceptance Mask − CANGAM

Master Control − CANMC

Bit-Timing Configuration − CANBTC

Error and Status − CANES

Transmit Error Counter − CANTEC

Receive Error Counter − CANREC

Global Interrupt Flag 0 − CANGIF0

Global Interrupt Mask − CANGIM

Mailbox Interrupt Mask − CANMIM

Mailbox Interrupt Level − CANMIL

Overwrite Protection Control − CANOPC

TX I/O Control − CANTIOC RX I/O Control − CANRIOC

Time Stamp Counter − CANTSC

Global Interrupt Flag 1 − CANGIF1

Time-Out Control − CANTOC

Time-Out Status − CANTOS

Reserved

eCAN-A Control and Status Registers

Message Identifier − MSGID

61E8h−61E9h

Message Control − MSGCTRL

Message Data Low − MDL

Message Data High − MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6000h 603Fh

Local Acceptance Masks (LAM)

(32 × 32-Bit RAM)

6040h 607Fh 6080h

60BFh

60C0h 60FFh

eCAN-A Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 × 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 × 32-Bit RAM)

Mailbox 0

6100h−6107h

Mailbox 1

6108h−610Fh

Mailbox 2

6110h−6117h

Mailbox 3

6118h−611Fh

eCAN-A Memory RAM (512 Bytes)

Mailbox 4

6120h−6127h

Mailbox 28

61E0h−61E7h

Mailbox 29

61E8h−61EFh

Mailbox 30

61F0h−61F7h

Mailbox 31

61F8h−61FFh

61EAh−61EBh 61ECh−61EDh

61EEh−61EFh

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

Figure 4-11. eCAN-A Memory Map

NOTE

Peripherals 70 Submit Documentation Feedback

www.ti.com

Mailbox Enable − CANME

Mailbox Direction − CANMD

Transmission Request Set − CANTRS

Transmission Request Reset − CANTRR

Transmission Acknowledge − CANTA

Abort Acknowledge − CANAA

Received Message Pending − CANRMP

Received Message Lost − CANRML Remote Frame Pending − CANRFP

Global Acceptance Mask − CANGAM

Master Control − CANMC

Bit-Timing Configuration − CANBTC

Error and Status − CANES

Transmit Error Counter − CANTEC

Receive Error Counter − CANREC Global Interrupt Flag 0 − CANGIF0

Global Interrupt Mask − CANGIM

Mailbox Interrupt Mask − CANMIM

Mailbox Interrupt Level − CANMIL

Overwrite Protection Control − CANOPC

TX I/O Control − CANTIOC RX I/O Control − CANRIOC

Time Stamp Counter − CANTSC

Global Interrupt Flag 1 − CANGIF1

Time-Out Control − CANTOC

Time-Out Status − CANTOS

Reserved

eCAN-B Control and Status Registers

Message Identifier − MSGID

63E8h−63E9h

Message Control − MSGCTRL

Message Data Low − MDL

Message Data High − MDH

Message Mailbox (16 Bytes)

Control and Status Registers

6200h 623Fh

Local Acceptance Masks (LAM)

(32 × 32-Bit RAM)

6240h 627Fh 6280h

62BFh

62C0h 62FFh

eCAN-B Memory (512 Bytes)

Message Object Time Stamps (MOTS)

(32 × 32-Bit RAM)

Message Object Time-Out (MOTO)

(32 × 32-Bit RAM)

Mailbox 0

6300h−6307h

Mailbox 1

6308h−630Fh

Mailbox 2

6310h−6317h

Mailbox 3

6318h−631Fh

eCAN-B Memory RAM (512 Bytes)

Mailbox 4

6320h−6327h

Mailbox 28

63E0h−63E7h

Mailbox 29

63E8h−63EFh

Mailbox 30

63F0h−63F7h

Mailbox 31

63F8h−63FFh

63EAh−63EBh 63ECh−63EDh

63EEh−63EFh

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM

Figure 4-12. eCAN-B Memory Map

can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Submit Documentation Feedback Peripherals 71

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-7. CAN Register Map

CANME 0x6000 0x6200 1 Mailbox enable

CANMD 0x6002 0x6202 1 Mailbox direction CANTRS 0x6004 0x6204 1 Transmit request set CANTRR 0x6006 0x6206 1 Transmit request reset

CANTA 0x6008 0x6208 1 Transmission acknowledge

CANAA 0x600A 0x620A 1 Abort acknowledge CANRMP 0x600C 0x620C 1 Receive message pending CANRML 0x600E 0x620E 1 Receive message lost

CANRFP 0x6010 0x6210 1 Remote frame pending

CANGAM 0x6012 0x6212 1 Global acceptance mask

CANMC 0x6014 0x6214 1 Master control

CANBTC 0x6016 0x6216 1 Bit-timing configuration

CANES 0x6018 0x6218 1 Error and status

CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter CANGIF0 0x601E 0x621E 1 Global interrupt flag 0

CANGIM 0x6020 0x6220 1 Global interrupt mask

CANGIF1 0x6022 0x6222 1 Global interrupt flag 1

CANMIM 0x6024 0x6224 1 Mailbox interrupt mask

CANMIL 0x6026 0x6226 1 Mailbox interrupt level

CANOPC 0x6028 0x6228 1 Overwrite protection control

CANTIOC 0x602A 0x622A 1 TX I/O control

CANRIOC 0x602C 0x622C 1 RX I/O control

CANTSC 0x602E 0x622E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)

CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

ECAN-A ECAN-B SIZE

ADDRESS ADDRESS (x32)

(1)

Peripherals 72 Submit Documentation Feedback

www.ti.com

Baud rate =

LSPCLK

(BRR ) 1) *8

when BRR ≠ 0

Baud rate = when BRR = 0

Max bit rate +

100 MHz

+ 6.25 106bńs

Max bit rate +

60 MHz

+ 3.75 106bńs

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)

The 280x devices include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

•

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h

(for 100 MHz devices)

(for 60 MHz devices)

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• Auto baud-detect hardware logic

Submit Documentation Feedback Peripherals 73

NOTE

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

• 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9 .

Table 4-8. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x7050 1 SCI-A Communications Control Register

SCICTL1A 0x7051 1 SCI-A Control Register 1

SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x7054 1 SCI-A Control Register 2

SCIRXSTA 0x7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register

SCIFFTXA SCIFFRXA SCIFFCTA

SCIPRIA 0x705F 1 SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2) (2) (2)

0x705A 1 SCI-A FIFO Transmit Register 0x705B 1 SCI-A FIFO Receive Register 0x705C 1 SCI-A FIFO Control Register

Table 4-9. SCI-B Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRB 0x7750 1 SCI-B Communications Control Register

SCICTL1B 0x7751 1 SCI-B Control Register 1

SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits

SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits

SCICTL2B 0x7754 1 SCI-B Control Register 2

SCIRXSTB 0x7755 1 SCI-B Receive Status Register

SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register

SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register

SCIFFTXB SCIFFRXB SCIFFCTB

SCIPRIB 0x775F 1 SCI-B Priority Control Register

(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2) (2) (2)

0x775A 1 SCI-B FIFO Transmit Register 0x775B 1 SCI-B FIFO Receive Register 0x775C 1 SCI-B FIFO Control Register

(1)

(1) (2)

Peripherals 74 Submit Documentation Feedback

www.ti.com

TX FIFO _0

LSPCLK

WUT

Frame Format and Mode

Even/Odd Enable

Parity

SCI RX Interrupt select logic

BRKDT

RXRDY

SCIRXST.6

SCICTL1.3

SCICTL2.1

RX/BK INT ENA

SCIRXD

SCIRXST.1

TXENA

SCI TX Interrupt select logic

TX EMPTY

TXRDY

SCICTL2.0

TX INT ENA

SCITXD

RXENA

SCIRXD

RXWAKE

SCICTL1.6

RX ERR INT ENA

TXWAKE

SCITXD

SCICCR.6 SCICCR.5

SCITXBUF.7-0

SCIHBAUD. 15 - 8

Baud Rate

MSbyte

SCILBAUD. 7 - 0

Transmitter-Data

Buffer Register

SCICTL2.6

SCICTL2.7

Baud Rate

LSbyte

RXSHF Register

TXSHF

SCIRXST.5

TX FIFO _1

-----

TX FIFO _15

TX FIFO registers

TX FIFO

TX Interrupt

Logic

TXINT

SCIFFTX.14

RX FIFO _15

SCIRXBUF.7-0

Receive Data Buffer register SCIRXBUF.7-0

-----

RX FIFO_1 RX FIFO _0

RX FIFO registers

SCICTL1.0

RX Interrupt

Logic

RXINT

RX FIFO

SCIFFRX.15

RXFFOVF

RX Error

SCIRXST.7

PEFE OE

RX Error

SCIRXST.4 - 2

To CPU

AutoBaud Detect logic

SCICTL1.1

SCIFFENA

Interrupts

Figure 4-13 shows the SCI module block diagram.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Submit Documentation Feedback Peripherals 75

Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram

www.ti.com

Baud rate =

LSPCLK

(SPIBRR ) 1)

when SPIBRR = 3 to 127

Baud rate = when SPIBRR = 0,1, 2

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)

The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules (SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave Baud rate: 125 different programmable rates.

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

• 16-level transmit/receive FIFO

• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 4-10 .

Peripherals 76 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-10. SPI-A Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7040 1 SPI-A Configuration Control Register

SPICTL 0x7041 1 SPI-A Operation Control Register SPISTS 0x7042 1 SPI-A Status Register SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register

SPIFFRX 0x704B 1 SPI-A FIFO Receive Register

SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Table 4-11. SPI-B Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7740 1 SPI-B Configuration Control Register

SPICTL 0x7741 1 SPI-B Operation Control Register SPISTS 0x7742 1 SPI-B Status Register SPIBRR 0x7744 1 SPI-B Baud Rate Register

SPIRXEMU 0x7746 1 SPI-B Receive Emulation Buffer Register

SPIRXBUF 0x7747 1 SPI-B Serial Input Buffer Register SPITXBUF 0x7748 1 SPI-B Serial Output Buffer Register

SPIDAT 0x7749 1 SPI-B Serial Data Register

SPIFFTX 0x774A 1 SPI-B FIFO Transmit Register

SPIFFRX 0x774B 1 SPI-B FIFO Receive Register

SPIFFCT 0x774C 1 SPI-B FIFO Control Register

SPIPRI 0x774F 1 SPI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Submit Documentation Feedback Peripherals 77

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-12. SPI-C Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7760 1 SPI-C Configuration Control Register

SPICTL 0x7761 1 SPI-C Operation Control Register SPISTS 0x7762 1 SPI-C Status Register SPIBRR 0x7764 1 SPI-C Baud Rate Register

SPIRXEMU 0x7766 1 SPI-C Receive Emulation Buffer Register

SPIRXBUF 0x7767 1 SPI-C Serial Input Buffer Register SPITXBUF 0x7768 1 SPI-C Serial Output Buffer Register

SPIDAT 0x7769 1 SPI-C Serial Data Register

SPIFFTX 0x776A 1 SPI-C FIFO Transmit Register

SPIFFRX 0x776B 1 SPI-C FIFO Receive Register

SPIFFCT 0x776C 1 SPI-C FIFO Control Register

SPIPRI 0x776F 1 SPI-C Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Table 4-13. SPI-D Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7780 1 SPI-D Configuration Control Register

SPICTL 0x7781 1 SPI-D Operation Control Register SPISTS 0x7782 1 SPI-D Status Register SPIBRR 0x7784 1 SPI-D Baud Rate Register

SPIRXEMU 0x7786 1 SPI-D Receive Emulation Buffer Register

SPIRXBUF 0x7787 1 SPI-D Serial Input Buffer Register SPITXBUF 0x7788 1 SPI-D Serial Output Buffer Register

SPIDAT 0x7789 1 SPI-D Serial Data Register

SPIFFTX 0x778A 1 SPI-D FIFO Transmit Register

SPIFFRX 0x778B 1 SPI-D FIFO Receive Register

SPIFFCT 0x778C 1 SPI-D FIFO Control Register

SPIPRI 0x778F 1 SPI-D Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

Peripherals 78 Submit Documentation Feedback

www.ti.com

SPICTL.0

SPI INT FLAG

SPI INT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

456 123 0

0123

SPI Bit Rate

State Control

SPIRXBUF

Buffer Register

Clock

Phase

Receiver

Overrun Flag

SPICTL.4

Overrun

INT ENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6 SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

Data Register

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

SW3

To CPU

SW1

SPITXBUF

Buffer Register

RX FIFO _0 RX FIFO _1

−−−−−

RX FIFO _15

TX FIFO registers

TX FIFO _0

TX FIFO _1

−−−−−

TX FIFO _15

RX FIFO registers

TX Interrupt

Logic

RX Interrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVF FLAG

SPIFFRX.15

TX FIFO Interrupt

RX FIFO Interrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

(A)

Figure 4-14 is a block diagram of the SPI in slave mode.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. SPISTE is driven low by the master for a slave device.

Submit Documentation Feedback Peripherals 79

Figure 4-14. SPI Module Block Diagram (Slave Mode)

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.10 Inter-Integrated Circuit (I2C)

The 280x device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces within the 280x device.

The I2C module has the following features:

• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)

• One 16-bit receive FIFO and one 16-bit transmit FIFO

• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the

following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave

• An additional interrupt that can be used by the CPU when in FIFO mode

• Module enable/disable capability

• Free data format mode

Peripherals 80 Submit Documentation Feedback

www.ti.com

SYSRS

Data[16]

SYSCLKOUT

Data[16]

Addr[16]

Control

I2CINT1A

I2CINT2A

C28X CPU

GPIO

MUX

I2C−A

System Control

Block

I2CAENCLK

PIE

Block

SDAA

SCLA

Peripheral Bus

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-15. I2C Peripheral Module Interfaces

The registers in Table 4-14 configure and control the I2C port operation.

Table 4-14. I2C-A Registers

NAME ADDRESS DESCRIPTION

I2COAR 0x7900 I2C own address register

I2CIER 0x7901 I2C interrupt enable register

I2CSTR 0x7902 I2C status register

I2CCLKL 0x7903 I2C clock low-time divider register

I2CCLKH 0x7904 I2C clock high-time divider register

I2CCNT 0x7905 I2C data count register I2CDRR 0x7906 I2C data receive register I2CSAR 0x7907 I2C slave address register

I2CDXR 0x7908 I2C data transmit register I2CMDR 0x7909 I2C mode register I2CISRC 0x790A I2C interrupt source register

I2CPSC 0x790C I2C prescaler register I2CFFTX 0x7920 I2C FIFO transmit register

I2CFFRX 0x7921 I2C FIFO receive register

I2CRSR - I2C receive shift register (not accessible to the CPU)

I2CXSR - I2C transmit shift register (not accessible to the CPU)

Submit Documentation Feedback Peripherals 81

www.ti.com

GPxDAT (read)

Input

Qualification

GPxMUX1/2

High Impedance

Output Control

GPIOx pin

XRS

0 = Input, 1 = Output

Low Power

Modes Block

GPxDIR (latch)

Peripheral 2 Input

Peripheral 3 Input

Peripheral 1 Output Peripheral 2 Output Peripheral 3 Output

Peripheral 1 Output Enable

Peripheral 2 Output Enable

Peripheral 3 Output Enable

00 01

10 11

GPxCTRL

Peripheral 1 Input

N/C

GPxPUD

LPMCR0

Internal

Pullup

GPIOLMPSEL

GPxQSEL1/2

GPxSET

GPxDAT (latch)

GPxCLEAR

GPxTOGGLE

GPIOXINT1SEL GPIOXINT2SEL

GPIOXNMISEL

= Default at Reset

PIE

External Interrupt

MUX

Asynchronous

path

Asynchronous path

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

4.11 GPIO MUX

On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 4-16 . Because of the open drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x280x System Control and Interrupts Reference Guide (literature number SPRU712) for details.

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

Figure 4-16. GPIO MUX Block Diagram

Peripherals 82 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO register mapping.

Table 4-15. GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)

GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)

GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)

reserved 2

GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 35) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 35) GPBQSEL2 0x6F94 2 reserved

GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 35)

GPBMUX2 0x6F98 2 reserved

GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 35)

GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 35)

reserved 2 reserved

reserved 32

GPADAT 0x6FC0 2 GPIO Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO Data Set Register (GPIO0 to 31)

GPACLEAR 0x6FC4 2 GPIO Data Clear Register (GPIO0 to 31)

GPATOGGLE 0x6FC6 2 GPIO Data Toggle Register (GPIO0 to 31)

GPBDAT 0x6FC8 2 GPIO Data Register (GPIO32 to 35) GPBSET 0x6FCA 2 GPIO Data Set Register (GPIO32 to 35)

GPBCLEAR 0x6FCC 2 GPIO Data Clear Register (GPIO32 to 35)

GPBTOGGLE 0x6FCE 2 GPIO Data Toggle Register (GPIO32 to 35)

reserved 16

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)

reserved 5

GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

reserved 22

0x6F8E 0x6F8F

0x6F9E 0x6F9F

0x6FA0

0x6FBF

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

0x6FD0 0x6FDF

0x6FE3 0x6FE7

0x6FEA

0x6FFF

Submit Documentation Feedback Peripherals 83

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 4-16. F2808 GPIO MUX Table

DEFAULT AT RESET

GPAMUX1/2

(1) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1. (2) This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin

descriptions for more detail.

(3) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(1)

PRIMARY I/O PERIPHERAL PERIPHERAL PERIPHERAL

(2)

SELECTION 2 SELECTION 3

BITS (GPxMUX1/2 (GPxMUX1/2 BITS = 0,1) (GPxMUX1/2 BITS = 1,0) (GPxMUX1/2 BITS = 1,1)

BITS = 0,0)

GPAMUX1

1-0 GPIO0 EPWM1A (O) Reserved

(3)

3-2 GPIO1 EPWM1B (O) SPISIMOD (I/O) Reserved 5-4 GPIO2 EPWM2A (O) Reserved

(3)

7-6 GPIO3 EPWM2B (O) SPISOMID (I/O) Reserved 9-8 GPIO4 EPWM3A (O) Reserved

(3)

Reserved

(3) (3) (3) (3) (3)

11-10 GPIO5 EPWM3B (O) SPICLKD (I/O) ECAP1 (I/O) 13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) SPISTED (I/O) ECAP2 (I/O) 17-16 GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O) 21-20 GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP4 (I/O) 25-24 GPIO12 TZ1 (I) CANTXB (O) SPISIMOB (I/O) 27-26 GPIO13 TZ2 (I) CANRXB (I) SPISOMIB (I/O) 29-28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O) 31-30 GPIO15 TZ4 (I) SCIRXDB (I) SPISTEB (I/O)

GPAMUX2

1-0 GPIO16 SPISIMOA (I/O) CANTXB (O) TZ5 (I) 3-2 GPIO17 SPISOMIA (I/O) CANRXB (I) TZ6 (I) 5-4 GPIO18 SPICLKA (I/O) SCITXDB (O) Reserved 7-6 GPIO19 SPISTEA (I/O) SCIRXDB (I) Reserved

(3) (3)

9-8 GPIO20 EQEP1A (I) SPISIMOC (I/O) CANTXB (O) 11-10 GPIO21 EQEP1B (I) SPISOMIC (I/O) CANRXB (I) 13-12 GPIO22 EQEP1S (I/O) SPICLKC (I/O) SCITXDB (O) 15-14 GPIO23 EQEP1I (I/O) SPISTEC (I/O) SCIRXDB (I) 17-16 GPIO24 ECAP1 (I/O) EQEP2A (I) SPISIMOB (I/O) 19-18 GPIO25 ECAP2 (I/O) EQEP2B (I) SPISOMIB (I/O) 21-20 GPIO26 ECAP3 (I/O) EQEP2I (I/O) SPICLKB (I/O) 23-22 GPIO27 ECAP4 (I/O) EQEP2S (I/O) SPISTEB (I/O) 25-24 GPIO28 SCIRXDA (I) Reserved 27-26 GPIO29 SCITXDA (O) Reserved 29-28 GPIO30 CANRXA (I) Reserved 31-30 GPIO31 CANTXA (O) Reserved

(3) (3) (3) (3)

TZ5 (I) TZ6 (I) Reserved Reserved

(3) (3)

GPBMUX1

1-0 GPIO32 SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O)

3-2 GPIO33 SCLA (I/OC ) EPWMSYNCO (O) ADCSOCBO (O)

5-4 GPIO34 Reserved

(3)

Reserved

(3)

Reserved

(3)

Peripherals 84 Submit Documentation Feedback

www.ti.com

GPyCTRL Reg

SYNC

SYSCLKOUT

Qualification

Input Signal Qualified By 3 or 6 Samples

GPIOx

Time between samples

GPxQSEL

Number of Samples

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices:

• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

• Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.

Figure 4-17. Qualification Using Sampling Window

• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).

• No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

Submit Documentation Feedback Peripherals 85

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

5 Device Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of 280x-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• 2808 eZdsp™

• Evaluation modules

• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB

• Universal 5-V dc power supply

• Documentation and cables

5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F2808). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical

specifications

TMP Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification

testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Device Support86 Submit Documentation Feedback

www.ti.com

PREFIX

TMS 320 F 28015 PZ

TMX = Experimental Device TMP = Prototype Device TMS = Qualified Device

DEVICE FAMILY

320 = TMS320E DSP Family

TECHNOLOGY

PACKAGE TYPE PZ = 100-Pin Low-Profile Quad

Flatpack (LQFP) GGM = 100-Ball Ball Grid Array (BGA) ZGM = 100-Ball Lead-Free BGA

F = Flash EEPROM

(1.8-V Core/3.3-V I/O)

DEVICE 2809 2808 2806 2802 2801 28015 28016

TEMPERATURE RANGE A = –405C to 855C S = –405C to 125 5C Q = –405C to 1255C — Q100 Fault Grading

A −60

Indicates 60-MHz device

Absence of “−60” indicates

100-MHz device.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend for reading the complete device name for any family member.

Submit Documentation Feedback Device Support 87

Figure 5-1. Example of TMS320x280x Device Nomenclature

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

5.2 Documentation Support

Extensive documentation supports all of the TMS320™ DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. Useful reference documentation includes:

CPU User's Guides SPRU430 TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central

processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.

SPRU712 TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide describes the

various interrupts and system control features of the 280x digital signal processors (DSPs).

Peripheral Guides SPRU566 TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference guides

of the 28x digital signal processors (DSPs).

SPRU716 TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide describes

how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.

SPRU791 TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide

describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion

SPRU924 TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes the

operation of the high-resolution extension to the pulse width modulator (HRPWM)

SPRU807 TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes the

enhanced capture module. It includes the module description and registers.

SPRU790 TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide

describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers

SPRU074 TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide

describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.

SPRU051 TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the

SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

SPRU059 TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI -

a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.

SPRU721 TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the features

and operation of the inter-integrated circuit (I2C) module that is available on the TMS320x280x digital signal processor (DSP).

SPRU722 TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and

features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is

Device Support88 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

located within that memory.

Tools Guides SPRU513 TMS320C28x Assembly Language Tools User's Guide describes the assembly language

tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device.

SPRU514 TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++

compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device.

SPRU608 The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core.

SPRU625 TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide

describes development using DSP/BIOS.

Application Reports and Software

Key Links Include:

1. C2000 Get Started - www.ti.com/c2000getstarted

2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw

3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib

4. DSP Power Management Reference Designs - www.ti.com/dsppower

SPRAAM0 Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development

flow and functional areas to make your design effort as seamless as possible. Tips on getting started with C28x™ DSP software and hardware development are provided to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, software, and tools for use in each phase of design.

SPRA958 Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the

requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are presented. Example code projects are included.

SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware

abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define macros and topics of code efficiency and special case registers are also addressed.

SPRAA88 Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method

for utilizing the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).

SPRAA91 TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents

hardware connections as well as software preparation and operation of the development system using a simple communication echo program.

SPRAAH1 Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the use

of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x, 28xxx family of processors.

SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the

Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration from the 281x to the 280x. While the main focus of this document is migration from 281x to 280x, users considering migrating in the reverse direction (280x to 281x) will also find this document useful.

Submit Documentation Feedback Device Support 89

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

SPRAAI1 Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control

provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.

SPRAAD5 Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller

presents a complete implementation of a power line modem following CEA-709 protocol using a single DSP.

SPRAAD8 TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the

absolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices. Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of the ADC to levels better than

0.5%. This application report has an option to download an example program that executes from RAM on the F2808 EzDSP.

SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for

online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that contains functions for implementing the overflow detection on both DSP/BIOS™ and non-DSP/BIOS applications.

SPRA806 An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP

provides instructions and suggestions to configure the C compiler to assist with understanding of parameter-passing conventions and environments expected by the C compiler.

Software SPRC191 C280x, C2801x C/C++ Header Files and Peripheral Examples

SPRM194 F2801 100-Pin GGM/ZGM BSDL Model SPRM195 F2801 100-Pin PZ BSDL Model SPRM196 F2806 100-Pin PZ BSDL Model SPRM197 F2808 100-Pin PZ BSDL Model SPRM198 F2808 100-Pin GGM/ZGM BSDL Model SPRM200 F2806 100-Pin GGM/ZGM BSDL Model SPRM244 F2809 GGM/ZGM BSDL Model SPRM245 F2809 PZ BSDL Model

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information.

Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com.

To send comments regarding this data manual (literature number SPRS230), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

90 Device Support Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320F280x DSPs.

6.1 Absolute Maximum Ratings

(1) (2)

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.

Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, IIK(V Output clamp current, IOK(V Operating ambient temperature ranges, TA: A version (GGM, PZ)

Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the

voltage to a diode drop above V (4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for

TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963)

DDIO DDA2 DD DD1A18 SSA2

, V

DD3VFL

, V

DDAIO

, V

SSAIO

< 0 or VIN> V

< 0 or VO> V

(4)

stg

with respect to V with respect to V with respect to V

DD2A18

, V

SS1AGND

SS2AGND

with respect to V with respect to V

SS SSA SS SSA SS

- 0.3 V to 4.6 V

- 0.3 V to 2.5 V

- 0.3 V to 0.3 V

- 0.3 V to 4.6 V

(3)

)

DDIO

) ± 20 mA

DDIO

TA: S version (GGM, PZ) TA: Q version ( PZ)

(4)

- 40 ° C to 85 ° C

- 40 ° C to 125 ° C

- 40 ° C to 150 ° C

- 65 ° C to 150 ° C

DDA2

or below V

SSA2

± 20 mA

Submit Documentation Feedback Electrical Specifications 91

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Device supply voltage, I/O, V Device supply voltage CPU, V Supply ground, VSS, V ADC supply voltage (3.3 V), V ADC supply voltage (1.8 V), V Flash supply voltage, V Device clock frequency (system clock), f

High-level input voltage, V Low-level input voltage, V

High-level output source current, V

Low-level output sink current, V

Ambient temperature, T

(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1

DDIO

SSIO

, V

DDA2

DDAIO

, V

DD1A18

DD3VFL

DD2A18

SYSCLKOUT

100-MHz devices 2 100 MHz 60-MHz devices 2 60 MHz

= 2.4 V, I

= V

MAX, I

All I/Os except Group 2 -4 mA

Group 2

(1)

All I/Os except Group 2 4 mA

Group 2

(1)

A version -40 85

S version -40 125 ° C Q version -40 125

MIN NOM MAX UNIT

3.14 3.3 3.47 V

1.71 1.8 1.89 V 0 V

3.14 3.3 3.47 V

1.71 1.8 1.89 V

3.14 3.3 3.47 V

2 V

DDIO

0.8

-8

6.3 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage V

Low-level output voltage IOL= IOLMAX 0.4 V

Pin with pullup

Input current

(low level)

enabled Pin with pulldown

enabled Pin with pullup

enabled

Input current Pin with pulldown

(high level) enabled

Pin with pulldown enabled

Output current, pullup or

pulldown disabled

Input capacitance 2 pF

IOH= IOHMAX 2.4 IOH= 50 μ A V

= 3.3 V, VIN= 0 V All I/Os (including XRS) -80 -140 -190

DDIO

= 3.3 V, VIN= 0 V ± 2

DDIO

= 3.3 V, VIN= V

DDIO

VO= V

= 3.3 V, VIN= V

or 0 V ± 2 μ A

DDIO

(F280x) 28 50 80 μ A

DDIO

(C280x) 80 140 190

DDIO

- 0.2

DDIO

μ A

± 2

Electrical Specifications92 Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6.4 Current Consumption

Table 6-1. TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz

SYSCLKOUT

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1/2/3/4/5/6

• eCAP1/2/3/4

• eQEP1/2

• eCAN-A

• SCI-A/B

• SPI-A

• ADC

Operational (Flash)

IDLE 75 mA 90 mA 500 μ A 2 mA 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

STANDBY 6 mA 12 mA 100 μ A 500 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

HALT Peripheral clocks are off. 70 μ A 60 μ A 120 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

(1) I (2) I

(3) I (4) The TYP numbers are applicable over room temperature and nominal voltage.

• I2C All PWM pins are toggled at 100 kHz. All I/O pins are left unconnected. Data is continuously transmitted out of the SCI-A, SCI-B, and eCAN-A ports. The hardware multiplier is exercised. Code is running out of flash with 3 wait-states. XCLKOUT is turned off.

Flash is powered down. XCLKOUT is turned off. The following peripheral clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C

Flash is powered down. Peripheral clocks are off.

Flash is powered down. Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

DDA2

(4)

TYP

195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

and V

MAX TYP

pins. In order to realize the I

DD2A18

pins.

DDAIO

(1)

DDIO

(4)

MAX TYP MAX TYP

DD3VFL

currents shown for IDLE, STANDBY, and HALT,

DDA18

(2)

DDA18

(4)

MAX TYP

DDA33

(4)

(3)

MAX

NOTE

The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables.

Submit Documentation Feedback Electrical Specifications 93

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 6-2. TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1/2/3/4/5/6

• eCAP1/2/3/4

• eQEP1/2

• eCAN-A

• SCI-A/B

• SPI-A

Operational (Flash)

IDLE 75 mA 90 mA 500 μ A 2 mA 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

STANDBY 6 mA 12 mA 100 μ A 500 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

HALT Peripheral clocks are off. 70 μ A 60 μ A 120 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

(1) I (2) I

(3) I (4) The TYP numbers are applicable over room temperature and nominal voltage.

• ADC

• I2C

All PWM pins are toggled at 100 kHz. All I/O pins are left unconnected. Data is continuously transmitted out of the SCI-A, SCI-B, and eCAN-A ports. The hardware multiplier is exercised. Code is running out of flash with 3 wait-states. XCLKOUT is turned off

Flash is powered down. XCLKOUT is turned off. The following peripheral clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C

Flash is powered down. Peripheral clocks are off.

Flash is powered down. Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

and V

DDA2

(4)

TYP

195 mA 230 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

and V

MAX TYP

pins. In order to realize the I

DD2A18

pins.

DDAIO

(1)

DDIO

(4)

MAX TYP

DD3VFL

(4)

MAX TYP

currents shown for IDLE, STANDBY, and HALT,

DDA18

(2)

DDA18

(4)

MAX TYP

DDA33

(4)

(3)

MAX

NOTE

94 Electrical Specifications Submit Documentation Feedback

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 6-3. TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz

SYSCLKOUT

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1/2/3

• eCAP1/2

• eQEP1

• eCAN-A

• SCI-A

• SPI-A

Operational (Flash)

IDLE 75 mA 90 mA 500 μ A 2 mA 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

STANDBY 6 mA 12 mA 100 μ A 500 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

HALT Peripheral clocks are off. 70 μ A 60 μ A 120 μ A 2 μ A 10 μ A 5 μ A 50 μ A 15 μ A 30 μ A

(1) I (2) I

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. (3) I (4) The TYP numbers are applicable over room temperature and nominal voltage.

• ADC

• I2C

Flash is powered down. XCLKOUT is turned off. The following peripheral clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C

Flash is powered down. Peripheral clocks are off.

Flash is powered down. Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA18

includes current into V

DDA33

and V

DD1A18

and V

DDA2

(4)

TYP

180 mA 210 mA 15 mA 27 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

MAX TYP

pins. In order to realize the I

DD2A18

pins.

DDAIO

(1)

DDIO

(4)

MAX TYP

DD3VFL

(4)

MAX TYP

currents shown for IDLE, STANDBY, and HALT,

DDA18

(2)

DDA18

(4)

MAX TYP

DDA33

(4)

(3)

MAX

NOTE

Submit Documentation Feedback Electrical Specifications 95

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 6-4. TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at

100-MHz SYSCLKOUT

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1/2/3

• eCAP1/2

• eQEP1

• eCAN-A

• SCI-A

• SPI-A

Operational (ROM)

IDLE 75 mA 90 mA 500 μ A 2 mA 5 μ A 50 μ A 15 μ A 30 μ A

STANDBY Peripheral clocks are off. 6 mA 12 mA 100 μ A 500 μ A 5 μ A 50 μ A 15 μ A 30 μ A HALT 70 μ A 80 μ A 120 μ A 5 μ A 50 μ A 15 μ A 30 μ A

(1) I

DDIO

(2) I

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. (3) I

DDA33

(4) The TYP numbers are applicable over room temperature and nominal voltage.

• ADC

• I2C

XCLKOUT is turned off. The following peripheral clocks are enabled:

• eCAN-A

• SCI-A

• SPI-A

• I2C

Peripheral clocks are off. Input clock is disabled.

150 mA 165 mA 5 mA 10 mA 30 mA 38 mA 1.5 mA 2 mA

current is dependent on the electrical loading on the I/O pins.

includes current into V includes current into V

and V

DD1A18

DDA2

and V

DD2A18

DDAIO

(4)

TYP

MAX TYP

pins. In order to realize the I

pins.

(1)

DDIO

(4)

MAX TYP

currents shown for IDLE, STANDBY, and HALT,

DDA18

(2)

DDA18

(4)

MAX TYP

DDA33

(4)

(3)

MAX

NOTE

96 Electrical Specifications Submit Documentation Feedback

www.ti.com

6.4.1 Reducing Current Consumption

280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been removed, the following new peripherals have been added on the 280x:

• 3 SPI modules

• 1 CAN module

• 1 I2C module

The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6), eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs incorporate a unique method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-5 indicates the typical reduction in current consumption achieved by turning off the clocks.

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Table 6-5. Typical Current Consumption by Various

Peripherals (at 100 MHz)

PERIPHERAL IDDCURRENT

MODULE REDUCTION (mA)

ADC 8

I2C 5

eQEP 5

ePWM 5

eCAP 2

SCI 4 SPI 5

eCAN 11

(1) All peripheral clocks are disabled upon reset. Writing to/reading

from peripheral registers is possible only after the peripheral clocks are turned on.

(2) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

DDIO

The baseline IDDcurrent (current when the core is executing a dummy loop with no peripherals enabled) is 110 mA, typical. To arrive at the IDDcurrent for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDDcurrent.

) as well.

DDA18

NOTE

(1)

(2)

Submit Documentation Feedback Electrical Specifications 97

www.ti.com

0.0

50.0

100.0

150.0

200.0

250.0

10 20 30 40 50 60 70 80 90 100

SYSCLKOUT (MHz)

Current (mA)

IDD IDDA18 IDDIO IDD3VFL 3.3-V current

1.8-V current

0.0

100.0

200.0

300.0

400.0

500.0

600.0

10 20 30 40 50 60 70 80 90 100

SYSCLKOUT (MHz)

Device Power (mW)

TOTAL POWER

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6.4.2 Current Consumption Graphs

Figure 6-1. Typical Operational Current Versus Frequency (F2808)

98 Electrical Specifications Submit Documentation Feedback

Typical operational current for 60-MHz devices can be estimated from Figure 6-1 . For I current alone, subtract the current contribution of non-existent peripherals after scaling the peripheral currents for 60 MHz. For example, to compute the current of F2801-60 device, the contribution by the following peripherals must be subtracted from Idd: ePWM4/5/6, eCAP3/4, eQEP2, SCI-B.

Figure 6-2. Typical Operational Power Versus Frequency (F2808)

NOTE

www.ti.com

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

VDDIO

DSP

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

TCK_RET

6inchesorless

GND

JTAGHeader

VDDIO

TMS320F2809, TMS320F2808, TMS320F2806

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

6.5 Emulator Connection Without Signal Buffering for the DSP

Figure 6-3 shows the connection between the DSP and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.

TMS320F2802, TMS320F2801

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

Figure 6-3. Emulator Connection Without Signal Buffering for the DSP

Submit Documentation Feedback Electrical Specifications 99

www.ti.com

TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801 TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230J – OCTOBER 2003 – REVISED SEPTEMBER 2007

6.6 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their Letters and symbols and their meanings: meanings:

a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width)

6.6.1 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

Electrical Specifications100 Submit Documentation Feedback

TEXAS INSTRUMENTS TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

1 F280x, F2801x, C280x DSPs

1.1 Features

1.2 Getting Started

2 Introduction

2.1 Pin Assignments

2.2 Signal Descriptions

3 Functional Overview

3.1 Memory Maps

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 Flash

3.2.6 ROM

3.2.7 M0, M1 SARAMs

3.2.8 L0, L1, H0 SARAMs

3.2.9 Boot ROM

3.2.10 Security

3.2.11 Peripheral Interrupt Expansion (PIE) Block

3.2.12 External Interrupts (XINT1, XINT2, XNMI)

3.2.13 Oscillator and PLL

3.2.14 Watchdog

3.2.15 Peripheral Clocking

3.2.16 Low-Power Modes

3.2.17 Peripheral Frames 0, 1, 2 (PFn)

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer

3.2.19 32-Bit CPU-Timers (0, 1, 2)

3.2.20 Control Peripherals

3.2.21 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 Interrupts

3.5.1 External Interrupts

3.6 System Control

3.6.1 OSC and PLL Block

3.6.2 Watchdog Block

3.7 Low-Power Modes Block

4 Peripherals

4.1 32-Bit CPU-Timers 0/1/2

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)

4.3 Hi-Resolution PWM (HRPWM)

4.4 Enhanced CAP Modules (eCAP1/2/3/4)

4.5 Enhanced QEP Modules (eQEP1/2)

4.6 Enhanced Analog-to-Digital Converter (ADC) Module

4.6.1 ADC Connections if the ADC Is Not Used

4.6.2 ADC Registers

4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)

4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)

4.10 Inter-Integrated Circuit (I2C)

4.11 GPIO MUX

5 Device Support

5.1 Device and Development Support Tool Nomenclature

5.2 Documentation Support

6 Electrical Specifications

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 Electrical Characteristics

6.4 Current Consumption

6.4.1 Reducing Current Consumption

6.4.2 Current Consumption Graphs

6.5 Emulator Connection Without Signal Buffering for the DSP

6.6 Timing Parameter Symbology

6.6.1 General Notes on Timing Parameters