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TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

TMS320F2806x Piccolo™ Microcontrollers

1 Device Overview

1.1 Features

• High-Efficiency 32-Bit CPU (TMS320C28x) – 90 MHz (11.11-ns Cycle Time) – 16 × 16 and 32 × 32 Multiply and Accumulate

(MAC) Operations – 16 × 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly)

• Floating-Point Unit (FPU) – Native Single-Precision Floating-Point

Operations

• Programmable Control Law Accelerator (CLA) – 32-Bit Floating-Point Math Accelerator – Executes Code Independently of the Main CPU

• Viterbi, Complex Math, CRC Unit (VCU) – Extends C28x Instruction Set to Support

Complex Multiply, Viterbi Operations, and Cyclic Redundency Check (CRC)

• Embedded Memory – Up to 256KB of Flash – Up to 100KB of RAM – 2KB of One-Time Programmable (OTP) ROM

• 6-Channel Direct Memory Access (DMA)

• Low Device and System Cost – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out

Reset – Low-Power Operating Modes – No Analog Support Pin

• Endianness: Little Endian

• JTAG Boundary Scan Support – IEEE Standard 1149.1-1990 Standard Test

Access Port and Boundary Scan Architecture

• Clocking – Two Internal Zero-Pin Oscillators – On-Chip Crystal Oscillator/External Clock Input – Watchdog Timer Module – Missing Clock Detection Circuitry

• Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

• Three 32-Bit CPU Timers

• Advanced Control Peripherals

• Up to 8 Enhanced Pulse-Width Modulator (ePWM) Modules

– 16 PWM Channels Total (8 HRPWM-Capable) – Independent 16-Bit Timer in Each Module

• Three Input Enhanced Capture (eCAP) Modules

• Up to 4 High-Resolution Capture (HRCAP) Modules

• Up to 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules

• 12-Bit Analog-to-Digital Converter (ADC), Dual Sample-and-Hold (S/H)

– Up to 3.46 MSPS – Up to 16 Channels

• On-Chip Temperature Sensor

• 128-Bit Security Key and Lock – Protects Secure Memory Blocks – Prevents Reverse-Engineering of Firmware

• Serial Port Peripherals – Two Serial Communications Interface (SCI)

[UART] Modules – Two Serial Peripheral Interface (SPI) Modules – One Inter-Integrated-Circuit (I2C) Bus – One Multichannel Buffered Serial Port (McBSP)

Bus – One Enhanced Controller Area Network (eCAN) – Universal Serial Bus (USB) 2.0

(see Device Comparison Table for Availability)

• Full-Speed Device Mode

• Full-Speed or Low-Speed Host Mode

• Up to 54 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug Through Hardware

• 2806x Packages – 80-Pin PFP and 100-Pin PZP PowerPAD™

Thermally Enhanced Thin Quad Flatpacks (HTQFPs)

– 80-Pin PN and 100-Pin PZ Low-Profile Quad

Flatpacks (LQFPs)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

1.2 Applications

• Switch Mode Power Supplies (SMPSs)

• Solar Micro Inverters and Converters

• Power Factor Correction (PFC)

• Smart Grid and Power Line Communications

• AC/DC Inverters

1.3 Description

The F2806x Piccolo™ family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HighResolution Pulse Width Modulator (HRPWM) module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric V and latency.

REFHI/VREFLO

references. The ADC interface has been optimized for low overhead

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Device Information

PART NUMBER PACKAGE BODY SIZE

TMS320F28069PZP HTQFP (100) 14.0 mm × 14.0 mm TMS320F28069PFP HTQFP (80) 12.0 mm × 12.0 mm TMS320F28069PZ LQFP (100) 14.0 mm × 14.0 mm TMS320F28069PN LQFP (80) 12.0 mm × 12.0 mm

(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable

Information.

(1)

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CLA Bus

DMA Bus

16-bit Peripheral Bus

32-bit Peripheral

Bus

Memory Bus

A7:0

B7:0

Memory Bus

DMA Bus

CLA Bus

DMA Bus

GPIO Mux

AIO Mux

32-bit Peripheral Bus

ADC

0-wait

Result

Regs

ADC

COMP

DAC

COMP1OUT

COMP2OUT

COMP3OUT

COMP1A

COMP2A

COMP3A

COMP1B

COMP2B

COMP3B

Boot-ROM

(32K 16)

(0-wait,

Non-Secure)

GPIO

Mux

GPIO

Mux

TRST

TCK, TDI, TMS

TDO

XCLKIN

LPM Wakeup

3 Ext. Interrupts

X1 X2

XRS

M0 SARAM (1K 16)

(0-wait, Non-Secure)

M1 SARAM (1K 16)

(0-wait, Non-Secure)

L5 DPSARAM (8K 16)

(0-wait, Non-Secure)

DMA RAM0

L6 DPSARAM (8K 16)

(0-wait, Non-Secure)

DMA RAM1

L7 DPSARAM (8K 16)

(0-wait, Non-Secure)

DMA RAM2

L8 DPSARAM (8K 16)

(0-wait, Non-Secure)

DMA RAM3

L0 DPSARAM (2K 16)

(0-wait, Secure) CLA Data RAM2

L1 DPSARAM (1K 16)

(0-wait, Secure) CLA Data RAM0

L2 DPSARAM (1K 16)

(0-wait, Secure) CLA Data RAM1

L3 DPSARAM (4K 16)

(0-wait, Secure)

CLA Program RAM

L4 SARAM (8K 16)

(0-wait, Secure)

Code

Security

Module

(CSM)

PSWD

OTP 1K 16

Secure

FLASH

128K 16

8 equal sectors

Secure

64K 16´

PUMP

OTP/Flash

Wrapper

32-bit Peripheral

Bus

USB-0

GPIO Mux

SCITXDx

SCIRXDx

SPISIMOx

SPISOMIx

SPICLKx

SPISTEx

SDAx

SCLx

MFSRA

MDRA

MCLKRA

MFSXA

MDXA

MCLKXA

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

HRCAPx

CANRXx

CANTXx

USB0DP

USB0DM

TZx

EPWMxA

EPWMxB

EPWMSYNCI

EPWMSYNCO

SCI-A SCI-B

(4L FIFO)

SPI-A SPI-B

(4L FIFO)

I2C-A

(4L FIFO)

32-bit Peripheral Bus

(CLA accessible)

ePWM1 to ePWM8

HRPWM (8ch)

McBSP-A

32-bit

Peripheral Bus

(CLA accessible)

eCAP1 eCAP2 eCAP3

eQEP1 eQEP2

32-bit Peripheral

Bus

HRCAP1 HRCAP2 HRCAP3 HRCAP4

eCAN-A

(32-mbox)

CLA +

Message

RAMs

DMA

6-ch

C28x 32-bit CPU

FPU VCU

OSC1, OSC2,

Ext, PLLs,

LPM, WD, CPU Timer 0, CPU Timer 1, CPU Timer 2,

PIE

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1.4 Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

A. Not all peripheral pins are available at the same time due to multiplexing.

Figure 1-1. Functional Block Diagram

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10-bit

DAC

Analog

Comparators

CMP1-Out

CMP2-Out

CMP3-Out

Trip Zone

Temp

Sensor

ADC

(DMA-

accessible)

12-bit

3.46-MSPS Dual

Sample-

andHold

SOC-based

REF

CLA Core

90-MHz Floating-Point

(Accelerator)

(DMA-accessible)

10-bit

DAC

10-bit

DAC

A2 A3 A4 A5 A6 A7

B1 B2 B3 B4 B5 B6 B7

eQEP 2´

HRCAP 4´

eCAP 3´

System

Vreg

Int-Osc-1

POR/BOR

Int-Osc-2

On-chip Osc

PLL

CLKSEL

Timers 32-bit

Timer-0

Timer-1

Timer-2

GPIO

Control

COMMS

X1 X2

REFLO

REFHI

C28x Core

(90-MHz)

FPU

VCU

Flash Memory

RAM

(Dual-Access)

eQEP

HRCAP

eCAP

PWM-1A PWM-1B

PWM-2A PWM-2B

PWM-3A PWM-3B

PWM-4A PWM-4B

PWM-5A PWM-5B

PWM-6A PWM-6B

PWM-7A PWM-7B

PWM-8A PWM-8B

TZ1 TZ2 TZ3

CMP1-out CMP2-out CMP3-out

PWM1

(DMA-accessible)

PWM5

(DMA-accessible)

PWM8

(DMA-accessible)

PWM7

(DMA-accessible)

PWM6

(DMA-accessible)

PWM4

(DMA-accessible)

PWM3

(DMA-accessible)

PWM2

(DMA-accessible)

UART 2´

SPI 2´

I C

CAN

McBSP

(DMA-accessible)

USB

(DMA-accessible)

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

1.5 System Device Diagram

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Figure 1-2. Peripheral Blocks

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TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

1.5 System Device Diagram.............................. 4

2 Revision History ......................................... 6

3 Device Comparison ..................................... 7

4 Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Signal Descriptions.................................. 11

5 Specifications........................................... 19

5.1 Absolute Maximum Ratings ........................ 19

5.2 ESD Ratings for TMS320F2806xU ................. 19

5.3 ESD Ratings for TMS320F2806x,

TMS320F2806xM, and TMS320F2806xF .......... 19

5.4 Recommended Operating Conditions............... 20

5.5 Electrical Characteristics............................ 20

5.6 Power Consumption Summary...................... 21

5.7 Thermal Resistance Characteristics ................ 25

5.8 Thermal Design Considerations .................... 27

5.9 Emulator Connection Without Signal Buffering for

the MCU............................................. 27

5.10 Parameter Information .............................. 28

5.11 Test Load Circuit .................................... 28

5.12 Power Sequencing.................................. 29

5.13 Clock Specifications................................. 32

5.14 Flash Timing ........................................ 35

6 Detailed Description................................... 37

6.1 Overview ............................................ 37

6.2 Memory Maps....................................... 47

6.3 Register Maps....................................... 58

6.4 Device Emulation Registers......................... 60

6.5 VREG, BOR, POR .................................. 62

6.6 System Control ...................................... 64

6.7 Low-power Modes Block ............................ 73

6.8 Interrupts ............................................ 74

6.9 Peripherals .......................................... 79

7 Applications, Implementation, and Layout ...... 156

7.1 TI Design or Reference Design.................... 156

7.2 Development Tools ................................ 157

7.3 Software Tools ..................................... 157

7.4 Training ............................................ 158

8 Device and Documentation Support.............. 159

8.1 Device Support..................................... 159

8.2 Documentation Support............................ 161

8.3 Related Links ...................................... 162

8.4 Community Resources............................. 162

8.5 Trademarks ........................................ 162

8.6 Electrostatic Discharge Caution ................... 162

8.7 Glossary............................................ 162

9 Mechanical Packaging and Orderable

Information............................................. 163

9.1 Packaging Information ............................. 163

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SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from July 2, 2014 to March 22, 2016 (from E Revision (July 2014) to F Revision) Page

• Global: Changed "CAN 2.0B" to "ISO11898-1 (CAN 2.0B)". .................................................................. 1

• Table 3-1 (Device Comparison): Changed the number of High-resolution ePWM Channels on the 80-Pin

PN/PFP packages from 6 to 8. ..................................................................................................... 7

• Table 3-1: Removed "Product status" row and associated footnote. ......................................................... 7

• Figure 4-1 (80-Pin PN and PFP Packages (Top View)): Added footnote about PowerPAD. .............................. 9

• Figure 4-2 (100-Pin PZ and PZP Packages (Top View)): Added footnote about PowerPAD. ........................... 10

• Section 4.2 (Signal Descriptions): Added "GPIO26–27" to NOTE. .......................................................... 11

• Table 4-1 (Signal Descriptions): Updated DESCRIPTION of X1, V

• Section 5.1 (Absolute Maximum Ratings): Added Input voltage, V

• Section 5.1: Added T

. ........................................................................................................... 19

stg

• Section 5.2 (ESD Ratings for TMS320F2806xU): Added section. ........................................................... 19

• Section 5.3 (ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF): Changed title from

"Handling Ratings" to "ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF". ................. 19

• Section 5.3: Updated footnotes. .................................................................................................. 19

• Section 5.4 (Recommended Operating Conditions): Removed footnote that read "V

maintained within approximately 0.3 V of each other". ........................................................................ 20

• Section 5.6 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power

Consumption Summary". .......................................................................................................... 21

• Section 5.12 (Power Sequencing): Updated paragraph that reads "There is no power sequencing requirement

needed ...". .......................................................................................................................... 29

• Table 5-10 (XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)): Added MAX value for t

• Table 5-10: Added MAX value for t

......................................................................................... 34

r(XCO)

• Table 5-15 (Flash/OTP Access Timing): Removed footnote. ................................................................. 36

• Figure 6-1 (28069 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ........ 48

• Figure 6-2 (28068 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ....... 49

• Figure 6-3 (28067 Memory Map): Added figure. ............................................................................... 50

• Figure 6-8 (28062 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ........ 55

• Section 6.6.2 (Crystal Oscillator Option): Added paragraph that begins "The on-chip crystal oscillator X1 and X2

pins are 1.8-V level signals ...". ................................................................................................... 67

• Section 6.9.6.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs

with "For all SPI slave modes ..." table footnotes. ............................................................................ 115

• Table 6-44 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all

SPI slave modes ..." footnote. ................................................................................................... 115

• Table 6-46 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all

SPI slave modes ..." footnote. ................................................................................................... 116

• Table 6-48 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all

SPI slave modes ..." footnote. ................................................................................................... 117

• Table 6-50 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all

SPI slave modes ..." footnote. ................................................................................................... 118

• Table 6-65 (HRCAP Registers): Added reference to footnote for HCICLR and HCIFRC. .............................. 137

• Section 7 (Applications, Implementation, and Layout): Added section. .................................................... 156

• Section 8.1.1.1 (Getting Started): Updated links. ............................................................................. 159

• Figure 8-1 (Device Nomenclature): Updated list of devices. ................................................................ 160

• Section 8.2 (Documentation Support): Added the Calculating Useful Lifetimes of Embedded Processors

Application Report (SPRABX4) to list of application reports. ............................................................... 161

• Section 8.2.1 (Receiving Notification of Document Updates): Added section. ............................................ 162

, V

REFHI

(X1). ................................................. 19

REFLO

, and V

DDIO

. ............................. 11

DDIO

and V

DDA

should be

f(XCO)

........ 34

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SPRS698F – NOVEMBER 2010–REVISED MARCH 2016

3 Device Comparison

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) and in the peripheral reference

guides. (2) USB is present on TMS320F2806xU, TMS320F2806xM, and TMS320F2806xF devices. (3) The "Q" temperature option is not available on the TMS320F2806xU devices. (4) TMS320F2806xM devices are InstaSPIN-MOTION-enabled MCUs. TMS320F2806xF devices are InstaSPIN-FOC-enabled MCUs. For more information, see Section 8.2 for a list of

InstaSPIN Technical Reference Manuals.

Table 3-1. Device Comparison

FEATURE TYPE

(1)

28069

28069U

(2) (3)

28069M

(2) (4)

28069F

(2) (4)

(90 MHz)

28068

28068U

(2) (3)

28068M

(2) (4)

28068F

(2) (4)

(90 MHz)

28067

28067U

(2) (3)

(90 MHz)

28066

28066U

(2) (3)

(90 MHz)

28065

28065U

(2) (3)

(90 MHz)

28064

28064U

(2) (3)

(90 MHz)

28063

28063U

(2) (3)

(90 MHz)

28062

28062U

(2) (3)

28062F

(2) (4)

(90 MHz)

Package Type (PFP andPZP are PowerPAD HTQFPs. PN andPZ are LQFPs.)

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

Instruction cycle – 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns Floating-Point Unit(FPU) Yes Yes Yes Yes Yes Yes Yes Yes VCU Yes Yes No No Yes Yes No No CLA 0 Yes No No No Yes No No No 6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes On-chip Flash(16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K On-chip SARAM(16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K Code securityfor on-chip Flash, SARAM,

and OTPblocks

– Yes Yes Yes Yes Yes Yes Yes Yes

Boot ROM(32K × 16) – Yes Yes Yes Yes Yes Yes Yes Yes One-time programmable(OTP) ROM

(16-bit word)

– 1K 1K 1K 1K 1K 1K 1K 1K

ePWM channels 1 16 14 16 14 16 14 16 14 16 14 16 14 16 14 16 14 High-resolution ePWMChannels 1 8 8 8 8 8 8 8 8 eCAP inputs 0 3 3 3 3 3 3 3 3 HRCAP 0 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes

12-Bit ADC

MSPS

3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46 Conversion Time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns Channels 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes

32-Bit CPUtimers – 3 3 3 3 3 3 3 3 Comparators withIntegrated DACs 0 3 3 3 3 3 3 3 3

I2C

0 1 1 1 1 1 1 1 1

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SPRS698F – NOVEMBER 2010–REVISED MARCH 2016

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Table 3-1. Device Comparison (continued)

FEATURE TYPE

(1)

28069

28069U

(2) (3)

28069M

(2) (4)

28069F

(2) (4)

(90 MHz)

28068

28068U

(2) (3)

28068M

(2) (4)

28068F

(2) (4)

(90 MHz)

28067

28067U

(2) (3)

(90 MHz)

28066

28066U

(2) (3)

(90 MHz)

28065

28065U

(2) (3)

(90 MHz)

28064

28064U

(2) (3)

(90 MHz)

28063

28063U

(2) (3)

(90 MHz)

28062

28062U

(2) (3)

28062F

(2) (4)

(90 MHz)

Package Type (PFP andPZP are PowerPAD HTQFPs. PN andPZ are LQFPs.)

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

100-Pin

PZP

80-Pin

PFP

(5) "Q" refers to Q100 qualification for automotive applications.

McBSP 1 1 1 1 1 1 1 1 1 eCAN 0 1 1 1 1 1 1 1 1 SPI 1 2 2 2 2 2 2 2 2 SCI 0 2 2 2 2 2 2 2 2 USB 0 1

(2)

2-pin Oscillator 1 1 1 1 1 1 1 1 0-pin Oscillator 2 2 2 2 2 2 2 2

I/O pins (shared)

GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40 AIO – 6 6 6 6 6 6 6 6

External interrupts – 3 3 3 3 3 3 3 3 Supply voltage(nominal) – 3.3 V 3.3 V 3.3 V 3.3V 3.3 V 3.3V 3.3 V 3.3V

Temperature options

T: –40°Cto 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP Q: –40°Cto 125°C

(3)(5)

– PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP

101112

GPIO23/EQEP1I/MFSXA/SCIRXDB

DDIO

GPIO20/EQEP1A/MDXA/COMP1OUT

GPIO21/EQEP1B/MDRA/COMP2OUT

GPIO4/EPWM3A

GPIO5/EPWM3B/SPISIMOA/ECAP1

XRS

TRST

DDIO

ADCINA6/COMP3A/AIO6

ADCINA5

ADCINA4/COMP2A/AIO4

ADCINA2/COMP1A/AIO2

ADCINA1

ADCINA0, V

REFHI

DDA

GPIO10/EPWM6A/ADCSOCBO

GPIO11/EPWM6B/SCIRXDB/ECAP1

GPIO36/TMS

GPIO35/TDI

GPIO37/TDO

GPIO34/COMP2OUT/COMP3OUT

GPIO38/XCLKIN/TCK

GPIO39

GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA

VDDVSSV

DDIO

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO7/EPWM4B/SCIRXDA/ECAP2

GPIO16/SPISIMOA/TZ2

GPIO8/EPWM5A/ADCSOCAO

GPIO17/SPISOMIA/TZ3

GPIO18/SPICLKA/SCITXDB/XCLKOUT

GPIO26/ECAP3/SPICLKB/USB0DP

GPIO27/HRCAP2/SPISTEB/USB0DM

DDIO

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO2/EPWM2A

GPIO1/EPWM1B/COMP1OUT

GPIO0/EPWM1A

GPIO15/ECAP2/SCIRXDB/SPISTEB

VREGENZ

DDIO

GPIO13/ /SPISOMIBTZ2

GPIO14/ /SCITXDB/SPICLKBTZ3

GPIO24/ECAP1/SPISIMOB

GPIO22/EQEP1S/MCLKXA/SCITXDB

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO29/SCITXDA/SCLA/TZ3

GPIO12/ /SCITXDA/SPISIMOBTZ1

TEST2

DD3VFL

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO28/SCIRXDA/SDAA/TZ2

GPIO30/CANRXA/EPWM7A

GPIO31/CANTXA/EPWM8A

GPIO25/ECAP2/SPISOMIB

DDIO

ADCINB6/COMP3B/AIO14

ADCINB5

ADCINB4/COMP2B/AIO12

ADCINB2/COMP1B/AIO10

ADCINB1

ADCINB0 V , V

REFLO SSA

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pin assignments on the 80-pin PN and PFP packages. Figure 4-2 shows the pin

assignments on the 100-pin PZ and PZP packages.

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

A. Pin 19: V

exclusive to one another. Pin 21: V

REFHI

is always connected to V

REFLO

and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually

B. The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must

be connected to the ground plane of the PCB. It should not be left unconnected. For more details, see the PowerPAD™ Thermally Enhanced Package Application Report (SLMA002).

Figure 4-1. 80-Pin PN and PFP Packages (Top View)

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100

DDIO

REFHI

DDIO

DD3VFL

SSA

TEST2

ADCINB7

ADCINB3

VREGENZ

REFLO

ADCINB6/COMP3B/AIO14

ADCINB5

ADCINB4/COMP2B/AIO12

ADCINB2/COMP1B/AIO10

ADCINB1

ADCINB0

GPIO0/EPWM1A

GPIO1/EPWM1B/COMP1OUT

GPIO2/EPWM2A

GPIO56/SPICLKA/EQEP2I/HRCAP3

GPIO57/ /EQEP2S/HRCAP4SPISTEA

GPIO58/MCLKRA/SCITXDB/EPWM7A

GPIO40/EPWM7A/SCITXDB

GPIO41/EPWM7B/SCIRXDB

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO44/MFSRA/SCIRXDB/EPWM7B

GPIO7/EPWM4B/SCIRXDA/ECAP2

GPIO8/EPWM5A/ADCSOCAO

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO10/EPWM6A/ADCSOCBO

GPIO11/EPWM6B/SCIRXDB/ECAP1

GPIO12/ /SCITXDA/SPISIMOBTZ1

GPIO13/ /SPISOMIBTZ2

GPIO14/ /SCITXDB/SPICLKBTZ3

GPIO15/ECAP2/SCIRXDB/SPISTEB

GPIO16/SPISIMOA/TZ2

GPIO17/SPISOMIA/TZ3

GPIO42/EPWM8A/ /COMP1OUTTZ1

GPIO43/EPWM8B/ /COMP2OUTTZ2

GPIO18/SPICLKA/SCITXDB/XCLKOUT

GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA

GPIO22/EQEP1S/MCLKXA/SCITXDB

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO25/ECAP2/EQEP2B/SPISOMIB

GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP

GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM

GPIO28/SCIRXDA/SDAA/TZ2

GPIO29/SCITXDA/SCLA/TZ3

GPIO30/CANRXA/EQEP2I/EPWM7A

GPIO50/EQEP1A/MDXA/TZ1

GPIO51/EQEP1B/MDRA/TZ2

GPIO52/EQEP1S/MCLKXA/TZ3

GPIO53/EQEP1I/MFSXA

GPIO54/SPISIMOA/EQEP2A/HRCAP1

GPIO55/SPISOMIA/EQEP2B/HRCAP2

GPIO31/CANTXA/EQEP2S/EPWM8A

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO34/COMP2OUT/COMP3OUT

GPIO35/TDI

GPIO36/TMS

GPIO37/TDO

GPIO38/XCLKIN/TCK

GPIO39

GPIO23/EQEP1I/MFSXA/SCIRXDB

GPIO20/EQEP1A/MDXA/COMP1OUT

GPIO21/EQEP1B/MDRA/COMP2OUT

GPIO4/EPWM3A

GPIO5/EPWM3B/SPISIMOA/ECAP1

ADCINA7

ADCINA3

XRS

TRST

ADCINA6/COMP3A/AIO6

ADCINA5

ADCINA4/COMP2A/AIO4

ADCINA2/COMP1A/AIO2

ADCINA1

ADCINA0

DDA

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A. The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must

be connected to the ground plane of the PCB. It should not be left unconnected. For more details, see the PowerPAD™ Thermally Enhanced Package Application Report (SLMA002).

Figure 4-2. 100-Pin PZ and PZP Packages (Top View)

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4.2 Signal Descriptions

Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

When the on-chip voltage regulator (VREG) is used, the GPIO19, GPIO26–27, and GPIO34–38 pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDDpins before or simultaneously with the V reached 0.7 V before the V

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NOTE

pins, ensuring that the VDDpins have

pins reach 0.7 V.

DDIO

Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

TRST 12 10 I

TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑) TMS See GPIO36 I

TDI See GPIO35 I

TDO See GPIO37 O/Z

DD3VFL

TEST2 45 36 I/O Test Pin. Reserved for TI. Must be left unconnected.

PZP

46 37 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

PFP

I/O/Z DESCRIPTION

JTAG

JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (↓)

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8-mA drive)

FLASH

(1)

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

XCLKOUT See GPIO18 O/Z

XCLKIN

X1 60 48 I

X2 59 47 O

XRS 11 9 I/OD

ADCINA7 16 – I ADC Group A, Channel 7 input ADCINA6 COMP3A I Comparator Input 3A AIO6 I/O Digital AIO 6 ADCINA5 18 15 I ADC Group A, Channel 5 input ADCINA4 COMP2A I Comparator Input 2A AIO4 I/O Digital AIO 4 ADCINA3 20 – I ADC Group A, Channel 3 input ADCINA2 COMP1A I Comparator Input 1A AIO2 I/O Digital AIO 2 ADCINA1 22 18 I ADC Group A, Channel 1 input

ADCINA0 23 19 I

PZP

See GPIO19 and

17 14

19 16

21 17

PFP

GPIO38

I/O/Z DESCRIPTION

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN

path must be disabled by bit 13 in the CLKCTL register. NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.

On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected.

RESET

Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-out condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor between 2.2 kΩ and 10 kΩ should be placed between XRS and V noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOLwithin 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (↑)

ADC, COMPARATOR, ANALOG I/O

I ADC Group A, Channel 6 input

I ADC Group A, Channel 4 input

I ADC Group A, Channel 2 input

ADC Group A, Channel 0 input. NOTE: V and their use is mutually exclusive to one another.

and ADCINA0 share the same pin on the 80-pin PN and PFP devices

REFHI

(1)

DDIO

(continued)

. If a capacitor is placed between XRS and VSSfor

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Table 4-1. Signal Descriptions

(1)

PIN NO.

PIN NAME

PZP

PFP

I/O/Z DESCRIPTION

ADC External Reference High – only used when in ADC external reference mode. See

REFHI

24 19

Section 6.9.2.1.

NOTE: V and their use is mutually exclusive to one another.

and ADCINA0 share the same pin on the 80-pin PN and PFP devices

REFHI

ADCINB7 35 – I ADC Group B, Channel 7 input ADCINB6 COMP3B I Comparator Input 3B

34 27

I ADC Group B, Channel 6 input

AIO14 I/O Digital AIO 14 ADCINB5 33 26 I ADC Group B, Channel 5 input ADCINB4 COMP2B I Comparator Input 2B

32 25

I ADC Group B, Channel 4 input

AIO12 I/O Digital AIO12 ADCINB3 31 – I ADC Group B, Channel 3 input ADCINB2 COMP1B I Comparator Input 1B

30 24

I ADC Group B, Channel 2 input

AIO10 I/O Digital AIO 10 ADCINB1 29 23 I ADC Group B, Channel 1 input ADCINB0 28 22 I ADC Group B, Channel 0 input

REFLO

27 21

ADC External Reference Low. NOTE: V

is always connected to V

REFLO

CPU AND I/O POWER

DDA

SSA

25 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin. 26 21

Analog Ground Pin. NOTE: V

is always connected to V

REFLO

3 2

14 12

37 29 63 51

CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDDpin and ground. Higher value capacitors may be used.

81 65 91 72

5 4

13 11

DDIO

38 30 61 49

Digital I/O and Flash Power Pin. Single supply source when VREG is enabled. Place a

2.2-uF decoupling capacitor on each pin. The exact value of the total decoupling capacitance should be determined by the system voltage regulation solution.

79 63 93 74

4 3 15 13 36 28

47 38

Digital Ground Pins 62 50 80 64 92 73

(continued)

on the 80-pin PN and PFP devices.

SSA

on the 80-pin PN and PFP devices.

SSA

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

VREGENZ 90 71 I Internal VREG Enable/Disable. Pull low to enable VREG, pull high to disable VREG.

GPIO0

EPWM1A O Enhanced PWM1 Output A and HRPWM channel

GPIO1

EPWM1B O Enhanced PWM1 Output B COMP1OUT O Direct output of Comparator 1

GPIO2

EPWM2A O Enhanced PWM2 Output A and HRPWM channel

GPIO3

EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in COMP2OUT O Direct output of Comparator 2

GPIO4

EPWM3A O Enhanced PWM3 output A and HRPWM channel

GPIO5

EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI-A slave in, master out ECAP1 I/O Enhanced Capture input/output 1

GPIO6

EPWM4A O Enhanced PWM4 output A and HRPWM channel EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output

GPIO7

EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data ECAP2 I/O Enhanced Capture input/output 2

GPIO8

EPWM5A O Enhanced PWM5 output A and HRPWM channel Reserved – Reserved ADCSOCAO O ADC start-of-conversion A

GPIO9

EPWM5B O Enhanced PWM5 output B SCITXDB O SCI-B transmit data ECAP3 I/O Enhanced Capture input/output 3

GPIO10

EPWM6A O Enhanced PWM6 output A and HRPWM channel Reserved – Reserved ADCSOCBO O ADC start-of-conversion B

GPIO11

EPWM6B O Enhanced PWM6 output B SCIRXDB I SCI-B receive data ECAP1 I/O Enhanced Capture input/output 1

PZP

87 69

86 68

84 67

83 66

9 7

10 8

58 46

57 45

54 43

49 39

74 60

73 59

PFP

I/O/Z DESCRIPTION

VOLTAGE REGULATOR CONTROL SIGNAL

GPIO AND PERIPHERAL SIGNALS

I/O/Z General-purpose input/output 0

I/O/Z General-purpose input/output 1

I/O/Z General-purpose input/output 2

I/O/Z General-purpose input/output 3

I/O/Z General-purpose input/output 4

I/O/Z General-purpose input/output 5

I/O/Z General-purpose input/output 6

I/O/Z General-purpose input/output 7

I/O/Z General-purpose input/output 8

I/O/Z General-purpose input/output 9

I/O/Z General-purpose input/output 10

I/O/Z General-purpose input/output 11

(1)

(continued)

(2)

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

GPIO12

TZ1 I Trip Zone input 1 SCITXDA O SCI-A transmit data SPISIMOB I/O SPI-B slave in, master out

GPIO13

TZ2 I Trip Zone input 2 Reserved – Reserved SPISOMIB I/O SPI-B slave out, master in

GPIO14

TZ3 I Trip zone input 3 SCITXDB O SCI-B transmit data SPICLKB I/O SPI-B clock input/output

GPIO15

ECAP2 I/O Enhanced Capture input/output 2 SCIRXDB I SCI-B receive data SPISTEB I/O SPI-B slave transmit enable input/output

GPIO16

SPISIMOA I/O SPI-A slave in, master out Reserved – Reserved TZ2 I Trip Zone input 2

GPIO17

SPISOMIA I/O SPI-A slave out, master in Reserved – Reserved TZ3 I Trip zone input 3

GPIO18

SPICLKA I/O SPI-A clock input/output SCITXDB O SCI-B transmit data XCLKOUT

GPIO19

XCLKIN

SPISTEA I/O SPI-A slave transmit enable input/output SCIRXDB I SCI-B receive data ECAP1 I/O Enhanced Capture input/output 1

GPIO20

EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data COMP1OUT O Direct output of Comparator 1

GPIO21

EQEP1B I Enhanced QEP1 input B MDRA I McBSP receive serial data COMP2OUT O Direct output of Comparator 2

PZP

44 35

95 75

96 76

88 70

55 44

52 42

51 41

64 52

6 5

7 6

PFP

I/O/Z DESCRIPTION

I/O/Z General-purpose input/output 12

I/O/Z General-purpose input/output 13

I/O/Z General-purpose input/output 14

I/O/Z General-purpose input/output 15

I/O/Z General-purpose input/output 16

I/O/Z General-purpose input/output 17

I/O/Z General-purpose input/output 18

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-

half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by

O/Z

bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4.

The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control

for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

I/O/Z General-purpose input/output 19

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken not to enable this path for clocking if it is

being used for the other peripheral functions.

I/O/Z General-purpose input/output 20

I/O/Z General-purpose input/output 21

(1)

(continued)

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

GPIO22

EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock SCITXDB O SCI-B transmit data

GPIO23

EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch SCIRXDB I SCI-B receive data

GPIO24

ECAP1 I/O Enhanced Capture input/output 1 EQEP2A

SPISIMOB I/O SPI-B slave in, master out

GPIO25

ECAP2 I/O Enhanced Capture input/output 2 EQEP2B I SPISOMIB I/O SPI-B slave out, master in

GPIO26

ECAP3 I/O Enhanced Capture input/output 3 EQEP2I I/O SPICLKB I/O SPI-B clock input/output USB0DP

GPIO27

HRCAP2 I High-Resolution Input Capture 2 EQEP2S I/O SPISTEB I/O SPI-B slave transmit enable input/output USB0DM

GPIO28

SCIRXDA I SCI-A receive data SDAA I/OD I2C data open-drain bidirectional port TZ2 I Trip zone input 2

GPIO29

SCITXDA O SCI-A transmit data SCLA I/OD I2C clock open-drain bidirectional port TZ3 I Trip zone input 3

GPIO30

CANRXA I CAN receive EQEP2I I/O EPWM7A O Enhanced PWM7 Output A and HRPWM channel

(3)

PZP

98 78

2 1

97 77

39 31

78 62

77 61

50 40

43 34

41 33

PFP

I/O/Z DESCRIPTION

I/O/Z General-purpose input/output 22

I/O/Z General-purpose input/output 23

I/O/Z General-purpose input/output 24

Enhanced QEP2 input A.

NOTE: eQEP2 is only available in the PZ and PZP packages.

I/O/Z General-purpose input/output 25

Enhanced QEP2 input B.

NOTE: eQEP2 is only available in the PZ and PZP packages.

I/O/Z General-purpose input/output 26

Enhanced QEP2 index.

NOTE: eQEP2 is only available in the PZ and PZP packages.

Positive Differential half of USB signal. To enable USB functionality on this pin, set the

I/O

USBIOEN bit in the GPACTRL2 register.

I/O/Z General-purpose input/output 27

Enhanced QEP2 strobe.

NOTE: eQEP2 is only available in the PZ and PZP packages.

Negative Differential half of USB signal. To enable USB functionality on this pin, set the

I/O

USBIOEN bit in the GPACTRL2 register.

I/O/Z General-purpose input/output 28

I/O/Z General-purpose input/output 29

I/O/Z General-purpose input/output 30

Enhanced QEP2 index.

NOTE: eQEP2 is only available in the PZ and PZP packages.

(1)

(continued)

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

GPIO31

CANTXA O CAN transmit EQEP2S I/O EPWM8A O Enhanced PWM8 Output A and HRPWM channel

GPIO32

SDAA I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A

GPIO33

SCLA I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B

GPIO34

COMP2OUT O Direct output of Comparator 2 COMP3OUT O Direct output of Comparator 3 GPIO35 TDI

GPIO36 TMS

GPIO37 TDO

GPIO38 XCLKIN

TCK I JTAG test clock with internal pullup GPIO39 66 53 I/O/Z General-purpose input/output 39

GPIO40

EPWM7A O Enhanced PWM7 output A and HRPWM channel SCITXDB O SCI-B transmit data

GPIO41

EPWM7B O Enhanced PWM7 output B SCIRXDB I SCI-B receive data

GPIO42

EPWM8A O Enhanced PWM8 output A and HRPWM channel TZ1 I Trip zone input 1 COMP1OUT O Direct output of Comparator 1

GPIO43

EPWM8B O Enhanced PWM8 output B TZ2 I Trip zone input 2 COMP2OUT O Direct output of Comparator 2

PZP

40 32

99 79

100 80

68 55

71 57

72 58

70 56

67 54

82 –

76 –

1 –

8 –

PFP

I/O/Z DESCRIPTION

I/O/Z General-purpose input/output 31

Enhanced QEP2 strobe.

NOTE: eQEP2 is only available in the PZ and PZP packages.

I/O/Z General-purpose input/output 32

I/O/Z General-purpose input/output 33

I/O/Z General-purpose input/output 34

I/O/Z General-purpose input/output 35

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

I/O/Z General-purpose input/output 36

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked

into the TAP controller on the rising edge of TCK.

I/O/Z General-purpose input/output 37

JTAG scan out, test data output (TDO). The contents of the selected register

O/Z

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).

I/O/Z General-purpose input/output 38

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken to not enable this path for clocking if it is

being used for the other functions.

I/O/Z General-purpose input/output 40

I/O/Z General-purpose input/output 41

I/O/Z General-purpose input/output 42

I/O/Z General-purpose input/output 43

(1)

(continued)

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Table 4-1. Signal Descriptions

PIN NO.

PIN NAME

GPIO44

MFSRA I/O McBSP receive frame synch SCIRXDB I SCI-B receive data EPWM7B O Enhanced PWM7 output B

GPIO50

EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data TZ1 I Trip zone input 1

GPIO51

EQEP1B I Enhanced QEP1 input B MDRA I McBSP receive serial data TZ2 I Trip zone input 2

GPIO52

EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock TZ3 I Trip zone input 3

GPIO53

EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch

GPIO54

SPISIMOA I/O SPI-A slave in, master out EQEP2A I Enhanced QEP2 input A HRCAP1 I High-Resolution Input Capture 1

GPIO55

SPISOMIA I/O SPI-A slave out, master in EQEP2B I Enhanced QEP2 input B HRCAP2 I High-Resolution Input Capture 2

GPIO56

SPICLKA I/O SPI-A clock input/output EQEP2I I/O Enhanced QEP2 index HRCAP3 I High-Resolution Input Capture 3

GPIO57

SPISTEA I/O SPI-A slave transmit enable input/output EQEP2S I/O Enhanced QEP2 strobe HRCAP4 I High-Resolution Input Capture 4

GPIO58

MCLKRA I/O McBSP receive clock SCITXDB O SCI-B transmit data EPWM7A O Enhanced PWM7 output A and HRPWM channel (1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown (2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the Systems Control and Interrupts chapter of the TMS320x2806x Piccolo Technical Reference Manual (SPRUH18).

(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more

information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Piccolo Technical Reference Manual (SPRUH18).

PZP

56 –

42 –

48 –

53 –

65 –

69 –

75 –

85 –

89 –

94 –

PFP

I/O/Z DESCRIPTION

I/O/Z General-purpose input/output 44

I/O/Z General-purpose input/output 50

I/O/Z General-purpose input/output 51

I/O/Z General-purpose input/output 52

I/O/Z General-purpose input/output 53

I/O/Z General-purpose input/output 54

I/O/Z General-purpose input/output 55

I/O/Z General-purpose input/output 56

I/O/Z General-purpose input/output 57

I/O/Z General-purpose input/output 58

(1)

(continued)

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5 Specifications

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

5.1 Absolute Maximum Ratings

(1)(2)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

(I/O and Flash) with respect to V

Supply voltage

Analog voltage V

Input voltage

Output voltage V

DDIO

VDDwith respect to V

with respect to V

DDA

VIN(3.3 V) –0.3 4.6 VIN(X1) –0.3 2.5

Input clamp current IIK(VIN< 0 or VIN> V Output clamp current IOK(VO< 0 or VO> V Junction temperature Storage temperature

(4)

stg

SSA

(3)

)

DDIO

) –20 20 mA

DDIO

–0.3 4.6 –0.3 2.5 –0.3 4.6 V

–0.3 4.6 V

–20 20 mA

–40 150 °C –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ±2 mA. (4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.

For additional information, see the IC Package Thermal Metrics Application Report (SPRA953).

5.2 ESD Ratings for TMS320F2806xU

VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(ESD)

Electrostatic discharge (ESD)

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1)

±2000

±500

5.3 ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 100-pin PZ and PZP packages

(ESD)

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 80-pin PN and PFP packages

(ESD)

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Electrostatic discharge

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Human body model (HBM), per AEC Q100-002

(1)

Charged device model (CDM), per AEC Q100-011

All pins ±2000

All pins ±500 Corner pins on 100-pin PZ and

PZP: 1, 25, 26, 50, 51, 75, 76, 100

Human body model (HBM), per AEC Q100-002

(1)

Charged device model (CDM), per AEC Q100-011

All pins ±2000

All pins ±500 Corner pins on 80-pin PN and

PFP: 1, 20, 21, 40, 41, 60, 61, 80

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VALUE UNIT

±750

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5.4 Recommended Operating Conditions

MIN NOM MAX UNIT

Device supply voltage, I/O, V

DDIO

Device supply voltage CPU, VDD(When internal VREG is disabled and 1.8 V is supplied externally)

Supply ground, V Analog supply voltage, V Analog ground, V

DDA

SSA

Device clock frequency (system clock) 2 90 MHz High-level input voltage, VIH(3.3 V) 2 V Low-level input voltage, VIL(3.3 V) VSS– 0.3 0.8 V High-level output source current, VOH= V

Low-level output sink current, VOL= V

Junction temperature, T

OL(MAX)

OH(MIN)

, I

All GPIO/AIO pins –4 Group 2

(1)

All GPIO/AIO pins 4 Group 2

(1)

T version –40 105 S version –40 125

Ambient temperature, T

Q version (Q100 qualification)

(2)

(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37. (2) The "Q" temperature option is not available on the 2806xU devices.

2.97 3.3 3.63 V

1.71 1.8 1.995

0 V

2.97 3.3 3.63 V 0 V

+ 0.3 V

DDIO

–8

–40 125

°C

5.5 Electrical Characteristics

(1)

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage

Low-level output voltage IOL= IOLMAX 0.4 V

Pin with pullup

Input current (low level)

enabled Pin with pulldown

enabled Pin with pullup

Input current (high level)

enabled Pin with pulldown

enabled

Output current, pullup or pulldown disabled

Input capacitance 2 pF V

BOR trip point Falling V

DDIO

BOR hysteresis 35 mV

DDIO

Supervisor reset release delay time

VREG VDDoutput Internal VREG on 1.9 V

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(VDD) go out of range.

IOH= IOHMAX 2.4 IOH= 50 μA V

= 3.3 V, VIN= 0 V

DDIO

= 3.3 V, VIN= 0 V ±2

DDIO

= 3.3 V, VIN= V

DDIO

= 3.3 V, VIN= V

DDIO

VO= V

DDIO

or 0 V ±2 μA

DDIO

All GPIO –80 –140 –205 XRS pin –230 –300 –375

Time after BOR/POR/OVR event is removed to XRS release

– 0.2

DDIO

28 50 80

2.50 2.78 2.96 V

400 800 μs

±2

μA

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5.6 Power Consumption Summary

Table 5-1. TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT

VREG ENABLED VREG DISABLED

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7, ePWM8

• eCAP1, eCAP2, eCAP3

• eQEP1, eQEP2

• eCAN

• CLA

• HRPWM

• SCI-A, SCI-B

Operational (Flash)

IDLE

STANDBY

HALT

(1) I (2) In order to realize the I

• SPI-A, SPI-B

• ADC

• I2C

• COMP1, COMP2, COMP3

• CPU-TIMER0, CPU-TIMER1, CPU-TIMER2

• McBSP

• USB

All PWM pins are toggled at 90 kHz. All I/O pins are left unconnected. Code is running out of flash with 3 wait-states. XCLKOUT is turned off.

Flash is powered down. XCLKOUT is turned off. All peripheral clocks are turned off.

Flash is powered down. Peripheral clocks are off.

Flash is powered down. Peripheral clocks are off. Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

(4) (5)

writing to the PCLKCR0 register.

185 mA

(7)

currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by

DDA

(1)

DDIO

(3)

TYP

22 mA 27 mA 15 µA 25 µA 5 µA 10 µA 21 mA 26 mA 120 µA 400 µA 15 µA 25 µA 5 µA 10 µA

9 mA 11 mA 15 µA 25 µA 5 µA 10 µA 8 mA 10 mA 120 µA 400 µA 15 µA 25 µA 5 µA 10 µA

75 µA 15 µA 25 µA 5 µA 10 µA 25 µA

MAX TYP

(6)

245 mA

(6)

(3) The TYP numbers are applicable over room temperature and nominal voltage. (4) The following is done in a loop:

• Data is continuously transmitted out of SPI-A, SPI-B, SCI-A, eCAN-A, McBSP-A, and I2C ports.

• The hardware multiplier is exercised.

• Watchdog is reset.

• ADC is performing continuous conversion.

• COMP1 and COMP2 are continuously switching voltages.

• GPIO17 is toggled. (5) CLA is continuously performing polynomial calculations. (6) For F2806x devices that do not have CLA, subtract the IDDcurrent number for CLA (see Table 5-2) from the IDD(VREG disabled)/I

(VREG enabled) current numbers shown in Table 5-1 for operational mode. (7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. (8) To realize the IDDnumber shown for HALT mode, the following must be done:

• PLL2 must be shut down by clearing bit 2 of the PLLCTL register.

• A value of 0x00FF must be written to address 0x6822.

(2)

DDA (3)

MAX TYP

16 mA 22 mA 35 mA 40 mA 165 mA

DD3VFL

(3)

MAX TYP

(3)

MAX TYP

(6)

(8)

220 mA

(6)

(1)

DDIO

(3)

MAX TYP

15 mA 20 mA 16 mA 22 mA 35 mA 40 mA

40 µA 15 µA 25 µA 5 µA 10 µA

DDA (3)

(2)

MAX TYP

DD3VFL

(3)

MAX

DDIO

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NOTE

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables.

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5.6.1 Reducing Current Consumption

The 2806x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 5-2 indicates the typical reduction in current consumption achieved by turning off the clocks.

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

Table 5-2. Typical Current Consumption by Various

Peripherals (at 90 MHz)

PERIPHERAL

MODULE

COMP/DAC 1

CPU-TIMER 1

Internal zero-pin oscillator 0.5

(1) All peripheral clocks (except CPU Timer clock) are disabled upon

reset. Writing to or reading from peripheral registers is possible only after the peripheral clocks are turned on.

(2) For peripherals with multiple instances, the current quoted is per

module. For example, the 2 mA value quoted for ePWM is for one ePWM module.

(3) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

) as well.

DDA

(2)

ADC 2

I2C 3

ePWM 2

eCAP 2 eQEP 2

SCI 2

SPI 2

HRPWM 3

HRCAP 3

USB 12

CAN 2.5

CLA 20

McBSP 6

(1)

IDDCURRENT

REDUCTION (mA)

(3)

current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

DDIO

The baseline IDDcurrent (current when the core is executing a dummy loop with no peripherals enabled) is 40 mA, typical. To arrive at the IDDcurrent for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDDcurrent.

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100

200

300

400

500

600

700

800

900

10 20 30 40 50 60 70 80 90

Operational Power (mW)

SYSCLKOUT (MHz)

Operational Power vs Frequency (Internal VREG)

100

150

200

250

10 20 30 40 50 60 70 80 90

Operational Current (mA)

SYSCLKOUT (MHz)

Operational Current (Flash) vs Frequency (Internal VREG)

IDDIO

IDDA

IDD3VFL

Total

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

Following are other methods to reduce power consumption further:

• The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18 mA (typical) in the VDDrail and 13 mA (typical) in the V

• Savings in I

may be realized by disabling the pullups on pins that assume an output function.

DDIO

5.6.2 Current Consumption Graphs (VREG Enabled)

DDIO

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rail.

Figure 5-1. Typical Operational Current Versus Frequency

Figure 5-2. Typical Operational Power Versus Frequency

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SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

5.7 Thermal Resistance Characteristics

5.7.1 PFP PowerPAD Package

(1)

°C/W

RΘ RΘ

JC JB

Junction-to-case thermal resistance 9.4 0 Junction-to-board thermal resistance 4.6 0

25.8 0

RΘ

(High k PCB)

Junction-to-free air thermal resistance

16.3 150

15.2 250

13.6 500

0.3 0

Psi

Junction-to-package top

0.4 150

0.4 250

0.5 500

4.6 0

Psi

Junction-to-board

4.4 150

4.3 250

4.3 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

AIR FLOW (lfm)

(2)

5.7.2 PZP PowerPAD Package

(1)

°C/W

RΘ RΘ

JC JB

Junction-to-case thermal resistance 9.4 0 Junction-to-board thermal resistance 4.4 0

24.4 0

RΘ

(High k PCB)

Junction-to-free air thermal resistance

15.1 150

13.9 250

12.4 500

0.3 0

Psi

Junction-to-package top

0.4 150

0.4 250

0.5 500

4.5 0

Psi

Junction-to-board

4.2 150

4.2 250

4.2 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

AIR FLOW (lfm)

(2)

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5.7.3 PN Package

(1)

°C/W

RΘ RΘ

JC JB

Junction-to-case thermal resistance 7.9 0 Junction-to-board thermal resistance 15.6 0

41.1 0

RΘ

(High k PCB)

Junction-to-free air thermal resistance

31.2 150

29.7 250

27.5 500

0.4 0

Psi

Junction-to-package top

0.6 150

0.7 250

0.9 500

15.3 0

Psi

Junction-to-board

14.6 150

14.4 250

14.1 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

AIR FLOW (lfm)

(2)

5.7.4 PZ Package

(1)

°C/W

RΘ RΘ

JC JB

Junction-to-case thermal resistance 7.2 0 Junction-to-board thermal resistance 19.6 0

42.2 0

RΘ

(High k PCB)

Junction-to-free air thermal resistance

32.4 150

30.9 250

28.7 500

0.4 0

Psi

Junction-to-package top

0.6 150

0.7 250

0.9 500

19.1 0

Psi

Junction-to-board

18.2 150

17.9 250

14.1 500

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

AIR FLOW (lfm)

(2)

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TRST

TMS

TDI

TDO

TCK

DDIO

MCU

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

TCK_RET

6 inches or less

GND

JTAG Header

DDIO

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5.8 Thermal Design Considerations

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

Based on the end application design and operational profile, the IDDand I Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJwithin the specified limits. T measured to estimate the operating junction temperature TJ. T

is normally measured at the center of

case

the package top-side surface. The thermal application report IC Package Thermal Metrics (SPRA953) helps to understand the thermal metrics and definitions.

5.9 Emulator Connection Without Signal Buffering for the MCU

Figure 5-3 shows the connection between the MCU and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-3 shows the simpler, no-buffering situation. For the pullup and pulldown resistor values, see Section 4.2.

currents could vary.

DDIO

case

should be

A. See Figure 6-54 for JTAG/GPIO multiplexing.

Figure 5-3. Emulator Connection Without Signal Buffering for the MCU

The 2806x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard, the EMU0/EMU1 pins on the header must be tied to V (typical) resistor.

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NOTE

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through a 4.7-kΩ

DDIO

Transmission Line

4.0 pF 1.85 pF

Z0 = 50

(A)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output Under Test

3.5 nH

Device Pin

(B)

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

5.10 Parameter Information

5.10.1 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

LOWERCASE SUBSCRIPTS AND THEIR MEANINGS: LETTERS AND SYMBOLS AND THEIR MEANINGS:

a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width)

5.10.2 General Notes on Timing Parameters

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All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

5.11 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 5-4. 3.3-V Test Load Circuit

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w(RSL1)

h(boot-mode)

(C)

V V

(3.3 V)

DDIO DDA

INTOSC1

X1/X2

XRS

(D)

Boot-Mode

Pins

V (1.8 V)

XCLKOUT

User-code dependent

Boot-ROM execution starts

Peripheral/GPIO function Based on boot code

GPIO pins as input

OSCST

Address/Data/

Control

(Internal)

Address/data valid, internal boot-ROM code execution phase

User-code execution phase

d(EX)

INTOSCST

(A)

(B)

I/O Pins

GPIO pins as input [state depends on internal pullup/pulldown (PU/PD)]

User-code dependent

(E)

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5.12 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO26–27, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above V any digital pin before powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

should be applied to

DDIO

A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset

state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.

B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that

XCLKOUT will not be visible at the pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT

will be based on user environment and could be with or without PLL enabled. D. Using the XRS pin is optional due to the on-chip POR circuitry. E. The internal pullup or pulldown will take effect when BOR is driven high.

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Figure 5-5. Power-on Reset

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h(boot-mode)

(A)

w(RSL2)

INTOSC1

X1/X2

XRS

Boot-Mode

Pins

XCLKOUT

I/O Pins

Address/Data/

Control

(Internal)

Boot-ROM Execution Starts

User-Code Execution Starts

User-Code Dependent

User-Code Execution Phase

User-Code Dependent

User-Code Execution

Peripheral/GPIO Function

User-Code Dependent

GPIO Pins as Input (State Depends on Internal PU/PD)

GPIO Pins as Input

Peripheral/GPIO Function

d(EX)

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SPRS698F –NOVEMBER 2010–REVISED MARCH 2016

Table 5-3. Reset (XRS) Timing Requirements

h(boot-mode)

w(RSL2)

Hold time for boot-mode pins 1000t Pulse duration, XRS low on warm reset 32t

Table 5-4. Reset (XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

w(RSL1)

w(WDRS)

d(EX)

INTOSCST

(1)

OSCST

(1) Dependent on crystal/resonator and board design.

Pulse duration, XRS driven by device 600 μs Pulse duration, reset pulse generated by watchdog 512t Delay time, address/data valid after XRS high 32t Start up time, internal zero-pin oscillator 3 μs On-chip crystal-oscillator start-up time 1 10 ms

c(OSCCLK)

c(OSCCLK) c(OSCCLK)

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MIN MAX UNIT

c(SCO)

cycles cycles

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in

debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The

SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

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Figure 5-6. Warm Reset

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