Texas instruments TMS320F28062, TMS320F28068, TMS320F28067, TMS320F28069, TMS320F28064 ADVANCE INFORMATION

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ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

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SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Piccolo Microcontrollers

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Samples: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063,

1 TMS320F2806x ( Piccolo™) MCUs

1.1 Features

123

• High-Efficiency 32-Bit CPU (TMS320C28x™) • Peripheral Interrupt Expansion (PIE) Block That – 80 MHz (12.5-ns Cycle Time) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly)

• Floating-Point Unit – Native Single-Precision Floating-Point

Operations

• Programmable Control Law Accelerator (CLA) – 32-Bit Floating-Point Math Accelerator – Executes Code Independently of the Main

CPU

• Viterbi, Complex Math, CRC Unit (VCU) – Extends C28x™ Instruction Set to Support

Complex Multiply, Viterbi Operations, and – Prevents Firmware Reverse Engineering Cyclic Redundency Check (CRC)

• Embedded Memory – Up to 256KB Flash (SCI) [UART] Modules – Up to 100KB RAM – Two Serial Peripheral Interface (SPI) – 2KB OTP ROM

• 6-Channel DMA

• Low Device and System Cost – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out

Reset – Low-Power Operating Modes – No Analog Support Pin

• Clocking – Two Internal Zero-pin Oscillators – On-Chip Crystal Oscillator/External Clock

Input – Dynamic PLL Ratio Changes Supported – Watchdog Timer Module – Missing Clock Detection Circuitry

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Piccolo, PowerPAD, C28x, TMS320C2000, C2000, Code Composer Studio, XDS510, XDS560, TMS320C28x, TMS320C54x, TMS320C55x

are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phaseof development. Characteristic dataand other specifications are subjectto change without notice.

TMS320F28062

Supports All Peripheral Interrupts

• Three 32-Bit CPU Timers

• Advanced Control Peripherals

• Up to 8 Enhanced Pulse Width Modulator (ePWM) Modules

– 16 PWM Channels Total (8 HRPWM-Capable) – Independent 16-Bit Timer in Each Module

• 3 Input Capture (eCAP) Modules

• 4 High-Resolution Input Capture (HRCAP) Modules

• 2 Quadrature Encoder (eQEP) Modules

• 12-Bit ADC, Dual Sample-and-Hold – Up to 3 MSPS – Up to 16 Channels

• On-Chip Temperature Sensor

• 128-Bit Security Key/Lock – Protects Secure Memory Blocks

• Serial Port Peripherals – Up to Two Serial Communications Interface

Modules – One Inter-Integrated-Circuit (I2C) Bus – One Multi-Channel Buffered Serial Port

(McBSP) Bus – One Enhanced Controller Area Network

(eCAN)

• Up to 54 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

• Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware

• 2806x Packages – 80-Pin PFP and 100-Pin PZP PowerPAD™

Low-Profile Quad Flatpacks (LQFPs)

– 80-Pin PN and 100-Pin PZ LQFPs

ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

1.2 Description

The F2806x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric V ADC interface has been optimized for low overhead/latency.

REFHI/VREFLO

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CLA Bus

GPIO Mux

DMA Bus

16-bit Peripheral Bus

32-bit Peripheral Bus

(CLA accessible)

32-bit Peripheral

Bus

32-bit Peripheral

Bus

32-bit

Peripheral Bus

(CLA accessible)

SCITXDx

SCIRXDx

SPISIMOx

SPISOMIx

SPICLKx

SPISTEx

SDAx

SCLx

TZx

EPWMxA

EPWMxB

ESYNCI

ESYNCO

MFSRA

MDRA

MCLKRA

MFSXA

MDXA

MCLKXA

ECAPx

EQEPxA

EQEPxB

EQEPxI

EQEPxS

HRCAPx

CANRXx

CANTXx

SCI-A/B

(4L FIFO)

SPI-A/B

(4L FIFO)

I2C-A

(4L FIFO)

ePWM1 to ePWM8

HRPWM (8ch)

McBSP-A

eCAP-

1/2/3

eQEP-

1/2

HRCAP-

1/2/3/4

eCAN-A

(32-mbox)

Memory Bus

A7:0

B7:0

Memory Bus

DMA Bus

CLA Bus

DMA Bus

GPIO Mux

AIO Mux

32-bit Peripheral Bus

GPIO

Mux

GPIO

Mux

ADC

0-wait

Result

Regs

ADC

COMP

DAC

COMP1OUT

COMP2OUT

COMP3OUT

COMP1A

COMP2A

COMP3A

COMP1B

COMP2B

COMP3B

Boot-ROM

(32Kx16)

(0-wait,

Non-Secure)

CLA +

Message

RAMs

DMA 6-ch

C28x 32-bit CPU

FPU VCU

OSC1, OSC2,

Ext, PLLs,

LPM, WD,

CPU Timers

0/1/2. PIE

TRST

TCK, TDI, TMS

TDO

XCLKIN

LPM Wakeup

3 Ext. Interrupts

X1 X2

XRS

PSWD

M0 SARAM (1Kx16)

(0-wait, Non-Secure)

M1 SARAM (1Kx16)

(0-wait, Non-Secure)

L5 DPSARAM (8Kx16)

(0-wait, Non-Secure)

DMA RAM0

L6 DPSARAM (8Kx16)

(0-wait, Non-Secure)

DMA RAM1

L7 DPSARAM (8Kx16)

(0-wait, Non-Secure)

DMA RAM2

L8 DPSARAM (8Kx16)

(0-wait, Non-Secure)

DMA RAM3

L0 DPSARAM (2Kx16)

(0-wait, Secure) CLA Data RAM2

L1 DPSARAM (1Kx16)

(0-wait, Secure) CLA Data RAM0

L2 DPSARAM (1Kx16)

(0-wait, Secure) CLA Data RAM1

L3 DPSARAM (4Kx16)

(0-wait, Secure)

CLA Program RAM

L4 SARAM (8Kx16)

(0-wait, Secure)

Code

Security

Module

(CSM)

OTP 1Kx16

Secure

FLASH

64K/128Kx16

8 equal sectors

Secure

PUMP

OTP/Flash

Wrapper

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1.3 Functional Block Diagram

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

A. Not all peripheral pins are available at the same time due to multiplexing.

Figure 1-1. Functional Block Diagram

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TMS320F28064 TMS320F28063 TMS320F28062

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10-bit

DAC

Analog

Comparators

CMP1-Out

CMP2-Out

CMP3-Out

Trip Zone

Temp

Sensor

ADC

(DMA-

accessible)

12-bit

3-MSPS

Dual-S/H

SOC-

based

REF

CLA Core

80-MHz Floating-Point

(Accelerator)

(DMA-accessible)

10-bit

DAC

10-bit

DAC

A2 A3 A4 A5 A6 A7

B1 B2 B3 B4 B5 B6 B7

eQEP x 2

HRCAP x 4

eCAP x 3

System

Vreg

Int-Osc-1

POR/BOR

Int-Osc-2

On-chip Osc

PLL

CLKSEL

Timers 32-bit

Timer-0

Timer-1

Timer-2

GPIO

Control

COMMS

X1 X2

REFLO

REFHI

C28x Core

(80-MHz)

FPU

VCU

Flash Memory

RAM

(Dual-Access)

eQEP

HRCAP

eCAP

PWM-1A PWM-1B

PWM-2A PWM-2B

PWM-3A PWM-3B

PWM-4A PWM-4B

PWM-5A PWM-5B

PWM-6A PWM-6B

PWM-7A PWM-7B

PWM-8A PWM-8B

TZ1 TZ2 TZ3

CMP1-out CMP2-out CMP3-out

PWM1

(DMA-accessible)

PWM5

(DMA-accessible)

PWM8

(DMA-accessible)

PWM7

(DMA-accessible)

PWM6

(DMA-accessible)

PWM4

(DMA-accessible)

PWM3

(DMA-accessible)

PWM2

(DMA-accessible)

UART x 2

SPI x 2

I2C

CAN

McBSP

(DMA-accessible)

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

1.4 System Device Diagram

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TMS320F28064 TMS320F28063 TMS320F28062

Figure 1-2. Peripheral Blocks

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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

1 TMS320F2806x ( Piccolo™) MCUs .................. 1

1.1 Features .............................................. 1

1.2 Description ........................................... 2

1.3 Functional Block Diagram ............................ 3

1.4 System Device Diagram ............................. 4 6.6 Current Consumption ............................... 67

2 Revision History ......................................... 6

3 Device Overview ........................................ 7

3.1 Device Characteristics ............................... 7

3.2 Memory Maps ...................................... 10

3.3 Pin Assignments .................................... 20

3.4 Signal Descriptions ................................. 22

3.5 Brief Descriptions ................................... 31

3.6 Register Map ....................................... 40

3.7 Device Emulation Registers ........................ 42

3.8 VREG/BOR/POR ................................... 43

3.9 System Control ..................................... 45

3.10 Low-power Modes Block ........................... 53

4 Device and Documentation Support ............... 54

4.1 Getting Started ..................................... 54

4.2 Development Support .............................. 54

4.3 Device and Development Support Tool

Nomenclature ....................................... 54

4.4 Documentation Support ............................ 56

4.5 Community Resources ............................. 57

5 Device Operating Conditions ....................... 58

5.1 Absolute Maximum Ratings ........................ 58

5.2 Recommended Operating Conditions .............. 58

5.3 Electrical Characteristics ........................... 59

6 Peripheral and Electrical Specifications .......... 60

6.1 Parameter Information .............................. 60

6.2 Test Load Circuit ................................... 60

6.3 Device Clock Table ................................. 61

6.4 Clock Requirements and Characteristics ........... 63

6.5 Power Sequencing ................................. 64

6.7 Emulator Connection Without Signal Buffering for

the MCU ............................................ 69

6.8 Interrupts ............................................ 70

6.9 Control Law Accelerator (CLA) Overview .......... 75

6.10 Analog Block ........................................ 78

6.11 Detailed Descriptions ............................... 92

6.12 Serial Peripheral Interface (SPI) Module ........... 93

6.13 Serial Communications Interface (SCI) Module

..................................................... 102

6.14 Multichannel Buffered Serial Port (McBSP) Module

..................................................... 105

6.15 Enhanced Controller Area Network (eCAN) Module

..................................................... 115

6.16 Inter-Integrated Circuit (I2C) ...................... 119

6.17 Enhanced Pulse Width Modulator (ePWM) Modules

(ePWM1/2/3/4/5/6/7/8) ............................ 122

6.18 High-Resolution PWM (HRPWM) ................. 129

6.19 Enhanced Capture Module (eCAP1) .............. 130

6.20 High-Resolution Capture (HRCAP) Module ....... 132

6.21 Enhanced Quadrature Encoder Modules (eQEP1/2)

..................................................... 133

6.22 JTAG Port ......................................... 136

6.23 General-Purpose Input/Output (GPIO) MUX ...... 137

6.24 Flash Timing ....................................... 149

7 Mechanical Packaging and Orderable

Information ............................................ 151

7.1 Thermal Data ...................................... 151

7.2 Packaging Information ............................ 152

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TMS320F28064 TMS320F28063 TMS320F28062

ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

2 Revision History

This data sheet revision history highlights the technical changes made to the SPRS698 device-specific data sheet to make it an SPRS698A revision.

Scope: Added 80-pin PN package and 100-pin PZ package.

Added "T" temperature range (–40°C to 105°C). Added new sections.

Information/data on the TMS320F2806x devices is now Advance Information.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS

Global

Section 1

TMS320F2806x (Piccolo™) MCUs

Section 3

Device Overview

Section 4

Device and Documentation Support

Section 7

Mechanical Packaging and Orderable Information

• Added 80-pin PN package

• Added 100-pin PZ package

• Added "T" temperature range (–40°C to 105°C)

• Added Section 1.2, Description

• Figure 1-1, Functional Block Diagram: – Removed "32-bit Peripheral Bus"

• Table 3-1, Hardware Features: – 6-Channel DMA: Added "0" to TYPE column – High-resolution capture modules (HRCAP): Added "0" to TYPE column – Multi-Channel Buffered Serial Port (McBSP): Added "1" to TYPE column – Updated "Temperature options"

• Added Section 3.2, Memory Maps

• Figure 3-8, 80-Pin PN/PFP LQFP (Top View): – Removed SCI-B signals and eQEP2 signals

• Table 3-6, Terminal Functions: – Added "SCI-B is only available in the PZ and PZP packages" note to DESCRIPTION of PN/PFP pins# 39,

59, 76, 70, 41, 52, 78, 1

– Added "eQEP2 is only available in the PZ and PZP packages" note to DESCRIPTION of PN/PFP

pins# 77, 31, 62, 61, 33, 32

• Added Section 3.5, Brief Descriptions

• Added Section 3.6, Register Map

• Added Section 3.7, Device Emulation Registers

• Added Section 3.8, VREG/BOR/POR

• Added Section 3.9, System Control

• Added Section 3.10, Low-power Modes Block

• Added Section 4.1, Getting Started

• Section 4.3, Device and Development Support Tool Nomenclature: – Updated PACKAGE TYPE in Figure 4-1, Device Nomenclature

• Added Section 4.4, Documentation Support

Added Section 6, Peripheral and Electrical Specifications

• Added Section 7.1, Thermal Data

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3 Device Overview

3.1 Device Characteristics

Table 3-1 lists the features of the TMS320F2806x devices.

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

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ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Table 3-1. Hardware Features

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FEATURE TYPE

Package Type PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP

Instruction cycle – 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes Viterbi, Complex Math,CRC Unit (VCU) Yes Yes No No Yes Yes No No Control Law Accelerator(CLA) 0 Yes No No No Yes No No No 6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes On-chip Flash (16-bitword) – 128K 128K 128K 128K 64K 64K 64K 64K On-chip SARAM (16-bitword) – 50K 50K 50K 34K 50K 50K 34K 26K Code security foron-chip

flash/SARAM/OTP blocks Boot ROM (32Kx 16) – Yes Yes Yes Yes Yes Yes Yes Yes One-time programmable (OTP)ROM

(16-bit word) ePWM outputs 1 19 15 19 15 19 15 19 15 19 15 19 15 19 15 19 15 High-resolution ePWM Channels 1 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 6 eCAP inputs 0 3 3 3 3 3 3 3 3 High-resolution capture modules

(HRCAP) eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes

MSPS 3 3 3 3 3 3 3 3 Conversion Time 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns

12-Bit ADC Channels 3 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12

Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes

Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes 32-Bit CPU timers – 3 3 3 3 3 3 3 3 Comparators with IntegratedDACs 0 3 3 3 3 3 3 3 3 Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1 1 Multi-Channel Buffered SerialPort

(McBSP) Enhanced Controller AreaNetwork

(eCAN) Serial Peripheral Interface(SPI) 1 2 2 2 2 2 2 2 2 Serial Communications Interface(SCI) 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

(1)

– Yes Yes Yes Yes Yes Yes Yes Yes

– 1K 1K 1K 1K 1K 1K 1K 1K

0 4 4 4 4 4 4 4 4

1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1

28069 28068 28067 28066 28065 28064 28063 28062

(80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz)

100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin

LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the

basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.

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ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

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Table 3-1. Hardware Features (continued)

FEATURE TYPE

Package Type PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP

2-pin Oscillator 1 1 1 1 1 1 1 1 0-pin Oscillator 2 2 2 2 2 2 2 2

I/O pins (shared)

External interrupts – 3 3 3 3 3 3 3 3 Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

Temperature options

Product status

GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40

AIO – 6 6 6 6 6 6 6 6

T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN

S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP

Q: –40°C to 125°C

(2)

(1)

– PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP – TMX TMX TMX TMX TMX TMX TMX TMX

(1) "Q" refers to Q100 qualification for automotive applications. (2) See Section 4.3, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMX" product status denotes an experimental device that is not necessarily

representative of the final device's electrical specifications.

28069 28068 28067 28066 28065 28064 28063 28062

(80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz) (80 MHz)

100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin

LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

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ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

3.2 Memory Maps

In Figure 3-1 through Figure 3-7, the following apply:

• Memory blocks are not to scale.

• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.

• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.

• Certain memory ranges are EALLOW protected against spurious writes after configuration.

• Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These locations are not programmable by the user.

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M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

0x00 2000

Reserved

Peripheral Frame 0

0x00 0800

0x00 1580

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

0x00 1400

0x00 0E00

0x00 1500

0x00 1480

CPU-to-CLA Message RAM

CLA-to-CPU Message RAM

CLA Registers

Peripheral Frame 0

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x00 5000

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM2)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, CLA Program RAM)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L8 DPSARAM (8K x 16)

(0-Wait, DMA RAM 3)

L7 DPSARAM (8K x 16)

(0-Wait, DMA RAM 2)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

0x01 0000

0x01 2000

Peripheral Frame 1 (4K x 16, Protected)

0x00 6000

Reserved

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x01 4000

Reserved

0x3D 7BFA

Reserved

FLASH

(128K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3D 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

Reserved

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-1. 28069 Memory Map

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TMS320F28064 TMS320F28063 TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

Peripheral Frame 0

0x00 0800

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

0x00 0E00

Peripheral Frame 0

0x00 1400

Reserved

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L8 DPSARAM (8K x 16)

(0-Wait, DMA RAM 3)

L7 DPSARAM (8K x 16)

(0-Wait, DMA RAM 2)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

0x01 0000

0x01 2000

Peripheral Frame 1 (4K x 16, Protected)

0x00 6000

Reserved

0x01 4000

Reserved

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x00 5000

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(128K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3D 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-2. 28068/28067 Memory Map

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ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

Peripheral Frame 0

0x00 0800

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

0x00 0E00

Peripheral Frame 0

0x00 1400

Reserved

Peripheral Frame 1 (4K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 6000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

Reserved

0x01 0000

Reserved

0x00 5000

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(128K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3D 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-3. 28066 Memory Map

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SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

0x00 2000

Reserved

Peripheral Frame 0

0x00 0800

0x00 1580

0x00 0D00

PIE Vector - RAM

(256 x 16) (Enabled if VMAP = 1, ENPIE = 1)

0x00 1400

0x00 0E00

0x00 1500

0x00 1480

CPU-to-CLA Message RAM

CLA-to-CPU Message RAM

CLA Registers

Peripheral Frame 0

Peripheral Frame 1 (4K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 6000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM2)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL, CLA Program RAM)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L8 DPSARAM (8K x 16)

(0-Wait, DMA RAM 3)

L7 DPSARAM (8K x 16)

(0-Wait, DMA RAM 2)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

0x01 0000

0x01 2000

Reserved

0x01 4000

Reserved

0x00 5000

Peripheral Frame 3

(4K x 16, Protected)

DMA-Accessible

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(64K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3E 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-4. 28065 Memory Map

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TMS320F28064 TMS320F28063 TMS320F28062

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ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

Peripheral Frame 0

0x00 0800

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

0x00 0E00

Peripheral Frame 0

0x00 1400

Reserved

Peripheral Frame 1 (4K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 6000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L8 DPSARAM (8K x 16)

(0-Wait, DMA RAM 3)

L7 DPSARAM (8K x 16)

(0-Wait, DMA RAM 2)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

0x01 0000

0x01 2000

Reserved

0x01 4000

Reserved

0x00 5000

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(64K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3E 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-5. 28064 Memory Map

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SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

Peripheral Frame 0

0x00 0800

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

0x00 0E00

Peripheral Frame 0

0x00 1400

Reserved

Peripheral Frame 1 (4K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 6000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K x 16)

(0-Wait, DMA RAM 1)

0x00 E000

Reserved

0x01 0000

Reserved

0x00 5000

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(64K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3E 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-6. 28063 Memory Map

Submit Documentation Feedback

TMS320F28064 TMS320F28063 TMS320F28062

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ADVANCEINFORMATION

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0000

0x00 0040

M1 SARAM (1K x 16, 0-Wait)

0x00 0400

Data Space Prog Space

Reserved

Peripheral Frame 0

0x00 0800

0x00 0D00

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1, ENPIE = 1)

0x00 0E00

Peripheral Frame 0

0x00 1400

Reserved

Peripheral Frame 1 (4K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

0x00 7000

0x00 6000

0x00 8000

L0 DPSARAM (2K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

L1 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 8C00

L2 DPSARAM (1K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 9000

L3 DPSARAM (4K x 16)

(0-Wait, Secure Zone + ECSL)

0x00 A000

L4 SARAM (8K x 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 C000

L5 DPSARAM (8K x 16)

(0-Wait, DMA RAM 0)

Reserved

0x00 E000

Reserved

0x00 5000

Peripheral Frame 3 (4K x 16, Protected)

DMA-Accessible

0x3D 7800

User OTP (1K x 16, Secure Zone + ECSL)

0x3D 7C80

Calibration Data

0x3D 7BFA

Reserved

FLASH

(64K x 16, 8 Sectors, Secure Zone + ECSL)

128-Bit Password

0x3E 8000

0x3F 7FF8

Boot ROM (32K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

0x3F 8000

0x3F FFC0

0x3D 7CC0

Get_mode function

0x3D 7CD0

Reserved

0x3D 7E80

PARTID

Calibration Data

Reserved

0x3D 7EB0

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

Figure 3-7. 28062 Memory Map

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TMS320F28064 TMS320F28063 TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Table 3-2. Addresses of Flash Sectors in F28069/28068/28067/28066

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3D 8000 – 0x3D BFFF Sector H (16K x 16) 0x3D C000 – 0x3D FFFF Sector G (16K x 16)

0x3E 0000 – 0x3E 3FFF Sector F (16K x 16)

0x3E 4000 – 0x3E 7FFF Sector E (16K x 16) 0x3E 8000 – 0x3E BFFF Sector D (16K x 16) 0x3E C000 – 0x3E FFFF Sector C (16K x 16)

0x3F 0000 – 0x3F 3FFF Sector B (16K x 16)

0x3F 4000 – 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Table 3-3. Addresses of Flash Sectors in F28065/28064/28063/28062

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

www.ti.com

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3E 8000 – 0x3E 9FFF Sector H (8K x 16) 0x3E A000 – 0x3E BFFF Sector G (8K x 16) 0x3E C000 – 0x3E DFFF Sector F (8K x 16) 0x3E E000 – 0x3E FFFF Sector E (8K x 16)

0x3F 0000 – 0x3F 1FFF Sector D (8K x 16)

0x3F 2000 – 0x3F 3FFF Sector C (8K x 16)

0x3F 4000 – 0x3F 5FFF Sector B (8K x 16)

0x3F 6000 – 0x3F 7F7F Sector A (8K x 16)

0x3F 7F80 – 0x3F 7FF5

0x3F 7FF6 – 0x3F 7FF7

0x3F 7FF8 – 0x3F 7FFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

NOTE

• When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000.

• If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program code.

Table 3-4 shows how to handle these memory locations.

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TMS320F28064 TMS320F28063 TMS320F28062

ADVANCEINFORMATION

www.ti.com

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Table 3-4. Impact of Using the Code Security Module

ADDRESS

0x3F 7F80 – 0x3F 7FEF Application code and data 0x3F 7FF0 – 0x3F 7FF5 Reserved for data only

CODE SECURITY ENABLED CODE SECURITY DISABLED

Fill with 0x0000

FLASH

Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 3-5.

Table 3-5. Wait-States

AREA WAIT-STATES (CPU) COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.

2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur

Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.

2-wait (reads)

Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA/DMA cycles. The wait

2-wait (reads) L0 SARAM 0-wait data and program Assumes no CPU conflicts L1 SARAM 0-wait data and program Assumes no CPU conflicts L2 SARAM 0-wait data and program Assumes no CPU conflicts L3 SARAM 0-wait data and program Assumes no CPU conflicts

OTP Programmable Programmed via the Flash registers.

1-wait minimum 1-wait is minimum number of wait states allowed.

FLASH Programmable Programmed via the Flash registers.

0-wait Paged min

1-wait Random min

Random ≥ Paged

FLASH Password 16-wait fixed Wait states of password locations are fixed.

Boot-ROM 0-wait

a 1-cycle stall (1-cycle delay).

states can be extended by peripherals generated ready.

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TMS320F28064 TMS320F28063 TMS320F28062

ADVANCEINFORMATION

101112

GPIO23/EQEP1I/MFSXA

DDIO

GPIO20/EQEP1A/MDXA/COMP1OUT

GPIO21/EQEP1B/MDRA/COMP2OUT

GPIO4/EPWM3A

GPIO5/EPWM3B/SPISIMOA/ECAP1

XRS

TRST

DDIO

ADCINA6/COMP3A/AIO6

ADCINA5

ADCINA4/COMP2A/AIO4

ADCINA2/COMP1A/AIO2

ADCINA1

ADCINA0, V

REFHI

DDA

GPIO10/EPWM6A/ADCSOCBO

GPIO11/EPWM6B/ECAP1

GPIO36/TMS

GPIO35/TDI

GPIO37/TDO

GPIO34/COMP2OUT/COMP3OUT

GPIO38/XCLKIN/TCK

GPIO39

GPIO19/XCLKIN/ /ECAP1SPISTEA

VDDVSSV

DDIO

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO7/EPWM4B/SCIRXDA/ECAP2

GPIO16/SPISIMOA/TZ2

GPIO8/EPWM5A/ADCSOCAO

GPIO17/SPISOMIA/TZ3

GPIO18/SPICLKA/XCLKOUT

GPIO26/ECAP3/SPICLKB

GPIO27/HRCAP2/SPISTEB

DDIO

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO2/EPWM2A

GPIO1/EPWM1B/COMP1OUT

GPIO0/EPWM1A

GPIO15/ECAP2/SPISTEB

VREGENZ

DDIO

GPIO13/ /SPISOMIBTZ2

GPIO14/ /SPICLKBTZ3

GPIO24/ECAP1/SPISIMOB

GPIO22/EQEP1S/MCLKXA

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO29/SCITXDA/SCLA/TZ3

GPIO12/ /SCITXDA/SPISIMOBTZ1

TEST2

DD3VFL

GPIO9/EPWM5B/ECAP3

GPIO28/SCIRXDA/SDAA/TZ2

GPIO30/CANRXA/EPWM7A

GPIO31/CANTXA/EPWM8A

GPIO25/ECAP2/SPISOMIB

DDIO

ADCINB6/COMP3B/AIO14

ADCINB5

ADCINB4/COMP2B/AIO12

ADCINB2/COMP1B/AIO10

ADCINB1

ADCINB0 V , V

REFLO SSA

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

3.3 Pin Assignments

Figure 3-8 shows the 80-pin PN/PFP Low-Profile Quad Flatpack (LQFP) pin assignments. Figure 3-9

shows the 100-pin PZ/PZP Low-Profile Quad Flatpack (LQFP) pin assignments.

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A. Pin 19: V

one another. Pin 21: V

and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to

REFHI

is always connected to V

REFLO

Figure 3-8. 80-Pin PN/PFP LQFP (Top View)

SSA

on the 80-pin PN/PFP device.

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100

DDIO

REFHI

DDIO

DD3VFL

SSA

TEST2

ADCINB7

ADCINB3

VREGENZ

REFLO

ADCINB6/COMP3B/AIO14

ADCINB5

ADCINB4/COMP2B/AIO12

ADCINB2/COMP1B/AIO10

ADCINB1

ADCINB0

GPIO0/EPWM1A

GPIO1/EPWM1B/COMP1OUT

GPIO2/EPWM2A

GPIO56/SPICLKA/EQEP2I/HRCAP3

GPIO57/ /EQEP2S/HRCAP4SPISTEA

GPIO58/MCLKRA/SCITXDB/EPWM7A

GPIO40/EPWM7A/SCITXDB

GPIO41/EPWM7B/SCIRXDB

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO44/MFSRA/SCIRXDB/EPWM7B

GPIO7/EPWM4B/SCIRXDA/ECAP2

GPIO8/EPWM5A/ADCSOCAO

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO10/EPWM6A/ADCSOCBO

GPIO11/EPWM6B/SCIRXDB/ECAP1

GPIO12/ /SCITXDA/SPISIMOBTZ1

GPIO13/ /SPISOMIBTZ2

GPIO14/ /SCITXDB/SPICLKBTZ3

GPIO15/ECAP2/SCIRXDB/SPISTEB

GPIO16/SPISIMOA/TZ2

GPIO17/SPISOMIA/TZ3

GPIO42/EPWM8A/ /COMP1OUTTZ1

GPIO43/EPWM8B/ /COMP2OUTTZ2

GPIO18/SPICLKA/SCITXDB/XCLKOUT

GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA

GPIO22/EQEP1S/MCLKXA/SCITXDB

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO25/ECAP2/EQEP2B/SPISOMIB

GPIO26/ECAP3/EQEP2I/SPICLKB

GPIO27/HRCAP2/EQEP2S/SPISTEB

GPIO28/SCIRXDA/SDAA/TZ2

GPIO29/SCITXDA/SCLA/TZ3

GPIO30/CANRXA/EQEP2I/EPWM7A

GPIO50/EQEP1A/MDXA/TZ1

GPIO51/EQEP1B/MDRA/TZ2

GPIO52/EQEP1S/MCLKXA/TZ3

GPIO53/EQEP1I/MFSXA

GPIO54/SPISIMOA/EQEP2A/HRCAP1

GPIO55/SPISOMIA/EQEP2B/HRCAP2

GPIO31/CANTXA/EQEP2S/EPWM8A

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO34/COMP2OUT/COMP3OUT

GPIO35/TDI

GPIO36/TMS

GPIO37/TDO

GPIO38/XCLKIN/TCK

GPIO39

GPIO23/EQEP1I/MFSXA/SCIRXDB

GPIO20/EQEP1A/MDXA/COMP1OUT

GPIO21/EQEP1B/MDRA/COMP2OUT

GPIO4/EPWM3A

GPIO5/EPWM3B/SPISIMOA/ECAP1

ADCINA7

ADCINA3

XRS

TRST

ADCINA6/COMP3A/AIO6

ADCINA5

ADCINA4/COMP2A/AIO4

ADCINA2/COMP1A/AIO2

ADCINA1

ADCINA0

DDA

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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Figure 3-9. 100-Pin PZ/PZP LQFP (Top View)

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SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

3.4 Signal Descriptions

Table 3-6 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDDpins prior to or simultaneously with the V the VDDpins have reached 0.7 V before the V

Table 3-6. Terminal Functions

TERMINAL

NAME

TRST 12 10 I normal device operation. An external pull-down resistor is required on this pin. The

TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑) TMS See GPIO36 I

TDI See GPIO35 I

TDO See GPIO37 O/Z register (instruction or data) are shifted out of TDO on the falling edge of TCK.

DD3VFL

TEST2 45 36 I/O Test Pin. Reserved for TI. Must be left unconnected.

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

PZ/PZP PN/PFP

PIN # PIN #

46 37 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

I/O/Z DESCRIPTION

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-high test pin and must be maintained low at all times during

value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (↓)

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected (8-mA drive)

pins reach 0.7 V.

DDIO

JTAG

FLASH

(1)

pins, ensuring that

DDIO

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

XCLKOUT See GPIO18 O/Z

XCLKIN I disabled by bit 13 in the CLKCTL register.

X1 60 48 I

X2 59 47 O

XRS 11 9 I/O

ADCINA7 16 – I ADC Group A, Channel 7 input ADCINA6 17 14 I ADC Group A, Channel 6 input COMP3A I Comparator Input 3A AIO6 I/O Digital AIO 6 ADCINA5 18 15 I ADC Group A, Channel 5 input ADCINA4 19 16 I ADC Group A, Channel 4 input COMP2A I Comparator Input 2A AIO4 I/O Digital AIO 4 ADCINA3 20 – I ADC Group A, Channel 3 input ADCINA2 21 17 I ADC Group A, Channel 2 input COMP1A I Comparator Input 1A AIO2 I/O Digital AIO 2 ADCINA1 22 18 I ADC Group A, Channel 1 input

ADCINA0 23 19 I NOTE: V

PZ/PZP PN/PFP

PIN # PIN #

See GPIO19 and

GPIO38

I/O/Z DESCRIPTION

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be

NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.

On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected.

RESET

Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 5.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup.

ADC, COMPARATOR, ANALOG I/O

ADC Group A, Channel 0 input. their use is mutually exclusive to one another.

and ADCINA0 share the same pin on the 80-pin PN/PFP device and

REFHI

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

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SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Table 3-6. Terminal Functions (continued)

TERMINAL

PZ/PZP PN/PFP

PIN # PIN #

24 19

NAME

REFHI

ADCINB7 35 – I ADC Group B, Channel 7 input ADCINB6 34 27 I ADC Group B, Channel 6 input COMP3B I Comparator Input 3B AIO14 I/O Digital AIO 14 ADCINB5 33 26 I ADC Group B, Channel 5 input ADCINB4 32 25 I ADC Group B, Channel 4 input COMP2B I Comparator Input 2B AIO12 I/O Digital AIO12 ADCINB3 31 – I ADC Group B, Channel 3 input ADCINB2 30 24 I ADC Group B, Channel 2 input COMP1B I Comparator Input 1B AIO10 I/O Digital AIO 10 ADCINB1 29 23 I ADC Group B, Channel 1 input ADCINB0 28 22 I ADC Group B, Channel 0 input V

REFLO

DDA

SSA

DDIO

27 21 NOTE: V

25 20 Analog Power Pin. Tie with a 2.2-mF capacitor (typical) close to the pin. 26 21

3 2 14 12 37 29 63 51 81 65 91 72

5 4 13 11 38 30 61 49 79 63 93 74

4 3 15 13 36 28 47 38 Digital Ground Pins 62 50 80 64 92 73

I/O/Z DESCRIPTION

ADC External Reference – only used when in ADC external reference mode. See

Section 6.10.1, Analog-to-Digital Converter (ADC).

NOTE: V their use is mutually exclusive to one another.

and ADCINA0 share the same pin on the 80-pin PN/PFP device and

REFHI

is always connected to V

REFLO

SSA

CPU AND I/O POWER

Analog Ground Pin. NOTE: V

is always connected to V

REFLO

SSA

CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time.

Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled.

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on the 80-pin PN/PFP device.

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

VREGENZ 90 71 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG.

GPIO0 87 69 I/O/Z General-purpose input/output 0 EPWM1A O Enhanced PWM1 Output A and HRPWM channel GPIO1 86 68 I/O/Z General-purpose input/output 1 EPWM1B O Enhanced PWM1 Output B COMP1OUT O Direct output of Comparator 1 GPIO2 84 67 I/O/Z General-purpose input/output 2 EPWM2A O Enhanced PWM2 Output A and HRPWM channel GPIO3 83 66 I/O/Z General-purpose input/output 3 EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in COMP2OUT O Direct output of Comparator 2 GPIO4 9 7 I/O/Z General-purpose input/output 4 EPWM3A O Enhanced PWM3 output A and HRPWM channel GPIO5 10 8 I/O/Z General-purpose input/output 5 EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI-A slave in, master out ECAP1 I/O Enhanced Capture input/output 1 GPIO6 58 46 I/O/Z General-purpose input/output 6 EPWM4A O Enhanced PWM4 output A and HRPWM channel EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 57 45 I/O/Z General-purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data ECAP2 I/O Enhanced Capture input/output 2 GPIO8 54 43 I/O/Z General-purpose input/output 8 EPWM5A O Enhanced PWM5 output A and HRPWM channel Reserved – Reserved ADCSOCAO O ADC start-of-conversion A

(1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the TMS320x2806x Piccolo System Control and Interrupts Reference Guide (literature number SPRUH15).

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

VOLTAGE REGULATOR CONTROL SIGNAL

GPIO AND PERIPHERAL SIGNALS

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

(1)

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

GPIO9 49 39 I/O/Z General-purpose input/output 9 EPWM5B O Enhanced PWM5 output B

SCITXDB O ECAP3 I/O Enhanced Capture input/output 3

GPIO10 74 60 I/O/Z General-purpose input/output 10 EPWM6A O Enhanced PWM6 output A and HRPWM channel Reserved – Reserved ADCSOCBO O ADC start-of-conversion B GPIO11 73 59 I/O/Z General-purpose input/output 11 EPWM6B O Enhanced PWM6 output B

SCIRXDB I ECAP1 I/O Enhanced Capture input/output 1

GPIO12 44 35 I/O/Z General-purpose input/output 12 TZ1 I Trip Zone input 1 SCITXDA O SCI-A transmit data SPISIMOB I/O SPI-B slave in, master out GPIO13 95 75 I/O/Z General-purpose input/output 13 TZ2 I Trip Zone input 2 Reserved – Reserved SPISOMIB I/O SPI-B slave out, master in GPIO14 96 76 I/O/Z General-purpose input/output 14 TZ3 I Trip zone input 3

SCITXDB O SPICLKB I/O SPI-B clock input/output

GPIO15 88 70 I/O/Z General-purpose input/output 15 ECAP2 I/O Enhanced Capture input/output 2

SCIRXDB I SPISTEB I/O SPI-B slave transmit enable input/output

GPIO16 55 44 I/O/Z General-purpose input/output 16 SPISIMOA I/O SPI-A slave in, master out Reserved – Reserved TZ2 I Trip Zone input 2 GPIO17 52 42 I/O/Z General-purpose input/output 17 SPISOMIA I/O SPI-A slave out, master in Reserved – Reserved TZ3 I Trip zone input 3

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages.

SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages.

SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages.

SCI-B receive data.

NOTE: SCI-B is only available in the PZ and PZP packages.

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

GPIO18 51 41 I/O/Z General-purpose input/output 18 SPICLKA I/O SPI-A clock input/output

SCITXDB O XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,

GPIO19 64 52 I/O/Z General-purpose input/output 19 XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the

SPISTEA I/O SPI-A slave transmit enable input/output SCIRXDB I ECAP1 I/O Enhanced Capture input/output 1

GPIO20 6 5 I/O/Z General-purpose input/output 20 EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data COMP1OUT O Direct output of Comparator 1 GPIO21 7 6 I/O/Z General-purpose input/output 21 EQEP1B I Enhanced QEP1 input B MDRA I McBSP receive serial data COMP2OUT O Direct output of Comparator 2 GPIO22 98 78 I/O/Z General-purpose input/output 22 EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock

SCITXDB O GPIO23 2 1 I/O/Z General-purpose input/output 23

EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch

SCIRXDB I GPIO24 97 77 I/O/Z General-purpose input/output 24

ECAP1 I/O Enhanced Capture input/output 1 EQEP2A I Enhanced QEP2 input A.

SPISIMOB I/O SPI-B slave in, master out GPIO25 39 31 I/O/Z General-purpose input/output 25 ECAP2 I/O Enhanced Capture input/output 2

EQEP2B I SPISOMIB I/O SPI-B slave out, master in

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages.

one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other peripheral functions.

SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages.

SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages.

SCI-B receive data.

NOTE: SCI-B is only available in the PZ and PZP packages.

NOTE: eQEP2 is only available in the PZ and PZP packages.

Enhanced QEP2 input B. NOTE: eQEP2 is only available in the PZ and PZP packages.

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

GPIO26 78 62 I/O/Z General-purpose input/output 26 ECAP3 I/O Enhanced Capture input/output 3

EQEP2I I/O SPICLKB I/O SPI-B clock input/output

GPIO27 77 61 I/O/Z General-purpose input/output 27 HRCAP2 I High-Resolution Input Capture 2

EQEP2S I/O SPISTEB I/O SPI-B slave transmit enable input/output

GPIO28 50 40 I/O/Z General-purpose input/output 28 SCIRXDA I SCI-A receive data SDAA I/OD I2C data open-drain bidirectional port TZ2 I Trip zone input 2 GPIO29 43 34 I/O/Z General-purpose input/output 29 SCITXDA O SCI-A transmit data SCLA I/OD I2C clock open-drain bidirectional port TZ3 I Trip zone input 3 GPIO30 41 33 I/O/Z General-purpose input/output 30 CANRXA I CAN receive

EQEP2I I/O EPWM7A O Enhanced PWM7 Output A and HRPWM channel

GPIO31 40 32 I/O/Z General-purpose input/output 31 CANTXA O CAN transmit

EQEP2S I/O EPWM8A O Enhanced PWM8 Output A and HRPWM channel

GPIO32 99 79 I/O/Z General-purpose input/output 32 SDAA I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A GPIO33 100 80 I/O/Z General-purpose input/output 33 SCLA I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B GPIO34 68 55 I/O/Z General-purpose input/output 34 COMP2OUT O Direct output of Comparator 2 COMP3OUT O Direct output of Comparator 3 GPIO35 71 57 I/O/Z General-purpose input/output 35 TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

GPIO36 72 58 I/O/Z General-purpose input/output 36 TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked

GPIO37 70 56 I/O/Z General-purpose input/output 37 TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

Enhanced QEP2 index. NOTE: eQEP2 is only available in the PZ and PZP packages.

Enhanced QEP2 strobe. NOTE: eQEP2 is only available in the PZ and PZP packages.

Enhanced QEP2 index. NOTE: eQEP2 is only available in the PZ and PZP packages.

Enhanced QEP2 strobe. NOTE: eQEP2 is only available in the PZ and PZP packages.

(instruction or data) on a rising edge of TCK.

into the TAP controller on the rising edge of TCK.

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).

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Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

GPIO38 67 54 I/O/Z General-purpose input/output 38 XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the

TCK I JTAG test clock with internal pullup GPIO39 66 53 I/O/Z General-purpose input/output 39 GPIO40 82 – I/O/Z General-purpose input/output 40 EPWM7A O Enhanced PWM7 output A and HRPWM channel SCITXDB O SCI-B transmit data GPIO41 76 – I/O/Z General-purpose input/output 41 EPWM7B O Enhanced PWM7 output B SCIRXDB I SCI-B receive data GPIO42 1 – I/O/Z General-purpose input/output 42 EPWM8A O Enhanced PWM8 output A and HRPWM channel TZ1 I Trip zone input 1 COMP1OUT O Direct output of Comparator 1 GPIO43 8 – I/O/Z General-purpose input/output 43 EPWM8B O Enhanced PWM8 output B TZ2 I Trip zone input 2 COMP2OUT O Direct output of Comparator 2 GPIO44 56 – I/O/Z General-purpose input/output 44 MFSRA I/O McBSP receive frame synch SCIRXDB I SCI-B receive data EPWM7B O Enhanced PWM7 output B GPIO50 42 – I/O/Z General-purpose input/output 50 EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data TZ1 I Trip zone input 1 GPIO51 48 – I/O/Z General-purpose input/output 51 EQEP1B I Enhanced QEP1 input B MDRA I McBSP receive serial data TZ2 I Trip zone input 2 GPIO52 53 – I/O/Z General-purpose input/output 52 EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock TZ3 I Trip zone input 3 GPIO53 65 – I/O/Z General-purpose input/output 53 EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch GPIO54 69 – I/O/Z General-purpose input/output 54 SPISIMOA I/O SPI-A slave in, master out EQEP2A I Enhanced QEP2 input A HRCAP1 I High-Resolution Input Capture 1

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions.

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

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TMS320F28064 TMS320F28063 TMS320F28062

ADVANCEINFORMATION

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

SPRS698A–NOVEMBER 2010–REVISED JANUARY 2011

Table 3-6. Terminal Functions (continued)

TERMINAL

NAME

GPIO55 75 – I/O/Z General-purpose input/output 55 SPISOMIA I/O SPI-A slave out, master in EQEP2B I Enhanced QEP2 input B HRCAP2 I High-Resolution Input Capture 2 GPIO56 85 – I/O/Z General-purpose input/output 56 SPICLKA I/O SPI-A clock input/output EQEP2I I/O Enhanced QEP2 index HRCAP3 I High-Resolution Input Capture 3 GPIO57 89 – I/O/Z General-purpose input/output 57 SPISTEA I/O SPI-A slave transmit enable input/output EQEP2S I/O Enhanced QEP2 strobe HRCAP4 I High-Resolution Input Capture 4 GPIO58 94 – I/O/Z General-purpose input/output 58 MCLKRA I/O McBSP receive clock SCITXDB O SCI-B transmit data EPWM7A O Enhanced PWM7 output A and HRPWM channel

PZ/PZP PN/PFP

PIN # PIN #

I/O/Z DESCRIPTION

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TMS320F28064 TMS320F28063 TMS320F28062

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Texas instruments TMS320F28062, TMS320F28068, TMS320F28067, TMS320F28069, TMS320F28064 ADVANCE INFORMATION

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Features

1.2 Description

1.3 Functional Block Diagram

1.4 System Device Diagram

2 Revision History

3 Device Overview

3.1 Device Characteristics

3.2 Memory Maps

3.3 Pin Assignments

3.4 Signal Descriptions