Texas Instruments TMS320F28044PZA, TMS320F28044 Datasheet

Digital Signal Processor

Data Manual

TMS320F28044

Literature Number: SPRS357B

August 2006 – Revised May 2007

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Contents

1 F28044 Digital Signal Processor ............................................................................................ 9

1.1 Features ....................................................................................................................... 9

1.2 Getting Started .............................................................................................................. 10

2 Introduction ....................................................................................................................... 11

2.1 Pin Assignments ............................................................................................................ 11

2.2 Signal Descriptions ......................................................................................................... 14

3 Functional Overview ........................................................................................................... 20

3.1 Memory Map ................................................................................................................ 21

3.2 Brief Descriptions ........................................................................................................... 23

3.2.1 C28x CPU ....................................................................................................... 23

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 23

3.2.3 Peripheral Bus .................................................................................................. 24

3.2.4 Real-Time JTAG and Analysis ................................................................................ 24

3.2.5 Flash .............................................................................................................. 24

3.2.6 M0, M1 SARAMs ............................................................................................... 24

3.2.7 L0, L1 SARAMs ................................................................................................. 24

3.2.8 Boot ROM ........................................................................................................ 25

3.2.9 Security .......................................................................................................... 26

3.2.10 Peripheral Interrupt Expansion (PIE) Block .................................................................. 27

3.2.11 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 27

3.2.12 Oscillator and PLL .............................................................................................. 27

3.2.13 Watchdog ........................................................................................................ 27

3.2.14 Peripheral Clocking ............................................................................................. 27

3.2.15 Low-Power Modes .............................................................................................. 27

3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 28

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 28

3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 28

3.2.19 Control Peripherals ............................................................................................. 28

3.2.20 Serial Port Peripherals ......................................................................................... 29

3.3 Register Map ................................................................................................................ 29

3.4 Device Emulation Registers ............................................................................................... 30

3.5 Interrupts .................................................................................................................... 31

3.5.1 External Interrupts .............................................................................................. 33

3.6 System Control ............................................................................................................. 34

3.6.1 OSC and PLL Block ............................................................................................ 36

3.6.2 Watchdog Block ................................................................................................. 38

3.7 Low-Power Modes Block .................................................................................................. 40

4 Peripherals ........................................................................................................................ 41

4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 41

4.2 Enhanced PWM Modules (ePWM1-16) ................................................................................. 43

4.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 48

4.4 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 49

4.5 ADC Connections if the ADC Is Not Used ................................................................... 52

4.6 Serial Communications Interface (SCI) Module (SCI-A) .............................................................. 54

4.7 Serial Peripheral Interface (SPI) Module (SPI-A) ...................................................................... 57

4.8 Inter-Integrated Circuit (I

4.9 GPIO MUX .................................................................................................................. 62

5 Device Support .................................................................................................................. 66

5.1 Device and Development Support Tool Nomenclature ................................................................ 66

5.2 Documentation Support ................................................................................................... 68

C) ............................................................................................... 60

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6 Electrical Specifications ...................................................................................................... 71

6.1 Absolute Maximum Ratings ............................................................................................... 71

6.2 Recommended Operating Conditions ................................................................................... 72

6.3 Electrical Characteristics ................................................................................................. 72

6.4 Current Consumption ..................................................................................................... 73

6.4.1 Reducing Current Consumption .............................................................................. 74

6.5 Emulator Connection Without Signal Buffering for the DSP .......................................................... 75

6.6 Timing Parameter Symbology ............................................................................................ 76

6.6.1 General Notes on Timing Parameters ........................................................................ 76

6.6.2 Test Load Circuit ................................................................................................ 77

6.6.3 Device Clock Table ............................................................................................. 77

6.7 Clock Requirements and Characteristics ............................................................................... 78

6.8 Power Sequencing ......................................................................................................... 79

6.8.1 Power Management and Supervisory Circuit Solutions .................................................... 79

6.9 General-Purpose Input/Output (GPIO) .................................................................................. 82

6.9.1 GPIO - Output Timing ........................................................................................... 82

6.9.2 GPIO - Input Timing ............................................................................................. 83

6.10 Enhanced Control Peripherals ............................................................................................ 88

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ......................................................... 88

6.10.2 Trip-Zone Input Timing .......................................................................................... 88

6.10.3 External Interrupt Timing ....................................................................................... 89

6.10.4 I

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing ..................................................... 90

6.10.6 SPI Slave Mode Timing ......................................................................................... 94

6.11 On-Chip Analog-to-Digital Converter .................................................................................... 97

6.11.1 ADC Power-Up Control Bit Timing ............................................................................ 98

6.11.2 Definitions ........................................................................................................ 99

6.11.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................. 100

6.11.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ........................................... 101

6.12 Detailed Descriptions .................................................................................................... 102

6.13 Flash Timing ............................................................................................................... 103

7 Mechanical Data ............................................................................................................... 105

C Electrical Specification and Timing ....................................................................... 90

Contents 3

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

List of Figures

2-1 100-Pin PZ LQFP (Top View) ................................................................................................... 12

2-2 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 13

3-1 Functional Block Diagram ........................................................................................................ 20

3-2 F28044 Memory Map ............................................................................................................. 21

3-3 External and PIE Interrupt Sources ............................................................................................. 31

3-4 Multiplexing of Interrupts Using the PIE Block ................................................................................ 32

3-5 Clock and Reset Domains ....................................................................................................... 34

3-6 OSC and PLL Block Diagram ................................................................................................... 36

3-7 Using a 3.3-V External Oscillator ............................................................................................... 36

3-8 Using a 1.8-V External Oscillator ............................................................................................... 36

3-9 Using the Internal Oscillator ..................................................................................................... 36

3-10 Watchdog Module ................................................................................................................. 39

4-1 CPU-Timers ........................................................................................................................ 41

4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 42

4-3 Multiple PWM Modules ........................................................................................................... 43

4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 48

4-5 Block Diagram of the ADC Module ............................................................................................. 50

4-6 ADC Pin Connections With Internal Reference ............................................................................... 51

4-7 ADC Pin Connections With External Reference .............................................................................. 52

4-8 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 56

4-9 SPI Module Block Diagram (Slave Mode) ..................................................................................... 59

4-10 I

4-11 GPIO MUX Block Diagram ....................................................................................................... 62

4-12 Qualification Using Sampling Window .......................................................................................... 65

5-1 Example of TMS320x280x Device Nomenclature ............................................................................ 67

6-1 Emulator Connection Without Signal Buffering for the DSP ................................................................. 75

6-2 3.3-V Test Load Circuit ........................................................................................................... 77

6-3 Clock Timing ....................................................................................................................... 79

6-4 Power-on Reset ................................................................................................................... 80

6-5 Warm Reset ........................................................................................................................ 81

6-6 Example of Effect of Writing Into PLLCR Register ........................................................................... 82

6-7 General-Purpose Output Timing ................................................................................................ 82

6-8 Sampling Mode .................................................................................................................... 83

6-9 General-Purpose Input Timing .................................................................................................. 84

6-10 IDLE Entry and Exit Timing ...................................................................................................... 85

6-11 STANDBY Entry and Exit Timing Diagram .................................................................................... 86

6-12 HALT Wake-Up Using GPIOn ................................................................................................... 87

6-13 PWM Hi-Z Characteristics ....................................................................................................... 88

6-14 ADCSOCAO or ADCSOCBO Timing ........................................................................................... 89

C Peripheral Module Interfaces ............................................................................................... 61

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6-15 External Interrupt Timing ......................................................................................................... 89

6-16 SPI Master Mode External Timing (Clock Phase = 0) ........................................................................ 92

6-17 SPI Master External Timing (Clock Phase = 1) ............................................................................... 94

6-18 SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 95

6-19 SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 96

6-20 ADC Power-Up Control Bit Timing .............................................................................................. 98

6-21 ADC Analog Input Impedance Model ........................................................................................... 99

6-22 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 100

6-23 Simultaneous Sampling Mode Timing ........................................................................................ 101

List of Figures 5

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

List of Tables

2-1 Hardware Features ............................................................................................................... 11

2-2 Signal Descriptions ............................................................................................................... 14

3-1 Addresses of Flash Sectors ..................................................................................................... 22

3-2 Wait-states ......................................................................................................................... 23

3-3 Boot Mode Selection .............................................................................................................. 25

3-4 Peripheral Frame 0 Registers ................................................................................................... 29

3-5 Peripheral Frame 1 Registers ................................................................................................... 30

3-6 Peripheral Frame 2 Registers ................................................................................................... 30

3-7 Device Emulation Registers ..................................................................................................... 30

3-8 PIE Peripheral Interrupts ......................................................................................................... 32

3-9 PIE Configuration and Control Registers ...................................................................................... 33

3-10 External Interrupt Registers ...................................................................................................... 33

3-11 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 35

3-12 PLLCR Register Bit Definitions .................................................................................................. 37

3-13 Possible PLL Configuration Modes ............................................................................................. 38

3-14 Low-Power Modes ................................................................................................................ 40

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 42

4-2 ePWM1-4 Control and Status Registers ....................................................................................... 44

4-3 ePWM5-8 Control and Status Registers ....................................................................................... 45

4-4 ePWM9-12 Control and Status Registers ...................................................................................... 46

4-5 ePWM13-16 Control and Status Registers .................................................................................... 47

4-6 ADC Registers ..................................................................................................................... 53

4-7 SCI-A Registers ................................................................................................................... 55

4-8 SPI-A Registers ................................................................................................................... 58

4-9 I

4-10 GPIO Registers ................................................................................................................... 63

4-11 F28044 GPIO MUX Table ........................................................................................................ 64

6-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............................. 73

6-2 Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 74

6-3 TMS320x280x Clock Table and Nomenclature ............................................................................... 77

6-4 Input Clock Frequency ........................................................................................................... 78

6-5 XCLKIN Timing Requirements - PLL Enabled ................................................................................ 78

6-6 XCLKIN Timing Requirements - PLL Disabled ................................................................................ 78

6-7 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................... 78

6-8 Power Management and Supervisory Circuit Solutions ...................................................................... 79

6-9 Reset ( XRS) Timing Requirements ............................................................................................ 81

6-10 General-Purpose Output Switching Characteristics .......................................................................... 82

6-11 General-Purpose Input Timing Requirements ................................................................................. 83

6-12 IDLE Mode Timing Requirements ............................................................................................... 85

C-A Registers .................................................................................................................... 61

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6-13 IDLE Mode Switching Characteristics .......................................................................................... 85

6-14 STANDBY Mode Timing Requirements ........................................................................................ 85

6-15 STANDBY Mode Switching Characteristics .................................................................................. 86

6-16 HALT Mode Timing Requirements .............................................................................................. 86

6-17 HALT Mode Switching Characteristics ........................................................................................ 87

6-18 ePWM Timing Requirements .................................................................................................... 88

6-19 ePWM Switching Characteristics ................................................................................................ 88

6-20 Trip-Zone input Timing Requirements .......................................................................................... 88

6-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) ................................................ 89

6-22 External ADC Start-of-Conversion Switching Characteristics ............................................................... 89

6-23 External Interrupt Timing Requirements ....................................................................................... 89

6-24 External Interrupt Switching Characteristics ................................................................................... 89

6-25 I

6-26 SPI Master Mode External Timing (Clock Phase = 0)........................................................................ 91

6-27 SPI Master Mode External Timing (Clock Phase = 1)........................................................................ 93

6-28 SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 94

6-29 SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 95

6-30 ADC Electrical Characteristics (over recommended operating conditions) ................................................ 97

6-31 ADC Power-Up Delays ........................................................................................................... 98

6-32 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .......................................... 98

6-33 Sequential Sampling Mode Timing ............................................................................................ 100

6-34 Simultaneous Sampling Mode Timing ........................................................................................ 101

6-35 Flash Endurance ................................................................................................................. 103

6-36 Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 103

6-37 Flash/OTP Access Timing ...................................................................................................... 103

6-38 Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 104

7-1 F28044 Thermal Model 100-pin GGM Results .............................................................................. 105

7-2 F28044 Thermal Model 100-pin PZ Results ................................................................................. 105

C Timing ......................................................................................................................... 90

List of Tables 7

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

This data manual was revised from SPRS357A to SPRS357B.

LOCATION ADDITIONS, MODIFICATIONS, DELETIONS

Global Document changed from Advance Information to Production Data to reflect device change from TMX to

TMS.

Section 1.1 Features list revised Section 1.2 Added Getting Started Section Section 4.5 Added subsection on pin connections when ADC is not used Section 5.2 Updated the documents list in Documentation Support Section 6.4.1 Added a note to the section on reducing current consumption Table 6-28 Modified values on last two rows of table Table 6-29 Modified values on last two rows of table

Changes in This Revision

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1 F28044 Digital Signal Processor

1.1 Features

• High-Performance 100-MHz (10-ns Cycle Time)

Processor

• TMS320C28x™ 32-Bit CPU – Single-cycle 16 × 16 and 32 × 32

Multiply-accumulate (MAC) Operations

– Dual 16 × 16 MAC – Fast Interrupt Response – Unified Memory Programming Model

• On-Chip Memory – 64K × 16 Flash – 10K × 16 SARAM – 1K × 16 OTP – 4K × 16 Boot ROM – Code Security Module Protects Against

Unauthorized Memory Access

• Clocking – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Clock-Fail-Detect Mode

• Interrupts – Support for up to Three External Core

Interrupts

– Peripheral Interrupt Expansion (PIE) Block

That Supports All Peripheral Interrupts

• High-speed, 12-Bit ADC – 80 ns (12.5 MSPS) Conversion Rate – 16 Channels – Two Sample-and-Hold – Single/Simultaneous Conversions – Internal or External Reference

• High-Resolution PWM – 16 Outputs with 150 ps Resolution – 14.8 Bits at 200-KHz Switching – 13.4 Bits at 500-KHz Switching – 12.4 Bits at 1-MHz Switching

• Communications Port Peripherals

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

– Serial Peripheral Interface (SPI) Module – Serial Communications Interface (SCI)

– Inter-Integrated Circuit (I2C) Bus

• Timers

– Three 32-bit CPU Timers – Up to 16 16-bit Timers – Watchdog Timer Module

• Up to 35 General-Purpose Input/Output (GPIO)

Pins With Input Filtering

• On-chip JTAG Emulation With Real-time

Debug via Hardware

• JTAG Boundary Scan Support

• Low-power IDLE, STANDBY, and HALT Modes

• Development Tools

– F28044 eZdsp Starter Kit – Code Composer Studio™ IDE With Flash

Programming Plug-in

– C28x-optimized ANSI C/C++

Compiler/Assembler/Linker – DSP/BIOS™ Real-time Operating System – USB-based JTAG Emulators

• Available Software

– C2000™ Digital Power Supply Software

Library – C28x™ IQ Math Library – C28x Header Files With Example Programs

for all Peripherals – C28x DSP Library – C28x Digital Motor Control Software Library

• Package Options

– 100-pin Thin Quad Flatpack (PZ) – 100-pin MicroStar BGA™ (GGM, ZGM) – RoHS-compliant, Green Packaging

• Temperature Range:

-40°C to 85°C (PZ, GGM, ZGM)

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

(1)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

TMS320C28x, Code Composer Studio, DSP/BIOS, C2000, C28x, MicroStar BGA, TMS320 are trademarks of Texas Instruments. eZdsp, XDS510USB are trademarks of Spectrum Digital. All other trademarks are the property of their respective owners.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

1.2 Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following:

• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

Step 1. Acquire the appropriate development tools

The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial development, which, in one package, includes:

• On-board JTAG emulation via USB or parallel port

• Appropriate emulation driver

• Code Composer Studio™ IDE for eZdsp

Once you have become familiar with the device and begin developing on your own hardware, purchase Code Composer Studio™ IDE separately for software development and a JTAG emulation tool to get started on your project.

Step 2. Download starter software

To simplify programming for C28x devices, it is recommended that users download and use the C/C++ Header Files and Example(s) to begin developing software for the C28x devices and their various peripherals.

After downloading the appropriate header file package for your device, refer to the following resources for step-by-step instructions on how to run the peripheral examples and use the header file structure for your own software

• The Quick Start Readme in the /doc directory to run your first application.

• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report

(literature number SPRAA85 )

Step 3. Download flash programming software

Many C28x devices include on-chip flash memory and tools that allow you to program the flash with your software IP.

• Flash Tools: C28x Flash Tools

• TMS320F281x Flash Programming Solutions (literature number SPRB169 )

• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature

number SPRA958 )

Step 4. Move on to more advanced topics

For more application software and other advanced topics, visit the TI website at

http://www.ti.com or http://www.ti.com/c2000getstarted .

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Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

2 Introduction

The TMS320F28044 device, member of the TMS320C28x™ DSP generation, is a highly integrated, high-performance solution for demanding control applications.

Throughout this document, TMS320F28044 is abbreviated as F28044. Table 2-1 provides a summary of the device's features.

Table 2-1. Hardware Features

FEATURE F28044

Instruction cycle (at 100 MHz) 10 ns Single-access RAM (SARAM) (16-bit word)

3.3-V on-chip flash (16-bit word) 64K On-chip ROM (16-bit word) – Code security for on-chip flash/SARAM/OTP blocks Yes Boot ROM (4K X16) Yes One-time programmable (OTP) ROM

(16-bit word) PWM outputs (one 16-bit timer/module) ePWM1-16 HRPWM channels ePWM1-16 Watchdog timer Yes

No. of channels 16

12-Bit ADC MSPS 12.5

Conversion time 80 ns 32-Bit CPU timers 3 Serial Peripheral Interface (SPI) SPI-A Serial Communications Interface (SCI) SCI-A Inter-Integrated Circuit (I2C) I2C-A Digital I/O pins (shared) 35 External interrupts 3 Supply voltage 1.8-V Core, 3.3-V I/O Yes Packaging 100-Pin PZ Yes

100-ball GGM, ZGM Yes Temperature options A: -40 ° C to 85 ° C (PZ, GGM, ZGM) Product status

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

(1)

(L0, L1, M0, M1)

TMS320F28044

10K

TMS

2.1 Pin Assignments

The TMS320F28044 100-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in

Figure 2-1 . The 100-ball GGM and ZGM ball grid array (BGA) terminal assignments are shown in Figure 2-2 . Table 2-2 describes the function(s) of each pin.

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50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

GPIO0/EPWM1A

TCK

TMS

TDI

XRS

TRST

DDIO

GPIO17/SPISOMIA/TZ6

DDIO

GPIO16/SPISIMOA/TZ5

DD2A18

SS2AGND

DDAIO

GPIO12/TZ1/EPWM13A

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3/EPWM15A

DD1A18

SS1AGND

SSA2

DDA2

GPIO15/TZ4/EPWM16A

SSAIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO13/TZ2/EPWM14A

DD3VFL

GPIO28/SCIRXDA/TZ5

DDIO

GPIO26

TEST2

TEST1

GPIO25

XCLKIN

EMU1

EMU0

GPIO24

GPIO27

TDO

GPIO30/TZ3

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM2A

GPIO2/EPWM3A

GPIO3/EPWM4A

XCLKOUT

GPIO20

GPIO9/EPWM10A

GPIO8/EPWM9A/ADCSOCAO

GPIO21

GPIO23

GPIO22

GPIO11/EPWM12A

GPIO10/EPWM11A/ADCSOCBO

GPIO6/EPWM7A/EPWMSYNCI/EPWMSYNCO

GPIO5/EPWM6A

GPIO7/EPWM8A

GPIO19/SPISTEA/TZ2

GPIO18/SPICLKA/TZ1

GPIO4/EPWM5A

GPIO31/TZ4

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 2-1. 100-Pin PZ LQFP (Top View)

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21 3

5 76 98 10

Bottom View

TRST TCK

TDI

TDO TMS

EMU0

EMU1

DD3VFL

TEST1

TEST2

XCLKOUT

XCLKIN

XRS

GPIO0

GPIO1

GPIO2 GPIO3 GPIO4

GPIO5

GPIO6GPIO7

GPIO9 GPIO8

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23GPIO24GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

DDA2

DD1A18 V

SS1AGND

DDIO

VSSAIO

DDAIO

VSSA2

ADCINA7

SS2AGND

DD2A18

DDIO

VSS

ADCINB2

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCINB7

ADCINB1

ADCINB0

ADCLO

ADCRESEXT

ADCREFIN

ADCREFP

ADCREFM

ADCINB3

ADCINB5

ADCINB4

ADCINB6

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 2-2. 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

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TMS320F28044 Digital Signal Processor

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2.2 Signal Descriptions

Table 2-2 describes the signals on the F28044 device. All digital inputs are TTL-compatible. All outputs

are 3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-2. Signal Descriptions

PIN NO.

NAME DESCRIPTION

PIN #

TRST 84 A6

TCK 75 A10 JTAG test clock with internal pullup (I, ↑ ) TMS 74 B10

TDI 73 C9

TDO 76 B9

EMU0 80 A8 (I/O/Z, 8 mA drive ↑ )

EMU1 81 B7 (I/O/Z, 8 mA drive ↑ )

DD3VFL

TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O) TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal

XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is

96 C4

GGM/

ZGM

BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (I, ↓ )

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑ )

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑ )

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM parts (C280x), this pin should be connected to V

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, used to feed clock to X1 pin), this pin must be tied to GND. (I)

DDIO

(1)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GGM/

ZGM

BALL #

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

X2 86 C6

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the

XRS 78 B8

location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑ ) The output buffer of this pin is an open-drain with an internal pullup (100 µ A, typical). It is recommended that this pin be driven by an open-drain device.

ADC SIGNALS

ADCINA7 16 F3 ADC Group A, Channel 7 input (I) ADCINA6 17 F4 ADC Group A, Channel 6 input (I) ADCINA5 18 G4 ADC Group A, Channel 5 input (I) ADCINA4 19 G1 ADC Group A, Channel 4 input (I) ADCINA3 20 G2 ADC Group A, Channel 3 input (I) ADCINA2 21 G3 ADC Group A, Channel 2 input (I) ADCINA1 22 H1 ADC Group A, Channel 1 input (I) ADCINA0 23 H2 ADC Group A, Channel 0 input (I) ADCINB7 34 K5 ADC Group B, Channel 7 input (I) ADCINB6 33 H4 ADC Group B, Channel 6 input (I) ADCINB5 32 K4 ADC Group B, Channel 5 input (I) ADCINB4 31 J4 ADC Group B, Channel 4 input (I) ADCINB3 30 K3 ADC Group B, Channel 3 input (I) ADCINB2 29 H3 ADC Group B, Channel 2 input (I) ADCINB1 28 J3 ADC Group B, Channel 1 input (I) ADCINB0 27 K2 ADC Group B, Channel 0 input (I) ADCLO 24 J1 Low Reference (connect to analog ground) (I) ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground. ADCREFIN 35 J5 External reference input (I)

ADCREFP 37 G5

ADCREFM 36 H5

Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 µ F to analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor of 2.2 µ F to analog ground. (O)

CPU AND I/O POWER PINS

DDA2

SSA2

DDAIO

SSAIO

DD1A18

SS1AGND

DD2A18

SS2AGND

15 F2 ADC Analog Power Pin (3.3 V) 14 F1 ADC Analog Ground Pin 26 J2 ADC Analog I/O Power Pin (3.3 V) 25 K1 ADC Analog I/O Ground Pin 12 E4 ADC Analog Power Pin (1.8 V) 13 E5 ADC Analog Ground Pin 40 J6 ADC Analog Power Pin (1.8 V) 39 K6 ADC Analog Ground Pin

(1)

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TMS320F28044 Digital Signal Processor

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

DDIO

GPIO0 General purpose input/output 0 (I/O/Z) EPWM1A Enhanced PWM1 Output and HRPWM channel (O)

- -

- GPIO1 General purpose input/output 1 (I/O/Z)

EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

- -

- GPIO2 General purpose input/output 2 (I/O/Z)

EPWM3A Enhanced PWM3 Output A and HRPWM channel (O)

- -

- GPIO3 General purpose input/output 3 (I/O/Z)

EPWM4A Enhanced PWM4 Output A and HRPWM channel (O)

- -

- GPIO4 General purpose input/output 4 (I/O/Z)

EPWM5A Enhanced PWM5 output A and HRPWM channel (O)

- -

- GPIO5 General purpose input/output 5 (I/O/Z)

EPWM6A Enhanced PWM6 Output A and HRPWM channel (O)

- -

GGM/

ZGM

BALL #

10 E2 42 G6 59 F10 68 D7

CPU and Logic Digital Power Pins (1.8 V)

85 B6 93 D4

3 C2 46 H7 65 E9

Digital I/O Power Pin (3.3 V)

82 A7

2 B1 11 E3 41 H6 49 K9 55 H10 62 F7 Digital Ground Pins 69 D10 77 A9 87 D6 89 A5 94 A4

47 K8

44 K7

45 J7

48 J8

51 J9

53 H9

GPIOA AND PERIPHERAL SIGNALS

(3)

(1)

(2)

(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

(3) The pullups on GPIO0-GPIO15 pins are not enabled at reset.

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO6 General purpose input/output 6 (I/O/Z) EPWM7A Enhanced PWM7 output A and HRPWM channel (O) EPWMSYNCI External ePWM sync pulse input (I) EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z) EPWM8A 58 G8 Enhanced PWM8 Output A and HRPWM channel (O)

- GPIO8 General purpose input/output 8 (I/O/Z)

EPWM9A Enhanced PWM9 output A(O)

- ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z) EPWM10A 61 F8 Enhanced PWM10 Output A and HRPWM channel (O)

- GPIO10 General purpose input/output 10 (I/O/Z)

EPWM11A Enhanced PWM11 Output A and HRPWM channel (O)

- ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z) EPWM12A 70 D9 Enhanced PWM12 Output A and HRPWM channel (O)

- GPIO12 General purpose input/output 12 (I/O/Z)

TZ1 Trip Zone input 1 (I) EPWM13A Enhanced PWM13 Output A and HRPWM channel (O)

- GPIO13 General purpose input/output 13 (I/O/Z)

TZ2 Trip zone input 2 (I) EPWM14A Enhanced PWM14 Output A and HRPWM channel (O)

- GPIO14 General purpose input/output 14 (I/O/Z)

TZ3 Trip zone input 3 (I) EPWM15A Enhanced PWM15 Output A and HRPWM channel (O)

- GPIO15 General purpose input/output 15 (I/O/Z)

TZ4 Trip zone input 4 (I) EPWM16A Enhanced PWM16 Output A and HRPWM channel (O)

- GPIO16 General purpose input/output 16 (I/O/Z)

SPISIMOA SPI-A slave in, master out (I/O)

- TZ5 Trip zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z) SPISOMIA SPI-A slave out, master in (I/O)

- TZ6 Trip zone input 6(I)

GPIO18 General purpose input/output 18 (I/O/Z) SPICLKA SPI-A clock input/output (I/O)

- TZ1 Trip zone input 1 (I)

GPIO19 General purpose input/output 19 (I/O/Z) SPISTEA SPI-A slave transmit enable input/output (I/O)

- TZ2 Trip zone input 2 (I)

GPIO20 General purpose input/output 20 (I/O/Z)

- -

56 G9

60 F9

64 E10

1 B2

95 B4

8 D3

9 E1

50 K10

52 J10

54 H8

57 G10

63 F6

GGM/

ZGM

BALL #

(3)

(4)

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(1)

(4) The pullups on GPIO16-GPIO34 are enabled upon reset.

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO21 General purpose input/output 21 (I/O/Z)

- -

67 E7

GGM/

ZGM

BALL #

(4)

- GPIO22 General purpose input/output 22 (I/O/Z)

- -

71 D8

(4)

- GPIO23 General purpose input/output 23 (I/O/Z)

- -

72 C10

(4)

- GPIO24 General purpose input/output 24 (I/O/Z)

- -

83 C7

(4)

- GPIO25 General purpose input/output 25 (I/O/Z)

- -

91 C5

(4)

- GPIO26 General purpose input/output 26 (I/O/Z)

- -

99 A2

(4)

- GPIO27 General purpose input/output 27 (I/O/Z)

- -

79 C8

(4)

- GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCIRXDA SCI receive data (I)

- -

92 D5

TZ5 Trip zone 5 (I) GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)

SCITXDA SCI transmit data (O)

- -

4 C3

TZ6 Trip zone 6 (I) GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)

- -

6 D2

TZ3 Trip zone input 3 (I) GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)

- -

7 D1

TZ4 Trip zone input 4 (I) GPIO32 General purpose input/output 32 (I/O/Z)

SDAA I2C data open-drain bidirectional port (I/OD) EPWMSYNCI Enhanced PWM external sync pulse input (I)

100 A1

(4)

ADCSOCAO ADC start-of-conversion (O)

(1)

(4)

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Table 2-2. Signal Descriptions (continued)

PIN NO.

NAME DESCRIPTION

PIN #

GPIO33 General-Purpose Input/Output 33 (I/O/Z) SCLA I2C clock open-drain bidirectional port (I/OD) EPWMSYNCO Enhanced PWM external synch pulse output (O) ADCSOCBO ADC start-of-conversion (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z)

- -

(1) The pullups on GPIO16-GPIO34 are enabled upon reset.

5 C1

43 G7

GGM/

ZGM

BALL #

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(1)

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INT[12:1]

Real-Time JTAG

(TDI, TDO, TRST, TCK,

TMS, EMU0, EMU1)

C28x CPU (100 MHz)

NMI, INT13

Memory Bus

Boot ROM

4 K 16

(1-wait state)

FLASH

64K x 16

L1 SARAM

(B)

4 K  16

(0-wait)

L0 SARAM

4 K  16 (0-wait)

M0 SARAM

1 K  16

M1 SARAM

1 K  16

INT14

32-bit CPU TIMER 0

32-bit CPU TIMER 1

32-bit CPU TIMER 2

SYSCLKOUT

RS CLKIN

12-Bit ADC

ADCSOCA/B

SOCA/B

16 Channels

XCLKOUT

XRS

XCLKIN

System Control

(Oscillator, PLL,

Peripheral Clocking,

Low Power Modes,

WatchDog)

ePWM1−16

(16 PWM outputs,

6 trip zones,

6 timers 16-bit)

External Interrupt

Control

PIE

(96 Interrupts)

(A)

FIFO

SCI-A

SPI-A

I2C-A

GPIO MUX

GPIOs

(35)

TINT0

TINT1

TINT2

OTP

(D)

1K  16

Peripheral Bus

Protected by the code-security module.

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3 Functional Overview

A. 43 of the possible 96 interrupts are used on the devices. B. The 1K x 16 OTP has been replaced with 1K x 16 ROM for the F28044 device.

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Figure 3-1. Functional Block Diagram

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3.1 Memory Map

0x00 0000

Block Start

Address

Data Space

M0 SARAM (1K y 16)

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8 0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP

(1 K y 16, Secure Zone)

FLASH

64 K y 16, Secure Zone)

Boot ROM (4 K y 16)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

Reserved

M1 SARAM (1K y 16)

L0 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L0 SARAM (0-wait) (4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k y 16, Secure Zone, Dual Mapped)

128-bit Password

0x3E 8000

Prog Space

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. Memory blocks are not to scale. B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order. D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

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User program cannot access these memory maps in program space.

Figure 3-2. F28044 Memory Map

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones.

Table 3-1. Addresses of Flash Sectors

ADDRESS RANGE PROGRAM AND DATA SPACE

0x3E 8000 - 0x3E BFFF Sector D (16K x 16) 0x3E C000 - 0x3E FFFF Sector C (16K x 16)

0x3F 0000 - 0x3F 3FFF Sector B (16K x 16) 0x3F 4000 - 0x3F 7F7F Sector A (16K x 16)

0x3F 7F80 - 0x3F 7FF5

0x3F 7FF6 - 0x3F 7FF7

0x3F 7FF8 - 0x3F 7FFF

Program to 0x0000 when using the

Code Security Module

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

The wait-states for the various spaces in the memory map area are listed in Table 3-2 .

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Table 3-2. Wait-states

AREA WAIT-STATES COMMENTS

M0 and M1 SARAMs 0-wait Fixed

Peripheral Frame 0 0-wait Fixed Peripheral Frame 1 Fixed.

Peripheral Frame 2 Fixed

L0 & L1 SARAMs 0-wait

OTP is possible at a reduced CPU frequency. See Section

Flash

Boot-ROM 1-wait Fixed

3.2 Brief Descriptions

0-wait (writes) 2-wait (reads)

Programmable,

1-wait minimum

Programmable, is possible at reduced CPU frequency. The CSM password

0-wait minimum locations are hardwired for 16 wait-states. See Section

Programmed via the Flash registers. 1-wait-state operation

Section 3.2.5 for more information.

Programmed via the Flash registers. 0-wait-state operation

Section 3.2.5 for more information.

3.2.1 C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a very efficient C/C++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2.2 Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)

Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)

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TMS320F28044 Digital Signal Processor

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3.2.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F28044 device adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the F28044. One version only supports 16-bit accesses (called peripheral frame 2). The other version supports both 16- and 32-bit accesses (called peripheral frame 1).

3.2.4 Real-Time JTAG and Analysis

The F28044 device implements the standard IEEE 1149.1 JTAG interface. Additionally, the device supports real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. The user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. The F28044 implements the real-time mode in hardware within the CPU. This is a unique feature to the F28044, no software monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user-selectable break events when a match occurs.

3.2.5 Flash

3.2.6 M0, M1 SARAMs

The F28044 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. Both devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables and should not contain program code.

NOTE

The F28044 Flash and OTP wait-states can be configured by the application. This allows

applications running at slower frequencies to configure the flash to use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution will be much faster than the raw performance indicated by the wait-state

configuration alone. The exact performance gain when using the Flash pipeline mode is

application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,

see the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide

(literature number SPRU712).

The F28044 device contains these two blocks (M0/M1) of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages.

3.2.7 L0, L1 SARAMs

The F28044 device contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K, L1-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to both program and data space.

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3.2.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 3-3. Boot Mode Selection

MODE DESCRIPTION GPIO34

Boot to Flash/ROM Jump to Flash/ROM address 0x3F 7FF6 1 1 1

You must have programmed a branch instruction here prior

to reset to redirect code execution as desired. SCI-A Boot Load a data stream from SCI-A 1 1 0 SPI-A Boot Load from an external serial SPI EEPROM on SPI-A 1 0 1 I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 0

the I2C bus eCAN-A Boot Reserved. This mode should not be used. 0 1 1 Boot to M0 SARAM Jump to M0 SARAM address 0x00 0000. 0 1 0 Boot to OTP Jump to OTP address 0x3D 7800 0 0 1 Parallel I/O Boot Load data from GPIO0 - GPIO15 0 0 0

GPIO18 GPIO29

SPICLKA SCITXDA

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.2.9 Security

The device supports high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit "KEY" value, which matches the value stored in the password locations within the Flash.

For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data, but must be programmed to 0x0000 when the Code Security Password is programmed. If security is not a concern, addresses 0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data variables and should not contain program code.

The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device.

NOTE

Code Security Module Disclaimer

THE CODE SECURITY MODULE ("CSM") INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

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3.2.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F28044 device, 43 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

3.2.11 External Interrupts (XINT1, XINT2, XNMI)

The F28044 device supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be configured to trigger any external interrupt.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.2.12 Oscillator and PLL

The F28044 device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.13 Watchdog

The F28044 device contains a watchdog timer. The user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be disabled if necessary.

3.2.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.

3.2.15 Low-Power Modes

The F28044 device is full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.

HALT: Turns off the internal oscillator. This mode basically shuts down the device and places it in

those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode.

An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event

the lowest possible power consumption mode. A reset or external signal can wake the device from this mode.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.2.16 Peripheral Frames 0, 1, 2 (PFn)

The F28044 device segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Control, Programming, Erase, Verify Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers (dual-mapped)

PF1: GPIO: GPIO MUX Configuration and Control Registers

ePWM: Enhanced Pulse Width Modulator Module and Registers

PF2: SYS: System Control Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Result Register I2C: Inter-Integrated Circuit Module and Registers

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes.

3.2.18 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.

3.2.19 Control Peripherals

The F28044 device supports the following peripherals which are used for embedded control and communication:

ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation,

adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM features.

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two

sample-and-hold units for simultaneous sampling.

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3.2.20 Serial Port Peripherals

The F28044 device supports the following serial communication peripherals:

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the F28044 device, the SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the F28044 device, the SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

I2C: The inter-integrated circuit (I2C) module provides an interface between a DSP and other

devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version

2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module. On the F28044 device, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.

3.3 Register Map

The F28044 device contains three peripheral register spaces. The spaces are categorized as follows:

Peripheral These are peripherals that are mapped directly to the CPU memory bus. Frame 0: See Table 3-4

Peripheral These are peripherals that are mapped to the 32-bit peripheral bus. Frame 1 See Table 3-5

Peripheral These are peripherals that are mapped to the 16-bit peripheral bus. Frame 2: See Table 3-6

Table 3-4. Peripheral Frame 0 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

Device Emulation Registers 0x0880 - 0x09FF 384 EALLOW protected FLASH Registers Code Security Module Registers 0x0AE0 - 0x0AEF 16 EALLOW protected

ADC Result Registers (dual-mapped) 0xB00 - 0xB0F 16 CPU-TIMER0/1/2 Registers 0x0C00 - 0x0C3F 64 Not EALLOW protected PIE Registers 0x0CE0 - 0x0CFF 32 PIE Vector Table 0x0D00 - 0x0DFF 256 EALLOW protected

(1) Registers in Frame 0 support 16-bit and 32-bit accesses. (2) Missing segments of memory space are reserved and should not be used in applications. (3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(4) The Flash Registers are also protected by the Code Security Module (CSM).

(4)

0x0A80 - 0x0ADF 96

(1) (2)

EALLOW protected CSM Protected

(3)

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 3-5. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

ePWM1 + HRPWM Registers 0x6800 - 0x683F 64 ePWM2 + HRPWM Registers 0x6840 - 0x687F 64 ePWM3 + HRPWM Registers 0x6880 - 0x68BF 64 ePWM4 + HRPWM Registers 0x68C0 - 0x68FF 64 ePWM5 + HRPWM Registers 0x6900 - 0x693F 64 ePWM6 + HRPWM Registers 0x6940 - 0x697F 64 ePWM7 + HRPWM Registers 0x6980 - 0x69BF 64 ePWM8 + HRPWM Registers 0x69C0 - 0x69FF 64 ePWM9 + HRPWM Registers 0x6600 - 0x663F 64 ePWM10 + HRPWM Registers 0x6640 - 0x667F 64 ePWM11 + HRPWM Registers 0x6680 - 0x66BF 64 ePWM12 + HRPWM Registers 0x66C0 - 0x66FF 64 ePWM13 + HRPWM Registers 0x6700 - 0x673F 64 ePWM14 + HRPWM Registers 0x6740 - 0x677F 64 ePWM15 + HRPWM Registers 0x6780 - 0x67BF 64 ePWM16 + HRPWM Registers 0x67C0 - 0x67FF 64 GPIO Control Registers 0x6F80 - 0x6FBF 128 EALLOW protected GPIO Data Registers 0x6FC0 - 0x6FDF 32 Not EALLOW protected GPIO Interrupt and LPM Select Registers 0x6FE0 - 0x6FFF 32 EALLOW protected

(1) All 32-bit accesses are aligned to even address boundaries. (2) Missing segments of memory space are reserved and should not be used in applications.

(1) (2)

Some ePWM registers are EALLOW protected. See Table 4-2

Table 3-6. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE

System Control Registers 0x7010 - 0x702F 32 EALLOW Protected SPI-A Registers 0x7040 - 0x704F 16 SCI-A Registers 0x7050 - 0x705F 16 External Interrupt Registers 0x7070 - 0x707F 16 Not EALLOW Protected ADC Registers 0x7100 - 0x711F 32 I2C Registers 0x7900 - 0x792F 48

(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written). (2) Missing segments of memory space are reserved and should not be used in applications.

(1) (2)

3.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-7 .

Table 3-7. Device Emulation Registers

NAME ADDRESS RANGE SIZE (x16) DESCRIPTION

DEVICECNF 2 Device Configuration Register PARTID 0x0882 1 Part ID Register 0x00FC - F28044

REVID 0x0883 1 Revision ID Register 0x0000 - Silicon Rev. 0 - TMX or TMS PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register

0x0880 0x0881

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XINT2

C28

CPU

CPU TIMER 2 (for TI/RTOS)

CPU TIMER 0

Watchdog

Peripherals

(SPI, SCI, I2C, ePWM, ADC)

TINT0

Interrupt Control

XNMICR(15:0)

XINT1

Interrupt Control

XINT1

XINT1CR(15:0)

Interrupt Control

XINT2

XINT2CR(15:0)

GPIO

MUX

WDINT

INT1 to

INT12

INT13

INT14

NMI

XINT1CTR(15:0)

XINT2CTR(15:0)

XNMICTR(15:0)

CPU TIMER 1 (for TI)

TINT2

Low Power Modes

LPMINT

WAKEINT

TINT1

int13_select

XNMI_XINT13

GPIO0.int

GPIO31.int

ADC

XINT2SOC

GPIOXINT1SEL(4:0)

GPIOXINT2SEL(4:0)

GPIOXNMISEL(4:0)

nmi_select

MUX

PIE

96 InterruptsMUXMUX

MUX

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.5 Interrupts

Figure 3-3 shows how the various interrupt sources are multiplexed within the F28044 device.

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Figure 3-3. External and PIE Interrupt Sources

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INT12

MUX

INT11

INT2

INT1

CPU

(Enable)(Flag)

INTx

INTx.8

PIEIERx(8:1) PIEIFRx(8:1)

MUX

INTx.7

INTx.6

INTx.5

INTx.4

INTx.3

INTx.2

INTx.1

From

Peripherals or

External

Interrupts

(Enable) (Flag)

IER(12:1)IFR(12:1)

Global

Enable

INTM

PIEACKx

(Enable/Flag)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. On the F28044 device, 43 of these are used by peripherals as shown in Table 3-8 .

Figure 3-4. Multiplexing of Interrupts Using the PIE Block

Table 3-8. PIE Peripheral Interrupts

CPU

INTERRUPTS

INT1 XINT2 XINT1 Reserved

INT2

INT3 INT4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT6 Reserved Reserved Reserved Reserved Reserved Reserved INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT8 Reserved Reserved Reserved Reserved Reserved Reserved

INT9 Reserved Reserved Reserved Reserved Reserved Reserved

INT10

INT11 INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These

interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

WAKEINT TINT0 ADCINT SEQ2INT SEQ1INT (LPM/WD) (TIMER 0) (ADC) (ADC) (ADC)

EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT

(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM8_INT EPWM7_INT EPWM6T_INTn EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT

(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)

EPWM16_TZINT EPWM15_TZINT EPWM14_TZINT EPWM13_TZINT EPWM12_TZINT EPWM11_TZINT EPWM10_TZINT EPWM9_TZINT

(ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9)

EPWM16_INT EPWM15_INT EPWM14_INT EPWM13_INT EPWM12_INT EPWM11_INT EPWM10_INT EPWM9_INT

(ePWM16) (ePWM15) (ePWM14) (ePWM13) (ePWM12) (ePWM11) (ePWM10) (ePWM9)

1. No peripheral within the group is asserting interrupts.

2. No peripheral interrupts are assigned to the group (example PIE group 12).

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PIE INTERRUPTS

(1)

SPITXINTA SPIRXINTA

(SPI-A) (SPI-A)

I2CINT2A I2CINT1A

(I2C-A) (I2C-A)

SCITXINTA SCIRXINTA

(SCI-A) (SCI-A)

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Table 3-9. PIE Configuration and Control Registers

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

NAME ADDRESS SIZE (X16) DESCRIPTION

PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA 6 Reserved

0x0CFF

(1)

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

3.5.1 External Interrupts

Table 3-10. External Interrupt Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XINT1CR 0x7070 1 XINT1 control register XINT2CR 0x7071 1 XINT2 control register

reserved 5 XNMICR 0x7077 1 XNMI control register

XINT1CTR 0x7078 1 XINT1 counter register XINT2CTR 0x7079 1 XINT2 counter register

reserved 5 XNMICTR 0x707F 1 XNMI counter register

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0x7072 0x7076

0x707A 0x707E

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PLL

Power Modes Control

Watchdog

Block

28x CPU

Peripheral Bus

Low-Speed Peripherals

SCI-A, SPI-A

Peripheral

Registers

High-Speed Prescaler

Low-Speed Prescaler

Clock Enables

GPIO MUX

System Control

Registers

XCLKIN

ADC

Registers

12-Bit ADC

16 ADC inputs

LSPCLK

I/O

Peripheral Reset

SYSCLKOUT

(A)

XRS

Reset

GPIOs

Peripheral

Registers

I/O

OSC

CLKIN

(A)

HSPCLK

I2C-A

Peripheral

Registers

I/O

ePWM 1−16

Peripheral

Registers

CPU

Timers

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide (literature number SPRU712 ).

3.6 System Control

This section describes the F28044 device oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-5 shows the various clock and reset domains in the F28044 device that will be discussed.

A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT).

Figure 3-5. Clock and Reset Domains

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TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-11 .

Table 3-11. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

XCLK 0x7010 1 XCLKOUT Pin Control, X1 and XCLKIN Status Register PLLSTS 0x7011 1 PLL Status Register

reserved 7 PCLKCR2 0x7019 1 Peripheral Clock Control Register 2

HISPCP 0x701A 1 High-Speed Peripheral Clock Prescaler Register (for HSPCLK) LOSPCP 0x701B 1 Low-Speed Peripheral Clock Prescaler Register (for LSPCLK) PCLKCR0 0x701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x701D 1 Peripheral Clock Control Register 1 LPMCR0 0x701E 1 Low Power Mode Control Register 0

reserved 1 PLLCR 0x7021 1 PLL Control Register

SCSR 0x7022 1 System Control and Status Register WDCNTR 0x7023 1 Watchdog Counter Register reserved 0x7024 1 WDKEY 0x7025 1 Watchdog Reset Key Register

reserved 3 WDCR 0x7029 1 Watchdog Control Register reserved 6

(1) All of the registers in this table are EALLOW protected.

0x7012 0x7018

0x701F 0x7020

0x7026 0x7028

0x702A 0x702F

(1)

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XCLKIN

(3.3-V clock input)

On chip

oscillator

xor

PLLSTS[OSCOFF]

OSCCLK

PLL

VCOCLK

4-bit PLL Select (PLLCR)

OSCCLK or

VCOCLK

CLKIN

OSCCLK

PLLSTS[PLLOFF]

n ≠ 0

PLLSTS[CLKINDIV]

External Clock Signal

(Toggling 0−V

DDIO

)

XCLKIN

External Clock Signal

(Toggling 0−VDD)

XCLKIN

X2X1

Crystal

XCLKIN

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.6.1 OSC and PLL Block

Figure 3-6 shows the OSC and PLL block on the F28044.

The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28044 device using the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following configurations:

1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V

2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V

The three possible input-clock configurations are shown in Figure 3-7 through Figure 3-9

Figure 3-6. OSC and PLL Block Diagram

DDIO

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Figure 3-7. Using a 3.3-V External Oscillator

Figure 3-8. Using a 1.8-V External Oscillator

Figure 3-9. Using the Internal Oscillator

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3.6.1.1 External Reference Oscillator Clock Option

The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:

• Fundamental mode, parallel resonant

• C

(load capacitance) = 12 pF

• C

= C

L1 shunt

= 24 pF

= 6 pF

• ESR range = 30 to 60 Ω

TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range.

3.6.1.2 PLL-Based Clock Module

The F28044 device has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK cycles.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 3-12. PLLCR Register Bit Definitions

PLLCR[DIV]

0000 (PLL bypass) 0 OSCCLK/2 0000 (PLL bypass) 1 OSCCLK

1011-1111 0 reserved

(1) This register is EALLOW protected. (2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output

clock from the CPU. The frequency of SYSCLKOUT is the same as CLKIN.

(1)

0001 0 (OSCCLK*1)/2 0010 0 (OSCCLK*2)/2 0011 0 (OSCCLK*3)/2 0100 0 (OSCCLK*4)/2 0101 0 (OSCCLK*5)/2 0110 0 (OSCCLK*6)/2 0111 0 (OSCCLK*7)/2 1000 0 (OSCCLK*8)/2 1001 0 (OSCCLK*9)/2 1010 0 (OSCCLK*10)/2

PLLSTS[CLKINDIV]

NOTE

PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be changed once PLLSTS[CLKINDIV] is set.

SYSCLKOUT

(CLKIN)

(2)

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the device.

• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 3-13. Possible PLL Configuration Modes

PLL MODE REMARKS PLLSTS[CLKINDIV]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block 0 OSCCLK/2

PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

PLL Bypass

PLL Enable 0 OSCCLK*n/2

is disabled in this mode. This can be useful to reduce system noise and for low before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN. PLL Bypass is the default PLL configuration upon power-up or after an external 0 OSCCLK/2

reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks.

3.6.1.3 Loss of Input Clock

In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or absent.

Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.

SYSCLKOUT

(CLKIN)

1 OSCCLK

3.6.2 Watchdog Block

The watchdog block on the F28044 is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-10 shows the various functional blocks within the watchdog module.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory and the V

rail.

DD3VFL

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/512

OSCCLK

WDCR (WDPS(2:0))

WDCLK

WDCNTR(7:0)

WDKEY(7:0)

Good Key

1 0 1

WDCR (WDCHK(2:0))

Bad WDCHK Key

WDCR (WDDIS)

Clear Counter

SCSR (WDENINT)

Watchdog

Prescaler

Generate

Output Pulse

(512 OSCCLKs)

8-Bit

Watchdog

Counter

CLR

WDRST

WDINT

Watchdog

55 + AA

Key Detector

XRS

Core-reset

WDRST

(A)

Internal

Pullup

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-10. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7 , Low-Power Modes Block, for details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

3.7 Low-Power Modes Block

The low-power modes on the F28044 device are similar to the 240x devices. Table 3-14 summarizes the various modes.

Table 3-14. Low-Power Modes

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

IDLE 00 On On On

STANDBY 01 Off Off

HALT 1X (oscillator and PLL turned off, Off Off

(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will

exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode.

(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is

still functional while on the 24x/240x the clock is turned off.

(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(watchdog still running) signal, debugger

watchdog not functional)

On XRS, Watchdog interrupt, GPIO Port A

Off

(2)

XRS, Watchdog interrupt, any enabled interrupt, XNMI

XRS, GPIO Port A signal, XNMI, debugger

(3)

(1)

(3)

, XNMI

The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by

the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.

HALT Mode: Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device

from HALT mode. The user selects the signal in the GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x System Control and Interrupts Reference Guide (literature number SPRU712) for details.

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4 Peripherals

Borrow

Reset

Timer Reload

SYSCLKOUT

TCR.4

(Timer Start Status)

TINT

16-Bit Timer Divide-Down

TDDRH:TDDR

32-Bit Timer Period

PRDH:PRD

32-Bit Counter

TIMH:TIM

16-Bit Prescale Counter

PSCH:PSC

Borrow

The integrated peripherals of the F28044 device are described in the following subsections:

• Three 32-bit CPU-Timers

• Up to 16 enhanced PWM modules (ePWM1-16)

• Enhanced analog-to-digital converter (ADC) module

• Serial communications interface module (SCI-A)

• Serial peripheral interface (SPI) module (SPI-A)

• Inter-integrated circuit module (I2C)

• Digital I/O and shared pin functions

4.1 32-Bit CPU-Timers 0/1/2

There are three 32-bit CPU-timers on the F28044 device (CPU-TIMER0/1/2). CPU-Timer 1 is reserved for TI system functions and Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0

can be used in user applications. These timers are different from the timers that are present in the ePWM modules.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

NOTE

NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.

Figure 4-1. CPU-Timers

In the F28044 device, the timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in

Figure 4-2 .

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INT1

INT12

INT14

C28x

TINT2

TINT0

PIE

CPU-TIMER 0

CPU-TIMER 2

(Reserved for

DSP/BIOS)

INT13

TINT1

CPU-TIMER 1

(Reserved for TI

system functions)

XINT13

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. The timer registers are connected to the memory bus of the C28x processor. B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock. C. While TIMER1 is reserved, INT13 is not reserved and the user can use XINT13 connected to INT13.

Figure 4-2. CPU-Timer Interrupt Signals and Output Signal

The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide (literature number SPRU712 ).

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register reserved 0x0C15 1

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PIE

TZ1

to TZ6

Peripheral Bus

ePWM1 module

ePWM2 module

ePWMx module

EPWM1SYNCI

EPWM2SYNCI

EPWM2SYNCO

EPWMxSYNCI

EPWMxSYNCO

ADC

GPIO

MUX

EPWM1SYNCI

EPWM1SYNCO

ADCSOCx0

EPWMxA

EPWMxB

EPWM2A

EPWM2B

EPWM1A

EPWM1B

EPWM1INT

EPWM1SOC

EPWM2INT

EPWM2SOC

EPWMxINT

EPWMxSOC

to eCAP1

module

(sync in)

TZ1 to TZ6

EPWM1SYNCO

Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High

reserved 40

0x0C18

0x0C3F

4.2 Enhanced PWM Modules (ePWM1-16)

The F28044 device contains up to 16 enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRU791) for details.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 4-3. Multiple PWM Modules

The F28044 device contains 16 enhanced PWM modules (EPWM) and 16 high resolution PWM modules (HRPWM). The EPWM modules synchronize input/output and the ADC start of conversion (SOCA/B)

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

signals are regrouped in the F28044. At reset, EPWMMODE bits in the GPAMCFG register configure the sync signals to be compatible to the TMS320F2808 device. In F28044 mode, the ePWMMODE bits are set to 11 to select the EPWMA signals on all 16 GPIOs (GPIO0-GPIO15). This mode selection also reconfigures the EPWM1 SYNCOUT to be connected to four groups of EPWM modules and as EPWMSYNCO signals on the pin:

• Group 1: EPWM2, EPWM3, EPWM4

• Group 2: EPWM5, EPWM6, EPWM7, EPWM8

• Group 3: EPWM9, EPWM10, EPWM11, EPWM12

• Group 4: EPWM13, EPWM14, EPWM15, EPWM16

See the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) User's Guide (SPRU791) for additional details.

Table 4-2 through Table 4-5 show the complete ePWM register set per module.

Table 4-2. ePWM1-4 Control and Status Registers

NAME EPWM1 EPWM2 EPWM3 EPWM4 DESCRIPTION

TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register

SIZE (x16) / #SHADOW

(1)

(1) Registers that are EALLOW protected.

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Table 4-3. ePWM5-8 Control and Status Registers

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

NAME EPWM5 EPWM6 EPWM7 EPWM8 DESCRIPTION

TBCTL 0x6900 0x6940 0x6980 0x69C0 1 / 0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 0x69C1 1 / 0 Time Base Status Register TBPHSHR 0x6902 0x6942 0x6982 0x69C2 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6903 0x6943 0x6983 0x69C3 1 / 0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 0x69C4 1 / 0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 0x69C5 1 / 1 Time Base Period Register Set CMPCTL 0x6907 0x6947 0x6987 0x69C7 1 / 0 Counter Compare Control Register CMPAHR 0x6908 0x6948 0x6988 0x69C8 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6909 0x6949 0x6989 0x69C9 1 / 1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 0x69CA 1 / 1 Counter Compare B Register Set AQCTLA 0x690B 0x694B 0x698B 0x69CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 0x69CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 0x69CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 0x69CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 0x69CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 0x69D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 0x69D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 0x69D2 1 / 0 Trip Zone Select Register TZCTL 0x6914 0x6954 0x6994 0x69D4 1 / 0 Trip Zone Control Register TZEINT 0x6915 0x6955 0x6995 0x69D5 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6916 0x6956 0x6996 0x69D6 1 / 0 Trip Zone Flag Register TZCLR 0x6917 0x6957 0x6997 0x69D7 1 / 0 Trip Zone Clear Register TZFRC 0x6918 0x6958 0x6998 0x69D8 1 / 0 Trip Zone Force Register ETSEL 0x6919 0x6959 0x6999 0x69D9 1 / 0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 0x69DA 1 / 0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 0x69DB 1 / 0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 0x69DC 1 / 0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 0x69DD 1 / 0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 0x69DE 1 / 0 PWM Chopper Control Register HRCNFG 0x6920 0x6960 0x69A0 0x69E0 1 / 0 HRPWM Configuration Register

SIZE (x16) /

#SHADOW

(1)

(1) Registers that are EALLOW protected.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 4-4. ePWM9-12 Control and Status Registers

NAME EPWM9 EPWM10 EPWM11 EPWM12 DESCRIPTION

TBCTL 0x6600 0x6640 0x6680 0x66C0 1 / 0 Time Base Control Register TBSTS 0x6601 0x6641 0x6681 0x66C1 1 / 0 Time Base Status Register TBPHSHR 0x6602 0x6642 0x6682 0x66C2 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6603 0x6643 0x6683 0x66C3 1 / 0 Time Base Phase Register TBCTR 0x6604 0x6644 0x6684 0x66C4 1 / 0 Time Base Counter Register TBPRD 0x6605 0x6645 0x6685 0x66C5 1 / 1 Time Base Period Register Set CMPCTL 0x6607 0x6647 0x6687 0x66C7 1 / 0 Counter Compare Control Register CMPAHR 0x6608 0x6648 0x6688 0x66C8 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6609 0x6649 0x6689 0x66C9 1 / 1 Counter Compare A Register Set CMPB 0x660A 0x664A 0x668A 0x66CA 1 / 1 Counter Compare B Register Set AQCTLA 0x660B 0x664B 0x668B 0x66CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x660C 0x664C 0x668C 0x66CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x660D 0x664D 0x668D 0x66CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x660E 0x664E 0x668E 0x66CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x660F 0x664F 0x668F 0x66CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6610 0x6650 0x6690 0x66D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6611 0x6651 0x6691 0x66D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6612 0x6652 0x6692 0x66D2 1 / 0 Trip Zone Select Register TZCTL 0x6614 0x6654 0x6694 0x66D4 1 / 0 Trip Zone Control Register TZEINT 0x6615 0x6655 0x6695 0x66D5 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6616 0x6656 0x6696 0x66D6 1 / 0 Trip Zone Flag Register TZCLR 0x6617 0x6657 0x6697 0x66D7 1 / 0 Trip Zone Clear Register TZFRC 0x6618 0x6658 0x6698 0x66D8 1 / 0 Trip Zone Force Register ETSEL 0x6619 0x6659 0x6699 0x66D9 1 / 0 Event Trigger Selection Register ETPS 0x661A 0x665A 0x669A 0x66DA 1 / 0 Event Trigger Prescale Register ETFLG 0x661B 0x665B 0x669B 0x66DB 1 / 0 Event Trigger Flag Register ETCLR 0x661C 0x665C 0x669C 0x66DC 1 / 0 Event Trigger Clear Register ETFRC 0x661D 0x665D 0x669D 0x66DD 1 / 0 Event Trigger Force Register PCCTL 0x661E 0x665E 0x669E 0x66DE 1 / 0 PWM Chopper Control Register HRCNFG 0x6620 0x6660 0x66A0 0x66E0 1 / 0 HRPWM Configuration Register

SIZE (x16) /

#SHADOW

(1)

(1) Registers that are EALLOW protected.

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Table 4-5. ePWM13-16 Control and Status Registers

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

NAME EPWM13 EPWM14 EPWM15 EPWM16 DESCRIPTION

TBCTL 0x6700 0x6740 0x6780 0x67C0 1 / 0 Time Base Control Register TBSTS 0x6701 0x6741 0x6781 0x67C1 1 / 0 Time Base Status Register TBPHSHR 0x6702 0x6742 0x6782 0x67C2 1 / 0 Time Base Phase HRPWM Register TBPHS 0x6703 0x6743 0x6783 0x67C3 1 / 0 Time Base Phase Register TBCTR 0x6704 0x6744 0x6784 0x67C4 1 / 0 Time Base Counter Register TBPRD 0x6705 0x6745 0x6785 0x67C5 1 / 1 Time Base Period Register Set CMPCTL 0x6707 0x6747 0x6787 0x67C7 1 / 0 Counter Compare Control Register CMPAHR 0x6708 0x6748 0x6788 0x67C8 1 / 1 Time Base Compare A HRPWM Register CMPA 0x6709 0x6749 0x6789 0x67C9 1 / 1 Counter Compare A Register Set CMPB 0x670A 0x674A 0x678A 0x67CA 1 / 1 Counter Compare B Register Set AQCTLA 0x670B 0x674B 0x678B 0x67CB 1 / 0 Action Qualifier Control Register For Output A AQCTLB 0x670C 0x674C 0x678C 0x67CC 1 / 0 Action Qualifier Control Register For Output B AQSFRC 0x670D 0x674D 0x678D 0x67CD 1 / 0 Action Qualifier Software Force Register AQCSFRC 0x670E 0x674E 0x678E 0x67CE 1 / 1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x670F 0x674F 0x678F 0x67CF 1 / 1 Dead-Band Generator Control Register DBRED 0x6710 0x6750 0x6790 0x67D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6711 0x6751 0x6791 0x67D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6712 0x6752 0x6792 0x67D2 1 / 0 Trip Zone Select Register TZCTL 0x6714 0x6754 0x6794 0x67D4 1 / 0 Trip Zone Control Register TZEINT 0x6715 0x6755 0x6795 0x67D5 1 / 0 Trip Zone Enable Interrupt Register TZFLG 0x6716 0x6756 0x6796 0x67D6 1 / 0 Trip Zone Flag Register TZCLR 0x6717 0x6757 0x6797 0x67D7 1 / 0 Trip Zone Clear Register TZFRC 0x6718 0x6758 0x6798 0x67D8 1 / 0 Trip Zone Force Register ETSEL 0x6719 0x6759 0x6799 0x67D9 1 / 0 Event Trigger Selection Register ETPS 0x671A 0x675A 0x679A 0x67DA 1 / 0 Event Trigger Prescale Register ETFLG 0x671B 0x675B 0x679B 0x67DB 1 / 0 Event Trigger Flag Register ETCLR 0x671C 0x675C 0x679C 0x67DC 1 / 0 Event Trigger Clear Register ETFRC 0x671D 0x675D 0x679D 0x67DD 1 / 0 Event Trigger Force Register PCCTL 0x671E 0x675E 0x679E 0x67DE 1 / 0 PWM Chopper Control Register HRCNFG 0x6720 0x6760 0x67A0 0x67E0 1 / 0 HRPWM Configuration Register

SIZE (x16) /

#SHADOW

(1)

(1) Registers that are EALLOW protected.

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CTR=PRD

TBPRD shadow (16)

TBPRD active (16)

Counter

up/down

(16 bit)

TBCNT

active (16)

TBCTL[CNTLDE]

TBCTL[SWFSYNC] (software forced sync)

EPWMxSYNCI

CTR=ZERO

CTR_Dir

CTR=CMPB

Disabled

Sync

in/out

select

Mux

TBCTL[SYNCOSEL]

EPWMxSYNCO

TBPHS active (24)

TBPHSHR (8)

Phase control

Time−base (TB)

CTR=CMPA

CMPA active (24)

CMPA shadow (24)

Action

qualifier

(AQ)

Counter compare (CC)

CMPB active (16)

CTR=CMPB

CMPB shadow (16)

CMPAHR (8)

EPWMA

EPWMB

Dead band

(DB) (PC)

chopper

PWM

zone

(TZ)

Trip

CTR = ZERO

EPWMxAO

EPWMxBO EPWMxTZINT TZ1 to TZ6

HiRes PWM (HRPWM)

CTR = PRD

CTR = ZERO

CTR = CMPB

CTR = CMPA

CTR_Dir

Event

trigger

and

interrupt

(ET)

EPWMxINT EPWMxSOCA EPWMxSOCB

CTR=ZERO

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

4.3 Hi-Resolution PWM (HRPWM)

Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

• Significantly extends the time resolution capabilities of conventionally derived digital PWM

• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies

greater than ~200 KHz when using a CPU/System clock of 100 MHz.

• This capability can be utilized in both duty cycle and phase-shift control methods.

• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and

Phase registers of the ePWM module.

• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

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4.4 Enhanced Analog-to-Digital Converter (ADC) Module

Digital Value + 0,

Digital Value + 4096

Input Analog Voltage * ADCLO

when input ≤ 0 V

when 0 V < input < 3 V

when input ≥ 3 VDigital V alue + 4095,

A simplified functional block diagram of the ADC module is shown in Figure 4-5 . The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H

• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)

• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS

• 16-channel, MUXed inputs

• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion

can be programmed to select any 1 of 16 input channels

• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers)

• Sixteen result registers (individually addressable) to store conversion values – The digital value of the input analog voltage is derived by:

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. All fractional values are truncated.

• Multiple triggers as sources for the start-of-conversion (SOC) sequence – S/W - software immediate start – ePWM start of conversion – XINT2 ADC start of conversion

• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.

• Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to

synchronize conversions.

• SOCA and SOCB triggers can operate independently in dual-sequencer mode.

• Sample-and-hold (S/H) acquisition time window has separate prescale control.

The ADC module in the F28044 device has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-5 shows the block diagram of the ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

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Result Registers

EPWMSOCB

S/W

GPIO/XINT2

_ADCSOC

EPWMSOCA

S/W

Sequencer 2

Sequencer 1

SOCSOC

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

Module

ADC

12-Bit

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

Control Block

High-Speed

Prescaler

HSPCLK

ADCENCLK

DSP

SYSCLKOUT

S/H

HALT

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 4-5. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( V V

, V

DD2A18

, V

DDA2

DDAIO

) from the digital supply.Figure 4-6 shows the ADC pin connections for the F28044

device.

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

– ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the

clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module, however, will be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

– HALT: This mode only affects the analog module. It does not affect the registers.

In this mode, the ADC module goes into low-power mode. This mode also will stop the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.

NOTE

DD1A18

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ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADC Reference Positive Output

ADCREFMADC Reference Medium Output

ADC Power

ADC Analog and Reference I/O Power

Analog input 0−3 V with respect to ADCLO

Connect to analog ground

22 kW

2.2 mF

(A)

2.2 mF

(A)

ADC Analog Power Pin (1.8 V) ADC Analog Power Pin (1.8 V)

ADC Analog Power Pin (3.3 V)

ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V)

ADCREFP and ADCREFM should not be loaded by external circuitry

ADC Analog Ground Pin

ADC 16-Channel Analog Inputs

Float or ground if internal reference is used

ADC Analog Ground Pin ADC Analog Ground Pin

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 4-6 shows the ADC pin-biasing for internal reference and Figure 4-7 shows the ADC pin-biasing for

external reference.

Figure 4-6. ADC Pin Connections With Internal Reference

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ADCINA[7:0] ADCINB[7:0]

ADCLO

ADCREFIN

ADC External Current Bias Resistor ADCRESEXT

ADCREFP

DD1A18

DD2A18

SS1AGND

SS2AGND

DDAIO

SSAIO

DDA2

SSA2

ADC Reference Positive Output

ADCREFMADC Reference Medium Output

ADC Analog Power

ADC Analog and Reference I/O Power

Analog input 0−3 V with respect to ADCLO

Connect to Analog Ground

22 kW

2.2 mF

(A)

2.2 mF

(A)

ADCREFP and ADCREFM should not

be loaded by external circuitry

ADC 16-Channel Analog Inputs

Connect to 1.500, 1.024, or 2.048-V precision source

(D)

ADC Analog Power Pin (1.8 V) ADC Analog Power Pin (1.8 V)

ADC Analog I/O Ground Pin

ADC Analog Power Pin (3.3 V) ADC Analog Ground Pin

ADC Analog Ground Pin ADC Analog Ground Pin

ADC Analog Power Pin (3.3 V)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. TAIYO YUDEN LMK212BJ225MG-T or equivalent B. External decoupling capacitors are recommended on all power pins. C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on

the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy of this voltage source.

Figure 4-7. ADC Pin Connections With External Reference

The temperature rating of any recommended component must match the rating of the end product.

4.5 ADC Connections if the ADC Is Not Used

It is recommended that the connections for the analog power pins be kept even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application:

• V

• ADCLO – Connect to V

• ADCREFIN – Connect to V

• ADCREFP/ADCREFM – Connect a 100 nF cap to V

• ADCRESEXT – Connect a 20-k Ω resistor (very loose tolerance) to V

• ADCINAn, ADCINBn - Connect to V

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.

When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (V

The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6 .

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DD1A18

, V

DDA2 SS1AGND

DDAIO

SS1AGND

DD2A18

– Connect to V

SS2AGND

– Connect to V

SS2AGND

, V

SSA2

NOTE

DDIO

, V

)

– Connect to V

SSAIO

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Table 4-6. ADC Registers

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(1)

NAME ADDRESS

ADCTRL1 0x7100 1 ADC Control Register 1 ADCTRL2 0x7101 1 ADC Control Register 2

ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x7107 1 ADC Auto-Sequence Status Register ADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x7110 0x0B08 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9

ADCRESULT10 0x7112 0x0B0A 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x7113 0x0B0B 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x7114 0x0B0C 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0x7115 0x0B0D 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0x7116 0x0B0E 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x7117 0x0B0F 1 ADC Conversion Result Buffer Register 15

ADCTRL3 0x7118 1 ADC Control Register 3

ADCST 0x7119 1 ADC Status Register

Reserved 2

ADCREFSEL 0x711C 1 ADC Reference Select Register

ADCOFFTRIM 0x711D 1 ADC Offset Trim Register

Reserved 2 ADC Status Register

(1) The registers in this column are Peripheral Frame 2 Registers. (2) The ADC result registers are dual mapped in the F28044 DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and

left justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.

(1)

ADDRESS

0x711A 0x711B

0x711E 0x711F

(2)

SIZE (x16) DESCRIPTION

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Baud rate =

LSPCLK

(BRR ) 1) *8

when BRR ≠ 0

Baud rate = when BRR = 0

Max bit rate +

100 MHz

+ 6.25 106bńs

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

4.6 Serial Communications Interface (SCI) Module (SCI-A)

The F28044 device includes a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

• Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

• Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

• Four error-detection flags: parity, overrun, framing, and break detection

• Two wake-up multiprocessor modes: idle-line and address bit

• Half- or full-duplex operation

• Double-buffered receive and transmit functions

• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

• Separate enable bits for transmitter and receiver interrupts (except BRKDT)

•

• NRZ (non-return-to-zero) format

• Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

• Auto baud-detect hardware logic

• 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 4-7 .

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Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 4-7. SCI-A Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

SCICCRA 0x7050 1 SCI-A Communications Control Register

SCICTL1A 0x7051 1 SCI-A Control Register 1

SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits

SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits

SCICTL2A 0x7054 1 SCI-A Control Register 2

SCIRXSTA 0x7055 1 SCI-A Receive Status Register

SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register

SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register

SCIFFTXA

SCIFFRXA

SCIFFCTA

SCIPRIA 0x705F 1 SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

(2) (2) (2)

0x705A 1 SCI-A FIFO Transmit Register 0x705B 1 SCI-A FIFO Receive Register 0x705C 1 SCI-A FIFO Control Register

(1)

TMS320F28044

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TX FIFO _0

LSPCLK

WUT

Frame Format and Mode

Even/Odd Enable

Parity

SCI RX Interrupt select logic

BRKDT

RXRDY

SCIRXST.6

SCICTL1.3

SCICTL2.1

RX/BK INT ENA

SCIRXD

SCIRXST.1

TXENA

SCI TX Interrupt select logic

TX EMPTY

TXRDY

SCICTL2.0

TX INT ENA

SCITXD

RXENA

SCIRXD

RXWAKE

SCICTL1.6

RX ERR INT ENA

TXWAKE

SCITXD

SCICCR.6 SCICCR.5

SCITXBUF.7-0

SCIHBAUD. 15 - 8

Baud Rate

MSbyte

SCILBAUD. 7 - 0

Transmitter-Data

Buffer Register

SCICTL2.6

SCICTL2.7

Baud Rate

LSbyte

RXSHF Register

TXSHF

SCIRXST.5

TX FIFO _1

-----

TX FIFO _15

TX FIFO registers

TX FIFO

TX Interrupt

Logic

TXINT

SCIFFTX.14

RX FIFO _15

SCIRXBUF.7-0

Receive Data

Buffer register

SCIRXBUF.7-0

-----

RX FIFO_1

RX FIFO _0

RX FIFO registers

SCICTL1.0

RX Interrupt

Logic

RXINT

RX FIFO

SCIFFRX.15

RXFFOVF

RX Error

SCIRXST.7

PEFE OE

RX Error

SCIRXST.4 - 2

To CPU

AutoBaud Detect logic

SCICTL1.1

SCIFFENA

Interrupts

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 4-8 shows the SCI module block diagram.

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Figure 4-8. Serial Communications Interface (SCI) Module Block Diagram

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4.7 Serial Peripheral Interface (SPI) Module (SPI-A)

Baud rate =

LSPCLK

(SPIBRR ) 1)

when SPIBRR = 3 to 127

Baud rate = when SPIBRR = 0,1, 2

The F28044 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

• Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

• Two operational modes: master and slave Baud rate: 125 different programmable rates.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

• Data word length: one to sixteen data bits

• Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

• Simultaneous receive and transmit operation (transmit function can be disabled in software)

• Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

• Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

• 16-level transmit/receive FIFO

• Delayed transmit control

The SPI port operation is configured and controlled by the registers listed in Table 4-8 .

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 4-8. SPI-A Registers

NAME ADDRESS SIZE (X16) DESCRIPTION

SPICCR 0x7040 1 SPI-A Configuration Control Register SPICTL 0x7041 1 SPI-A Operation Control Register SPISTS 0x7042 1 SPI-A Status Register SPIBRR 0x7044 1 SPI-A Baud Rate Register

SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register

SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register

SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register

SPIDAT 0x7049 1 SPI-A Serial Data Register

SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register

SPIFFRX 0x704B 1 SPI-A FIFO Receive Register

SPIFFCT 0x704C 1 SPI-A FIFO Control Register

SPIPRI 0x704F 1 SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

(1)

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SPICTL.0

SPI INT FLAG

SPI INT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

456 123 0

0123

SPI Bit Rate

State Control

SPIRXBUF

Buffer Register

Clock

Phase

Receiver

Overrun Flag

SPICTL.4

Overrun

INT ENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6 SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

Data Register

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

SW3

To CPU

SW1

SPITXBUF

Buffer Register

RX FIFO _0 RX FIFO _1

−−−−−

RX FIFO _15

TX FIFO registers

TX FIFO _0

TX FIFO _1

−−−−−

TX FIFO _15

RX FIFO registers

TX Interrupt

Logic

RX Interrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVF FLAG

SPIFFRX.15

TX FIFO Interrupt

RX FIFO Interrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

(A)

Figure 4-9 is a block diagram of the SPI in slave mode.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 4-9. SPI Module Block Diagram (Slave Mode)

A. SPISTE is driven low by the master for a slave device.

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

4.8 Inter-Integrated Circuit (I2C)

The F28044 device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces within the F28044 device.

The I2C module has the following features:

• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)

• One 16-bit receive FIFO and one 16-bit transmit FIFO

• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the

following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave

• An additional interrupt that can be used by the CPU when in FIFO mode

• Module enable/disable capability

• Free data format mode

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SYSRS

Data[16]

SYSCLKOUT

Data[16]

Addr[16]

Control

I2CINT1A

I2CINT2A

C28X CPU

GPIO

MUX

I2C−A

System Control

Block

I2CAENCLK

PIE

Block

SDAA

SCLA

Peripheral Bus

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 4-10. I2C Peripheral Module Interfaces

The registers in Table 4-9 configure and control the I2C port operation.

Table 4-9. I2C-A Registers

NAME ADDRESS DESCRIPTION

I2COAR 0x7900 I2C own address register

I2CIER 0x7901 I2C interrupt enable register

I2CSTR 0x7902 I2C status register

I2CCLKL 0x7903 I2C clock low-time divider register

I2CCLKH 0x7904 I2C clock high-time divider register

I2CCNT 0x7905 I2C data count register I2CDRR 0x7906 I2C data receive register I2CSAR 0x7907 I2C slave address register I2CDXR 0x7908 I2C data transmit register I2CMDR 0x7909 I2C mode register

I2CISRC 0x790A I2C interrupt source register

I2CPSC 0x790C I2C prescaler register

I2CFFTX 0x7920 I2C FIFO transmit register

I2CFFRX 0x7921 I2C FIFO receive register

I2CRSR - I2C receive shift register (not accessible to the CPU) I2CXSR - I2C transmit shift register (not accessible to the CPU)

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GPxDAT (read)

Input

Qualification

GPxMUX1/2

High Impedance

Output Control

GPIOx pin

XRS

0 = Input, 1 = Output

Low Power

Modes Block

GPxDIR (latch)

Peripheral 2 Input

Peripheral 3 Input

Peripheral 1 Output Peripheral 2 Output Peripheral 3 Output

Peripheral 1 Output Enable

Peripheral 2 Output Enable

Peripheral 3 Output Enable

00 01

00 01 10

GPxCTRL

Peripheral 1 Input

N/C

GPxPUD

LPMCR0

Internal

Pullup

GPIOLMPSEL

GPxQSEL1/2

GPxSET

GPxDAT (latch)

GPxCLEAR

GPxTOGGLE

GPIOXINT1SEL GPIOXINT2SEL

GPIOXNMISEL

= Default at Reset

PIE

External Interrupt

MUX

Asynchronous

path

Asynchronous path

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

4.9 GPIO MUX

On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 4-11 . Because of the open drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide (literature number SPRU712 ) for details.

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

Figure 4-11. GPIO MUX Block Diagram

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The F28044 supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-10 shows the GPIO register mapping.

Table 4-10. GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)

GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)

GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)

GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)

GPAMCFG 0x6F8E 2 GPIO A Miscellaneous Configuration Register (GPIO0 to 31)

GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 35) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 35) GPBQSEL2 0x6F94 2 reserved

GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 35)

GPBMUX2 0x6F98 2 reserved

GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 35)

GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 35)

reserved 2 reserved

reserved 32

GPADAT 0x6FC0 2 GPIO Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO Data Set Register (GPIO0 to 31)

GPACLEAR 0x6FC4 2 GPIO Data Clear Register (GPIO0 to 31)

GPATOGGLE 0x6FC6 2 GPIO Data Toggle Register (GPIO0 to 31)

GPBDAT 0x6FC8 2 GPIO Data Register (GPIO32 to 35) GPBSET 0x6FCA 2 GPIO Data Set Register (GPIO32 to 35)

GPBCLEAR 0x6FCC 2 GPIO Data Clear Register (GPIO32 to 35)

GPBTOGGLE 0x6FCE 2 GPIO Data Toggle Register (GPIO32 to 35)

reserved 16

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)

GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)

reserved 5

GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

reserved 22

0x6F9E

0x6F9F

0x6FA0 0x6FBF

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

0x6FD0 0x6FDF

0x6FE3 0x6FE7

0x6FEA 0x6FFF

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Table 4-11. F28044 GPIO MUX Table

GPxMUX1/2 DEFAULT AT PERIPHERAL PERIPHERAL PERIPHERAL

(1)

BITS FUNCTION 1,1)

1-0 GPIO0 EPWM1A (O) EPWM1A (O) Reserved Reserved 3-2 GPIO1 EPWM1B (O) EPWM2A (O) Reserved Reserved 5-4 GPIO2 EPWM2A (O) EPWM3A (O) Reserved Reserved 7-6 GPIO3 EPWM2B (O) EPWM4A (O) Reserved Reserved

9-8 GPIO4 EPWM3A (O) EPWM5A (O) Reserved Reserved 11-10 GPIO5 EPWM3B (O) EPWM6A (O) Reserved Reserved 13-12 GPIO6 EPWM4A (O) EPWM7A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) EPWM8A (O) Reserved Reserved 17-16 GPIO8 EPWM5A (O) EPWM9A (O) Reserved ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) EPWM10A (O) Reserved Reserved 21-20 GPIO10 EPWM6A (O) EPWM11A (O) Reserved ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) EPWM12A (O) Reserved Reserved 25-24 GPIO12 TZ1 (I) EPWM13A (O) Reserved Reserved 27-26 GPIO13 TZ2 (I) EPWM14A (O) Reserved Reserved 29-28 GPIO14 TZ3 (I) EPWM15A (O) Reserved Reserved 31-30 GPIO15 TZ4 (I) EPWM16A (O) Reserved Reserved

1-0 GPIO16 SPISIMOA (I/O) Reserved TZ5 (I)

3-2 GPIO17 SPISOMIA (I/O) Reserved TZ6 (I)

5-4 GPIO18 SPICLKA (I/O) Reserved TZ1 (I)

7-6 GPIO19 SPISTEA (I/O) Reserved TZ2 (I)

9-8 GPIO20 Reserved Reserved Reserved 11-10 GPIO21 Reserved Reserved Reserved 13-12 GPIO22 Reserved Reserved Reserved 15-14 GPIO23 Reserved Reserved Reserved 17-16 GPIO24 Reserved Reserved Reserved 19-18 GPIO25 Reserved Reserved Reserved 21-20 GPIO26 Reserved Reserved Reserved 23-22 GPIO27 Reserved Reserved Reserved 25-24 GPIO28 SCIRXDA (I) Reserved TZ5 (I) 27-26 GPIO29 SCITXDA (O) Reserved TZ6 (I) 29-28 GPIO30 Reserved Reserved TZ3 (I) 31-30 GPIO31 Reserved Reserved TZ4 (I)

1-0 GPIO32 SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O)

3-2 GPIO33 SCLA (I/OC ) EPWMSYNCO (O) ADCSOCBO (O)

5-4 GPIO34 Reserved Reserved Reserved

(1) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1. (2) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. (3) The options GPAMCFG(EPWMMODE) = 0, 1 and 1, 0 are reserved. (4) This is the default configuration upon reset.

RESET SELECTION 1

(GPxMUX1/2

BITS = 0,0)

GPAMCFG(EPWMMODE)

(4)

0,0

(2)

(3)

1,1

GPAMUX1

GPAMUX2

GPBMUX1

SELECTION 2

(2)

SELECTION 3

(2)

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GPyCTRL Reg

SYNC

SYSCLKOUT

Qualification

Input Signal Qualified By 3 or 6 Samples

GPIOx

Time between samples

GPxQSEL

Number of Samples

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices:

• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

• Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.

Figure 4-12. Qualification Using Sampling Window

• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).

• No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the F28044 device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

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5 Device Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of 280x-based applications:

Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator

• Application algorithms

• Sample applications code

Hardware Development Tools

• 2808 eZdsp™

• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB™

• Universal 5-V dc power supply

• Documentation and cables

5.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F2808). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical

specifications

TMP Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification

testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

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PREFIX

TMS 320 F 28044 PZ

TMX = Experimental Device TMP = Prototype Device TMS = Qualified Device

DEVICE FAMILY

320 = TMS320E DSP Family

TECHNOLOGY

PACKAGE TYPE

PZ = 100-Pin Low-Profile Quad

Flatpack (LQFP) GGM = 100-Ball Ball Grid Array (BGA) ZGM = 100-Ball Lead-Free BGA

F = Flash EEPROM

(1.8-V Core/3.3-V I/O)

DEVICE 28044

TEMPERATURE RANGE A = –405C to 855C S = –405C to 1255C Q = –405C to 1255C — Q100 Fault Grading

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend for reading the complete device name for any family member.

Figure 5-1. Example of TMS320x280x Device Nomenclature

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5.2 Documentation Support

Extensive documentation supports all of the TMS320™ DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. TMS320F28044 device reference guides are applicable to the UCD9501 device as well. Useful reference documentation includes:

CPU User's Guides SPRU430 TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central

processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.

SPRU712 TMS320x28xx, 28xxx System Control and Interrupts Reference Guide describes the various

interrupts and system control features of the 280x digital signal processors (DSPs).

Peripheral Guides SPRU566 TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference guides

of the 28x digital signal processors (DSPs).

SPRU716 TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide describes

how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.

SPRU791 TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide

describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion

SPRU924 TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes the

operation of the high-resolution extension to the pulse width modulator (HRPWM)

SPRU807 TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes the

enhanced capture module. It includes the module description and registers.

SPRU790 TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide

describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers

SPRU074 TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide

describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.

SPRU051 TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the

SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

SPRU059 TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI -

a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.

SPRU721 TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the features

and operation of the inter-integrated circuit (I2C) module that is available on the TMS320x280x digital signal processor (DSP).

SPRU722 TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and

features of the bootloader (factory-programmed boot-loading software). It also describes

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other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.

Tools Guides SPRU513 TMS320C28x Assembly Language Tools User's Guide describes the assembly language

tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device.

SPRU514 TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++

compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device.

SPRU608 The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core.

SPRU625 TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide

describes development using DSP/BIOS.

Application Reports and Software

Key Links Include:

1. C2000 Get Started - www.ti.com/c2000getstarted

2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw

3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib

4. DSP Power Management Reference Designs - www.ti.com/dsppower

SPRAAM0 Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development

flow and functional areas to make your design effort as seamless as possible. Tips on getting started with C28x™ DSP software and hardware development are provided to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, software, and tools for use in each phase of design.

SPRA958 Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the

requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are presented. Example code projects are included.

SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware

abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define macros and topics of code efficiency and special case registers are also addressed.

SPRAA88 Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method

for utilizing the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).

SPRAA91 TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents

hardware connections as well as software preparation and operation of the development system using a simple communication echo program.

SPRAAH1 Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the use

of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x, 28xxx family of processors.

SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the

Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration from the 281x to the 280x. While the main focus of this document is migration from 281x to 280x, users considering migrating in the reverse direction (280x to 281x) will also find this

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document useful.

SPRAAI1 Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control

provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.

SPRAAD5 Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller

presents a complete implementation of a power line modem following CEA-709 protocol using a single DSP.

SPRAAD8 TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the

absolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices. Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of the ADC to levels better than

0.5%. This application report has an option to download an example program that executes from RAM on the F2808 EzDSP.

SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for

online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that contains functions for implementing the overflow detection on both DSP/BIOS™ and non-DSP/BIOS applications.

SPRA806 An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP

provides instructions and suggestions to configure the C compiler to assist with understanding of parameter-passing conventions and environments expected by the C compiler.

Software SPRC191 Download: C280x, C2801x C/C++ Header Files and Peripheral Examples

SPRM246 F28044 GGM/ZGM BSDL Model SPRM247 F28044 PZ BSDL Model

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information.

Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com.

To send comments regarding this data manual (literature number SPRS230), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.

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6 Electrical Specifications

This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320F28044 DSP.

6.1 Absolute Maximum Ratings

(1) (2)

Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.

Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, IIK(V Output clamp current, IOK(V Operating ambient temperature range, TA: A version (GGM, PZ) Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the

voltage to a diode drop above V (4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953 ) and Reliability Data for

TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963 )

DDIO DDA2 DD DD1A18 SSA2

, V

DD3VFL

, V

DDAIO

, V

SSAIO

< 0 or VIN> V

< 0 or VO> V

(4)

stg

with respect to V with respect to V with respect to V

DD2A18

, V

SS1AGND

SS2AGND

with respect to V with respect to V

SS SSA SS SSA SS

- 0.3 V to 4.6 V

- 0.3 V to 2.5 V

- 0.3 V to 0.3 V

- 0.3 V to 4.6 V

(3)

)

DDIO

) ± 20 mA

DDIO

(4)

- 40 ° C to 85 ° C

- 40 ° C to 150 ° C

(4)

DDA2

or below V

SSA2

- 65 ° C to 150 ° C

± 20 mA

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6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Device supply voltage, I/O, V Device supply voltage CPU, V Supply ground, VSS, V ADC supply voltage (3.3 V), V ADC supply voltage (1.8 V), V Flash supply voltage, V Device clock frequency (system clock), f High-level input voltage, V Low-level input voltage, V

High-level output source current, V

Low-level output sink current, V

Ambient temperature, T

(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1

DDIO

SSIO

, V

DDA2

DDAIO

, V

DD1A18

DD3VFL

DD2A18

SYSCLKOUT

= 2.4 V, I

= V

MAX, I

All I/Os except Group 2 -4 mA

Group 2

(1)

All I/Os except Group 2 4 mA

Group 2

(1)

A version -40 85 ° C

MIN NOM MAX UNIT

3.14 3.3 3.47 V

1.71 1.8 1.89 V 0 V

3.14 3.3 3.47 V

1.71 1.8 1.89 V

3.14 3.3 3.47 V

2 100 MHz 2 V

DDIO

0.8

-8

6.3 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage V

Low-level output voltage IOL= IOLMAX 0.4 V

Pin with pullup

Input current

(low level)

enabled Pin with pulldown

enabled Pin with pullup

enabled

Input current Pin with pulldown

(high level) enabled

Pin with pulldown enabled

Output current, pullup or

pulldown disabled

Input capacitance 2 pF

IOH= IOHMAX 2.4 IOH= 50 µ A V

= 3.3 V, VIN= 0 V All I/Os (including XRS) -80 -140 -190

DDIO

= 3.3 V, VIN= 0 V ± 2

DDIO

= 3.3 V, VIN= V

DDIO

VO= V

= 3.3 V, VIN= V

or 0 V ± 2 µ A

DDIO

(F280x) 28 50 80 µ A

DDIO

(C280x) 80 140 190

DDIO

- 0.2

DDIO

µ A

± 2

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6.4 Current Consumption

Table 6-1. TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

MODE TEST CONDITIONS

The following peripheral clocks are enabled:

• ePWM1-16

• SCI-A

• SPI-A

• ADC

• I2C

Operational (Flash)

IDLE 75 mA 90 mA 500 µ A 2 mA 2 µ A 10 µ A 5 µ A 50 µ A 15 µ A 30 µ A

STANDBY 6 mA 12 mA 100 µ A 500 µ A 2 µ A 10 µ A 5 µ A 50 µ A 15 µ A 30 µ A

HALT Peripheral clocks are off. 70 µ A 60 µ A 120 µ A 2 µ A 10 µ A 5 µ A 50 µ A 15 µ A 30 µ A

(1) I (2) I

(3) I (4) The TYP numbers are applicable over room temperature and nominal voltage.

All PWM pins are toggled at 100 kHz. All I/O pins are left unconnected. Data is continuously transmitted out of the SCI-A port. The hardware multiplier is exercised. Code is running out of flash with 3 wait-states. XCLKOUT is turned off.

Flash is powered down. XCLKOUT is turned off. The following peripheral clocks are enabled:

• SCI-A

• SPI-A

• I2C

Flash is powered down. Peripheral clocks are off.

Flash is powered down. Input clock is disabled.

current is dependent on the electrical loading on the I/O pins.

DDIO

includes current into V

DDA18

clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.

includes current into V

DDA33

DD1A18

DDA2

(4)

TYP

205 mA 230 mA 10 mA 15 mA 35 mA 40 mA 30 mA 38 mA 1.5 mA 2 mA

and V

MAX TYP

pins. In order to realize the I

DD2A18

pins.

DDAIO

(1)

DDIO

(4)

MAX TYP MAX TYP

DD3VFL

currents shown for IDLE, STANDBY, and HALT,

DDA18

(2)

DDA18

(4)

MAX TYP

DDA33

(4)

(3)

MAX

NOTE

The peripheral - I/O multiplexing implemented in the F28044 device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables.

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6.4.1 Reducing Current Consumption

Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2 indicates the typical reduction in current consumption achieved by turning off the clocks.

Table 6-2. Typical Current Consumption by Various

Peripherals (at 100 MHz)

PERIPHERAL IDDCURRENT

MODULE REDUCTION (mA)

ADC 8

I2C 5

ePWM 5

SCI 4 SPI 5

(1) All peripheral clocks are disabled upon reset. Writing to/reading

from peripheral registers is possible only after the peripheral clocks are turned on.

(2) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (I

) as well.

DDA18

(1)

(2)

NOTE

current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

DDIO

NOTE

The baseline IDDcurrent (current when the core is executing a dummy loop with no peripherals enabled) is 110 mA, typical. To arrive at the IDDcurrent for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDDcurrent.

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6.5 Emulator Connection Without Signal Buffering for the DSP

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

VDDIO

DSP

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

TCK_RET

6inchesorless

GND

JTAGHeader

VDDIO

Figure 6-1 shows the connection between the DSP and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-1 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP Controllers CPU and Instruction Set Reference Guide (literature number SPRU160).

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 6-1. Emulator Connection Without Signal Buffering for the DSP

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.6 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their Letters and symbols and their meanings: meanings:

a access time H High c cycle time (period) L Low d delay time V Valid

f fall time X h hold time Z High impedance

r rise time su setup time t transition time v valid time w pulse duration (width)

Unknown, changing, or don't care level

6.6.1 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document.

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Transmission Line

4.0 pF 1.85 pF

Z0 = 50 Ω

(Α)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output Under Test

42 Ω 3.5 nH

Device Pin

(B)

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.6.2 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

TMS320F28044

Figure 6-2. 3.3-V Test Load Circuit

6.6.3 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options available on the F28044 DSP. Table 6-3 lists the cycle times of various clocks.

Table 6-3. TMS320x280x Clock Table and Nomenclature

, Cycle time 28.6 50 ns

On-chip oscillator clock

(1)

XCLKIN

SYSCLKOUT

XCLKOUT

HSPCLK

LSPCLK

(2)

ADC clock

(1) This also applies to the X1 pin if a 1.8-V oscillator is used. (2) Lower LSPCLK and HSPCLK will reduce device power consumption. (3) This is the default reset value if SYSCLKOUT = 100 MHz.

c(OSC)

Frequency 20 35 MHz t

, Cycle time 10 250 ns

c(CI)

Frequency 4 100 MHz t

, Cycle time 10 500 ns

c(SCO)

Frequency 2 100 MHz t

, Cycle time 10 2000 ns

c(XCO)

Frequency 0.5 100 MHz t

, Cycle time 10 20

c(HCO)

Frequency 50 t

, Cycle time 10 40

c(LCO)

Frequency 25 t

c(ADCCLK)

, Cycle time 80 ns

Frequency 12.5 MHz

MIN NOM MAX UNIT

(3) (3) (3) (3)

100 MHz

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.7 Clock Requirements and Characteristics

Input clock frequency Crystal (X1/X2) 20 35 MHz

Limp mode SYSCLKOUT frequency range (with /2 enabled) 1-5 MHz

Table 6-4. Input Clock Frequency

PARAMETER MIN TYP MAX UNIT

Resonator (X1/X2) 20 35

External oscillator/clock source (XCLKIN or X1 pin) 4 100

Table 6-5. XCLKIN

(1)

Timing Requirements - PLL Enabled

NO. MIN MAX UNIT

C8 t

C9 t C10 t C11 t C12 t

c(CI) f(CI) r(CI) w(CIL) w(CIH)

Cycle time, XCLKIN 33.3 200 ns Fall time, XCLKIN 6 ns Rise time, XCLKIN 6 ns Pulse duration, XCLKIN low as a percentage of t Pulse duration, XCLKIN high as a percentage of t

c(OSCCLK)

45 55 % 45 55 %

(1) This applies to the X1 pin also.

Table 6-6. XCLKIN

(1)

Timing Requirements - PLL Disabled

NO. MIN MAX UNIT

C8 t

C9 t

c(CI) f(CI)

Cycle time, XCLKIN 10 250 ns Fall time, XCLKIN Up to 20 MHz 6 ns

20 MHz to 100 MHz 2 ns

C10 t

r(CI)

Rise time, XCLKIN Up to 20 MHz 6 ns

20 MHz to 100 MHz 2 ns C11 t C12 t

w(CIL) w(CIH)

Pulse duration, XCLKIN low as a percentage of t Pulse duration, XCLKIN high as a percentage of t

c(OSCCLK)

45 55 % 45 55 %

(1) This applies to the X1 pin also.

The possible configuration modes are shown in Table 3-13 .

Table 6-7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

(1) (2)

NO. PARAMETER MIN TYP MAX UNIT

C1 t C3 t C4 t C5 t C6 t

c(XCO) f(XCO) r(XCO) w(XCOL) w(XCOH)

Cycle time, XCLKOUT 10 ns Fall time, XCLKOUT 2 ns Rise time, XCLKOUT 2 ns Pulse duration, XCLKOUT low H-2 H+2 ns Pulse duration, XCLKOUT high H-2 H+2 ns PLL lock time 131072t

c(OSCCLK)

(1) A load of 40 pF is assumed for these parameters. (2) H = 0.5t (3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.

c(XCO)

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XCLKOUT

(B)

XCLKIN

(A)

C10

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is

intended to illustrate the timing parameters only and may differ based on actual configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 6-3. Clock Timing

6.8 Power Sequencing

No requirements are placed on the power up/down sequence of the various power pins to ensure the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the V simultaneously with the V reach 0.7 V.

pins, ensuring that the V

DDIO

pins have reached 0.7 V before the V

TMS320F28044

pins prior to or

pins

DDIO

There are some requirements on the XRS pin:

1. During power up, the XRS pin must be held low for t

w(RSL1)

after the input clock is stable (see

Table 6-9 ). This is to enable the entire device to start from a known condition.

2. During power down, the XRS pin must be pulled low at least 8 µ s prior to V enhance flash reliability.

Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

6.8.1 Power Management and Supervisory Circuit Solutions

Table 6-8 lists the power management and supervisory circuit solutions for F28044 DSP. LDO selection

depends on the total power consumed in the end application. Go to www.power.ti.com for a complete list of TI power ICs or select TI DSP Power Solutions for links to the DSP Power Selection Guide (slub006a.pdf) and links to specific power reference designs.

Table 6-8. Power Management and Supervisory Circuit Solutions

SUPPLIER TYPE PART DESCRIPTION

Texas Instruments LDO TPS767D301 Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS) Texas Instruments LDO TPS70202 Dual 500/250-mA LDO with SVS Texas Instruments LDO TPS766xx 250-mA LDO with PG Texas Instruments SVS TPS3808 Open Drain SVS with programmable delay Texas Instruments SVS TPS3803 Low-cost Open-drain SVS with 5 µ S delay Texas Instruments LDO TPS799xx 200-mA LDO in WCSP package Texas Instruments LDO TPS736xx 400-mA LDO with 40 mV of V Texas Instruments DC/DC TPS62110 High Vin1.2-A dc/dc converter in 4x4 QFN package Texas Instruments DC/DC TPS6230x 500-mA converter in WCSP package

reaching 1.5 V. This is to

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w(RSL1)

h(boot-mode)

(B)

DDIO

, V

DD3VFL

DDA2

, V

DDAIO

(3.3 V)

XCLKIN

X1/X2

XRS

Boot-Mode

Pins

VDD, V

DD1A18,

DD2A18

(1.8 V)

XCLKOUT

I/O Pins

(C)

User-Code Dependent

Boot-ROM Execution Starts

Peripheral/GPIO Function Based on Boot Code

GPIO Pins as Input

OSCCLK/8

(A)

GPIO Pins as Input (State Depends on Internal PU/PD)

OSCST

User-Code Dependent

Address/Data/

Control

(Internal)

Address/Data Valid. Internal Boot-ROM Code Execution Phase

User-Code Execution Phase

d(EX)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset

state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8 during this phase.

B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.

Figure 6-4. Power-on Reset

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h(boot-mode)

(A)

w(RSL2)

XCLKIN

X1/X2

XRS

Boot-Mode

Pins

XCLKOUT

I/O Pins

Address/Data/

Control

(Internal)

Boot-ROM Execution Starts

User-Code Execution Starts

User-Code Dependent

User-Code Execution Phase

(Don’t Care)

User-Code Dependent

User-Code Execution

Peripheral/GPIO Function

User-Code Dependent

GPIO Pins as Input (State Depends on Internal PU/PD)

GPIO Pins as Input

Peripheral/GPIO Function

d(EX)

OSCCLK * 5

OSCCLK/8

(1)

w(RSL1)

w(RSL2)

w(WDRS)

d(EX)

(2)

OSCST

h(boot-mode)

(1) In addition to the t (2) Dependent on crystal/resonator and board design.

Pulse duration, stable XCLKIN to XRS high 8t Pulse duration, XRS low Warm reset 8t Pulse duration, reset pulse generated by

watchdog Delay time, address/data valid after XRS high 32t Oscillator start-up time 1 10 ms Hold time for boot-mode pins 200t

requirement, XRS has to be low at least for 1 ms after V

w(RSL1)

Table 6-9. Reset ( XRS) Timing Requirements

reaches 1.5 V.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

MIN NOM MAX UNIT

c(OSCCLK) c(OSCCLK)

512t

c(OSCCLK)

cycles cycles

cycles

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 6-5. Warm Reset

Figure 6-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =

0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.

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OSCCLK

SYSCLKOUT

Write to PLLCR

OSCCLK * 2

(Current CPU

Frequency)

OSCCLK/2

(CPU Frequency While PLL is Stabilizing

With the Desired Frequency. This Period

(PLL Lock-up Time, tp) is

131072 OSCCLK Cycles Long.)

OSCCLK * 4

(Changed CPU Frequency)

GPIO

r(GPO)

f(GPO)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Figure 6-6. Example of Effect of Writing Into PLLCR Register

6.9 General-Purpose Input/Output (GPIO)

6.9.1 GPIO - Output Timing

Table 6-10. General-Purpose Output Switching Characteristics

PARAMETER MIN MAX UNIT

r(GPO)

f(GPO)

fGPO

Rise time, GPIO switching low to high All GPIOs 8 ns Fall time, GPIO switching high to low All GPIOs 8 ns Toggling frequency, GPO pins 25 MHz

Figure 6-7. General-Purpose Output Timing

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GPIO Signal

Sampling Window

Output From

Qualifier

1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

(SYSCLKOUT cycle * 2 * QUALPRD) * 5

(C)

)

(A)

GPxQSELn = 1,0 (6 samples)

Sampling Period determined by GPxCTRL[QUALPRD]

(B)

(D)

w(SP)

w(IQSW)

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.9.2 GPIO - Input Timing

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It

can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin

will be sampled). B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is

used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or

greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure

5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide

pulse ensures reliable recognition.

TMS320F28044

Figure 6-8. Sampling Mode

Table 6-11. General-Purpose Input Timing Requirements

w(SP)

w(IQSW)

w(GPI)

Sampling period

Input qualifier sampling window t

(2)

Pulse duration, GPIO low/high

(1) "n" represents the number of qualification samples as defined by GPxQSELn register. (2) For t

, pulse width is measured from VILto VILfor an active low signal and VIHto VIHfor an active high signal.

w(GPI)

QUALPRD = 0 1t QUALPRD ≠ 0 2t

Synchronous mode 2t With input qualifier t

MIN MAX UNIT

c(SCO)

* QUALPRD cycles

c(SCO)

w(SP)

+ t

w(IQSW)

w(SP)

(1)

* (n

- 1) cycles

c(SCO)

+ 1t

c(SCO)

cycles

cycles cycles

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GPIOxn

XCLKOUT

w(GPI)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.9.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of

the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0

Figure 6-9. General-Purpose Input Timing

NOTE

The pulse-width requirement for general-purpose input is applicable for the XINT2_ADCSOC signal as well.

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WAKE INT

(A)

XCLKOUT

Address/Data

(internal)

d(WAKE−IDLE)

w(WAKE−INT)

6.9.4 Low-Power Mode Wakeup Timing

Table 6-12 shows the timing requirements, Table 6-13 shows the switching characteristics, and Figure 6-10 shows the timing diagram for IDLE mode.

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 6-12. IDLE Mode Timing Requirements

(1)

MIN NOM MAX UNIT

w(WAKE-INT)

Pulse duration, external wake-up signal cycles

Without input qualifier 2t With input qualifier 5t

c(SCO)

+ t

c(SCO)

w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-11 .

Table 6-13. IDLE Mode Switching Characteristics

(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Delay time, external wake signal to program execution resume

• Wake-up from Flash – Flash module in active state With input qualifier 20t

d(WAKE-IDLE)

• Wake-up from Flash – Flash module in sleep state With input qualifier 1050t

• Wake-up from SARAM

(2)

Without input qualifier 20t

c(SCO)

Without input qualifier 1050t

c(SCO)

Without input qualifier 20t With input qualifier 20t

c(SCO)

(1) For an explanation of the input qualifier parameters, see Table 6-11 . (2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered

by the wake up) signal involves additional latency.

c(SCO)

+ t

w(IQSW)

c(SCO)

+ t

w(IQSW)

c(SCO)

+ t

w(IQSW)

cycles

A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

Figure 6-10. IDLE Entry and Exit Timing

Table 6-14. STANDBY Mode Timing Requirements

TEST CONDITIONS MIN NOM MAX UNIT

w(WAKE-INT)

Pulse duration, external wake-up signal

Without input qualification 3t With input qualification

(1)

(2 + QUALSTDBY) * t

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

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w(WAKE-INT)

d(WAKE-STBY)

d(IDLE−XCOL)

Wake−up

Signal

X1/X2 or

X1 or

XCLKIN

XCLKOUT

STANDBY Normal ExecutionSTANDBY

Flushing Pipeline

(A)

(B)

(C)

(D)

(E)

(F)

Device

Status

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 6-15. STANDBY Mode Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(IDLE-XCOL)

d(WAKE-STBY)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered

by the wake up signal) involves additional latency.

Delay time, IDLE instruction executed to XCLKOUT low

Delay time, external wake signal to program execution resume

• Wake up from flash – Flash module in active

state

• Wake up from flash – Flash module in sleep

state

• Wake up from SARAM

32t

c(SCO)

(1)

Without input qualifier 100t With input qualifier 100t Without input qualifier 1125t With input qualifier 1125t Without input qualifier 100t

With input qualifier 100t

+ t

c(SCO)

+ t

c(SCO)

+ t

c(SCO)

45t

c(SCO)

cycles

c(SCO)

cycles

w(WAKE-INT)

c(SCO)

cycles

w(WAKE-INT)

c(SCO)

w(WAKE-INT)

cycles

A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being

turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 6-11. STANDBY Entry and Exit Timing Diagram

Table 6-16. HALT Mode Timing Requirements

w(WAKE-GPIO)

w(WAKE-XRS)

Pulse duration, GPIO wake-up signal t Pulse duration, XRS wakeup signal t

(1) See Table 6-9 for an explanation of t

Electrical Specifications86 Submit Documentation Feedback

oscst

+ 2t

oscst

+ 8t

oscst

MIN NOM MAX UNIT

c(OSCCLK)

(1)

c(OSCCLK)

cycles cycles

www.ti.com

d(IDLE−XCOL)

X1/X2

XCLKOUT

HALT HALT

Wake-up Latency

Flushing Pipeline

d(WAKE−HALT)

(A)

(B)

(C)

(D)

Device

Status

(E)

(G)

(F)

PLL Lock-up Time

Normal

Execution

w(WAKE-GPIO)

GPIOn

Oscillator Start-up Time

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 6-17. HALT Mode Switching Characteristics

PARAMETER MIN TYP MAX UNIT

d(IDLE-XCOL)

d(WAKE-HALT)

Delay time, IDLE instruction executed to XCLKOUT low 32t

c(SCO)

PLL lock-up time 131072t Delay time, PLL lock to program execution resume

• Wake up from flash – Flash module in sleep state

• Wake up from SARAM

45t

c(SCO)

c(OSCCLK)

1125t

c(SCO)

35t

c(SCO)

cycles cycles

cycles

A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is

turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as

the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.

D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The

GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.

E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or

XCLKIN) cycles.

F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT

mode is now exited.

G. Normal operation resumes.

Figure 6-12. HALT Wake-Up Using GPIOn

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PWM

(B)

XCLKOUT

(A)

w(TZ)

d(TZ-PWM)HZ

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.10 Enhanced Control Peripherals

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing

Table 6-18 shows the PWM output timing requirements and Table 6-19 , switching characteristics.

Table 6-18. ePWM Timing Requirements

w(SYCIN)

(1) For an explanation of the input qualifier parameters, see Table 6-11 .

Sync input pulse width Asynchronous 2t

Table 6-19. ePWM Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT

w(PWM)

w(SYNCOUT)

d(PWM)tza

d(TZ-PWM)HZ

Pulse duration, PWMx output high/low 20 ns Sync output pulse width 8t Delay time, trip input active to PWM forced high no pin load 25 ns

Delay time, trip input active to PWM forced low Delay time, trip input active to PWM Hi-Z 20 ns

6.10.2 Trip-Zone Input Timing

(1)

TEST CONDITIONS MIN MAX UNIT

c(SCO)

Synchronous 2t With input qualifier 1t

c(SCO)

+ t

w(IQSW)

c(SCO)

cycles cycles cycles

cycles

A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM

recovery software.

Figure 6-13. PWM Hi-Z Characteristics

Table 6-20. Trip-Zone input Timing Requirements

w(TZ)

(1) For an explanation of the input qualifier parameters, see Table 6-11 .

Pulse duration, TZx input low Asynchronous 1t

Table 6-21 shows the high-resolution PWM switching characteristics.

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(1)

Synchronous 2t With input qualifier 1t

c(SCO)

c(SCO) c(SCO)

+ t

w(IQSW)

MIN MAX UNIT

cycles cycles cycles

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ADCSOCAO

ADCSOCBO

w(ADCSOCAL)

XNMI, XINT1, XINT2

w(INT)

Interrupt Vector

d(INT)

Address bus

(internal)

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 6-21. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)

MIN TYP MAX UNIT

Micro Edge Positioning (MEP) step size

(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase

with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation.

Table 6-22. External ADC Start-of-Conversion Switching Characteristics

PARAMETER MIN MAX UNIT

w(ADCSOCAL)

Pulse duration, ADCSOCAO low 32t

(1)

Figure 6-14. ADCSOCAO or ADCSOCBO Timing

150 310 ps

c(HCO)

TMS320F28044

cycles

6.10.3 External Interrupt Timing

Figure 6-15. External Interrupt Timing

Table 6-23. External Interrupt Timing Requirements

(2)

w(INT)

(1) For an explanation of the input qualifier parameters, see Table 6-11 . (2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

d(INT)

(1) For an explanation of the input qualifier parameters, see Table 6-11 .

Pulse duration, INT input low/high Synchronous 1t

With qualifier 1t

Table 6-24. External Interrupt Switching Characteristics

PARAMETER MIN MAX UNIT

Delay time, INT low/high to interrupt-vector fetch t

(1)

TEST CONDITIONS MIN MAX UNIT

c(SCO)

+ t

c(SCO)

w(IQSW)

(1)

+ 12t

w(IQSW)

c(SCO)

cycles cycles

cycles

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TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.10.4 I2C Electrical Specification and Timing

SCL clock frequency I2C clock module frequency is between 400 kHz

SCL

Low level input voltage 0.3 V

High level input voltage 0.7 V

Input hysteresis 0.05 V

hys

Low level output voltage 3 mA sink current 0 0.4 V

Low period of SCL clock I2C clock module frequency is between 1.3 µ s

LOW

High period of SCL clock I2C clock module frequency is between 0.6 µ s

HIGH

Input current with an input voltage -10 10 µ A

between 0.1 V

and 0.9 V

DDIO

MAX

DDIO

Table 6-25. I2C Timing

TEST CONDITIONS MIN MAX UNIT

7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately

DDIO DDIO DDIO

V V V

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing

Table 6-26 lists the master mode timing (clock phase = 0) and Table 6-27 lists the timing (clock

phase = 1). Figure 6-16 and Figure 6-17 show the timing waveforms.

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Table 6-26. SPI Master Mode External Timing (Clock Phase = 0)

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(1) (2) (3) (4) (5)

NO. SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD UNIT

SPIBRR = 0 OR 2 AND SPIBRR > 3

MIN MAX MIN MAX

1 t 2 t

3 t

4 t

5 t

8 t

9 t

c(SPC)M w(SPCH)M

w(SPCL)M

w(SPCH)M

d(SPCH-SIMO)M

d(SPCL-SIMO)M

v(SPCL-SIMO)M

v(SPCH-SIMO)M

su(SOMI-SPCL)M

su(SOMI-SPCH)M

v(SPCL-SOMI)M

v(SPCH-SOMI)M

Cycle time, SPICLK 4t Pulse duration, SPICLK high 0.5t

(clock polarity = 0) Pulse duration, SPICLK low 0.5t

(clock polarity = 1) Pulse duration, SPICLK low 0.5t

(clock polarity = 0) Pulse duration, SPICLK high 0.5

(clock polarity = 1)

tc(SPC)M

c(SPC)M

c(LCO)

-10 0.5t

- 10 0.5t

- 10 0.5

- 10 0.5t

128t

c(LCO)

c(SPC)M

tc(SPC)M

c(SPC)M

0.5t

c(SPC)M

0.5t

c(SPC)M

0.5t

c(SPC)M

0.5t

c(SPC)M

c(LCO)

- 0.5t

+ 0.5t

c(LCO)

- 10 0.5t

-10 0.5t

- 10 0.5t

c(SPC)

c(SPC)M

127t

c(LCO)

M - 0.5t

c(LCO)

- 0.5t

c(SPC)M

c(LCO)

+ 0.5t

c(LCO)

+ 0.5t

c(LCO)

Delay time, SPICLK high to SPISIMO 10 10 ns valid (clock polarity = 0)

Delay time, SPICLK low to SPISIMO 10 10 valid (clock polarity = 1)

Valid time, SPISIMO data valid after 0.5t SPICLK low (clock polarity = 0)

Valid time, SPISIMO data valid after 0.5t SPICLK high (clock polarity = 1)

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

+ 0.5t

c(SPC)M

+ 0.5t

c(SPC)M

-10

c(LCO)

-10

c(LCO)

Setup time, SPISOMI before SPICLK 35 35 ns low (clock polarity = 0)

Setup time, SPISOMI before SPICLK 35 35 ns high (clock polarity = 1)

Valid time, SPISOMI data valid after 0.25t SPICLK low (clock polarity = 0)

Valid time, SPISOMI data valid after 0.25t SPICLK high (clock polarity = 1)

-10 0.5t

c(SPC)M

- 10 0.5t

c(SPC)M

- 0.5t

c(SPC)M

- 0.5t

c(SPC)M

- 10

c(LCO)

- 10 ns

c(LCO)

ns ns

(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) t (3) t (4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

c(SPC)

= LSPCLK cycle time

c(LCO)

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

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SPISOMI

SPISIMO

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

Master In Data

Must Be Valid

Master Out Data Is Valid

SPISTE

(A)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. In the master mode, SPISTE goes active 0.5t

word, the SPISTE will go inactive 0.5t stays active between back-to-back transmit words in both FIFO and nonFIFO modes.

c(SPC)

(minimum) before valid SPI clock edge. On the trailing end of the

c(SPC)

after the receiving edge (SPICLK) of the last data bit, except that SPISTE

Figure 6-16. SPI Master Mode External Timing (Clock Phase = 0)

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Table 6-27. SPI Master Mode External Timing (Clock Phase = 1)

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(1) (2) (3) (4) (5)

NO. SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD UNIT

OR SPIBRR = 0 OR 2 AND SPIBRR > 3

MIN MAX MIN MAX

1 t 2 t

3 t

6 t

c(SPC)M w(SPCH)M

w(SPCL))M

w(SPCL)M

w(SPCH)M

su(SIMO-SPCH)M

Cycle time, SPICLK 4t Pulse duration, SPICLK high (clock 0.5t

polarity = 0) Pulse duration, SPICLK low (clock 0.5t

polarity = 1) Pulse duration, SPICLK low (clock 0.5t

polarity = 0) Pulse duration, SPICLK high (clock 0.5t

polarity = 1) Setup time, SPISIMO data valid 0.5t

before SPICLK high (clock polarity

c(LCO)

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

128t

c(LCO)

c(SPC)M

c(LCO)

0.5t

c(SPC)M

0.5

tc(SPC)M

- 0.5t

c(SPC)M

- 0.5t

c(SPC)M

+ 0.5t

-10 0.5t

c (LCO)

-10 0.5t

c (LCO)

- 10 0.5t

c(LCO)

-10 0.5t

c(LCO)

- 10 ns

c(SPC)M

127t

c(LCO)

- 0.5t

c(SPC)M

c(LCO)

- 0.5t

c(LCO

+ 0.5t

c(LCO)

+ 0.5t

c(LCO)

= 0)

su(SIMO-SPCL)M

Setup time, SPISIMO data valid 0.5t before SPICLK low (clock polarity =

-10 0.5t

c(SPC)M

- 10 ns

c(SPC)M

7 t

10 t

11 t

v(SPCH-SIMO)M

v(SPCL-SIMO)M

su(SOMI-SPCH)M

su(SOMI-SPCL)M

v(SPCH-SOMI)M

v(SPCL-SOMI)M

Valid time, SPISIMO data valid after 0.5t SPICLK high (clock polarity = 0)

Valid time, SPISIMO data valid after 0.5t SPICLK low (clock polarity = 1)

-10 0.5t

c(SPC)M

-10 0.5t

c(SPC)M

- 10 ns

c(SPC)M

-10 ns

c(SPC)M

Setup time, SPISOMI before 35 35 ns SPICLK high (clock polarity = 0)

Setup time, SPISOMI before 35 35 ns SPICLK low (clock polarity = 1)

Valid time, SPISOMI data valid after 0.25t SPICLK high (clock polarity = 0)

Valid time, SPISOMI data valid after 0.25 SPICLK low (clock polarity = 1)

-10 0.5t

c(SPC)M

-10 0.5

tc(SPC)M

-10 ns

c(SPC)M

-10 ns

tc(SPC)M

ns ns

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. (2) t (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

c(SPC)

Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX

Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX. (4) t (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

c(LCO)

= LSPCLK cycle time

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Data Valid

SPISOMI

SPISIMO

SPICLK

(clock polarity = 1)

SPICLK

Master In Data Must

Be Valid

Master Out Data Is Valid

SPISTE

(A)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.10.6 SPI Slave Mode Timing

NO. MIN MAX UNIT

12 t 13 t

14 t

15 t

16 t

19 t

20 t

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. (2) t (3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

(4) t (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

A. In the master mode, SPISTE goes active 0.5t

word, the SPISTE will go inactive 0.5t

c(SPC)

(minimum) before valid SPI clock edge. On the trailing end of the

c(SPC)

after the receiving edge (SPICLK) of the last data bit, except that SPISTE

stays active between back-to-back transmit words in both FIFO and nonFIFO modes.

Figure 6-17. SPI Master External Timing (Clock Phase = 1)

Table 6-28 lists the slave mode external timing (clock phase = 0) and Table 6-29 (clock phase = 1). Figure 6-18 and Figure 6-19 show the timing waveforms.

Table 6-28. SPI Slave Mode External Timing (Clock Phase = 0)

c(SPC)S w(SPCH)S

w(SPCL)S w(SPCL)S

w(SPCH)S d(SPCH-SOMI)S

d(SPCL-SOMI)S v(SPCL-SOMI)S

v(SPCH-SOMI)S su(SIMO-SPCL)S

su(SIMO-SPCH)S v(SPCL-SIMO)S

v(SPCH-SIMO)S

= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

c(SPC)

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

= LSPCLK cycle time

c(LCO)

Cycle time, SPICLK Cycle time, SPICLK 4t Pulse duration, SPICLK high (clock polarity = 0) 0.5t Pulse duration, SPICLK low (clock polarity = 1) 0.5t Pulse duration, SPICLK low (clock polarity = 0) 0.5t Pulse duration, SPICLK high (clock polarity = 1) 0.5t Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 35 ns Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 35 ns Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75t Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75t Setup time, SPISIMO before SPICLK low (clock polarity = 0) 35 ns Setup time, SPISIMO before SPICLK high (clock polarity = 1) 35 ns Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5t Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5t

(1) (2) (3) (4) (5)

c(SPC)S c(SPC)S c(SPC)S c(SPC)S

c(SPC)S-10 c(SPC)S-10

c(LCO)

- 10 0.5t

c(SPC)S c(SPC)S

c(SPC)S c(SPC)S c(SPC)S c(SPC)S

ns ns ns ns ns

ns ns

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SPISIMO

SPISOMI

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

SPISIMO Data Must Be Valid

SPISOMI Data Is Valid

SPISTE

(A)

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Submit Documentation Feedback Electrical Specifications 95

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t

edge and remain low for at least 0.5t

after the receiving edge (SPICLK) of the last data bit.

c(SPC)

(minimum) before the valid SPI clock

c(SPC)

Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 0)

Table 6-29. SPI Slave Mode External Timing (Clock Phase = 1)

NO. MIN MAX UNIT

12 t

c(SPC)S

13 t

w(SPCH)S

w(SPCL)S

14 t

w(SPCL)S

w(SPCH)S

17 t

su(SOMI-SPCH)S

su(SOMI-SPCL)S

18 t

v(SPCH-SOMI)S

v(SPCL-SOMI)S

21 t

su(SIMO-SPCH)S

su(SIMO-SPCL)S

22 t

v(SPCH-SIMO)S

v(SPCL-SIMO)S

= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

c(SPC)

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

Cycle time, SPICLK 8t Pulse duration, SPICLK high (clock polarity = 0) 0.5t Pulse duration, SPICLK low (clock polarity = 1) 0.5t Pulse duration, SPICLK low (clock polarity = 0) 0.5t Pulse duration, SPICLK high (clock polarity = 1) 0.5t Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125t Setup time, SPISOMI before SPICLK low (clock polarity = 1 0.125t Valid time, SPISOMI data valid after SPICLK low (clock polarity 0.75t

= 0) Valid time, SPISOMI data valid after SPICLK high 0.75t

(clock polarity = 1) Setup time, SPISIMO before SPICLK high (clock polarity = 0) 35 ns Setup time, SPISIMO before SPICLK low (clock polarity = 1) 35 ns Valid time, SPISIMO data valid after SPICLK high 0.5t

(clock polarity = 0) Valid time, SPISIMO data valid after SPICLK low (clock polarity 0.5t

= 1)

(1) (2) (3) (4)

c(LCO)

- 10 0.5t

c(SPC)S

- 10 0.5t

c(SPC)S

- 10 0.5t

c(SPC)S

- 10 0.5t

c(SPC)S

c(SPC)S c(SPC)S c(SPC)S

c(SPC)S

c(SPC)S-10

c(SPC)S c(SPC)S c(SPC)S c(SPC)S

ns ns ns ns ns ns ns ns

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Data Valid

SPISIMO

SPISOMI

SPICLK

(clock polarity = 1)

SPICLK

(clock polarity = 0)

SPISIMO Data

Must Be Valid

SPISOMI Data Is Valid

SPISTE

(A)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t

remain low for at least 0.5t

after the receiving edge (SPICLK) of the last data bit.

c(SPC)

Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 1)

before the valid SPI clock edge and

c(SPC)

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6.11 On-Chip Analog-to-Digital Converter

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

Table 6-30. ADC Electrical Characteristics (over recommended operating conditions)

(1) (2)

PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS

Resolution 12 Bits ADC clock 1 kHz

25 MHz

ACCURACY

INL (Integral nonlinearity) 1 - 25-MHz ADC clock (12.5 MSPS) ± 2.0 LSB DNL (Differential nonlinearity) Offset error

(4)

(3)

1 - 25-MHz ADC clock (12.5 MSPS) ± 1 LSB

-60 60 LSB Offset error with hardware trimming ± 4 LSB Overall gain error with internal reference

(5)

-60 60 LSB Overall gain error with external reference -60 60 LSB Channel-to-channel offset variation ± 4 LSB Channel-to-channel gain variation ± 4 LSB

ANALOG INPUT

Analog input voltage (ADCINx to ADCLO)

(6)

0 3 V ADCLO -5 0 5 mV Input capacitance 10 pF Input leakage current ± 5 µ A

INTERNAL VOltAGE REFERENCE

ADCREFP

internal reference V

ADCREFM

internal reference

- ADCREFP output voltage at the pin based on 1.275 V

- ADCREFM output voltage at the pin based on 0.525 V

(5)

Voltage difference, ADCREFP - ADCREFM 0.75 V Temperature coefficient 50 PPM/ ° C

EXTERNAL VOltAGE REFERENCE

(5) (7)

ADCREFSEL[15:14] = 11b 1.024 V

ADCREFIN

- External reference voltage input on ADCREFIN

pin 0.2% or better accurate reference recommended

ADCREFSEL[15:14] = 10b 1.500 V ADCREFSEL[15:14] = 01b 2.048 V

AC SPECIFICATIONS

SINAD (100 kHz) Signal-to-noise ratio + distortion 67.5 dB SNR (100 kHz) Signal-to-noise ratio 68 dB THD (100 kHz) Total harmonic distortion -79 dB ENOB (100 kHz) Effective number of bits 10.9 Bits SFDR (100 kHz) Spurious free dynamic range 83 dB

(1) Tested at 25-MHz ADCCLK. (2) All voltages listed in this table are with respect to V (3) TI specifies that the ADC will have no missing codes.

SSA2

(4) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV. (5) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track

together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will depend on the temperature profile of the source used.

(6) Voltages above V

To avoid this, the analog inputs should be kept within these limits.

+ 0.3 V or below V

DDA

- 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.

(7) TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.

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ADC Power Up Delay

ADC Ready for Conversions

PWDNBG

PWDNREF

PWDNADC

Request for

ADC

Conversion

d(BGR)

d(PWD)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.11.1 ADC Power-Up Control Bit Timing

Figure 6-20. ADC Power-Up Control Bit Timing

Table 6-31. ADC Power-Up Delays

PARAMETER

d(BGR)

d(PWD)

Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 5 ms register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.

Delay time for power-down control to be stable. Bit delay time for band-gap 20 50 µ s reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3

(1)

MIN TYP MAX UNIT

1 ms

(1) Timings maintain compatibility to the 281x ADC module. The F28044 ADC also supports driving all 3 bits at the same time and waiting

ms before first conversion.

d(BGR)

Table 6-32. Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)

ADC OPERATING MODE CONDITIONS V

Mode A (Operational Mode): 30 2 mA

• BG and REF enabled

DDA18

DDA3.3

(1) (2)

• PWD disabled

Mode B: 9 0.5 mA

• ADC clock enabled

• BG and REF enabled

• PWD enabled

Mode C: 5 20 µ A

• ADC clock enabled

• BG and REF disabled

• PWD enabled

Mode D: 5 15 µ A

• ADC clock disabled

• BG and REF disabled

• PWD enabled

(1) Test Conditions:

SYSCLKOUT = 100 MHz ADC module clock = 25 MHz ADC performing a continuous conversion of all 16 channels in Mode A

(2) V

includes current into V

DDA18

and V

DD1A18

DD2A18

. V

includes current into V

DDA3.3

and V

DDA2

DDAIO

UNIT

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ADCIN0

10 pF

1 kΩ

1.64 pF

Switch

Typical Values of the Input Circuit Components: Switch Resistance (Ron): 1 kΩ

Sampling Capacitor (Ch): 1.64 pF Parasitic Capacitance (Cp): 10 pF Source Resistance (Rs): 50 Ω

28x DSP

Source

Signal

Figure 6-21. ADC Analog Input Impedance Model

TMS320F28044

Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.11.2 Definitions

Reference Voltage

The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.

Analog Inputs

The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time. These inputs are software-selectable.

Converter

The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low power consumption.

Conversion Modes

The conversion can be performed in two different conversion modes:

• Sequential sampling mode (SMODE = 0)

• Simultaneous sampling mode (SMODE = 1)

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Analog Input on

Channel Ax or Bx

ADC Clock

Sample and Hold

SH Pulse

SMODE Bit

dschx_n

dschx_n+1

Sample n

Sample n+1

Sample n+2

ADC Event Trigger from ePWM or Other Sources

d(SH)

TMS320F28044 Digital Signal Processor

SPRS357B – AUGUST 2006 – REVISED MAY 2007

6.11.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)

In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).

d(SH)

d(schx_n)

d(schx_n+1)

Figure 6-22. Sequential Sampling Mode (Single-Channel) Timing

Table 6-33. Sequential Sampling Mode Timing

SAMPLE n SAMPLE n + 1 ADC CLOCK, REMARKS

Delay time from event trigger to 2.5t sampling

Sample/Hold width/Acquisition (1 + Acqps) * 40 ns with Acqps = 0 Acqps value = 0-15 Width t

Delay time for first result to appear 4t in Result register

Delay time for successive results to (2 + Acqps) * 80 ns appear in Result register t

c(ADCCLK)

AT 25-MHz

c(ADCCLK)

160 ns

= 40 ns

ADCTRL1[8:11]

Electrical Specifications100 Submit Documentation Feedback

Texas Instruments TMS320F28044PZA, TMS320F28044 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 F28044 Digital Signal Processor

1.1 Features

1.2 Getting Started

2 Introduction

2.1 Pin Assignments

2.2 Signal Descriptions

3 Functional Overview

3.1 Memory Map

3.2 Brief Descriptions

3.2.1 C28x CPU

3.2.2 Memory Bus (Harvard Bus Architecture)

3.2.3 Peripheral Bus

3.2.4 Real-Time JTAG and Analysis

3.2.5 Flash

3.2.6 M0, M1 SARAMs

3.2.7 L0, L1 SARAMs

3.2.8 Boot ROM

3.2.9 Security

3.2.10 Peripheral Interrupt Expansion (PIE) Block

3.2.11 External Interrupts (XINT1, XINT2, XNMI)

3.2.12 Oscillator and PLL

3.2.13 Watchdog

3.2.14 Peripheral Clocking

3.2.15 Low-Power Modes

3.2.16 Peripheral Frames 0, 1, 2 (PFn)

3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

3.2.18 32-Bit CPU-Timers (0, 1, 2)

3.2.19 Control Peripherals

3.2.20 Serial Port Peripherals

3.3 Register Map

3.4 Device Emulation Registers

3.5 Interrupts

3.5.1 External Interrupts

3.6 System Control

3.6.1 OSC and PLL Block

3.6.2 Watchdog Block

3.7 Low-Power Modes Block

4 Peripherals

4.1 32-Bit CPU-Timers 0/1/2

4.2 Enhanced PWM Modules (ePWM1-16)

4.3 Hi-Resolution PWM (HRPWM)

4.4 Enhanced Analog-to-Digital Converter (ADC) Module

4.5 ADC Connections if the ADC Is Not Used

4.6 Serial Communications Interface (SCI) Module (SCI-A)

4.7 Serial Peripheral Interface (SPI) Module (SPI-A)

4.8 Inter-Integrated Circuit (I2C)

4.9 GPIO MUX

5 Device Support

5.1 Device and Development Support Tool Nomenclature

5.2 Documentation Support

6 Electrical Specifications

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 Electrical Characteristics

6.4 Current Consumption

6.4.1 Reducing Current Consumption

6.5 Emulator Connection Without Signal Buffering for the DSP

6.6 Timing Parameter Symbology

6.6.1 General Notes on Timing Parameters

6.6.2 Test Load Circuit

6.6.3 Device Clock Table

6.7 Clock Requirements and Characteristics

6.8 Power Sequencing

6.8.1 Power Management and Supervisory Circuit Solutions

6.9 General-Purpose Input/Output (GPIO)

6.9.1 GPIO - Output Timing

6.9.2 GPIO - Input Timing

6.10 Enhanced Control Peripherals

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing

6.10.2 Trip-Zone Input Timing

6.10.3 External Interrupt Timing

6.10.4 I2C Electrical Specification and Timing

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing

6.10.6 SPI Slave Mode Timing

6.11 On-Chip Analog-to-Digital Converter

6.11.1 ADC Power-Up Control Bit Timing