Texas Instruments TMS320F28044PZA, TMS320F28044 Datasheet
Digital Signal Processor
Data Manual
TMS320F28044
Literature Number: SPRS357B
August 2006 – Revised May 2007
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Contents
1 F28044 Digital Signal Processor ............................................................................................ 9
1.1 Features ....................................................................................................................... 9
1.2 Getting Started .............................................................................................................. 10
2 Introduction ....................................................................................................................... 11
2.1 Pin Assignments ............................................................................................................ 11
2.2 Signal Descriptions ......................................................................................................... 14
3 Functional Overview ........................................................................................................... 20
3.1 Memory Map ................................................................................................................ 21
3.2 Brief Descriptions ........................................................................................................... 23
3.2.1 C28x CPU ....................................................................................................... 23
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 23
3.2.3 Peripheral Bus .................................................................................................. 24
3.2.4 Real-Time JTAG and Analysis ................................................................................ 24
3.2.5 Flash .............................................................................................................. 24
3.2.6 M0, M1 SARAMs ............................................................................................... 24
3.2.7 L0, L1 SARAMs ................................................................................................. 24
3.2.8 Boot ROM ........................................................................................................ 25
3.2.9 Security .......................................................................................................... 26
3.2.10 Peripheral Interrupt Expansion (PIE) Block .................................................................. 27
3.2.11 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 27
3.2.12 Oscillator and PLL .............................................................................................. 27
3.2.13 Watchdog ........................................................................................................ 27
3.2.14 Peripheral Clocking ............................................................................................. 27
3.2.15 Low-Power Modes .............................................................................................. 27
3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 28
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 28
3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 28
3.2.19 Control Peripherals ............................................................................................. 28
3.2.20 Serial Port Peripherals ......................................................................................... 29
3.3 Register Map ................................................................................................................ 29
3.4 Device Emulation Registers ............................................................................................... 30
3.5 Interrupts .................................................................................................................... 31
3.5.1 External Interrupts .............................................................................................. 33
3.6 System Control ............................................................................................................. 34
3.6.1 OSC and PLL Block ............................................................................................ 36
3.6.2 Watchdog Block ................................................................................................. 38
3.7 Low-Power Modes Block .................................................................................................. 40
4 Peripherals ........................................................................................................................ 41
4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 41
4.2 Enhanced PWM Modules (ePWM1-16) ................................................................................. 43
4.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 48
4.4 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 49
4.5 ADC Connections if the ADC Is Not Used ................................................................... 52
4.6 Serial Communications Interface (SCI) Module (SCI-A) .............................................................. 54
4.7 Serial Peripheral Interface (SPI) Module (SPI-A) ...................................................................... 57
4.8 Inter-Integrated Circuit (I
4.9 GPIO MUX .................................................................................................................. 62
5 Device Support .................................................................................................................. 66
5.1 Device and Development Support Tool Nomenclature ................................................................ 66
5.2 Documentation Support ................................................................................................... 68
2
C) ............................................................................................... 60
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
6 Electrical Specifications ...................................................................................................... 71
6.1 Absolute Maximum Ratings ............................................................................................... 71
6.2 Recommended Operating Conditions ................................................................................... 72
6.3 Electrical Characteristics ................................................................................................. 72
6.4 Current Consumption ..................................................................................................... 73
6.4.1 Reducing Current Consumption .............................................................................. 74
6.5 Emulator Connection Without Signal Buffering for the DSP .......................................................... 75
6.6 Timing Parameter Symbology ............................................................................................ 76
6.6.1 General Notes on Timing Parameters ........................................................................ 76
6.6.2 Test Load Circuit ................................................................................................ 77
6.6.3 Device Clock Table ............................................................................................. 77
6.7 Clock Requirements and Characteristics ............................................................................... 78
6.8 Power Sequencing ......................................................................................................... 79
6.8.1 Power Management and Supervisory Circuit Solutions .................................................... 79
6.9 General-Purpose Input/Output (GPIO) .................................................................................. 82
6.9.1 GPIO - Output Timing ........................................................................................... 82
6.9.2 GPIO - Input Timing ............................................................................................. 83
6.10 Enhanced Control Peripherals ............................................................................................ 88
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ......................................................... 88
6.10.2 Trip-Zone Input Timing .......................................................................................... 88
6.10.3 External Interrupt Timing ....................................................................................... 89
6.10.4 I
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing ..................................................... 90
6.10.6 SPI Slave Mode Timing ......................................................................................... 94
6.11 On-Chip Analog-to-Digital Converter .................................................................................... 97
6.11.1 ADC Power-Up Control Bit Timing ............................................................................ 98
6.11.2 Definitions ........................................................................................................ 99
6.11.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................. 100
6.11.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ........................................... 101
6.12 Detailed Descriptions .................................................................................................... 102
6.13 Flash Timing ............................................................................................................... 103
7 Mechanical Data ............................................................................................................... 105
2
C Electrical Specification and Timing ....................................................................... 90
Contents 3
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
List of Figures
2-1 100-Pin PZ LQFP (Top View) ................................................................................................... 12
2-2 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 13
3-1 Functional Block Diagram ........................................................................................................ 20
3-2 F28044 Memory Map ............................................................................................................. 21
3-3 External and PIE Interrupt Sources ............................................................................................. 31
3-4 Multiplexing of Interrupts Using the PIE Block ................................................................................ 32
3-5 Clock and Reset Domains ....................................................................................................... 34
3-6 OSC and PLL Block Diagram ................................................................................................... 36
3-7 Using a 3.3-V External Oscillator ............................................................................................... 36
3-8 Using a 1.8-V External Oscillator ............................................................................................... 36
3-9 Using the Internal Oscillator ..................................................................................................... 36
3-10 Watchdog Module ................................................................................................................. 39
4-1 CPU-Timers ........................................................................................................................ 41
4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 42
4-3 Multiple PWM Modules ........................................................................................................... 43
4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 48
4-5 Block Diagram of the ADC Module ............................................................................................. 50
4-6 ADC Pin Connections With Internal Reference ............................................................................... 51
4-7 ADC Pin Connections With External Reference .............................................................................. 52
4-8 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 56
4-9 SPI Module Block Diagram (Slave Mode) ..................................................................................... 59
4-10 I
4-11 GPIO MUX Block Diagram ....................................................................................................... 62
4-12 Qualification Using Sampling Window .......................................................................................... 65
5-1 Example of TMS320x280x Device Nomenclature ............................................................................ 67
6-1 Emulator Connection Without Signal Buffering for the DSP ................................................................. 75
6-2 3.3-V Test Load Circuit ........................................................................................................... 77
6-3 Clock Timing ....................................................................................................................... 79
6-4 Power-on Reset ................................................................................................................... 80
6-5 Warm Reset ........................................................................................................................ 81
6-6 Example of Effect of Writing Into PLLCR Register ........................................................................... 82
6-7 General-Purpose Output Timing ................................................................................................ 82
6-8 Sampling Mode .................................................................................................................... 83
6-9 General-Purpose Input Timing .................................................................................................. 84
6-10 IDLE Entry and Exit Timing ...................................................................................................... 85
6-11 STANDBY Entry and Exit Timing Diagram .................................................................................... 86
6-12 HALT Wake-Up Using GPIOn ................................................................................................... 87
6-13 PWM Hi-Z Characteristics ....................................................................................................... 88
6-14 ADCSOCAO or ADCSOCBO Timing ........................................................................................... 89
2
C Peripheral Module Interfaces ............................................................................................... 61
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
6-15 External Interrupt Timing ......................................................................................................... 89
6-16 SPI Master Mode External Timing (Clock Phase = 0) ........................................................................ 92
6-17 SPI Master External Timing (Clock Phase = 1) ............................................................................... 94
6-18 SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 95
6-19 SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 96
6-20 ADC Power-Up Control Bit Timing .............................................................................................. 98
6-21 ADC Analog Input Impedance Model ........................................................................................... 99
6-22 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 100
6-23 Simultaneous Sampling Mode Timing ........................................................................................ 101
List of Figures 5
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
List of Tables
2-1 Hardware Features ............................................................................................................... 11
2-2 Signal Descriptions ............................................................................................................... 14
3-1 Addresses of Flash Sectors ..................................................................................................... 22
3-2 Wait-states ......................................................................................................................... 23
3-3 Boot Mode Selection .............................................................................................................. 25
3-4 Peripheral Frame 0 Registers ................................................................................................... 29
3-5 Peripheral Frame 1 Registers ................................................................................................... 30
3-6 Peripheral Frame 2 Registers ................................................................................................... 30
3-7 Device Emulation Registers ..................................................................................................... 30
3-8 PIE Peripheral Interrupts ......................................................................................................... 32
3-9 PIE Configuration and Control Registers ...................................................................................... 33
3-10 External Interrupt Registers ...................................................................................................... 33
3-11 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 35
3-12 PLLCR Register Bit Definitions .................................................................................................. 37
3-13 Possible PLL Configuration Modes ............................................................................................. 38
3-14 Low-Power Modes ................................................................................................................ 40
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 42
4-2 ePWM1-4 Control and Status Registers ....................................................................................... 44
4-3 ePWM5-8 Control and Status Registers ....................................................................................... 45
4-4 ePWM9-12 Control and Status Registers ...................................................................................... 46
4-5 ePWM13-16 Control and Status Registers .................................................................................... 47
4-6 ADC Registers ..................................................................................................................... 53
4-7 SCI-A Registers ................................................................................................................... 55
4-8 SPI-A Registers ................................................................................................................... 58
4-9 I
4-10 GPIO Registers ................................................................................................................... 63
4-11 F28044 GPIO MUX Table ........................................................................................................ 64
6-1 TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............................. 73
6-2 Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 74
6-3 TMS320x280x Clock Table and Nomenclature ............................................................................... 77
6-4 Input Clock Frequency ........................................................................................................... 78
6-5 XCLKIN Timing Requirements - PLL Enabled ................................................................................ 78
6-6 XCLKIN Timing Requirements - PLL Disabled ................................................................................ 78
6-7 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................... 78
6-8 Power Management and Supervisory Circuit Solutions ...................................................................... 79
6-9 Reset ( XRS) Timing Requirements ............................................................................................ 81
6-10 General-Purpose Output Switching Characteristics .......................................................................... 82
6-11 General-Purpose Input Timing Requirements ................................................................................. 83
6-12 IDLE Mode Timing Requirements ............................................................................................... 85
2
C-A Registers .................................................................................................................... 61
List of Tables6 Submit Documentation Feedback
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
6-13 IDLE Mode Switching Characteristics .......................................................................................... 85
6-14 STANDBY Mode Timing Requirements ........................................................................................ 85
6-15 STANDBY Mode Switching Characteristics .................................................................................. 86
6-16 HALT Mode Timing Requirements .............................................................................................. 86
6-17 HALT Mode Switching Characteristics ........................................................................................ 87
6-18 ePWM Timing Requirements .................................................................................................... 88
6-19 ePWM Switching Characteristics ................................................................................................ 88
6-20 Trip-Zone input Timing Requirements .......................................................................................... 88
6-21 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) ................................................ 89
6-22 External ADC Start-of-Conversion Switching Characteristics ............................................................... 89
6-23 External Interrupt Timing Requirements ....................................................................................... 89
6-24 External Interrupt Switching Characteristics ................................................................................... 89
6-25 I
6-26 SPI Master Mode External Timing (Clock Phase = 0)........................................................................ 91
6-27 SPI Master Mode External Timing (Clock Phase = 1)........................................................................ 93
6-28 SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 94
6-29 SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 95
6-30 ADC Electrical Characteristics (over recommended operating conditions) ................................................ 97
6-31 ADC Power-Up Delays ........................................................................................................... 98
6-32 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .......................................... 98
6-33 Sequential Sampling Mode Timing ............................................................................................ 100
6-34 Simultaneous Sampling Mode Timing ........................................................................................ 101
6-35 Flash Endurance ................................................................................................................. 103
6-36 Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 103
6-37 Flash/OTP Access Timing ...................................................................................................... 103
6-38 Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 104
7-1 F28044 Thermal Model 100-pin GGM Results .............................................................................. 105
7-2 F28044 Thermal Model 100-pin PZ Results ................................................................................. 105
2
C Timing ......................................................................................................................... 90
List of Tables 7
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
This data manual was revised from SPRS357A to SPRS357B.
LOCATION ADDITIONS, MODIFICATIONS, DELETIONS
Global Document changed from Advance Information to Production Data to reflect device change from TMX to
TMS.
Section 1.1 Features list revised
Section 1.2 Added Getting Started Section
Section 4.5 Added subsection on pin connections when ADC is not used
Section 5.2 Updated the documents list in Documentation Support
Section 6.4.1 Added a note to the section on reducing current consumption
Table 6-28 Modified values on last two rows of table
Table 6-29 Modified values on last two rows of table
Changes in This Revision
List of Tables8 Submit Documentation Feedback
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1 F28044 Digital Signal Processor
1.1 Features
• High-Performance 100-MHz (10-ns Cycle Time)
Processor
• TMS320C28x™ 32-Bit CPU
– Single-cycle 16 × 16 and 32 × 32
Multiply-accumulate (MAC) Operations
– Dual 16 × 16 MAC
– Fast Interrupt Response
– Unified Memory Programming Model
• On-Chip Memory
– 64K × 16 Flash
– 10K × 16 SARAM
– 1K × 16 OTP
– 4K × 16 Boot ROM
– Code Security Module Protects Against
Unauthorized Memory Access
• Clocking
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Clock-Fail-Detect Mode
• Interrupts
– Support for up to Three External Core
Interrupts
– Peripheral Interrupt Expansion (PIE) Block
That Supports All Peripheral Interrupts
• High-speed, 12-Bit ADC
– 80 ns (12.5 MSPS) Conversion Rate
– 16 Channels
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Internal or External Reference
• High-Resolution PWM
– 16 Outputs with 150 ps Resolution
– 14.8 Bits at 200-KHz Switching
– 13.4 Bits at 500-KHz Switching
– 12.4 Bits at 1-MHz Switching
• Communications Port Peripherals
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
– Serial Peripheral Interface (SPI) Module
– Serial Communications Interface (SCI)
– Inter-Integrated Circuit (I2C) Bus
• Timers
– Three 32-bit CPU Timers
– Up to 16 16-bit Timers
– Watchdog Timer Module
• Up to 35 General-Purpose Input/Output (GPIO)
Pins With Input Filtering
• On-chip JTAG Emulation With Real-time
Debug via Hardware
• JTAG Boundary Scan Support
• Low-power IDLE, STANDBY, and HALT Modes
• Development Tools
– F28044 eZdsp Starter Kit
– Code Composer Studio™ IDE With Flash
Programming Plug-in
– C28x-optimized ANSI C/C++
Compiler/Assembler/Linker
– DSP/BIOS™ Real-time Operating System
– USB-based JTAG Emulators
• Available Software
– C2000™ Digital Power Supply Software
Library
– C28x™ IQ Math Library
– C28x Header Files With Example Programs
for all Peripherals
– C28x DSP Library
– C28x Digital Motor Control Software Library
• Package Options
– 100-pin Thin Quad Flatpack (PZ)
– 100-pin MicroStar BGA™ (GGM, ZGM)
– RoHS-compliant, Green Packaging
• Temperature Range:
-40°C to 85°C (PZ, GGM, ZGM)
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
(1)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C28x, Code Composer Studio, DSP/BIOS, C2000, C28x, MicroStar BGA, TMS320 are trademarks of Texas Instruments.
eZdsp, XDS510USB are trademarks of Spectrum Digital.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
1.2 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial
development, which, in one package, includes:
• On-board JTAG emulation via USB or parallel port
• Appropriate emulation driver
• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own
hardware, purchase Code Composer Studio™ IDE separately for software development and
a JTAG emulation tool to get started on your project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software
• The Quick Start Readme in the /doc directory to run your first application.
• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report
(literature number SPRAA85 )
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.
• Flash Tools: C28x Flash Tools
• TMS320F281x Flash Programming Solutions (literature number SPRB169 )
• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature
number SPRA958 )
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit the TI website at
http://www.ti.com or http://www.ti.com/c2000getstarted .
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Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
2 Introduction
The TMS320F28044 device, member of the TMS320C28x™ DSP generation, is a highly integrated,
high-performance solution for demanding control applications.
Throughout this document, TMS320F28044 is abbreviated as F28044. Table 2-1 provides a summary of
the device's features.
Table 2-1. Hardware Features
FEATURE F28044
Instruction cycle (at 100 MHz) 10 ns
Single-access RAM (SARAM) (16-bit word)
3.3-V on-chip flash (16-bit word) 64K
On-chip ROM (16-bit word) –
Code security for on-chip flash/SARAM/OTP blocks Yes
Boot ROM (4K X16) Yes
One-time programmable (OTP) ROM
(16-bit word)
PWM outputs (one 16-bit timer/module) ePWM1-16
HRPWM channels ePWM1-16
Watchdog timer Yes
No. of channels 16
12-Bit ADC MSPS 12.5
Conversion time 80 ns
32-Bit CPU timers 3
Serial Peripheral Interface (SPI) SPI-A
Serial Communications Interface (SCI) SCI-A
Inter-Integrated Circuit (I2C) I2C-A
Digital I/O pins (shared) 35
External interrupts 3
Supply voltage 1.8-V Core, 3.3-V I/O Yes
Packaging 100-Pin PZ Yes
100-ball GGM, ZGM Yes
Temperature options A: -40 ° C to 85 ° C (PZ, GGM, ZGM)
Product status
(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.
(1)
(L0, L1, M0, M1)
TMS320F28044
10K
1K
TMS
2.1 Pin Assignments
The TMS320F28044 100-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2-1 . The 100-ball GGM and ZGM ball grid array (BGA) terminal assignments are shown in
Figure 2-2 . Table 2-2 describes the function(s) of each pin.
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50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GPIO0/EPWM1A
TCK
TMS
TDI
XRS
TRST
V
SS
V
DD
V
DDIO
V
SS
V
DD
V
SS
GPIO17/SPISOMIA/TZ6
V
SS
V
SS
V
DD
V
DDIO
GPIO16/SPISIMOA/TZ5
V
DD2A18
V
SS2AGND
V
DDAIO
GPIO12/TZ1/EPWM13A
V
SS
V
DDIO
GPIO29/SCITXDA/TZ6
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO14/TZ3/EPWM15A
V
SS
V
DD
V
DD1A18
V
SS1AGND
V
SSA2
V
DDA2
GPIO15/TZ4/EPWM16A
V
SSAIO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO13/TZ2/EPWM14A
V
DD3VFL
V
SS
V
DD
GPIO28/SCIRXDA/TZ5
V
SS
V
SS
V
DD
V
SS
V
DDIO
GPIO26
TEST2
TEST1
GPIO25
XCLKIN
X1
X2
EMU1
EMU0
GPIO24
GPIO27
TDO
GPIO30/TZ3
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFIN
ADCREFM
ADCREFP
ADCRESEXT
GPIO34
GPIO1/EPWM2A
GPIO2/EPWM3A
GPIO3/EPWM4A
XCLKOUT
GPIO20
GPIO9/EPWM10A
GPIO8/EPWM9A/ADCSOCAO
GPIO21
GPIO23
GPIO22
GPIO11/EPWM12A
GPIO10/EPWM11A/ADCSOCBO
GPIO6/EPWM7A/EPWMSYNCI/EPWMSYNCO
GPIO5/EPWM6A
GPIO7/EPWM8A
GPIO19/SPISTEA/TZ2
GPIO18/SPICLKA/TZ1
GPIO4/EPWM5A
GPIO31/TZ4
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Figure 2-1. 100-Pin PZ LQFP (Top View)
Introduction 12 Submit Documentation Feedback
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4
C
B
A
D
E
21 3
K
F
G
H
J
5 76 98 10
Bottom View
TRST TCK
TDI
TDO TMS
EMU0
EMU1
V
DD3VFL
TEST1
TEST2
XCLKOUT
XCLKIN
X1
X2
XRS
GPIO0
GPIO1
GPIO2 GPIO3 GPIO4
GPIO5
GPIO6GPIO7
GPIO9 GPIO8
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23GPIO24GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
V
DDA2
V
DD1A18 V
SS1AGND
V
DD
V
DDIO
VSSAIO
V
DDAIO
VSSA2
ADCINA7
V
SS2AGND
V
DD2A18
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDIO
V
DDIO
V
DDIO
VSS
V
SS
V
SS
V
SS
V
SS
VSS
V
SS
V
SS
V
SS
V
SS
V
SS
ADCINB2
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB1
ADCINB0
ADCLO
ADCRESEXT
ADCREFIN
ADCREFP
ADCREFM
ADCINB3
ADCINB5
ADCINB4
ADCINB6
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Figure 2-2. 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
2.2 Signal Descriptions
Table 2-2 describes the signals on the F28044 device. All digital inputs are TTL-compatible. All outputs
are 3.3 V with CMOS levels. Inputs are not 5-V tolerant.
Table 2-2. Signal Descriptions
PIN NO.
NAME DESCRIPTION
PIN #
TRST 84 A6
TCK 75 A10 JTAG test clock with internal pullup (I, ↑ )
TMS 74 B10
TDI 73 C9
TDO 76 B9
EMU0 80 A8 (I/O/Z, 8 mA drive ↑ )
EMU1 81 B7 (I/O/Z, 8 mA drive ↑ )
V
DD3VFL
TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is
PZ
96 C4
GGM/
ZGM
BALL #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of
the debugger and the application. (I, ↓ )
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑ )
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑ )
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
FLASH
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to V
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
used to feed clock to X1 pin), this pin must be tied to GND. (I)
DDIO
(1)
.
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME DESCRIPTION
PIN #
GGM/
PZ
ZGM
BALL #
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
X2 86 C6
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
XRS 78 B8
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑ )
The output buffer of this pin is an open-drain with an internal pullup (100 µ A, typical). It is
recommended that this pin be driven by an open-drain device.
ADC SIGNALS
ADCINA7 16 F3 ADC Group A, Channel 7 input (I)
ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)
ADCINA4 19 G1 ADC Group A, Channel 4 input (I)
ADCINA3 20 G2 ADC Group A, Channel 3 input (I)
ADCINA2 21 G3 ADC Group A, Channel 2 input (I)
ADCINA1 22 H1 ADC Group A, Channel 1 input (I)
ADCINA0 23 H2 ADC Group A, Channel 0 input (I)
ADCINB7 34 K5 ADC Group B, Channel 7 input (I)
ADCINB6 33 H4 ADC Group B, Channel 6 input (I)
ADCINB5 32 K4 ADC Group B, Channel 5 input (I)
ADCINB4 31 J4 ADC Group B, Channel 4 input (I)
ADCINB3 30 K3 ADC Group B, Channel 3 input (I)
ADCINB2 29 H3 ADC Group B, Channel 2 input (I)
ADCINB1 28 J3 ADC Group B, Channel 1 input (I)
ADCINB0 27 K2 ADC Group B, Channel 0 input (I)
ADCLO 24 J1 Low Reference (connect to analog ground) (I)
ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground.
ADCREFIN 35 J5 External reference input (I)
ADCREFP 37 G5
ADCREFM 36 H5
Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor
of 2.2 µ F to analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor
of 2.2 µ F to analog ground. (O)
CPU AND I/O POWER PINS
V
DDA2
V
SSA2
V
DDAIO
V
SSAIO
V
DD1A18
V
SS1AGND
V
DD2A18
V
SS2AGND
15 F2 ADC Analog Power Pin (3.3 V)
14 F1 ADC Analog Ground Pin
26 J2 ADC Analog I/O Power Pin (3.3 V)
25 K1 ADC Analog I/O Ground Pin
12 E4 ADC Analog Power Pin (1.8 V)
13 E5 ADC Analog Ground Pin
40 J6 ADC Analog Power Pin (1.8 V)
39 K6 ADC Analog Ground Pin
(1)
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME DESCRIPTION
PIN #
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
GPIO0 General purpose input/output 0 (I/O/Z)
EPWM1A Enhanced PWM1 Output and HRPWM channel (O)
- -
- GPIO1 General purpose input/output 1 (I/O/Z)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)
- -
- GPIO2 General purpose input/output 2 (I/O/Z)
EPWM3A Enhanced PWM3 Output A and HRPWM channel (O)
- -
- GPIO3 General purpose input/output 3 (I/O/Z)
EPWM4A Enhanced PWM4 Output A and HRPWM channel (O)
- -
- GPIO4 General purpose input/output 4 (I/O/Z)
EPWM5A Enhanced PWM5 output A and HRPWM channel (O)
- -
- GPIO5 General purpose input/output 5 (I/O/Z)
EPWM6A Enhanced PWM6 Output A and HRPWM channel (O)
- -
- -
GGM/
PZ
ZGM
BALL #
10 E2
42 G6
59 F10
68 D7
CPU and Logic Digital Power Pins (1.8 V)
85 B6
93 D4
3 C2
46 H7
65 E9
Digital I/O Power Pin (3.3 V)
82 A7
2 B1
11 E3
41 H6
49 K9
55 H10
62 F7 Digital Ground Pins
69 D10
77 A9
87 D6
89 A5
94 A4
47 K8
44 K7
45 J7
48 J8
51 J9
53 H9
GPIOA AND PERIPHERAL SIGNALS
(3)
(3)
(3)
(3)
(3)
(3)
(1)
(2)
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
(3) The pullups on GPIO0-GPIO15 pins are not enabled at reset.
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME DESCRIPTION
PIN #
GPIO6 General purpose input/output 6 (I/O/Z)
EPWM7A Enhanced PWM7 output A and HRPWM channel (O)
EPWMSYNCI External ePWM sync pulse input (I)
EPWMSYNCO External ePWM sync pulse output (O)
GPIO7 General purpose input/output 7 (I/O/Z)
EPWM8A 58 G8 Enhanced PWM8 Output A and HRPWM channel (O)
- GPIO8 General purpose input/output 8 (I/O/Z)
EPWM9A Enhanced PWM9 output A(O)
- ADCSOCAO ADC start-of-conversion A (O)
GPIO9 General purpose input/output 9 (I/O/Z)
EPWM10A 61 F8 Enhanced PWM10 Output A and HRPWM channel (O)
- GPIO10 General purpose input/output 10 (I/O/Z)
EPWM11A Enhanced PWM11 Output A and HRPWM channel (O)
- ADCSOCBO ADC start-of-conversion B (O)
GPIO11 General purpose input/output 11 (I/O/Z)
EPWM12A 70 D9 Enhanced PWM12 Output A and HRPWM channel (O)
- GPIO12 General purpose input/output 12 (I/O/Z)
TZ1 Trip Zone input 1 (I)
EPWM13A Enhanced PWM13 Output A and HRPWM channel (O)
- GPIO13 General purpose input/output 13 (I/O/Z)
TZ2 Trip zone input 2 (I)
EPWM14A Enhanced PWM14 Output A and HRPWM channel (O)
- GPIO14 General purpose input/output 14 (I/O/Z)
TZ3 Trip zone input 3 (I)
EPWM15A Enhanced PWM15 Output A and HRPWM channel (O)
- GPIO15 General purpose input/output 15 (I/O/Z)
TZ4 Trip zone input 4 (I)
EPWM16A Enhanced PWM16 Output A and HRPWM channel (O)
- GPIO16 General purpose input/output 16 (I/O/Z)
SPISIMOA SPI-A slave in, master out (I/O)
- TZ5 Trip zone input 5 (I)
GPIO17 General purpose input/output 17 (I/O/Z)
SPISOMIA SPI-A slave out, master in (I/O)
- TZ6 Trip zone input 6(I)
GPIO18 General purpose input/output 18 (I/O/Z)
SPICLKA SPI-A clock input/output (I/O)
- TZ1 Trip zone input 1 (I)
GPIO19 General purpose input/output 19 (I/O/Z)
SPISTEA SPI-A slave transmit enable input/output (I/O)
- TZ2 Trip zone input 2 (I)
GPIO20 General purpose input/output 20 (I/O/Z)
- -
- -
- -
PZ
56 G9
60 F9
64 E10
1 B2
95 B4
8 D3
9 E1
50 K10
52 J10
54 H8
57 G10
63 F6
GGM/
ZGM
BALL #
(3)
(3)
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
(1)
(4) The pullups on GPIO16-GPIO34 are enabled upon reset.
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME DESCRIPTION
PIN #
GPIO21 General purpose input/output 21 (I/O/Z)
- -
- -
PZ
67 E7
GGM/
ZGM
BALL #
(4)
- GPIO22 General purpose input/output 22 (I/O/Z)
- -
- -
71 D8
(4)
- GPIO23 General purpose input/output 23 (I/O/Z)
- -
- -
72 C10
(4)
- GPIO24 General purpose input/output 24 (I/O/Z)
- -
- -
83 C7
(4)
- GPIO25 General purpose input/output 25 (I/O/Z)
- -
- -
91 C5
(4)
- GPIO26 General purpose input/output 26 (I/O/Z)
- -
- -
99 A2
(4)
- GPIO27 General purpose input/output 27 (I/O/Z)
- -
- -
79 C8
(4)
- GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)
SCIRXDA SCI receive data (I)
- -
92 D5
TZ5 Trip zone 5 (I)
GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)
SCITXDA SCI transmit data (O)
- -
4 C3
TZ6 Trip zone 6 (I)
GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)
- -
- -
6 D2
TZ3 Trip zone input 3 (I)
GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)
- -
- -
7 D1
TZ4 Trip zone input 4 (I)
GPIO32 General purpose input/output 32 (I/O/Z)
SDAA I2C data open-drain bidirectional port (I/OD)
EPWMSYNCI Enhanced PWM external sync pulse input (I)
100 A1
(4)
ADCSOCAO ADC start-of-conversion (O)
(1)
(4)
(4)
(4)
(4)
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME DESCRIPTION
PIN #
GPIO33 General-Purpose Input/Output 33 (I/O/Z)
SCLA I2C clock open-drain bidirectional port (I/OD)
EPWMSYNCO Enhanced PWM external synch pulse output (O)
ADCSOCBO ADC start-of-conversion (O)
GPIO34 General-Purpose Input/Output 34 (I/O/Z)
- -
- -
- -
(1) The pullups on GPIO16-GPIO34 are enabled upon reset.
PZ
5 C1
43 G7
GGM/
ZGM
BALL #
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
(1)
(1)
(1)
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INT[12:1]
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
C28x CPU
(100 MHz)
NMI, INT13
Memory Bus
Boot ROM
4 K 16
(1-wait state)
FLASH
64K x 16
L1 SARAM
(B)
4 K 16
(0-wait)
L0 SARAM
4 K 16
(0-wait)
M0 SARAM
1 K 16
M1 SARAM
1 K 16
INT14
32-bit CPU TIMER 0
32-bit CPU TIMER 1
32-bit CPU TIMER 2
SYSCLKOUT
RS
CLKIN
12-Bit ADC
ADCSOCA/B
SOCA/B
16 Channels
16
32
XCLKOUT
XRS
XCLKIN
X1
X2
32
System Control
(Oscillator, PLL,
Peripheral Clocking,
Low Power Modes,
WatchDog)
ePWM1−16
(16 PWM outputs,
6 trip zones,
6 timers 16-bit)
External Interrupt
Control
PIE
(96 Interrupts)
(A)
FIFO
FIFO
FIFO
SCI-A
SPI-A
I2C-A
2
16
4
GPIO MUX
GPIOs
(35)
TINT0
TINT1
TINT2
7
OTP
(D)
1K 16
Peripheral Bus
Protected by the code-security module.
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
3 Functional Overview
A. 43 of the possible 96 interrupts are used on the devices.
B. The 1K x 16 OTP has been replaced with 1K x 16 ROM for the F28044 device.
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Figure 3-1. Functional Block Diagram
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3.1 Memory Map
0x00 0000
Block Start
Address
Data Space
M0 SARAM (1K y 16)
0x00 0400
0x00 0800
0x00 0D00
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3F 7FF8
0x3F 8000
0x3F 9000
0x3F A000
0x3F F000
0x3F FFC0
OTP
(1 K y 16, Secure Zone)
FLASH
64 K y 16, Secure Zone)
Boot ROM (4 K y 16)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
Reserved
M1 SARAM (1K y 16)
L0 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
L1 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
L0 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
L1 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
128-bit Password
0x3E 8000
Prog Space
Peripheral Frame 0
Peripheral Frame 1
(protected)
Peripheral Frame 2
(protected)
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
0x00 0E00
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
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User program cannot access these memory maps in program space.
Figure 3-2. F28044 Memory Map
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
Table 3-1. Addresses of Flash Sectors
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000 - 0x3E BFFF Sector D (16K x 16)
0x3E C000 - 0x3E FFFF Sector C (16K x 16)
0x3F 0000 - 0x3F 3FFF Sector B (16K x 16)
0x3F 4000 - 0x3F 7F7F Sector A (16K x 16)
0x3F 7F80 - 0x3F 7FF5
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
Program to 0x0000 when using the
Code Security Module
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
The wait-states for the various spaces in the memory map area are listed in Table 3-2 .
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Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 3-2. Wait-states
AREA WAIT-STATES COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait Fixed
Peripheral Frame 1 Fixed.
Peripheral Frame 2 Fixed
L0 & L1 SARAMs 0-wait
OTP is possible at a reduced CPU frequency. See Section
Flash
Boot-ROM 1-wait Fixed
3.2 Brief Descriptions
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
Programmable,
1-wait minimum
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See Section
Programmed via the Flash registers. 1-wait-state operation
Section 3.2.5 for more information.
Programmed via the Flash registers. 0-wait-state operation
Section 3.2.5 for more information.
3.2.1 C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a
very efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the
F28044 device adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus
are supported on the F28044. One version only supports 16-bit accesses (called peripheral frame 2). The
other version supports both 16- and 32-bit accesses (called peripheral frame 1).
3.2.4 Real-Time JTAG and Analysis
The F28044 device implements the standard IEEE 1149.1 JTAG interface. Additionally, the device
supports real-time mode of operation whereby the contents of memory, peripheral and register locations
can be modified while the processor is running and executing code and servicing interrupts. The user can
also single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F28044 implements the real-time mode in hardware within the CPU. This is a unique
feature to the F28044, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
3.2.5 Flash
3.2.6 M0, M1 SARAMs
The F28044 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. Both
devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The
user can individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that
erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve
higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used
to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for
data variables and should not contain program code.
NOTE
The F28044 Flash and OTP wait-states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide
(literature number SPRU712).
The F28044 device contains these two blocks (M0/M1) of single access memory, each 1K x 16 in size.
The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other
memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use
M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x
device presents a unified memory map to the programmer. This makes for easier programming in
high-level languages.
3.2.7 L0, L1 SARAMs
The F28044 device contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,
L1-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is
mapped to both program and data space.
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3.2.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 3-3. Boot Mode Selection
MODE DESCRIPTION GPIO34
Boot to Flash/ROM Jump to Flash/ROM address 0x3F 7FF6 1 1 1
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
SCI-A Boot Load a data stream from SCI-A 1 1 0
SPI-A Boot Load from an external serial SPI EEPROM on SPI-A 1 0 1
I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 0
the I2C bus
eCAN-A Boot Reserved. This mode should not be used. 0 1 1
Boot to M0 SARAM Jump to M0 SARAM address 0x00 0000. 0 1 0
Boot to OTP Jump to OTP address 0x3D 7800 0 0 1
Parallel I/O Boot Load data from GPIO0 - GPIO15 0 0 0
GPIO18 GPIO29
SPICLKA SCITXDA
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
3.2.9 Security
The device supports high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents via the JTAG port,
executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct
128-bit "KEY" value, which matches the value stored in the password locations within the Flash.
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code
Security Password is programmed. If security is not a concern, addresses 0x3F7F80
through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are
reserved for data variables and should not contain program code.
The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
NOTE
NOTE
Code Security Module Disclaimer
THE CODE SECURITY MODULE ("CSM") INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS
INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND
CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE
WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER,
EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN
ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
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3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28044 device, 43 of the possible 96
interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed
into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector
stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical
CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is
controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE
block.
3.2.11 External Interrupts (XINT1, XINT2, XNMI)
The F28044 device supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be
connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative,
positive, or both negative and positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a
valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike
the 281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can
be configured to trigger any external interrupt.
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
3.2.12 Oscillator and PLL
The F28044 device can be clocked by an external oscillator or by a crystal attached to the on-chip
oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be
changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power
operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be
set in bypass mode.
3.2.13 Watchdog
The F28044 device contains a watchdog timer. The user software must regularly reset the watchdog
counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The
watchdog can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) and the ADC
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled
from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The F28044 device is full static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
HALT: Turns off the internal oscillator. This mode basically shuts down the device and places it in
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
the lowest possible power consumption mode. A reset or external signal can wake the
device from this mode.
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
The F28044 device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Control, Programming, Erase, Verify Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers (dual-mapped)
PF1: GPIO: GPIO MUX Configuration and Control Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Result Register
I2C: Inter-Integrated Circuit Module and Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system
functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of
the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
3.2.19 Control Peripherals
The F28044 device supports the following peripherals which are used for embedded control and
communication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.
ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
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3.2.20 Serial Port Peripherals
The F28044 device supports the following serial communication peripherals:
TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the F28044 device, the SPI contains a 16-level receive and
transmit FIFO for reducing interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F28044 device, the SCI contains a 16-level receive and transmit
FIFO for reducing interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module.
On the F28044 device, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
3.3 Register Map
The F28044 device contains three peripheral register spaces. The spaces are categorized as follows:
Peripheral These are peripherals that are mapped directly to the CPU memory bus.
Frame 0: See Table 3-4
Peripheral These are peripherals that are mapped to the 32-bit peripheral bus.
Frame 1 See Table 3-5
Peripheral These are peripherals that are mapped to the 16-bit peripheral bus.
Frame 2: See Table 3-6
Table 3-4. Peripheral Frame 0 Registers
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
Device Emulation Registers 0x0880 - 0x09FF 384 EALLOW protected
FLASH Registers
Code Security Module Registers 0x0AE0 - 0x0AEF 16 EALLOW protected
ADC Result Registers (dual-mapped) 0xB00 - 0xB0F 16
CPU-TIMER0/1/2 Registers 0x0C00 - 0x0C3F 64 Not EALLOW protected
PIE Registers 0x0CE0 - 0x0CFF 32
PIE Vector Table 0x0D00 - 0x0DFF 256 EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).
(4)
0x0A80 - 0x0ADF 96
(1) (2)
EALLOW protected
CSM Protected
(3)
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TMS320F28044
Digital Signal Processor
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Table 3-5. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
ePWM1 + HRPWM Registers 0x6800 - 0x683F 64
ePWM2 + HRPWM Registers 0x6840 - 0x687F 64
ePWM3 + HRPWM Registers 0x6880 - 0x68BF 64
ePWM4 + HRPWM Registers 0x68C0 - 0x68FF 64
ePWM5 + HRPWM Registers 0x6900 - 0x693F 64
ePWM6 + HRPWM Registers 0x6940 - 0x697F 64
ePWM7 + HRPWM Registers 0x6980 - 0x69BF 64
ePWM8 + HRPWM Registers 0x69C0 - 0x69FF 64
ePWM9 + HRPWM Registers 0x6600 - 0x663F 64
ePWM10 + HRPWM Registers 0x6640 - 0x667F 64
ePWM11 + HRPWM Registers 0x6680 - 0x66BF 64
ePWM12 + HRPWM Registers 0x66C0 - 0x66FF 64
ePWM13 + HRPWM Registers 0x6700 - 0x673F 64
ePWM14 + HRPWM Registers 0x6740 - 0x677F 64
ePWM15 + HRPWM Registers 0x6780 - 0x67BF 64
ePWM16 + HRPWM Registers 0x67C0 - 0x67FF 64
GPIO Control Registers 0x6F80 - 0x6FBF 128 EALLOW protected
GPIO Data Registers 0x6FC0 - 0x6FDF 32 Not EALLOW protected
GPIO Interrupt and LPM Select Registers 0x6FE0 - 0x6FFF 32 EALLOW protected
(1) All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.
(1) (2)
Some ePWM registers are EALLOW
protected.
See Table 4-2
Table 3-6. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
System Control Registers 0x7010 - 0x702F 32 EALLOW Protected
SPI-A Registers 0x7040 - 0x704F 16
SCI-A Registers 0x7050 - 0x705F 16
External Interrupt Registers 0x7070 - 0x707F 16 Not EALLOW Protected
ADC Registers 0x7100 - 0x711F 32
I2C Registers 0x7900 - 0x792F 48
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
(2) Missing segments of memory space are reserved and should not be used in applications.
(1) (2)
3.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-7 .
Table 3-7. Device Emulation Registers
NAME ADDRESS RANGE SIZE (x16) DESCRIPTION
DEVICECNF 2 Device Configuration Register
PARTID 0x0882 1 Part ID Register 0x00FC - F28044
REVID 0x0883 1 Revision ID Register 0x0000 - Silicon Rev. 0 - TMX or TMS
PROTSTART 0x0884 1 Block Protection Start Address Register
PROTRANGE 0x0885 1 Block Protection Range Address Register
0x0880
0x0881
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