SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
D
Very Low Power Consumption
1 mW Typ at VDD = 5 V
D
Capable of Operation in Astable Mode
D
CMOS Output Capable of Swinging Rail
to Rail
D
High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
D
Output Fully Compatible With CMOS, TTL,
and MOS
D
Low Supply Current Reduces Spikes
During Output Transitions
D
Single-Supply Operation From 2 V to 15 V
D
Functionally Interchangeable With the
NE555; Has Same Pinout
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2
description
The TLC555 is a monolithic timing circuit
fabricated using the TI LinCMOS process. The
D, DB, JG, P, OR PW PACKAGE
(TOP VIEW)
GND
TRIG
OUT
RESET
NC
TRIG
NC
OUT
NC
NC – No internal connection
1
2
3
4
FK PACKAGE
(TOP VIEW)
NC
3212019
4
5
6
7
8
910111213
NC
GND
NC
NC
RESET
8
7
6
5
V
DD
NC
18
17
16
15
14
NC
CONT
V
DD
DISCH
THRES
CONT
NC
DISCH
NC
THRES
NC
timer is fully compatible with CMOS, TTL, and
MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses
smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations
are possible. Power consumption is low across the full range of power supply voltage.
Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and
GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.
The TLC555C is characterized for operation from 0°C to 70°C. The TLC555I is characterized for operation from
– 40°C to 85°C. The TLC555M is characterized for operation over the full military temperature range of – 55°C
to 125°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
available from Texas Instruments.
Copyright 1997, Texas Instruments Incorporated
1
TLC555, TLC555Y
CHIP
LinCMOS TIMERS
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
AVAILABLE OPTIONS
PACKAGED DEVICES
V
T
A
0°C to
70°C
–40°C to
85°C
–55°C to
125°C
The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available
left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25°C.
DD
RANGE
2 V to 15 VTLC555CDTLC555CDBLE——TLC555CPTLC555CPWLE
3 V to 15 VTLC555ID———TLC555IP—
5 V to 15 VTLC555MD—TLC555MFKTLC555MJGTLC555MP—
SMALL
OUTLINE
(D)
RESET
VOLTAGE
†
For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.
†
<MINIrrelevantIrrelevantLOn
>MAX<MINIrrelevantHOff
>MAX>MAX>MAXLOn
>MAX>MAX<MINAs previously established
SSOP
(DB)
TRIGGER
VOLTAGE
†
CHIP
CARRIER
(FK)
FUNCTION TABLE
THRESHOLD
VOLTAGE
†
CERAMIC
DIP
(JG)
OUTPUT
PLASTIC
DIP
(P)
DISCHARGE
SWITCH
TSSOP
(PW)
FORM
(Y)
TLC555Y
functional block diagram
CONT
V
DD
8
R
TRIG
6
R
2
R
1
GND
THRES
Pin numbers are for all packages except the FK package.
RESET can override TRIG, which can override THRES.
RESET
5
4
R1
3
R
1
S
OUT
7
DISCH
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC555, TLC555Y
LinCMOS TIMERS
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
TLC555Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
RESETCONT
50
64
(5)
V
DD
(8)
R
THRES
(6)
R
(2)
TRIG
R
(1)
GND
RESET can override TRIG, which can override THRES.
(4)
R1
R
S
1
(3)
(7)
OUT
DISCH
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
T
l
R
l
D
7
11
94
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
equivalent schematic (each channel)
CONT
THRES
COMPONENT COUNT
Transistors
Resistors
39
OUT
TLC555, TLC555Y
LinCMOS
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
emp
5
V
DD
TIMERS
ate
e
ease
ate:
–
–
TRIGRESET
DISCH
GND
TLC555, TLC555Y
LinCMOS TIMERS
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, DB, P, or PW package 260°C. . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network GND.
SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I
TEST
CONDITIONS
I(TRIG)
I(TRIG)
I(RESET)
I(RESET)
Control voltage (open circuit) as
a percentage of supply voltage
Discharge switch on-stage
voltage
Discharge switch off-stage
current
p
p
pp
†
Full range is 0°C to 70°C for the TLC555C and – 40°C to 85°C for the TLC555I. For conditions shown as MAX, use the appropriate value specified
in the recommended operating conditions table.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
OL
OH
OL
= 1
= –
= 1
A
25°C0.951.331.651.62.4
Full range0.851.751.52.5
25°C1010
MAX75150
25°C0.40.670.950.7111.29
Full range0.31.050.611.39
25°C1010
MAX75150
25°C0.41.11.50.41.11.5
Full range0.320.31.8
25°C1010
MAX75150
MAX66.7%66.7%
25°C0.030.20.030.2
Full range0.250.375
25°C0.10.1
MAX0.5120
25°C1.51.91.51.9
Full range1.52.5
25°C0.070.30.070.3
Full range0.350.4
25°C250250
Full range400500
TLC555CTLC555I
MINTYPMAXMINTYPMAX
p
p
p
µ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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