Texas Instruments JM38510-36101B2A, JM38510-36101BFA, JM38510-36101BEA, SN54173J, SN54LS173AJ Datasheet
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SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
D
3-State Outputs Interface Directly With
System Bus
D
Gated Output-Control LInes for Enabling or
SN54173, SN54LS173A ...J OR W PACKAGE
SN74173 ...N PACKAGE
SN74LS173A ...D or N PACKAGE
(TOP VIEW)
Disabling the Outputs
1
D
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
– Parallel Load
– Do Nothing (Hold)
D
For Application as Bus Buffer Registers
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
M
N
1Q
2Q
3Q
4Q
CLK
GND
16
V
15
14
13
12
11
10
CC
CLR
1D
2D
3D
4D
2
G
9
G
1
2
3
4
5
6
7
8
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
TYPICAL
TYPE
’173 23 ns 35 MHz
’LS173A 18 ns 50 MHz
PROPAGATION
DELAY TIME
MAXIMUM
CLOCK
FREQUENCY
description
The ’173 and ’LS173A 4-bit registers include
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
V
CC
CLR
18
17
16
15
14
1Q
2Q
NC
3Q
4Q
NMNC
3212019
4
5
6
7
8
910111213
1D
2D
NC
3D
4D
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
high-impedance third state and increased
CLK
GND
NC – No internal connection
NC
G1
G2
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively . Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G
1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54173, SN54LS173A, SN74173, SN74LS173A
CLR
CLK
Q
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
FUNCTION TABLE
INPUTS
DATA ENABLE
G1 G2
H X X X X L
L LXXX Q
L↑HXX Q
L↑XHX Q
L↑L
L↑LLH H
When either M or N (or both) is (are) high, the output is
disabled to the high-impedance state; however, sequential
operation of the flip-flops is not affected.
DATA
L
D
L
OUTPUT
0
0
0
L
15
1
2
9
10
7
14
13
12
11
†
’173 ’LS173A
R
&
&
1D
EN
C1
3
1Q
4
2Q
5
3Q
6
4Q
CLR
G
G2
CLK
1D
2D
3D
4D
15
1
M
2
N
9
1
10
7
14
13
12
11
R
&
EN
&
C1
1D
logic symbol
CLR
M
N
G
1
2
G
CLK
1D 1Q
2D
3D
4D
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
3
4
2Q
5
3Q
6
4Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
Output
Control
M
2
N
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
Data
Enable
1D
G
G
2D
CLK
3D
14
9
1
10
2
13
7
12
1D
R
1D
R
1D
C1
C1
3
1Q
4
2Q
11
4D
15
CLR
Pin numbers shown are for D, J, N, and W packages.
R
1D
R
C1
C1
5
3Q
6
4Q
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
schematics of inputs and outputs
’173 ’LS173A
Equivalent of Each Input Equivalent of Each Input
V
CC
4 kΩ NOM
V
CC
20 kΩ NOM
Input
Typical of All Outputs
V
CC
90 Ω NOM
Output
Input
Typical of All Outputs
V
CC
100 Ω NOM
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage: ’173 –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
4
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
’LS173A –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†
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