Sony HCD-SR4W Service Manual

HCD-SR4W

Amplifier section

Stereo mode (rated) 65 W + 65 W (4 ohms at

1 kHz, DIN)

Surround mode Front:

114

W +

114

W
(reference) (with SS-TS21)
music power output Center*:

114

W
(with SS-CT33)
Surround*:

114

W +

114

W

(with SA-TS22W,
Subwoofer*:

115

W × 2

(with SS-WS12)

*Depending on the sound field settings and the source

,

there may be no sound output.

Inputs VIDEO/TV/SAT:

Sensitivity: 250 mV/
450 mV/450 mV

Impedance: 50 kilohms

Output SURROUND BACK

Voltage: 2V
Impedance: 1 kilohms

Phones Accepts low-and high-

impedance headphones.

Super Audio CD/DVD system

Laser Semiconductor laser

(Super Audio CD/DVD: λ
= 650 nm)
(CD: λ = 780 nm)
Emission duration:
continuous

Signal format system PAL/NTSC
Frequency response (at 2 CH STEREO mode)

DVD (PCM): 2 Hz to 22
kHz (±1.0 dB)

CD: 2 Hz to 20 kHz (±1.0
dB)

Harmonic distortion Less than 0.03 %

Tuner section

System PLL quartz-locked digital

synthesizer system
FM tuner section
Tuning range 87.5 – 108.0 MHz (50 kHz

step)
Antenna (aerial) FM wire antenna (aerial)
Antenna (aerial) terminals

75 ohms, unbalanced
Intermediate frequency 10.7 MHz
AM tuner section
Tuning range
European, Russian models:

531 – 1,602 kHz (with the

interval set at 9 kHz)

531 – 1,602 kHz (with the

interval set at 9 kHz)

531 – 1,602 kHz (with the

interval set at 9 kHz)

530 – 1,710 kHz (with the

interval set at 10 kHz )
Antenna (aerial) AM loop antenna (aerial)
Intermediate frequency 450 kHz

Middle Easten models:

Other models:

European, Russian models:

Video section

Outputs

Video: 1 Vp-p 75 ohms
V
S video:

Y: 1 Vp-p 75 ohms
C:0.286 Vp-p 75 ohms
COMPONENT:
Y: 1 Vp-p 75 ohms
P

B/CB

, PR/CR: 0.7 Vp-p

75 ohms

ideo: Vp-p 75 ohmsOther models:

General

Power requirements
European models: 230 V AC, 50/60 Hz
Other models: 220 – 240 V AC,

50/60 Hz

Power consumption 90 W

0.3 W (at the Power
Saving mode)

Dimensions (approx.) 430 × 60 × 385 mm

incl. projecting

parts

Mass (approx.) 4.7 kg

Design and specifications are subject to change
without notice.

/h/d) (w

SS-TS21)

SERVICE MANUAL

Ver 1.0 2004.07

HCD-SR4W is the amplifier, DVD/
SACD and tuner section in DAV-SR4W.

SPECIFICATIONS

AEP Model

UK Model

E Model

Australian Model

Chinese Model

Model Name Using Similar Mechanism HCD-SR1
Mechanism T ype CDM80A-DVBU24
Optical Pick-up Name DBU-1

9-879-095-01

2004G1678-1
© 2004.07

Sony Corporation

Audio Group
Published by Sony Engineering Corporation

SACD/DVD RECEIVER

HCD-SR4W

Laser component in this product is capable of emitting radiation
exceeding the limit for Class 1.

This appliance is classified as
a CLASS 1 LASER product.
The CLASS 1 LASER
PRODUCT MARKING is
located on the rear exterior.

CAUTION

Use of controls or adjustments or performance of procedures
other than those specified herein may result in hazardous radiation
exposure.

Notes on chip component replacement

• Never reuse a disconnected chip component.

• Notice that the minus side of a tantalum capacitor may be

damaged by heat.

Flexible Circuit Board Repairing

• Keep the temperature of the soldering iron around 270 °C
during repairing.

• Do not touch the soldering iron on the same conductor of the
circuit board (within 3 times).

• Be careful not to apply force on the conductor when soldering
or unsoldering.

UNLEADED SOLDER

Boards requiring use of unleaded solder are printed with the lead­free mark (LF) indicating the solder contains no lead.
(Caution: Some printed circuit boards may not come printed with

the lead free mark due to their particular size)

: LEAD FREE MARK

Unleaded solder has the following characteristics.

• Unleaded solder melts at a temperature about 40 °C higher
than ordinary solder.
Ordinary soldering irons can be used but the iron tip has to be
applied to the solder joint for a slightly longer time.
Soldering irons using a temperature regulator should be set to
about 350 °C.
Caution: The printed pattern (copper foil) may peel away if

the heated tip is applied for too long, so be careful!

• Strong viscosity
Unleaded solder is more viscou-s (sticky, less prone to flow)
than ordinary solder so use caution not to let solder bridges
occur such as on IC pins, etc.

• Usable with ordinary solder
It is best to use only unleaded solder but unleaded solder may
also be added to ordinary solder.

SAFETY-RELATED COMPONENT WARNING!!

COMPONENTS IDENTIFIED BY MARK 0 OR DOTTED LINE
WITH MARK 0 ON THE SCHEMATIC DIAGRAMS AND IN
THE PARTS LIST ARE CRITICAL TO SAFE OPERATION.
REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE
PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR
IN SUPPLEMENTS PUBLISHED BY SONY.

2

TABLE OF CONTENTS

HCD-SR4W

1. SERVICING NOTE ................................................... 4

2. GENERAL ................................................................... 5

3. DISASSEMBLY

3-1. Disassembly Flow ........................................................... 8

3-2. Side Panel (R)(L), Front Panel Section ........................... 9

3-3. Fl Board........................................................................... 9

3-4. Mechanism Deck (CDM80A-DVBU24)......................... 10

3-5. AMP Board...................................................................... 10

3-6. Switching Regulator ........................................................ 11

3-7. Tuner Unit, IO Board ...................................................... 11

3-8. DMB08 Board ................................................................. 12

3-9. Chassis (Top) ................................................................... 12

3-10. Lever (Loading R/L)........................................................ 13

3-11. Disc Stop Lever, Disc Sensor Lever ................................ 14

3-12. DRIVER Board ............................................................... 14

3-13. RF Board ......................................................................... 15

3-14. Optical Pick-up (DBU-1) ................................................ 15

3-15. Base Unit ......................................................................... 16

3-16. Lever (BU Lock) ............................................................. 16

3-17. Close Lever...................................................................... 17

3-18. Dir Lever, Gear (IDL-B).................................................. 17

3-19. Gear (IDL-C).................................................................... 18

4. TEST MODE ............................................................... 19

5. ELECTRICAL ADJUSTMENT ............................. 27

6. DIAGRAMS

6-1. Block Diagram – RF/SERVO Section – .......................... 30

6-2. Block Diagram – AUDIO (DSP) Section – ..................... 31

6-3. Block Diagram – AUDIO (OUT) Section – .................... 32

6-4. Block Diagram – VIDEO Section – ................................ 33

6-5. Block Diagram – DIAT TRANSMIT Section – .............. 34

6-6. Block Diagram – POWER Section –............................... 35

6-7. Printed Wiring Board – RF Board – ................................ 36

6-8. Schematic Diagram – RF Board –................................... 37

6-9. Printed Wiring Board – DRIVER Board – ...................... 38

6-10. Schematic Diagram – DRIVER Board –......................... 38

6-11. Printed Wiring Board – DMB08 Board (Side A) – ......... 39

6-12. Printed Wiring Board – DMB08 Board (Side B) – ......... 40

6-13. Schematic Diagram – DMB08 Board (1/10) –................ 41

6-14. Schematic Diagram – DMB08 Board (2/10) –................ 42

6-15. Schematic Diagram – DMB08 Board (3/10) –................ 43

6-16. Schematic Diagram – DMB08 Board (4/10) –................ 44

6-17. Schematic Diagram – DMB08 Board (5/10) –................ 45

6-18. Schematic Diagram – DMB08 Board (6/10) –................ 46

6-19. Schematic Diagram – DMB08 Board (7/10) –................ 47

6-20. Schematic Diagram – DMB08 Board (8/10) –................ 48

6-21. Schematic Diagram – DMB08 Board (9/10) –................ 49

6-22. Schematic Diagram – DMB08 Board (10/10) –.............. 50

6-23. Printed Wiring Board – AMP Board (Side A) – .............. 51

6-24. Printed Wiring Board – AMP Board (Side B) – .............. 52

6-25. Schematic Diagram – AMP Board (1/4) – ...................... 53

6-26. Schematic Diagram – AMP Board (2/4) – ...................... 54

6-27. Schematic Diagram – AMP Board (3/4) – ...................... 55

6-28. Schematic Diagram – AMP Board (4/4) – ...................... 56

6-29. Printed Wiring Board – IO Section – .............................. 57

6-30. Schematic Diagram – IO Section (1/2) – ........................ 58

6-31. Schematic Diagram – IO Section (2/2) – ........................ 59

6-32. Printed Wiring Board – DDCON Board –....................... 60

6-33. Schematic Diagram – DDCON Board – ......................... 61

6-34. Printed Wiring Board – DIAT TRANSMIT Board – ...... 62

6-35. Schematic Diagram – DIAT TRANSMIT Board – ........ 63

6-36. Printed Wiring Board – SPEAKER OUT Section –........ 64

6-37. Schematic Diagram – SPEAKER OUT Section – .......... 65

6-38. Printed Wiring Board – FL Board – ................................ 66

6-39. Schematic Diagram – FL Board – ................................... 67

6-40. Printed Wiring Board

– POWER/FRONT PANEL Section –............................. 68

6-41. Schematic Diagram

– POWER/FRONT PANEL Section –............................. 69

7. EXPLODED VIEWS

7-1. Case Section ................................................................... 103

7-2. Front Panel Section ........................................................ 104

7-3. Chassis Section............................................................... 105

7-4. Mechanism Deck Section-1 (CDM80A-DVBU24) ....... 106

7-5. Mechanism Deck Section-2 (CDM80A-DVBU24) ....... 107

7-6. Mechanism Deck Section-3 (CDM80A-DVBU24) ....... 108

7-7. Base Unit Section ........................................................... 109

8. ELECTRICAL PARTS LIST ................................. 110

3

HCD-SR4W

SECTION 1

SERVICING NOTE

NOTES ON HANDLING THE OPTICAL PICK-UP
BLOCK OR BASE UNIT

The laser diode in the optical pick-up block may suffer electrostatic
break-down because of the potential difference generated by the
charged electrostatic load, etc. on clothing and the human body.
During repair, pay attention to electrostatic break-down and also
use the procedure in the printed matter which is included in the
repair parts.
The flexible board is easily damaged and should be handled with
care.

NOTES ON LASER DIODE EMISSION CHECK

The laser beam on this model is concentrated so as to be focused on
the disc reflective surface by the objective lens in the optical pick­up block. Therefore, when checking the laser diode emission,
observe from more than 30 cm away from the objective lens.

MODEL IDENTIFICATION

— BACK PANEL —

Part No.

Model Name Part No.

EA 2-109-513-0[]
HK, SP, TW, KR, CH 2-109-513-1[]
AEP, UK 4-253-896-7[]
RU 4-253-896-8[]
MX, AUS, E41 4-253-896-9[]

• Abbrevia tion
AUS : Australian model
CH : Chinese model
E41 : 230 V AC area in E model
EA : Saudi Arabia model
HK : Hong Kong model
KR : Korean model
MX : Mexican model
RU : Russian model
SP : Singapore model
TW : Taiwan model

4

Front Panel

SECTION 2

GENERAL

HCD-SR4W

This section is extracted
from instruction manual.

A [/1 (power) switch/STANDBY indicator F VOLUME +/–
B Disc slot
C (remote sensor)
D Front panel display
E PHONES (on the side of the system)

jack

G ./>
H x (stop)
I (play/pause)
J FUNCTION
K

Z

(eject)

5

HCD-SR4W

Rear Panel
(European, Russian models)

SPEAKER

A SPEAKER jacks (14)
B SURROUND BACK jack (16)
C VIDEO AUDIO IN (L/R) jacks (21)
D SAT OPTICAL DIGITAL IN jack (22)
E AM terminals (19)

Rear Panel
(Other models)

VIDEO

AUDIO IN

CENTER FRONT LFRONT R

DIR-T1

WOOFERWOOFER

RL

SURROUND

RL

BACK

AUDIO IN

EURO AV OUTPUT(TO TV)

SAT

OPTICAL
DIGITAL IN

SAT

AM

FM 75

COAXIAL

F FM 75 Ω COAXIAL jack (19)
G EURO AV OUTPUT (TO TV) jacks (21)
H SAT AUDIO IN (L/R) jacks (21)
I DIR-T1 jack (14)

A SP EAKER jacks (14)
B SURROUND BACK jack (16)
C VIDEO AUDIO IN (L/R) jacks (21)
D COMPONENT VIDEO OUT jacks (21)
E SA T OPTICA L DIGITAL IN jack (22)
F AM terminals (19)

6

SPEAKER

CENTER FRONT LFRONT R

VIDEO

YP

AUDIO IN

DIR-T1

WOOFERWOOFER

RL

SURROUND

RL

BACK

AUDIO IN

B/CBPR/CR

COMPOMEMT VIDEO OUT

SAT

S VIDEO

(DVD ONLY)

VIDEO

MONITOR OUT

OPTICAL
DIGITAL IN

SAT

AM

FM 75

COAXIAL

G FM 75 Ω COAXIAL jack (19)
H MONITOR OUT (VIDEO/S VIDEO) jacks

(21)

I SAT AUDIO IN (L/R) jacks (21)
J DIR-T1 jack (14)

Remote

Open the cover.

Note

This remote control glows in the dark. However,
before glowing, the remote must be exposed to light for
awhile.

HCD-SR4W

AZ (eject)
B DISPLAY
C SLEEP
D ./>, PRESET –/+
E H (play)
F DVD TOP MENU/ALBUM–
G C/X/x/c/ENTER
H DVD DISPLAY
I AUTO FORMAT DIRECT
J DSGX
K DVD SETUP
L SUBTITLE
M AUDIO
N ANGLE
O Number buttons
P ENTER
Q TUNER MENU
R TV [/1 (on/standby)
S "/1 (standby)
T SONY TV DIRECT
U TUNER/BAND
V FUNCTION
W m/M// SLOW, TUNING –/+
X x (stop)
Y X (pause)
Z MUTING

wj DVD MENU/ALBUM+
wk VOL +/–
wl O RETURN
e; MODE
ea NIGHT MODE
es PLAY MODE
ed REPEAT
ef TV
eg TV/VIDEO
eh TV CH +/–
ej TV VOL +/–
ek AMP MENU

el CLEAR
r; FM MODE

7

HCD-SR4W

SECTION 3

DISASSEMBLY

•This is can be assemble according to the following sequence.

3-1. DISASSEMBLY FLOW

SET

3-2.

SIDE PANEL (R)(L),

FRONT PANEL SECTION

(Page 9)

MECHANISM DECK

3-4.

(CDM80A-DVBU24)

(Page 10)

3-9

. CHASSIS (TOP)

(Page 12)

. LEVER (LOADING R/L)

3-10

(Page 13)

3-

3. FL BOARD

(Page 9)

. AMP BOARD

3-5

(Page 10)

. DRIVER BOARD

3-12

(Page 14)

3-11

. DISC STOP LEVER,

DISC SENSOR LEVER

(Page 14)

SWITCHING REGULATOR

3-6.

(Page 11)

. RF BOARD

3-13

(Page 15)

3-14

. OPTICAL PICK-UP

(DBU-1)

(Page 15)

3-7

. TUNER UNIT, IO BOARD

(Page 11)

. DMB08 BOARD

3-8

(Page 12)

. BASE UNIT

3-15

(Page 16)

3-16

. LEVER (BU LOCK)

(Page 16)

. CLOSE LEVER

3-17

(Page 17)

. DIR LEVER,

3-18

GEAR (IDL-B)

(Page 17)

. GEAR (IDL-C)

3-19

(Page 18)

8

3-2. SIDE PANEL (R)(L), FRONT PANEL SECTION

s

s

qd

front panel section

qa

four screws
(+BV3)

qs

wire (flat type)
(17 core) (CN801)

5

two screws
(+BV3)

7

side panel (L)

q;

three screws
(+BV3)

9

three screws
(+BV3)

HCD-SR4W

3-3. FL BOARD

6

three screws
(+BV3)

3

7

wire (flat type)
(7 core) (CN812)

connector
(5p) (CN811)

8

three screws
(+BV3)

5

2

three screws
(+BV3)

6

wire (flat type)
(17 core) (CN803)

8

FL board

two screws
(+BV3)

4

side panel (R)

2

cover

1

two screw
(+BV3)

3

connector
(2p)

4

connector
(3p)

1

four screw
(+BV3)

9

HCD-SR4W

3-4. MECHANISM DECK (CDM80A-DVBU24)

3

wire (flat type)
(29 core)

4

mechanism deck

(CDM80A-DVBU24)

2

connector
(7p) (CN701)

3-5. AMP BOARD

1

three screws
(+BV3)

2

1

3

connector
(4p) (CN4)

wire (flat type)
(9 core) (CN302)

wire (flat type)
(17 core) (CN301)

6

four screws
(+BV3)

5

screw
(+BVTP 3

×

16)

4

connector
(2p) (CN7)

9

connector
(5p) (CN306)

8

connector
(6p) (CN313)

q;

AMP board

7

connector
(2p) (CN300)

10

3-6. SWITCHING REGULATOR

6

7

connector
(4p) (CN4)

connector
(12p) (CN8)

8

connector
(2p) (CN3)

1

screw
(+BV3)

2

power sheet (top)

5

connector (2p) (CN7)

4

connector (2p) (CN5)

3

three screws
(+BV3)

qa

switching regulator

q;

power sheet

9

Remove the two solderings.

HCD-SR4W

3-7. TUNER UNIT, IO BOARD

3

tuner unit

2

wire (flat type)
(11 core)

4

wire (flat type)
(15 core) (CN201)

7

IO board

6

connector
(10p) (CN205)

5

wire (flat type)
(29 core) (CN601)

1

five screws
(+BV3)

11

HCD-SR4W

)

)

3-8. DMB08 BOARD

5

q;

wire (flat type)
(17 core) (CN005)

9

wire (flat type)
(29 core) (CN401)

3

wire (flat type)
(15 core) (CN003)

2

wire (flat type)
(29 core) (CN002)

bracket (DMB)

1

connector
(7p) (CN007)

4

four screws
(+BV3)

6

connector
(13p) (CN008)

7

qa

DMB08 board

wire (flat type)
(17 core) (CN004)

8

wire (flat type)
(9 core) (CN001

3-9. CHASSIS (TOP)

3

two screws
(+P 2

5

chassis (top)

4

three screws
(+BVTP 2.6

×

10)

1

×

8)

screw
(+BVTP 2.6

2

lever (CL UP2

×

8)

12

3-10. LEVER (LOADING R/L)

HCD-SR4W

5

lever (loading R)

1

spr-T (loading L) spr-T (loading R)

4

two hooks

1

2

two hooks

3

lever (loading L)

PRECAUTION DURING LEVER (LOADING R / L) INSTALLATION

Align the horizontal position.

lever (loading L)

Install the

both levers so that they move symmetrically.

lever (loading R)

13

HCD-SR4W

)

3-11. DISC STOP LEVER, DISC SENSOR LEVER

1

gear (cap)

2

gear (IDL L)

PRECAUTION DURING DISC STOP LEVER INSTALLATION

5

two hooks

6

disc stop lever

3-12. DRIVER BOARD

3

Remove soldering

from the two points.

3

two claws

4

disc sensor lever

hole

hole

Install the disc stop lever so that the both holes
are aligned.

2

three screws
(+BVTP 2.6

5

DRIVER board

chassis (top)

disc stop lever

×

8

14

4

motor (pully) assy

1

belt (MOT)

3-13. RF BOARD

)

2

claw

5

RF board

HCD-SR4W

4

wire (flat type)

(CN001)

3-14. OPTICAL PICK-UP (DBU-1)

5

optical pick-up

(DBU-1)

2

step screw (M)

3

two insulators

3

wire (flat type)

(CN003)

1

claw

1

two step screws (M

4

insulator

15

HCD-SR4W

3-15. BASE UNIT

6

base unit

4

floating screw
(+PTPWHM 2.6)

3

holder down spring

2

lever (CL UP2)

1

screw
(+BVTP 2.6

3-16. LEVER (BU LOCK)

6

lever (BU lock)

1

gear (cap)

2

gear (BU lock)

3

floating screw
(+PTPWHM 2.6)

5

floating screw
(+PTPWHM 2.6)

×

8)

5

three hooks

4

16

3-17. CLOSE LEVER

3

5

claw

close lever

1

washer (3-1-0.4)

2

4

shaft disc stop

HCD-SR4W

close lever spring

3-18. DIR LEVER, GEAR (IDL-B)

1

6

Loosen the screw.

2

claw

9

DIR lever

DIR spring

3

gear puley

4

gear (cap)

5

gear (IDL-A)

q;

gear (IDL-B)

8

stopper

7

Hold the release lever

and change the direction.

17

HCD-SR4W

3-19. GEAR (IDL-C)

3

gear (IDL-D)

2

two claws

4

three hooks

1

gear (IDL-F)

7

6

gear (IDL-C)

claw

5

gear loading lever

18

SECTION 4

TEST MODE

HCD-SR4W

[Version Display Mode]

*The software version is displayed.

Procedure:

1. Press three buttons of [VOLUME -], [VOLUME +] and A si­multaneously for two seconds.

2. The message “VERSION” is displayed. The version display
mode is activated.

3. Press the > button. “IF ***” is displayed.

4. Each time the > button is pressed, the display changes in
the order of DVD, AREA, VERSION and IF.

5. To exit from this mode, press the ?/1 button.

[Key T est Mode]

* Button check

Procedure:

1. Press three buttons of [VOLUME -], [VOLUME +] and [FUNC­TION] simultaneously.

2. The message “KEY NUM 0” is displayed and “0” blinks.

3. Each time a button is pressed, “KEY NUM 0” value increases.
However, once a button is pressed, it is no longer taken into
account.

4. When all buttons are pressed, “KEY NUM 9” appears and the
number blinking is stopped.

5. To exit from this mode, disconnect the power cord.

[Display T est Mode]

Procedure:

1. Press three buttons of [VOLUME -], . and A simulta-
neously.

2. All segments are turned on.

TITLE TRK CHAP SLEEP NTSC TUNED ST MONO NIGHT

CD MULTIPBC

ALBM

1

SB

DSGX
kHz D

a

MHz PL II

a

DTS-ES NEO:6

ALL1DISC S PGM
ALBM SHUF REP
MP3 JPEG

-

SA

3. When the > button is pressed, the display will light up as
follows.

ALL1DISC S PGM
ALBM SHUF REP
MP3 JPEG

-

CD MULTIPBC

SA

ALBM TITLE TRK CHAP SLEEP NTSC TUNED ST MONO NIGHT

1

DSGX

SB

kHz D

a

MHz PL II

a

DTS-ES NEO:6

4. Press the > button and confirm the display.

[Cold Reset]

* The cold reset clears all data including preset data stored in

the RAM to initial conditions. Execute this mode when
returning the set to the customers.

Procedure:

1. Press the ?/1 button to turn the power on.

2. Press three buttons of . , HX and A simultaneously.

3. When this button is operated, display as “COLD RESET” for
a while and all of the settings are reset.

[Disc Slot Lock]

The disc slot lock function for the antitheft of an demonstration
disc in the store is equipped.

Setting Procedure:

1. Turn the set on.

2. Press two buttons of x and A simultaneously for five sec-
onds.

3. The message “LOCKED” is displayed and the slot is locked.

Releasing Procedure:

1. Press two buttons of x and A simultaneously for five sec-
onds again.

2. The message “UNLOCKED” is displayed and the slot is
unlocked.

Note : When “LOCKED” is displayed, the slot lock is not released by

turning power on/off with the ?/1 button.

[Repeat Limit Release Mode]

Procedure:

1. Press three buttons of A , > and [VOLUME+] simulta-
neously.

2. Repeat limit is released.

DEC

EX

[CDM Ship Mode]

*This mode moves the optical pick-up to the position durable

to vibration. Use this mode when returning the set to the
customer after repair.

Procedure:

1. Turn the set on.

DEC

EX

2. Set the function to DVD.

3. Press three buttons of > , . and A simultaneously.

4. The message “MECHA LOCK” is displayed.

5. The CDM ship mode is set.

5. Press the > button, all segments are turned off.

6. Every pressing of the > button turns on each segments in
the same order.

7. To exit from this mode, press the ?/1 button.

19

HCD-SR4W

[GENERAL DESCRIPTION]

The T est Mode allows you to make dia gnosis and adjustment easily
using the remote commander and monitor TV. The instructions,
diagnostic results, etc. are given on the on-screen display (OSD).

[TEST DISC LIST]

Use the following test disc on test mode.
TDV-520CSO (DVD-SL) : PART No. J-2501-236-A
LUV-P01 (CD) : PART No. 4-999-032-01
TDV-540C (DVD-DL) : PART No. J-2501-235-A

Note: Do not use exiting test disc for DVD.

[STARTING TEST MODE]

1. Press the @/1 button to turn the power on, and set the function
to DVD.

2. Press three buttons of A , x and [VOLUME+] simultaneously
to enter the test mode.

3. It displays “SERVICE IN” on the fluorescent indicator tube,
and displays the Test Mode Menu on the monitor screen as
follows. (At the bottom of the menu screen, the model name
and revision number are displayed)

Test Mode Menu

0. Syscon Diagnosis

1. Drive Auto Adjustment

2. Drive Manual Operation

3. Mecha Aging

4. Emergency History

5. Mecha Error History

6. Version Information

7. Video Level Adjustment
Exit: POWER Key

Model :DAV-xxx xx
Revision :x.xx

4. To execute each function, select the desired menu and press
its number on the remote commander (RM-SP320).

5. To release from test mode, press the @/1 button and turn the
power off.

[OPERATING TEST MODE]

0. SYSCON DIAGNOSIS

The same contents as board detail check by serial interface can be
checked from the remote commander operation.
On the Test Mode Menu screen, press [0] key on the remote
commander, and the following Check Menu will be displayed.

### Syscon Diagnosis ###

Check Menu

0. Quit

1. All

2. Version

3. EEPROM

4. GPIO

5. SD Bus

6. Video

0-0. Quit

Quit the Syscon Diagnosis and return to the Test Mode Menu.

0-1. All (All items continuous check)

This menu checks all diagnostic items continuously. Normally, all
items are checked successively one after another automatically
unless an error is found, but at a certain item that requires judgment
through a visual check to the result, the following screen is displayed
for the key entry.

• Example display

### Syscon Diagnosis ###

Diag All Check
No.2 Version

2-2. Version

ROM Revision = x.xx

Press NEXT Key to Continue
Press PREV Key to Repeat

For the ROM Check, the check sum calculated by the Syscon is
output, and therefore you must compare it with the specified value
for confirmation.
Following the message, press the > button to go to the next
item, or press the . button to repeat the same operation again.
To quit the diagnosis and return to Check Menu screen, press the
[RETURN] key on the remote commander to display Check Menu.

• Error occurred
If an error occurred, the diagnosis is suspended and error is displayed.
Press the [RETURN] key on the remote commander to quit the
diagnosis, or press the . button to repeat the same check where
an error occurred, or press the > button to continue the check
from the item next to faulty item.

General Description of Checking Method

Selecting 2 and subsequent items calls the submenu screen of each
item. And selecting 2 and subsequent items executes respective
menus and outputs the results.
For the contents of each submenu, see “Check Items List” as below .

Check Items List:

0-2. Version

0-2-1. All
0-2-2. Revision
0-2-3. ROM Check Sum
0-2-4. Model Type
0-2-5. Region

0-3. EEPROM Check

0-3-1. Sampling Check

0-3-2. Detail Check
0-4. GP I/O Check
0-5. SD Bus Check
0-6. Video Check

0-2. Version

0-2-2. Revision

The revision number of ROM (IC205) that the program

for the DVD system processor (IC206) is stored.

0-2-3. ROM Check Sum

Check sum is calculated. (4 digits hexadecimal number)

20

HCD-SR4W

0-2-4. Model Type

Model name is displayed. (DAV-SR4W)

0-2-5. Region

Model destination code is displayed. (2 digits number)

0-3. EEPROM Check

0-3-1. Sampling Check

EEPROM check at every 64 words.
It compares read data with write data of each address.
When there are discrepancies between two data, it displays
error.

0-3-2. Detail Check

EEPROM check at every 1 word.
It compares read data with write data of each address.
When there are discrepancies between two data, it displays
error.

0-4. GP I/O Check

Pull up/down setting check of the DVD system processor (IC206)
pin 150, 151 and 154 (for clock setting port).

0-5. SD Bus Check

SD bus data check between DVD decoder (IC701) and D-RAM
(IC706).

0-6. Video Check

Output the color bars for video level adjustment.

1. DRIVE AUTO ADJUSTMENT

On the Test Mode Menu screen, press the [1] key on the remote
commander, and the Adjustment Menu will be displayed.

## Drive Auto Adjustment ##

Adjustment Menu

0. ALL

1. DVD-SL

2. CD

3. DVD-DL

1-1. DVD-SL (single layer)

Press the [1] key on the remote commander and insert a D VD single
layer disc following the message. Then the adjustment will be made
through the steps below, then adjusted values will be written to the
EEPROM.

DVD Single Layer Disc Adjustment Steps:

1. Sled tilt reset

2. Disc check memory SL

3. Wait 300 msec

4. Set disc type SL

5. LD on

6. Spindle start

7. Wait 1 sec

8. Focus servo on 0

9. Auto track offset adjust

10. CLVA on

11. Wait 500 msec

12. Tracking on

13. Wait 1 sec

14. Sled on

15. Check CLV on

16. Auto LFO adjust

17. Auto focus offset adjust

18. Auto tilt position adjust

19. Auto focus gain adjust

20. Auto focus offset adjust

21. EQ boost adjust

22. Auto loop filter offset adjust

23. Auto track gain adjust
Search Check

24. 32 track jump forward

25. 32 track jump reverse

26. 500 track jump forward

27. 500 track jump reverse

28. All servo stop

29. EEP copy loop filter offset

1-2. CD

Press the [2] key on the remote commander and insert a CD disc
following the message. Then the adjustment will be made through
the steps below , then adjusted values will be written to the EEPR OM.

Exit: RETURN

Normally, [0] is selected to adjust D VD (single layer), CD and DVD
(dual layer) in this order. But, individual items can be adjusted for
the case where adjustment is suspended due to an error. In this mode,
the adjustment can be made easily through the operation following
the message displayed on the screen.
The disc used for adjustment must be the one specified for
adjustment.

1-0. ALL

Press the [0] key on the remote commander, and the servo set data
in EEPROM will be initialized. Then, 1. DVD-SL disc, 2. CD disc
and 3. DVD-DL disc are adjusted in this order.
Each time one disc was adjusted, it is ejected. Replace it with the
specified disc following the message. Y ou can finish the adjustment
by pressing the [RETURN] button on the remote commander.

Note: During adjustment of each disc, the measurement for disc type

judgment is made. As automatic adjustment does not judge the disc
type unlike conventional models, take care not to insert wrong type
discs. Also, do not give a shock during adjustment.

CD Adjustment Steps

1. Sled tilt rest

2. Disc check memory CD

3. Wait 500 msec

4. Set disc type CD

5. LD on

6. Spindle start

7. Wait 500 msec

8. Focus servo on 0

9. Auto track offset adjust

10. CLVA on

11. Wait 500 msec

12. Tracking on

13. (TC display start)

14. Wait 1 sec

15. Jitter display start

16. Sled ON

17. Check CLV on

18. Auto loop filter offset adjust

19. Auto focus offset adjust

20. Auto focus gain adjust

21. Auto focus offset adjust

22. EQ boost adjust

23. Auto LFO Adjust

21

HCD-SR4W

24. Auto track gain adjust
Search Check

25. 32Tj forward

26. 32Tj reverse

27. 500Tj forward

28. 500Tj reverse

29. All servo stop

1-3. DVD-DL (dual layer)

Press the [3] key on the remote commander and insert a DVD dual
layer disc following the message. Then the adjustment will be made
through the steps below, then adjusted values will be written to the
EEPROM.

DVD Dual Layer Disc Adjustment Steps:

1. Sled tilt reset

2. Disc check memory DL

3. Wait 500 msec

4. Set disc type DL

5. LD on

6. Spindle start

7. Wait 1 sec

Layer 1 Adjust

8. Focus servo on 0

9. Auto track offset adjust

10. CLVA on

11. Wait 500 msec

12. Tracking on

13. Wait 500 msec

14. Sled on

15. Check CLV lock

16. Auto loop filter offset adjust, Auto focus adjust

17. Auto focus gain adjust

18. Auto focus offset adjust

19. EQ boost adjust

20. Auto loop filter offset adjust

21. Auto Track Gain Adjust
Search Check

22. 32 track jump forward

23. 32 track jump reverse

24. 500 track jump forward

25. 500 track jump reverse

Layer 0 Adjust

26. Focus jump (L1 t L0)

27. Auto track offset adjust L0

28. CLVA on

29. Wait 500 msec

30. Tracking on

31. Wait 500 msec

32. Sled on

33. Check CLV lock

34. Auto focus filter offset adjust

35. Auto Focus Adjust

36. Auto focus gain adjust

37. Auto focus offset adjust

38. EQ boost adjust

39. Auto Loop Filter Offset

40. Auto track gain adjust

Search Check

41. 32 track jump forward

42. 32 track jump reverse

43. 500 track jump forward

44. 500 track jump reverse

Layer Jump Check

45. Layer jump (L0 t L1)

46. Layer jump (L1 t L0)

47. All servo stop

2. DRIVE MANUAL OPERATION

Note: This mode is used for design, and not used in service fundamentally.

On the Test Mode Menu screen, press the [2] key on the remote
commander, and the Operation Menu will be displayed. For the
manual operation, each servo on/off control and adjustment can be
executed manually.

## Drive Manual Operation ##

Operation Menu

1. Disc Type

2. Servo Control

3. Track/Layer Jump

4. Non EEPROM Write Adjust

5. EEPROM Write Adjust

6. Memory Check

7. Disc Check Memory

8. Error Rate Display

9. SACD Water Mark

Exit: RETURN

In using the manual operation menu, take care of the following
points. These commands do not provide protection, thus requiring
correct operation. The sector address or time code field is displayed
when a disc is loaded.

Note:

1. Set correctly the disc type to be used on the Disc
Type screen.

2. In case of an alarm, immediately press the x button
to stop the servo oper ation, and press the +/1 but­ ton to turn the power off.

Basic operation:

(controllable from front panel or remote commander)

@/1 :Power OFF (release the Test Mode)
x : Servo stop

Z : Stop and eject

[RETURN] : Return to Operation Menu or T est Mode Menu

. , > :Transition between sub modes of menu

[1] to [9], [0] : Selection of menu items

Cursor o/

: Increase/Decrease in manually adjusted value

O

22

HCD-SR4W

Servo Control

1.LD off R.Sled FWD

2.Focus off L.Sled REV

3.SPDL off U.Sled Reset

4.CLVA off D.Sled Limit

5.Trk. off

6.Sled off

7.Fcs.Srch off

0.All Servo Off

Exit: RETURN

2-1. Disc Type

Disc Type

Disc Type Select

1. Disc Type Auto Check

2. Set Disc Type DVD

3. Set Disc Type CD

4. Set Disc Type Hybrid

Exit: RETURN

2-1-1. Disc Type Auto Check

1) Press the [1] key on the remote commander to display the Disc
Type Auto Check screen.

2) Insert a disc and press the [ENTER] key on the remote com-
mander.

3) It judges the type of inserted disc automatically and displays
the disc type and so on as below.

Disc Type Auto Check

2-1-3. Disc Type CD

It sets up so that it may judge as a disc type of specification of the
disc with which the set was inserted.

[1]: CD disc (normal speed, 12 cm)
[2]: CD disc (double speed, 12 cm)
[3]: CD disc (normal speed, 8 cm)
[4]: CD disc (double speed, 8 cm)
[5]: CD-RW disc (normal speed, 12 cm)
[6]: CD-RW disc (double speed, 12 cm)
[7]: CD-RW disc (normal speed, 8 cm)
[8]: CD-RW disc (double speed, 8 cm)

2-1-4. Disc Type Hybrid

It sets up so that it may judge as a disc type of specification of the
disc with which the set was inserted.

[1]: SACD Hybrid disc (SACD layer, 12 cm)
[2]: SACD Hybrid disc (CD layer, normal speed, 12 cm)
[3]: SACD Hybrid disc (CD layer, double speed, 12 cm)
[4]: SACD Hybrid disc (SACD layer, 8 cm)
[5]: SACD Hybrid disc (CD layer, normal speed, 8 cm)
[6]: SACD Hybrid disc (CD layer, double speed, 8 cm)

2-2. Servo Control

Note: Be sure to perform the disc type setup befor eperforming this item.

Disc Type xx
Layer xx
Mirr Time xx
Mirr Count xx
FZC Count xx
PI Reference xx
PI Peak xx

ENTER.Execute

Disc Type : CD, DVD or Hybrid (SACD)
Layer : SINGLE, DUAL or HYBRID
Mirr Time : Mirror time of between disc surface and record

surface when disc type judgment. (hexadecimal
number)

Mirr Count : The number of times which mirror counts between

disc surface and record surface when disc type
judging. (hexadecimal number)

FZC Count : The number of times which focus zero cross points

of each layer when lens down. (hexadecimal

number)
PI Reference : The average of PI reference voltage. (hexadecimal
number)
PI Peak : PI peak level voltage. It performs only when disc

type judgment is successful. (hexadecimal number)

2-1-2. Disc Type DVD

It sets up so that it may judge as a disc type of specification of the
disc with which the set was inserted.

[1]: DVD single layer disc (12 cm)
[2]: DVD dual layer disc (0 layer, 12 cm)
[3]: DVD dual layer disc (1 layer, 12 cm)
[4]: DVD-RW disc (12 cm)
[5]: DVD single layer disc (8 cm)
[6]: DVD dual layer disc (0 layer, 8 cm)
[7]: DVD dual layer disc (1 layer, 8 cm)

Exit: RETURN

On this screen, the servo on/off control necessary for replay is
executed. Normally, turn on each servo from 1 sequentially and
when CLVA is turned on, the usual trace mode becomes active. In
the trace mode, DVD sector address or CD time code is displayed.
This is not displayed where the spindle is not locked.
The spindle could run overriding the control if the spindle system is
faulty or RF is not present. In such a case, do not operate CLVA.

[1] LD : Turn on/off the laser.
[2] Focus : Search the focus and turn on the focus.
[3] SPDL : Turn on/off the spindle.
[4] CLVA : Turn on/off normal servo of spindle servo.
[5] Trk. : Turn on/off the tracking servo.
[6] Sled : Turn on/off the sled servo.
[7] FCS. Srch : Turn on/off the focus search.
[8] FCS. OppL : Turn on/of f the focus search to another layer

of designated layer in Disc Type setting.
(dual layer disc only)

[0] : All servo off.

p Sled FWD (right cursor) : Move the sled forward.
P Sled REV (left cursor) : Move the sled reverse.
O Sled FWD (up cursor) : Reset the sled.
o Sled REV (down cursor) : Limit in the sled.

23

HCD-SR4W

2-3. Track/Layer Jump

Track/Layer Jump

1. 1Tj FWD R.Lj L0>L1

2. 1Tj REV L.Lj L1>L0

3.500Tj Fine FWD U.Fj L0>L1

4.500Tj Fine REV D.Fj L1>L0

5.10kTj Dirc FWD

6.10kTj Dirc REV

7.20kTj Dirc FWD

8.20kTj Dirc REV

0. All Servo Off

Exit: RETURN

On this screen, track jump, etc. can be performed. Only for the DVD
dual layer disc, the focus jump and layer jump are displayed in the
right field

[1] 1Tj FWD : 1 track jump forward.
[2] 1Tj REV : 1 track jump reverse.
[3] 500Tj FWD : 500 track jump (fine search)forward.
[4] 500Tj REV : 500 track jump (fine search) reverse.
[5] 10kTj FWD : 10k track jump (direct search) forward.
[6] 10kTj REV : 10k track jump (direct search) reverse.
[7] 20kTj FWD : 20k track jump (direct search) forward.
[8] 20kTj REV : 20k track jump (direct search) reverse.
[0] : All servo off.

2-4. Non EEPROM Write Adjust

2-5. EEPROM Write Adjust

EEPROM Write Adjust

1. Focus Offset

2. Focus Gain

3. Trk. Offset Coarse

4. ——————

5. Trk. Gain

6. EQ Boost

0.All Servo Off

Exit: RETURN

On this screen, each item can be adjusted automatically. Select the
desired number [1] to [0] from the remote commander, and selected
item is adjusted automatically.

[1] Focus Offset : Adjusts focus offset.
[2] Focus Gain : Adjusts focus gain.
[3] TRK. Offset : Adjusts tracking offset of the RF amp

(IC001) side.

[5] TRK. Gain : Adjusts track gain.
[6] EQ Boost : Adjusts amount of boost of equalizer.
[0] : All servo off.

2-6. Memory Check

Display images are shown as follows, and all two screens are able
to switch by the O key (UP) or o key (DW).

Non EEPROM Write Adjust

1. Focus Offset

2. Focus Gain

3. Trk. Offset Coarse

4. Trk. Offset Fine

5. Trk. Gain

6. EQ Boost

0.All Servo Off

Exit: RETURN

On this screen, each item can be adjusted manually. Select the desired
number [1] to [0] from the remote commander, and current setting
for the selected item will be displayed, then increase or decrease
numeric value with the O key or o key. This value is stored in the
EEPROM. If CLV has been applied, the jitter is displayed for
reference for the adjustment.

[1] Focus Offset : Adjusts focus offset.
[2] Focus Gain : Adjusts focus gain.
[3] TRK. Offset : Adjusts tracking offset of the RF amp

(IC001) side.

[4] TRK. Offset : Adjusts tracking offset of the DSP

(IC401) side.

[5] TRK. Gain : Adjusts track gain.
[6] EQ Boost : Adjusts amount of boost of equalizer.
[0] : All servo off.

24

EEPROM Data 1/2 CD SL L0 L1
Focus Gain xx xx xx xx
Trk. Gain xx xx xx xx
Focus Offset xx xx xx xx
Trk. Offset xx xx xx xx
EQ. Boost xx xx xx xx
PI Level xx xx -- -­Fcs. Balance -- xx -- -­Jitter xx xx xx xx
Mirror Time xx xx xx -­FE Level -- xx -- -­Traverse Lv1. -- xx -- -­Next:DW Default:CLR Exit:RET

EEPROM Data 2/2 CDRW DVDRW
Focus Gain xx xx
Trk. Gain xx xx
Focus Offset xx xx
Trk. Offset xx xx
EQ. Boost xx xx

Prev:UP Default:CLR Exit:RET

On this screen, current servo adjusted data stored in the EEPROM
are displayed. The adjusted data are initialized by pressing the
[CLEAR] key, but be careful that they are not recoverable after
initialization.
Before clearing the adjusted data, make a note of the set data. This
screen will also appear if [0]-All is selected in the Drive Auto
Adjustment. In this case, default setting cannot be made.

HCD-SR4W

### EMG. History ###

Laser Hours CD xxxxhxxm
DVD xxxxhxxm

a. bb xx xx xx xx xx xx xx
xx xx xx xx xx xx xx xx

a. bb xx xx xx xx xx xx xx
xx xx xx xx xx xx xx xx

Select:1-9 Scroll:UP/DOWN
(1.Latest EMG.) Exit: RETURN

2-7. Disc Check Memory

Disc Check Memory

1. SL Disc check

2. CD Disc check

3. DL Disc check

On this screen, measure the mirror time of chucked disc, and write
to the EEPROM.

2-8. Error Rate Display

Error Rate Display

UC CR Address

PI1 Err Now xx xxxx xxxxxxxx

Max xx xxxx xxxxxxxx
Avg xx xxxx

PI2 Err Now xx xxxx xxxxxxxx

Max xx xxxx xxxxxxxx
Avg xx xxxx

PO Err Now xx xxxx xxxxxxxx

Max xx xxxx xxxxxxxx
Avg xx xxxx

Start: ENTER Exit: RETURN

On this screen, measure and display the error rate.

UC : Incorrect value
CR : Correct value

2-9. SACD Water Mark Check

SACD Water Mark Check

PSP AMP
PSN

Start: ENTER Exit: RETURN

On this screen, measure the PSP AMP v alue and PSN value of SACD
water mark.

3. EMERGENCY HISTORY

On the Test Mode Menu screen, selecting [4] displays the
information such as servo emergency history.
The history information from last 1 up to 10 can be scrolled with
the O key or o key. Also, specific information can be displayed
by directly entering that number with ten keys.

Exit: RETURN

xxxxhxxm : The laser on total hours. Data below minutes
are omitted.
a. : Error number.
bb : Error code.
xx : Not used.

• Clearing History Information

Clearing laser hours:

Press the [DVD DISPLAY] and [CLEAR] keys in this order.
Then both CD and DVD data are cleared.

Clearing emergency history:

Press the [DVD TOP MENU] and [CLEAR] keys in this order.

Initializing set up data:

Press [DVD MENU] and [CLEAR] keys in this order.
The data have been initialized when “EEPROM Initialize
Finished.”. messa ge is displayed. The EMG. History screen
will be restored soon.

• Code list of Emergency History
10: Communication to RF AMP (IC001) failed.
11: Each servo for focus, tracking, and spindle is unlocked.
12: Check sum error of EEPROM (IC203).
14: Communication to servo DSP (IC401) failed, or servo DSP

(IC401) is faulty.

15: Communication to DVD decoder (IC701) failed, or DVD

decoder (IC701) is faulty.

16: Communication to DSD decoder (IC801) failed, or DSD

decoder (IC801) is faulty.

20: Initialization of sled servo failed. It is not placed in the initial

position.
23: Sled servo operation error.
24: Made a request to move the sled servo to wrong position.
30: Tracking balance adjustment error.
31: Tracking gain adjustment error.
33: Focus bias adjustment error.
34: Focus gain adjustment error.
35: Equalizer adjustment error.
40: Focus servo does not operate.
41: With a DVD dual layer disc, focus jump failed.
50: CLV (spindle) servo does not operate.
51: Spindle does not stop.
60: Made a request to seek nonexistent address.
61: Seek error of retry more than regulated times.
70: Control data could not be read.
80: Disc reading failed.

25

HCD-SR4W

4. MECHA ERROR HISTORY

On the Test Mode Menu screen, selecting [5] displays the
information of mechanism deck error history.
The history information from last 1 up to 8 can be scrolled with the

O key or o key. Also, specific information can be displayed by

directly entering that number with ten keys.

### Mecha Error History ###

1. aa bb cc dd xx xx xx xx

2. aa bb cc dd xx xx xx xx

3. aa bb cc dd xx xx xx xx

4. aa bb cc dd xx xx xx xx

5. aa bb cc dd xx xx xx xx

6. aa bb cc dd xx xx xx xx

7. aa bb cc dd xx xx xx xx

8. aa bb cc dd xx xx xx xx

Scroll:UP/DOWN

(1.Latest Err.) Exit: RETURN

aa : The error in the midst of initializing the mechanism deck.
bb : The error in the midst of loading operation.
cc : The error in the midst of up/down the stocker.
dd : The error in the midst of switching the mechanism deck

mode.

xx : Not used.

• Error code (bb)
00 : Initializing the mechanism deck.
10 : Retry over of eject and loading.
30 : Open operation in no disc status.
60 : Retry over of eject and loading.
70 : Disc is chucking position.
81 : Retry failed of disc movement from chucking position to

stocker.

83 : Retry pr eparation failed of disc movement from chucking

position to stocker.
90 : Disc is stored in the stocker.
A1 : Retry failed of disc movement from stocker to chucking

position.
A3 : Retry preparation failed of disc movement from stocker to

chucking position.
B0 : Just before the release operation.
B1 : Retry failed of the release operation.

• Error code (cc)
10 : Under a stop.
22 : Retry preparation failed.
23 : Retry failed.

• Error code (dd)
10 : Under a stop.
22 : Retry preparation failed.
23 : Retry failed.

• Error code (aa)
FF : Complete the initializing. (normal operation)
11 : Stocker movement (to chucking position) failing in the midst

of initializing the mechanism deck.

12 : Stocker movement (to chucking position) failing in the midst

of initializing the mechanism deck.
1x : Initializing the mechanism deck.
2x : Initializing the mechanism deck.
3x : Initializing the mechanism deck.
41 : Disc eject failing in the midst of initializing the mechanism

deck.
4x : Initializing the mechanism deck.
50 : Disc eject failing in the midst of initializing the mechanism

deck.
5x : Initializing the mechanism deck.
A2 : Disc eject failing in the midst of initializing the mechanism

deck.
Ax : Initializing the mechanism deck.
D3 : Disc eject failing in the midst of initializing the mechanism

deck.
Dx : Initializing the mechanism deck.
Ex : Initializing the mechanism deck.

5. VERSION INFORMATION

On the Test Mode Menu screen, selecting [6] displays the ROM
version and region code.
The parenthesized hexadecimal number in version field is checksum
value of ROM.

## Version Information ##

IF con. Ver.x. xx

SYScon. Ver.x. xx (xxxx)
Model DAV-xxx
Region
Config xxxxxxxx

Front End Ver.x.xx

IF con. : The version of system controller (IC901).
SYScon. : The version of DVD system processor (IC206).
Front End : The version of mechanism controller (IC301).

6. VIDEO LEVEL ADJUSTMENT

On the T est Mode Menu screen, selecting [7] displays color bars for
video level adjustment. During display of color bars, OSD disappears
but the menu screen will be restored if pressing the [RETURN] key.

0x

Exit: RETURN

26

SECTION 5

p

ELECTRICAL ADJUSTMENT

HCD-SR4W

[TEST DISC LIST]

Use the following test disc on test mode.
TDV-520CSO (DVD-SL) : PART No. J-2501-236-A
LUV-P01 (CD) : PART No. 4-999-032-01
TDV-540C (DVD-DL) : PART No. J-2501-235-A

Note: Do not use exiting test disc for DVD.

AUTO SERVO ADJUSTMENT

After parts related to the servo circuit (RF amplifier (IC001), DSP
(IC401), motor driver (IC501), EEPR OM (IC302) so on) and optical
pick-up (DBU-1) are replaced, re-adjusting the servo circuit is
necessary. Select “ALL” at “1. DRIVE AUTO ADJUSTMENT”
(Refer to page 25 in TEST MODE) and adjust DVD-SL (single
layer), CD and DVD-DL (dual layer).

DIAT SIGNAL RF LEVEL ADJUSTMENT

This adjustment is performed in order to adjust the transmission
distance of RF signal for DIAT communication.

Connection:

DIA T TRANSMIT
board

TP815
(RF AMP OUT)

Procedure:

1. Connect the oscilloscope to TP815 (RF AMP OUT) and GND
on the DIAT TRANSMIT board.

2. Connect DIR-T1 to DIR-T1 jack (J301).

3. Adjust RV801 on the DIAT TRANSMIT board so that the
center of waveform becomes 1.0 Vp-p.

4. Confirm trigger is locked.

5. Adjust RV801 on the DIAT TRANSMIT board so that the
center of waveform becomes 2.2 to 2.4 Vp-p.

oscilloscope

Adjustment Location:

– DIAT TRANSMIT Board (SIDE A) –

IC804

(RF AMP OUT)

IC805

TP815

RF Signal Reference Waveform

VOLT/DIV : 500 mV
TIME/DIV : 500 ns

level : 2.2 to 2.4 Vp-

27

HCD-SR4W

• Circuit Boards Location

SONY LAMP board

PW KEY board

RF board

SECTION 6

DIAGRAMS

DRIVER board

DIA T TRANSMIT board

FL board

DMB08 board

LF board

DDCON board

CONTROL KEY board

TUNER UNIT

SWITCHING REGLATOR

DIAT PW board

HP board

IO board

SCART board
(only for AEP, UK and Russian models)

DIAT SPK board

AMP board

28

HCD-SR4W

d

d

THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)

For Schematic Diagrams.
Note:

• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except f or electrolytics and
tantalums.

• All resistors are in Ω and 1/
specified.

• f : internal component.

• C : panel designation.

Note:

The components identi­fied by mark 0 or dot­ted line with mark 0 are
critical for safety.
Replace only with part
number specified.

• A : B+ Line.

• B : B– Line.

• H : adjustment for repair.

•Voltages and wavef orms are dc with respect to ground un­der no-signal (detuned) conditions.

•Voltages and wavefor ms are dc with respect to ground in
service mode.

•Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.

•Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production
tolerances.
no mark : DVD STOP

• Circled numbers refer to waveforms.

• Signal path.

F : AUDIO
J : CD PLAY
c : DVD PLAY
d : TUNER
L : VIDEO
i : OPTICAL DIGITAL IN
a : CHROMA
E : Y
r : COMPONENT VIDEO
e : AUX IN
I : SACD PLAY
q : R, G, B

•Abbreviation
AUS: Australian model
CH : Chinese model
E41 : 230 V AC area in E model
HK : Hong Kong model
KR : Korean model
MX : Mexican model
RU : Russian model
SP : Singapore model
TW : Taiwan model

4

W or less unless otherwise

For Printed Wiring Boards.
Note:

• X : parts extracted from the component side.

• a : Through hole.

• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)

Caution:
Pattern face side: Parts on the pattern face side seen from
(Side A) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Side B) the parts face are indicated.

• Indication of transistor

CEB

These are omitte

C

Q

These are omitte

EB

MEMO

HCD-SR4W

2929

HCD-SR4W

6-1. BLOCK DIAGRAM — RF/SERVO SECTION —

OPTICAL PICK-UP

BLOCK

DETECTOR

LASER

CD LD

DIODE

(FOR CD)

LASER

DVD LD

DIODE

(FOR DVD)

INLIM

FCS+
FCS–

2AXIS
DEVICE
FOCUS/

COIL

TRK+
TRK–

TRACKING

RF

A
B
C
D

F
E

PD

SW

AUTOMATIC POWER

CONTROL (FOR CD)

AUTOMATIC POWER

CONTROL (FOR DVD)

LASER DIODE

(SPINDLE)

Q301

SELECT

(SLED)

MM

D

Q002

Q001

CBA

MM

1

63

3
4
5
6

18
17

B

12

A

11

D

10

C

9

B

16

A

15

D

14

C

13

22

24
23

21

36

FOCUS/TRACKING COIL DRIVER,
SPINDLE, SLED MOTOR DRIVER

36 48
37 1

34 3
35 4

32
31
30
29

27
28

47
46

RFSIN

A2
B2
C2
D2

CD E
CD F

A
B
C
D

CD A
CD B
CD C
CD D

CDLD

CDPD
DVDPD

DVDLD

V125

ATON

IC501

BUFFER

FOCUS COIL

DRIVE

TRACKING COIL

DRIVE

SLED MOTOR

DRIVE

SLED MOTOR

DRIVE

SPINDLE MOTOR

DRIVE

BUFFER

ATOP

DVDRFP

FNP

62
61

AIP

59

FNN

AIN

60

IC001

CD/DVD/SACD RF AMP,

FOCUS/TRACKING ERROR AMP

4042

FF

FR

TF

TR

7

10

19

MUTE12

20

MUTE34

21

MUTE5

22

TSD-M

13

45

535254

AVC

(1.65V)

WARFI

CDDOUT

117

RFIN

64

DOUT

DIP

55

DIN

RFAC

SDATA

SCLK

SDEN

MIRR

LDON

FF
FR

57

47
46
48

39

TE

40

FE

42MNTR

27

26

7

FCS_JMP_1

8

FCS_JMP_2

44

SLED_B

43

SLED_A

60

MUTE_2D

63

SP_ON

73

TSD-M

62

FG

28

76 31

LDON

LDSEL

SLED

DATA_RF

CLK_RF

SDEN

MIRR

INLIM

61

TE

FE
PI

TE

FE
PI

CLK_RF

DATA_RF

82

83

SDCLK RF

SDATA RF

IC402 (1/2)

AMP

SDEN

2

65

SDEN

50

RFAC

IC401

DIGITAL SIGNAL PROCESSOR,

DIGITAL SERVO PROCESSOR

SSTP

26

41

TE

40

SE
FE

39
43

RFDC

VC

38

CE

42

FF

33

FFDR

FR

34

FRDR

TF

31

TFDR

TR

32

TRDR

SFDR

29

SRDR

30

MIRR

PI

FE

TE

67PI66

FE

TE

IC301 (1/2)

MECHANISM

CONTROLLER

PCMD

BCLK
LRCK
C2PO

WDCK

WFCK

SBSO
EXCK

XTAI

MDP

SCOR

XTSL

MD2

DATA
CLOK

XLAT
SENS
SQSO
SQCK

LOCK

GFS

MUTE

XRST

COUT
SCLK

FOK

MIRR

66

BCLK

67

LRCK

65

C2PO

14

GSCOR

17

WFCK

10

SBSO

79

EXCK

80

SCOR

IC303

CLOCK

GENERATOR

10 3

71

26

10

3

49
50
27

9
52
54

75
71
59

98

30
72
74
29

IC703 (2/2)

SCOR

CDSP2

DOCTRL/
ISBTEST

DATA_CD
CLOK_CD
LAT_CD
SENS_CD
SQSO
SQCK

LOCK_CD
GFS_CD
MUTE_CD

XDRST

COUT_CD
SCLK_CD
FOK_CD
MIRR

25

15

69

63

4
6
5

7
76
77

24
13

3

2

19

8
22
20

7 8

XTI

SO2

MO1

13 9

27M

BUFFER

SDOUT_DSD

X302

27MHz

XTO

SO3

SO1

768FS

XRD

XWR

XCS_DVD
INIT0_DVD
INIT1_DVD

GFS_DVD

XRST_DVD

XRST_DSD

JIT OFFSET

SACD/DVD

EEP_RDY

EEP_SI

EEP_CLK

EEP_CS

SDIN_DSD

SCK_DSD

XMSLAT

READY_DSD

MUTE_DSD

JIT

14-21

D0 – D7

89-96

A0 – A7

85
84
12
22
23

58

25

4

45

64

77

6

5

100

99

47
46
24
51
48
53

BCLK
LRCK
C2PO
GSCOR

WFCK
SBSO
EXCK
SCOR

IC703 (1/2)

COMPARATOR

5

SDA

6

SCL

7

WP

MSDATO

MSDATI

MSCK

XMSLAT
SHRRDY
SHRMUT

160

MDAT

158

BCK

163

LRCK

155

C2PO

146

GSCOR

151

WFCK

148

SBIN

147

EXCK

150

SCOR

DVD DECODER

167

XTA1

169

XTA2

170

XTAL

137

MDIN2

135

SPO

D0 – D7

172-176, 1, 2, 4

A0 – A7

5, 7, 9-14

17

XRD

18

XWR

19

XCS

20

XINT0

21

XINT1

107

GFS

164

XRST

IC302

EEPROM

IC701

AEP0

109

HDB0 – HDB7

XHWR

XDRQ
HDB8
XHRD

MNT2

MDB0 – MDB9,

MDBA – MDBF

MA0 – MA9

XMWE

XMOE

XRAS
XCAS

XHAC

MNT1

53

92

44, 41, 39, 35,

48
46
26
49

93

66-69, 71, 73-75, 96, 97,

79, 80, 82-87,

76
94
78
95

AV DATA BUS

32, 30, 27, 24

XDCK
XSAK

SDEF

XSHD

2-5, 7-10,

41-44, 46-49

99, 101, 102, 104-106

89, 91

27-32

21-24,

17

WE

33

OE

18

RAS

34

UCAS

35

LCAS

IC814

SACD/DVD

SELECT

XMSLAT, SHRRDY, SHRMUT

• SIGNAL PATH

I/O0 – I/O15A0 – A9

IC706
16Mbit
D-RAM

MSDATO, MSDATI, MSCK,

: CD

SD0 – SD7

(for AUDIO SYSTEM)

SD0 – SD7

(for VIDEO SYSTEM)

XDCK, XSAK, SDEF, XSHD

(for AUDIO SYSTEM)

XDCK, XSAK, SDEF

(for VIDEO SYSTEM)

768FS

27M

XRST_DSD

XSRQ

XSRQ-ZIVA

: DVD

WCK

A
B

C

D

E

F

G

H

I

J

K
L

M

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

VIDEO

SECTION

AUDIO(DSP)

SECTION

VIDEO

SECTION

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

VIDEO

SECTION

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

VIDEO

SECTION

AUDIO(DSP)

SECTION

: AUDIO
: VIDEO

: SACD

HCD-SR4W

3030

6-2. BLOCK DIAGRAM — AUDIO (DSP) SECTION —

HCD-SR4W

HCD-SR4W

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

VIDEO

SECTION

RF/SERVO

SECTION

VIDEO

SECTION

VIDEO

SECTION

VIDEO

SECTION

AUDIO (OUT)

SECTION

WARFI

A

WCK

G

SD0 - SD7

C

SDEF, XSHD,
XDCK, XSAK

E

768FS

H

MSDATO, MSDATI, MSCK,
XMSLAT, SHRRDY, SHRMUT

M

XRST_DSD

J

XSRQ

K

TDOSA, TDISA,
TCK, TMS, TRST

N

CDDOUT

B

SPDIF

O

L, R

X

COAXIAL

FM

75 ohm

AM

AV1, AV3,
RGB SEL, DVD SEL

P

RSTAD

S

R

SAT

J601

VIDEO

D5V

AV DATA BUS

R-CH

AUDIO IN

AUDIO IN

FM/AM TUNER PACK

FM ANT

L-CH

GND

R-CH

AM ANT

GND

TUNED

FM-DET

DI

DO

CK
CE

IC402 (2/2)

REFERENCE VOLTAGE

GENERATOR

XDCK
XSAK
SDEF
XSHD

L

R

L

R

R-CH

TUDI

TUDO

TUCLK

TCE
TUN

DET AMP

LEVEL SHIFT

LEVEL SHIFT

OPTICAL

DIGITAL IN

R-CH

R-CH

Q103

IC812

IC813

MSDATO
MSDATI
MSCK
XMSLAT
SHRRDY
SHRMUT

TDOSA
TDISA
TCK
TMS
TRST

OPTICAL RECEIVER

AEP, UK, RU

Q101

AMP

4

X101

4.332MHz

127

126

123

169 - 176

166

167

168

165

11

6

4

3

2

7

10

9

164

29

27

26

30

31

IC603

IC602

AUDIO INPUT

SELECTOR

4

Y3

2

Y2

1

Y0

5

Y1

Q604 Q605

AV0

RDATA

MUX

RCLK

XI XO

13

14

WAVRB

WARFI

WCK

SD0 - SD7

SDCK

XSAK

SDEF

XSHD

MCKI

DSD DECODER

MSDATO

MSDATI

MSCK

XMSLAT

MSREADY

SMUTE

XRST

XSRQ

TDO

TDI

TCK

TMS

TRST

Y

AB

10

9

AV2

2

16

RDS DECODER

IC801

12.288MHz

3

AEP, UK, RU

RDSD

RDSC

IC101

X600

DSAL

DSAR

DSAC

DSALFE

DSALS

DSARS

BCKAO

EXCKO1

XWE

XRAS

XCAS

DCKE

DCLK

3

LOW-PASS

64

66

69

71

74

76

60

13

134-131

139-136,

DQ0 - DQ7A0 - A11

162-159, 157-154,

152, 151, 149, 148

143

145

144

142

141

5

4

3

22

21

20

IC603

FILTER

R-CH

DIN2

DIN1

DIN0

XIN

XOUT

XMCK

1

9, 11, 12

DQ0 - DQ7

2, 3, 5, 6, 8,

IC808

16Mbit

SD-RAM

20, 19

A0 - A11

21-24, 27-32,

15

WE

17

RAS

16

CAS

34

CKE

35

CLK

IC606

DIGITAL AUDIO

INTERFACE

XSTATE

XMODE

IC609

A/D CONVERTER

1

LIN

5

RIN

15

DATA

CKOUT

BCK

LRCK

ERROR

AUDIO

DOUT

BCK

LRCK

SCK

PDWN

7

RSTDSP

12

DSP-BST

DSP-RST

D1 - D3, SCK,
BCKO, LRCKO

DIGDI, DIGCLK

SOFTMUTE

AUDIO (OUT)

Q

SECTION

AUDIO (OUT)

T

SECTION

AUDIO (OUT)

R

SECTION

R-ch is omitted due to same as L-ch.

SIGNAL PATH

: AUDIO
: CD
: SACD

: AUX IN
: OPTICAL

39

DSIFL

40

DSIFR

41

DSICT

42

DSISW

43

DSISL

44

DSISR

38

DSBCK

27

MCK

IC612

DIGITAL AUDIO

EXIFLR

EXIMCK
EXIBCK
EXILRCK

EXID1

PLOCK

DIGDI

DIGCLK

CSDIR

XST

RSTDIR

EXID1

BCKI

LRCKI

DO

EXIFLR

EXIMCK

EXIBCK

EXILRCK

TUDI
TUDO
TUCLK
TCE
TUN

RDSD
RDSC

AV0
AV1
AV2

RGB SEL

DVD SEL

AV3

33

AD-RST

52

TUN-DI

54

TUN-DO

55

TUN-CLK

53

TUN-CE

51

TUNED

88

RDS_DATA

94

RDS_CLK

95

AV-SEL0

96

AV-SEL1

48

VIDEO-MUTE

73

RGB SEL

70

DVD SEL

98

AV-SEL3

65

89

DF-RST

DVD-POWER

16

13

14

15

36

DI

35

DO

38

CL

37

CE

17

48

34

24

12

11

10

AEP, UK ,RU

35

EXIFLR

29

EXIMCK

31

EXIBCK

32

EXILRCK

34

EXICSW

47

INIT

2

SELTES

SELEXT

4

Q908 - 910

ENABLE
SWITCH

97

PROCESSOR

DF-SW

DIGDI

7

DIG-DI

25

POCSW

MCKOUT

DO

DIRDO

POFLR

POSLR

PBCK

PLRCK

CSDIR

DIGCLK

8

20

DIG-CLK

23

22

21

17

19

20

RSTDIR

24

DIR-CE

DIR-XMODE

BCKI
LRCKI

X601

13.9MHz

DIGDI
DIGCLK

XST

PLOCK

IC900

LEVEL SHIFT

22

18

6

DSP-DO

DIR-XST

DIR-ZERO

IC901 (1/3)

SYSTEM CONTROLLER

15

17

DSP-HACN

DSP-GP9

18

SDI1

30

SDI2

114

SDI3

22

KFSIO

17

BCKI1

15

LRCKI1

SIGNAL PROCESSOR

29

BCKI2

28

LRCKI2

MCLK1

9

12

MCLK2

33

HDIN

34

HCLK

35

HDOUT

32

HACN

68

GP9

19

DIR-ERR

IC607

DIGITAL AUDIO

EXLOCK

59

23

GP8

69

DIR-AD

SDO4

SDO1

SDO2

SDO3

SCKOUT

BCKO

LRCKO

GP10

CS0

WE0

HCS

BST

XRST

Q903

D903

D0 - D15A0 - A15

PM

26

23

24

25

14

20

19

67

108, 107, 105-102, 99

112, 110, 109,97-92,

44

45

113

36

56

2

SUR BACK

98, 80-77, 75-72

82, 85-83, 66-64

RSTDSP

D1

D2

D3

SCK

BCKO

LRCKO

D0 - D15

7-10, 13-16,

29-32, 35-38

S-RAM

A0 - A15

5-1, 44-42,

27-24, 21-18

6

CS

17

WE

PM
HCS
BST

PM

13

IC604

HCS

14

DSP-PM

BST

16

DSP-CS

DIGITAL IN

: TUNER

3131

HCD-SR4W

6-3. BLOCK DIAGRAM — AUDIO (OUT) SECTION —

DIGDI, DIGCLK

T

RSTAD

S

J602

MUTE DRIVE

FL DRIVER

5 - 39

S1 - S35

40 - 51

G1 - G12

AUDIO(DSP)

SECTION

D1 - D3, SCK,
BCKO, LRCKO

Q

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

SURROUND

BACK

FL801

FLUORESCENT

INDICATOR TUBE

Q607,608

IC803

SUR BACK

SCK
BCKO
LRCKO

DAT
CLK

CS

RST

VFL

P1

63
62
61
60

56

1

DIGDI
DIGCLK

LED DRIVE

Q900

SWITCH

VFL

Q810

D/A CONVERTER

3

SDTI

1

MCLK

2

BICK

4

LRCK

8

CDTI

7

CCLK

1

IC606

(2/2)

IC608

60
57
61
56

AOUTL+

AOUTL-

PDN

3

2

FL-DATA
FL-CLK
FL-CS
FL-MUTE

12
11

CSN

65

IC605

CONVERTER

2

VOUT

IC901 (2/3)

SYSTEM CONTROLLER

DATA

CLK

VIN

SBR-OUT

SB-OUT

1

4
5

SB-MUTE

SB-SCK

SB-DATA

HPSW

HP-MUTE

DAC-LAT

OVERFLOW1

IC108

STREAM PROCESSOR

45

HPOUTL1

43

HPOUTL2

41

HPOUTR1

39

HPOUTR2

DAC-LAT

IC606

(1/2)

5

7

6

47
50
49

64
46
32
85

HP-SW

HP-MUTE

DAC-LAT

2

IC904(2/3)

BUFFER

D1

SCK
BCKO
LRCKO

SCDT
SHIFT
LATCH1
INIT
NSPMUTE
SOFTMUTE

6

31

36
30
29

21
22
23
27
18
19
24

DATA

XFSIIN
BCK
LRCK

SCDT
SCSHIFT
SCLATCH
INIT
NSPMUTE
SOFTMUTE
OVF FLAGR

OUTL1

OUTL2

OUTR1

OUTR2

XFS0OUT

FSOI

XFSOIN

11

9

6

4

14

38

48

IC305

OSC

X450

49.152MHz

IC301

HEADPHONE

AMP

HP-MUTE

POWER DRIVER

2

PWMBP

17

PWMAP

4

RESET

POWER DRIVER

2

PWMBP

17

PWMAP

4

RESET

Q902

MUTING

CONTROL

IC101

OUTB

OUTA

8 13

IC102

OUTB

OUTA

8

DIAGA

DIAGA

13

Q801-804

MUTING

29

LPF

30
25

LPF

26

SD

29
30

25
26

SD

LPF

LPF

Q101, 102

OVER LOAD

DETECT

Q103, 104

OVER LOAD

DETECT

HP-SW

TB301

SPEAKER

J800

PHONES

(+)

FRONT

L

(ñ)

(+)

FRONT

R

(ñ)

CSOD

XRST

DIAT TRANSMIT

SECTION

AUDIO(DSP)

Y

VIDEO

SECTION

VIDEO

SECTION

SECTION

XLAT

SDATA

SCDT

D2(SL/SR)

BCKO

LRCKO

R-ch is omitted due to same as L-ch.
SIGNAL PATH

: AUDIO

ZIVARESET

V

I2CDATA, I2CCLK

W

R

S800, 801, 807-809,
S815 - 818

SCDT

SHIFT

D2

BCKO

LRCKO

Q913

DISC INSERT

DETECT

IC801

REMOTE CONTROL

RECEIVER

SONY

KEY2

IC903

KEY INPUT

DETECT

Q906, 907

SIRCS DETECT

INVERTER

IC7004

I2CDATA
I2CCLK

D821D819

D802

66

STBY LED

82 - 84

KEY0 - KEY2

38

81
78
93

92

91

100

99

4

3
5

SEN2
LSEN
WAKE

SIRCS

POWER SW

XRST
XLAT

CQ-RST

I2C-DATA
I2C-CLK

OVERFLOW2

SCDT

SHIFT

LAT1
LAT2
LAT3

INIT

SOFTMUTE

DRI-RST

DRI-OCP

X1

X2

X901

20MHz

39

IC110

STREAM PROCESSOR

3

SCDT

SHIFT
LATCH1
LATCH2
LATCH3

INIT

SOFTMUTE

5

IC904(3/3)

BUFFER

7

IC904 (1/3)

BUFFER

D3

SCK
BCKO
LRCKO

SCDT
SHIFT
LAT3
INIT
NSPMUTE
SOFTMUTE

1

86

1

2
29
30
31
26
28

43

44

24

18

21
17
16

21
22
23
27
18
19

OVF FLAGR

DATA

XFSIIN
BCK
LRCK

SCDT
SCSHIFT
SCLATCH
INIT
NSPMUTE
SOFTMUTE

OUTL1

OUTL2

OUTR1

OUTR2

FSOI

FSOCKO

XFSOIN

11

9

6

4

38
37

48

IC105

POWER DRIVER

2

PWMBP

17

PWMAP

4

RESET

IC106

POWER DRIVER

2

PWMBP

17

PWMAP

4

RESET

Q301

PROTECT DETECT

IC107

POWER DRIVER

2

PWMBP

17

PWMAP

4

RESET

13

SD

OUTB

OUTA

DIAGA

8

OUTB

OUTA

DIAGA

8

OUTB

OUTA

29

LPF

30
25

LPF

26

SD

13

29
30

25
26

SD

13

29
30

25
26

LPF

LPF

LPF

LPF

Q109, 110

OVER LOAD

DETECT

Q111, 112

OVER LOAD

DETECT

FAN

DRIVE

Q303,304

+12V

(+)

(ñ)

(+)

(ñ)

FAN

Q113, 114

OVER LOAD

DETECT

CENTER

WOOFER

HCD-SR4W

3232

6-4. BLOCK DIAGRAM — VIDEO SECTION —

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

RF/SERVO

SECTION

AUDIO(DSP)

SECTION

D

F

I
L

O

SD0 - SD7

XDCK, XSAK,
SDEF

27M

XSRQ_ZIVA

SPDIF

AV DATA BUS

XDCK
XSAK
SDEF

177-174, 171-168

SDDATA0 - SDDATA7

SDCLK

183

SDEN

179

SDERROR

182

XIN

139

SDREQ

178

IEC958

156

VDAC_0

VDAC_2

VDAC_1

VDAC_3

VDAC_4

HCD-SR4W

V

131

Y

125

C

128

CB/B

122

CR/R

119

IC201

VIDEO AMP, 75ohm DRIVER

6

YIN

2

CIN

4

VIN

12

CYIN

14

CBIN

16

CRIN

YOUT

COUT

S-DCOUT

CYOUT

CBOUTB

CROUTB

21

26
27

25

S1

23

CY

20

18

16

VOUT

CYOUT

CBOUT

CROUT

34

12

VIDEO

PB/CB

PR/CR

Y

S VIDEO

COMPONENT

VIDEO OUT

J202

MONITOR OUT

J201

AEP, UK, RUEXCEPT AEP, UK, RU

J203

CROUT

CYOUT

CBOUT

VOUT

L

R

15

R/C OUT

G OUT

11

B OUT

7

V/Y OUT

19

BLANK

16

OUT

8

FUNCTION
SW

6

A(L) IN

2

A(R) IN

EURO AV

T OUTPUT

(TO TV)

AUDIO (OUT)

SECTION

AUDIO (DSP)

SECTION

AUDIO (OUT)

SECTION

ZIVARESET

V

TDOSA, TDISA,
TCK, TMS, TRST

N

I2CDATA, I2CCLK

W

TDOSA
TDISA
TCK
TMS
TRST

I2CDATA
I2CCLK

MUTE1

RESET

202

TDI

199

TDO

198

TCK

201

TMS

200

TRST

197

IC206

DVD SYSTEM PROCESSOR

I2C_DA

I2C_CL

DRVTX

DRVRX

DRVCLK

HIRQ1

161

78

I2C_SIO

160

186

79

34

I2C_SCL

EXTAL

41 40

X301

20MHz

187

185

33

35

SI_ZIVA

SO_ZIVA

XTAL

184

36

DRVIRQ

SCK_ZIVA

DRVRDY

188

3

IC803

FLIP-FLOP

6

1

37

DRVRDY

IC301 (2/2)

MECHANISM CONTROLLER

4

SWITCHING

1

IC802

6
5
4

HIRQ2

WRITE_CTRL(ZIVA_E2P)

116

165

1

8

WC

R/B

DO
DI
SK

IC203

EEPROM

2

3

CS

Q302

CS(ZIVA_E2P)

191

162

32

38

CS_ZIVA

RST_SPC

RST

DATA & ADDRESS BUS

HAD0 - HAD15

29,31,33,35,38,40,42,44,

30,32,34,36,39,41,43,45

DQ0 - DQ15

22, 19-14, 11-3 2, 207, 206

HAD0 - HAD15 HA1 - HA3

DATA & ADDRESS BUS

HAD0 - HAD15 HA1 - HA3

55, 54, 52, 51,

49-47, 45-40, 38-36

1D1 - 1D10, 2D1 - 2D6

1Q1 - 1Q10, 2Q1 - 2Q9

2, 3, 5, 6, 8-10, 12-17,

HA1 -HA3

25-23

A0 - A2

PROGRAMMABLE ROM

MUTE2

3

15

HA1 - HA3HAD0 - HAD15

34, 33, 31

2D7 - 2D9

19-21, 23, 24, 26

ADDRESS BUS

22-18, 8-1, 48,

17, 16, 9, 10, 13

A3 - A21

IC205

AV3

AV1

190

56 29

BUS INTERFACE

HA4 - HA22

ALE

1LE

2LE

IC215

Q204-206

DVD SEL DVD SEL

107

VS

HCS0

WEH.UDS

HREAD

195

27

25 56

CEWEOE

FUNCTION

SWITCH

MD0 - MD31

57-60, 64-71, 75-78,

81-84, 88-95, 99-102

2,4,5,7,8,10,11,13,74,76,77,79,80,82,83,85,31,

33,34,36,37,39,40,42,45,47,48,50,51,53,54,56

RGB SEL

DQ0 - DQ31 A0 - A11

Q201-203

BLANKOUT

SWITCH

MA0 - MA11

42-33, 45, 46

60-66,24,21

IC202

128Mbit SD-RAM

25-27,

RGB SEL, DVD SEL

MCLK

BA1

BS1

MCS0

49

53

68

20

17

CS

CLK

BA0

48

47

22

23

BS0

SIGNAL PATH

CE

OE

WE

26

28OE11

CE

WE

L, R

X

AV3

P

MWE

MRAS

MCAS

MDQM0

MDQM1

MDQM2

73

71

DQM0

86

28

DQM1

97

59

DQM2

MDQM3

DQM3

51

52

62

19

18

16

WE

CAS

RAS

: VIDEO
: Y
: CHROMA
: COMPONENT VIDEO
: R, G, B

AUDIO(DSP)

SECTION

AUDIO(DSP)

SECTION

HCD-SR4W

3333

HCD-SR4W

6-5. BLOCK DIAGRAM — DIAT TRANSMIT SECTION —

AUDIO(OUT)

SECTION

Y

SWITCHING

REGULATOR

LRCKO

BCKO

D2(SL/SR)

XRST

CSOD

SDATA

XLAT

SCLK

D-GND

+15V

4

VCC(9V)

R835

R836

5

4

12

13

10

IC802

LEVEL SHIFT

4

5

10

9

13

12

1

2

6

8

11

3

6

11

8

IC900

1

REG

D800

6

+2.5V REG

IC801

+2.5V

4

IC804

RF MODULATOR

D/A CONVERTER

49

LRCK

50

BCK

48

DTIN

41

APS

64

16

15

13

14

XRST

CSOD

SWDT

SCLK

XSCEN

DAAOUT

21

Q801

BUFFER

RV801

IC805

RF AMP

3
4

C842

1

J301

WIRELESS

SPEAKER

9

LEVEL SHIFT

IC803

X801

24.576MHz

C820

C819

54

57

59

60

C SST

O SCI

OSCO

XTCK4

SIGNAL PATH

: AUDIO

HCD-SR4W

3434

6-6. BLOCK DIAGRAM — POWER SECTION —

TO FLUORESCENT

INDICATOR TUBE

FL+

FL-

VFL

RECT
D810,811
D813,814

HCD-SR4W

DC/DC

CONVERTER

T801

OSC

Q802

IC901 (3/3)

SYSTEM CONTROLLER

L SEN

OPT-SEN

PARA DO2

PARA-RST

PARA-LT1

78

79

67

68

69

F-IN

R-IN

SW1

D-SEN
(SW3)

SW2

12V

M12V

A-3.3V

D5V
A5V

S701

S702

S703

7

FIN

8

RIN

IC701

LOADING

MOTOR
DRIVER

(DISC IN/OUT)

(TRIGGER)

(CHUKING)

4

OUT1

2

OUT2

MTR+

MTR-

DA03V

2.5V

DA05V

M

IC605

REG

M701

(LOADING)

1

IC001

3

REG

IC005

3

REG

+5V

1

+10V

1

+2.5V

+1.8V

IC002

3

REG

3

3

4

3

IC601

REG

IC004

REG

IC704

REG

IC006

REG

1

1

1

5

1

+12V

6.2V

3.3V
E5.6V

AC DET

AC ON/OFF

(AC IN)

V CONTROL

HCD-SR4W

+1.8V

90STOP

34RESET

45AC ON/OFF

11V CONTROL

Q901

RESET SWITCH

IC907

RESET SIGNAL

GENERATOR

E5.6V

IC303

4

REG

5

3535

HCD-SR4W

6-7. PRINTED WIRING BOARD — RF BOARD —

1 2 3 4 5 6 7 8 9 10 11 12 13

A

B

E

E

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

RF BOARD

(SIDE A)

FLEXIBLE BOARD

OPTICAL PICK-UP

BLOCK

(DBU-1)

RF BOARD

(SIDE B)

C

D

DMB08 BOARD

E

F

A

CN401

(Page 39)

1-684-822-

11

(11)

64 49

1

IC001

16

17 32

48

33

11

(11)

• Semiconductor
Location

Ref. No.

D001 B-3
D002 B-3

Location

1-684-822-

HCD-SR4W

IC001 D-11
Q001 C-11

Q002 B-11

3636

HCD-SR4W

6-8. SCHEMATIC DIAGRAM — RF BOARD —

CN001

24P

D

C

RF

GND

VC

(DBU-1)

FLEXIBLE

BOARD

LD GND

DVD LD

INLIM_3V

VCC

E

A

B

F

N.C

PD

VR

VCC

SW

INLIM

CD LD

FCS+

FCS-

TRK+

TRK-

• See page 70 for Waveforms. • See page 80 for IC Block Diagram.

R023

820

C024

JL005

R024

D

C

RFP

C009

0.1
RFP

A

E

A

B

B

C

F

D

100

R001

FD+

FD-

TD+

TD-

PD FD-

DVD_LD

CD_LD

R041

1k

E

F

D
P

R019 R020

00

JL007

R035

0

R025

100

R022

C019

220

5600p

C017

2200p

C016

0.01

0

22p

22p

22p

C020

C021

C022

2200p

2200p

C015

2200p

C014

C042
180p

0

R014

0

R013

0

R012

0

R011

0

R018

0

R017

0

R016

0

R015

RFMON

C006

R026C027C028

C031

12k0.10.1

1000p

0.01

4

IC B/D

IC001

CXD1881AR

C030

C029

0.01

0

R027

0

R028

0

R029

C032

0.047
JL006

3

JL003

R032

C033 C012

100

2

JL002

JL001

R033

0

330p

0.033

0.033

C036

R034

0.47

C037

C039

C038

N

R

O

IR

D
L

M

10M

C034

0.1

C026

C025

0.1

0.1

JL004

22p

5600p

1

C023

C018

CD/DVD/SACD RF AMP,

FOCUS/TRACKING ERROR AMP

C041

C008

0.1

0.1

R021

0

C040

0.1

22

10V

0.1 0.1

C013

0.1

C035

0.1

MIRR

PI/CE

TE

FE

SDEN

SDEN

DATA_RF

DATA_RF

CLK_RF

CLK_RF

LDON

C005

22
10V

C049

0.1

RFMON

FE

TE

PI/CE

CN002

29P

AGND

RFAC

AGND

AVC

AVC

MIRR

PI

TE

FE

A5V

A5V

SDEN

DATA_RF

CLK_RF

LDON

A3V

RFMON

INLIM

LDSEL

FD+

TD-

TD+

SLB-

SLB+

SLA-

SLA+

FD-

FD+

TD-

TD+

SLEDB-

SLEDB+

SLEDA-

SLEDA+

SPDL-

SPDL+

DMB08 BOARD

(1/10)
CN401

(Page 41)

HCD-SR4W

CD_LD

C001

R004R003

R005 R009

3333

IOP2

Q001 Q002

2SB1132-T100-QR 2SB1132-T100-QR

AUTOMATIC POWER

CONTROL

1SS355TE

-17

(FOR DVD)

L001

47µH

C002D001

10

16V

CN003

9P

SLEDA+

SLEDB+

SLEDB-

SLEDA-

{LIMIT-SW(A)}

LED

{LIMIT-SW(B)}

GND

{LIMIT-SW(B)}

INLIM

SPDL-

SPDL+

SLA+

SLB+

SLB-

SLA-

DVD_LD

47k 47k

C010

1000p

R006

100

470

6.3V
IOP1

AUTOMATIC POWER

CONTROL

(FOR CD)

1SS355TE

-17

L002

47µH

C004D002

10

16V

C003

R010R008R007

100

4703333

6.3V

C011

1000p

No mark : DVD STOP

3737

HCD-SR4W

A

B

C

• See page 28 for Circuit Boards Location.

:Uses unleaded solder.

12

(TRIGGER) (DISC IN/OUT)

9

IC701

1

6-10. SCHEMATIC DIAGRAM — DRIVER BOARD —6-9. PRINTED WIRING BOARD — DRIVER BOARD —

34

(CHUKING)

M701

M

(LOADING)

DMB08 BOARD

CN007

G

(Page 39)

100

R702

D701

TZJ-T-77-4.7C
M

R701

680

C705

0.01

IC B/D

IC701

BA6956AN

• See page 78 for IC Block Diagram.

S703 S701 S702

(TRIGGER) (DISC IN/OUT) (CHUKING)

+7V

CN701

7P

C711

50V

10

CT-L

G

DMB08 BOARD (10/10)

CN007

(Page 50)

M701

(LOADING)

No mark : DVD STOP

HCD-SR4W

3838

HCD-SR4W

6-11. PRINTED WIRING BOARD — DMB08 BOARD (SIDE A) —

12

A

B

IC901

D

DDCON

BOARD
CN800

(Page 60)

C

FOR

CHECK

IC301

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

3456789

DRIVER

G

BOARD

CN701

(Page 38)

IC612

IC801

IC813

DIAT TRANSMIT BOARD

Y

CN010

CN801

(Page 62)

IC606

IC607

IC605

AMP

BOARD

CN302

(Page 52)

B

C

AMP

BOARD

CN301

(Page 52)

D

E

F

FOR

CHECK

IC402

IC401

IC701

BOARD

A

CN002

(Page 36)

RF

IC206

BOARD

F

CN201

(Page 57)

SWITCHING

REGULATOR

CN8

IO

E

IO

BOARD

CN601

(Page 57)

• Semiconductor Location

Ref. No.

D900 C-2
D901 C-4

IC206 D-5
IC301 C-2
IC401 D-2
IC402 D-2
IC605 C-8

Location

Ref. No.

IC606 C-7
IC607 B-7
IC612 B-6
IC701 D-4
IC801 B-5
IC813 C-4
IC901 B-2

Location

HCD-SR4W

3939

HCD-SR4W

6-12. PRINTED WIRING BOARD — DMB08 BOARD (SIDE B) —

12

A

B

IC604

IC005

C

IC004

IC608

D

IC904

IC609

IC601

IC002

IC203

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

345678

IC900

IC7004

IC215

IC704

IC205

IC808

IC303

IC202

IC812

IC814

IC706

IC803

IC903

IC802

IC907

EXCEPT
AEP,UK,KR,CH

EXCEPT
HK,SP,TW

IC302

• Semiconductor
Location

Ref. No.

D902 B-7
D903 B-6
D904 C-7
D907 B-7

IC001 E-3
IC002 D-2
IC004 C-2
IC005 C-2
IC006 E-4
IC202 D-4
IC203 D-3
IC205 D-4
IC215 C-3
IC302 C-7
IC303 C-4
IC501 E-7
IC601 D-2
IC603 E-2
IC604 C-2
IC608 D-2
IC609 D-2
IC703 E-5
IC704 C-4
IC706 D-5
IC802 C-7
IC803 C-6
IC808 B-4
IC812 C-5
IC814 C-5
IC900 B-3
IC903 C-6
IC904 D-1
IC907 B-7
IC7004 B-3

Location

E

HCD-SR4W

IC603

IC001

IC006

AEP,UK,RU

IC703

4040

IC501

Q301 D-6
Q302 D-3
Q900 B-7
Q901 B-7
Q902 B-7
Q903 B-6
Q906 B-6
Q907 C-7
Q908 B-3
Q909 B-3
Q910 B-3
Q913 B-7

HCD-SR4W

6-13. SCHEMATIC DIAGRAM — DMB08 BOARD (1/10) —

C406

0.0022

C405

CN401

29P

37

JL544

JL537

JL536

JL535
JL531
JL530
JL529
JL527

JL526
JL525
JL524

JL523
JL522
JL501
JL502

JL500
JL511
JL512
JL509
JL510

JL503
JL504
JL505
JL506

JL507
JL508

10

16V

• See page 73 for IC Block Diagram. • See page 88 for IC Pin Function Description.

C411

C410

10

0.1

16V

0

1.600

401
R

R413

R412

C407

R411

0

10k

10k

10

10V

1.6

0

0

0
0

0

1.6

DIGITAL SIGNAL PROCESSOR,
DIGITAL SERVO PROCESSOR

C409

0.0022

C408

0.1

C412

0.0022

C413

0.0022

C419

0.047
B

R441

1k

C418

0.1

R421
R423
R425

R426
R429
R430

C420

0.0022

3.3

1k

0.8

1k

0.8

1k

0

1k

0

1k

0

1k

0

1.6

1.6

1.6

R443

47k

1.6

1.6

1.2

0.9

3.3

R445
R450

1k
1k

C425

0.0022
C424

0.022

B

k
33

.0033

449

0

R

28
C4

B

AMP, REFERENCE

VOLTAGE GENERATOR

R414

0

R428

1k

C414

0.01

R433

C404

R418

0.1

10k

R419

68k

0.7

0.7

0.7

(TE2)
V

IC402

3404A
JM

N

5

0.8

0.8

1.6

R440

47k

R437

R434

47k

47k

47k

C415

0.01

C426

0.01

0

1.6

10k

447
R

B

0

IC401

CXD3068Q

IC B/D

1.6

1.703.3

0k
10

55
4

C432

R

100p

C427

0.47
B

C433

0.0015

R457

FL401

0UH

(2012)

C401

C402

0.1

10

3.2

3.2

3.2

3.2

3.200

3.3

5
0
0

0.2

R451

10k

3

R420

0

1.3

1.6

1.6
0

1.6

R439

C417

330

C416

10

10V

R442

0.1

10k

0

0

3.3

3.3

0

C422
100p

0

0.4

R444
470k

R453

C423

1M

452
R

1M

0.1

FL402

0UH

(2012)

C436C435

0.10.1

3.3

3.3

3.3

1k

R446

10k

448
R

C421

0.1

3.3k

C434

10

10V

HCD-SR4W

NO MARK : DVD STOP

42

4141

HCD-SR4W

6-14. SCHEMATIC DIAGRAM — DMB08 BOARD (2/10) —

FOCUS/TRACKING COIL DRIVER,
SPINDLE, SLED MOTOR DRIVER

C526

22

16V

C527

0.1

41

R581

12k

R580

582

10k

R

12

0

0

0

0

IC501

FAN8035L

1

1

0.9

0.9

0

10k

R583

0

3.2

33k
C519

0.01

1.6

1.6

R579

8.2k

C514

0.01

C512

0.01

R532

0

R533

33k

R534

56k

R529

33k

R530 R531

56k 0

R535

0

R592

0.9

0.9

0

0.9

0.9

0.9

R510

R511

150k

150k

C529

0.1

C524

0.1

514
R

R416

0

10k

C525

0.1

C528

6.3V

47

R513

C503

R515

56k

504
C

33000p

10k

R512

56k

33000p

C510

0.001

R522

4.7k

C509
330p

R536
200k

R516 R517

C506

4.7k 2. 2k
330p

R527

2.2k

R525

10k

R524
10k

R521
100k

R523

10k

R519
100k

R520

10k

C508

0.001

NO MARK : DVD STOP

HCD-SR4W

4242

6-15. SCHEMATIC DIAGRAM — DMB08 BOARD (3/10) — • See page 76 for IC Block Diagrams. • See page 93 for IC Pin Function Description.

HCD-SR4W

IC B/D

NJM3404AV(TE2)

R765

22k

R767

47k

IC703(2/2)

FL704

0UH

(2012)

C774

0.0047

FL706

(2012)

(2012)

TP702

R729

8.2k

BUFFER

R544

R545

100k

100k

1.6

C523

0.0015

1.6

C521

0.0015

0UH

FL703

0UH

C780

10

10V

C781

10
10V

R764

1M

C771

0.047
B

R540

10k

1.6

R541
100k

R538
100k

C729

10

10V

FL701

0UH

(2012)

R701

C777

0.01
B

C776

0.1
F

C772

0.1

C773

0.47
B

680

FL702

0UH

(2012)

R771

C779

2.2k

10

10V

C775

R763

C770

8.2k

0.01

R762

22k

R760

0

C767

0.01
B

R778
100k

C706

0.1
F

C702

R707

100

100

4V

B

1
.0
0

8
7
7
C

0.01 B

C769

0.01 B

C768

0.01 B

R708
470k

1.6

1.6

1.6

1.6

3.3

0

1.6

3.3

1.6

0

0

5

2

0

1.6

5

0

5

3.2

3.3

C709

0.1
F

C708

C752

0.01

0.1

1.9

1.6

1.5

C711

R710

0.01

10k

k
.2

2

R709

1

150k

1
7
R

3.3

3.3

1.6

1.5

COMPARATOR

C715

0.0015

R748

33k

C712

C703

100p

0.1
CH

k

F
0
1

.1
3

0
1
7

3

R

1

7

C

k

k

0

k

0

1

3

1

3

2
1

4

7

7

1

R

4

7

7

R

R

1.6

0.5

0.9

0.3

3.3

R726R725

1.8k

100k

5

1.6

1.6

C720

0.1

R724

F

.1
0

4
1
7
C

3.3

B

1k

R721

33k

C717

R720

0.01

1k

B

k
0

C716

1

0.47

5

B

1
7
R

k

0

k

0

0

0

1

1

0
1

1

9

8

6

1

7

1

7

7

7

R

1

R

7

R

R

1.6

1.6

1.6

1.6

1.6

1.5

0

1.6

R799

R776

R750

10k

R777

0

C766

0

0

C765

0.01
B

3.2

100p

3.2

3.2

1

1

3.3

2.5

2.6

2.6

2.6

0

TP701

IC703(1/2)

NJM3404AV(TE2)

R727

3.3k

4.6

C721

0.1 B

IC B/D

C728

0.1

R728

B

10k

FL705

0UH

(2012)

3.3

F

C727

4
2

10

7

.1

C

10V

C718

0.01
B

8

k

1

0

7

1

R

0
0

8
7
R

1.6

3.2

1.700005003.20003.200

0

0.01
B

DVD DECODER

IC701

TMC57929PGF

-RDP

000000000

000

0

000

3.3

C723C722

C725

0.01

0.1 F

B

0.2

M51V18165M-60TS-

0

0.8

16 Mbit D-RAM

IC706

KR1

IC B/D

0.4

R772

3.200.8

3.2

2.100.2

22

3.3

0.4

0.4

0.4

0.4

0.4

0.4

3

0.4

2.1

3.2

3.2

0

0

0

5

0

0

0

0

0

5

3.3

5

5

5

5

5

5

5

3.2

5

3.3

0

2.3

5

5

0.4

0.4

0.4

0.420.4

R732

10k

R702

10k

R703

10k

R735

10k

R704

10k

R737

10k

R705

10k

R706

10k

R743

22

0.4

0.4

0.4

3.3

C726

0.1
F

C730

0.01
B

C740

0.01
B

R730

22

R731

22

C741

0.01
B

C742

0.01
B

C743

0.01
B

C744

0.01
B

R741

22

R742

22

C745

0.01
B

44

HCD-SR4W

000

C764

0.01

0

050

0

3.3

B

3.203.2

3.2

3.2

3.2

3.2

R746
47k

C763

0.01
B

3.2

3.2

05050

3.3

R744

R745
47k

C762

0.01
B

22

0

0

3.3

C760

0.01
B

C761

0.01
B

0

0

0

5

NO MARK : DVD STOP

45

4343

HCD-SR4W

6-16. SCHEMATIC DIAGRAM — DMB08 BOARD (4/10) — • See page 76, 77 for IC Block Diagrams. • See page 97 for IC Pin Function Description.

R888

R886

R884

R882

10k

10k

R885

R883

10k

10k

C842

0.01
B

3.3

0.8

3.2000000

0

0

0

0

3.3

R805
10k

SL813

C871

0.01
B

002.5

2.5

0

0.7

2.5

00000

3.2

3.2

3.2

SL811

C815

0.01
B

0

3.3

R842

10k

0

C865

0.01
B

3.3

C867 C866

0.01
B

3.3

2.5

3.3

2.5

POWER-EMIS

(3216)

REG

FL812

FL810

(2012)

R808

IC704

TK11125CSCL-G

0UH

IC B/D

10k

C840

10

10V

C841

10

10V

10k

10k

R889

R887

10k

10k

IC B/D

3.3

C797

100 4V

16Mbit SD-RAM

IC808

MSM56V16160F-8TK

-7R1

C870 R803

0

C805

0.01
B

C796

0.1
F

C843

0.01
B

C848

0.01

B

00003.30000

0

000

3.2

C854

0.01
B

0

R804

33000p 100

SL812

0

3.3

0

FL811

POWER-EMIS

3.3

0.01
B

3.3

C803

C802

0.01

IC B/D

IC814

TC7WH157FK

(TE85R)

10

10V

3.3

0
0
0
0
0
0
0
0

3.3

3.2
0
0

1.5

C849

B

0.01

0

3.2

C837

0.01
B

C811

C804

0.01

0.01
B

C819

0.01
B

R830

4.7k

C812

0.01

1.2

FL807

0UH

(2012)

SACD/DVD SELECT

R847

22

3.2
0

C813

3.3

0.01

3.3
0
0
0
0
0
0
0
0

3.3

5.1

5.1
0

2.2

IC B/D

IC812

SN74LV245APWR

IC813

SN74LV245APWR

43

LEVEL SHIFT

0.8

0
0

3.2
0
0
0
0
0

0.8

3.2

3.2

3.2

3.2

3.2

0
0
0
0
0

2.5
0
0

3.2
0
0
0
0
0
0

3.2
0
0
0
0
0
0
0
0
0
0
0
0
0

DSD DECODER

IC801

CXD2753R

C861

0.01
B

2.5

C857

0.01
B

R826

3.2

22

1.6

R850

1.6

22

C855

0.01
B

1.6

R849

22

1.6

R848

22

1.6

1.6

R821

22

1.6

R822

22

R823

22

1.6

R867

0

2.5

2.5

C856

0.01
B

3.2

HCD-SR4W

LEVEL SHIFT

IC B/D

3.2

3.202.5

3.2

3.2

3.200.7

3.2

33k

C808
100p

C817 C818

R806

0

0.01
B

0

R829

k

0
8

100

.7

R

4

R831

B
0
1

1

8
C

.0

0

B
7
0

1

8
C

.0

0

0

8

9
3
8
R

0

C839

k

k

2

1

8

0.01

.7

.7

R

4

4

7

B

2
8
R

3.3

0.9

3.3

3.3

3.2

3.2

0.2

2.5

C838

0.01
B

0.01
B

NO MARK : DVD STOP

45

4444

HCD-SR4W

6-17. SCHEMATIC DIAGRAM — DMB08 BOARD (5/10) —

FL301

0UH

(2012)

C302

0.01
B

C301

10

10V

C320

0.01
B

3.2

3.2

3.2

3.2

10k

EEPROM

IC B/D

IC302

BR24L16F-WE2

• See page 70 for Waveforms. • See page 72, 73 for IC Block Diagrams. • See page 86 for IC Pin Function Description.

(3/10)

3

22

22

R304

R303

3.2

3.2

3.2

3.2

3.2

R738

22

0

0

3.2

R361

3.2

22

0
0
0
0

3.2

R316

10k

3.2

2.5

2.5

2.6

2.6
0
0
0
0

3.1

3.1

3.2

3.2

10k

0

0

0

3.2

3.2

100

100

R317

R318

R311R312

43

3.203.20000

000

3.2

100

R321

100

R323

3.2

3.2

C303

0.01
B

3.2

MECHANISM

CONTROLLER

IC301

CXP973064-245R

10

3.1

3.2

20MHz

X301

3.2

1.5

0

R324

C307

44

Q301

LASER DIODE

22

10k

22

22

R306

R305

R307

R308

3.2

3.2

3.2

3.2

3.2

3.2

4.1

4.100

1.5

3.2

1.6

1.6

0.603.2

100

R326

100

R327

100

R328

3.203.2

100

R329

100

R330

R360

10k

R325

33k

B

B

C304

0.01

0.01

0
0

0.5

3.2
0

3.2

3.2

1.6

1.1

1.6

3.3

1.6

1.1

1.6

1.6

3.2
0
0
0

3.2
0
0

3.2

R364

4.7k

FL304

0UH

(2012)

R350

100

C311

0.01
B

R333

10k

R332 R365

10k 100k

C309
100p

R335

C308

33000p

C310
100p

C312

10

10V

R346

1k

R344

1k

R363

10k

R337

100

22

R366
100k

Q301

DTC114EKA

-T146

0

SELECT

5

L301

FL303

0UH

(2012)

R359

R353

SWITCHING

IC802

TC7S32FU(TE85R)

3.2
0

SN74AHC2G74HDCUR

3.1

3.2

0.1

C809

0.01

R355

CL301

22

C318

12p

X302

C317

12p

C316

10 16V

C313

0.1 F

10k

10k

JL301
JL302

JL303
JL304
JL305
JL306

JL307

27MHz

R362

R354

150

CN301

3.2

3.2

IC803

3.2

3.2

3.2

FLIP-FLOP

3.2

1.2

9

3.2

1.4

1.4

1M

7P

5

IC303

SM8707GV -G-E2

CLOCK

GENERATOR

8

0.6

3.2

0.6

0.6

6

IC B/D

CL304

R356

68

CL303

CL302

R357

68

R358

7

68

HCD-SR4W

R331

220

NO MARK : DVD STOP

4545

HCD-SR4W

6-18. SCHEMATIC DIAGRAM — DMB08 BOARD (6/10) —

R608

3.3k

0

C636

0.1

3.3

0

R625

3.3k

R628

R631

0

4.9

4

100

100

0

R639

100

C665

0.01

R699

2.2k

C675

0.01

R697

4.7k

4.7

• See page 70 for Waveforms. • See page 74, 75 for IC Block Diagrams.

R600

100

6p
5

z

2p

603

H

2

C

8M

600
X

C604

8

12.28

R602

1M

76
R

1.7

16

0

1.6

1.6

IC606

LC89056W-E

DIGITAL AUDIO

INTERFACE

0.1
100

C608

603
R

3.3

3.2

3.2

IC B/D

3.3

3.3

3.3

R640

C648

100

0.1

R661

100

0

1.6

2.5

1.6

1.6

1.6

1.6

1.6

1.6

1.6

2.5

C661

0.01

DIGITAL AUDIO PROCESSOR

4.7

3.233.2

R692

2.2k

k
1

100

605

604

R

R

1.6

1.6

1.7

1.6

IC612

CXD9742Q

IC B/D

4.7k
1
69

R

R687

1k

0

0

10

10

606

607

R

R

C609

0.1

C612

10

1.6

C616

0.1

C626

0.01

3.3

2.9

2.9

3.2

3.3

0

0

0

0

4.8

C646

0.01

R642

100

C666

3.3

1.6

0.01

1

2.6

0

1

0

1.7

1.7

3.3

1.6

100

611
R

5.6k

R616

C637

0.01

C652

220

4V

C668

0.01

100

R672

2.6

C673

R698

10k

C679

0.01

0.01

0.1

0.01

4

C63

627

33k

C

614
R

R615

4.7k

R623

100

R629

100

R995

4.7k

L602

FL606

0UH

C667

10

220

R673

220

R674

220

R675

220

R676

220

R677

C664

C671

10

0.01

FL607

0UH

R637

2.2k

C632

15p

C629

X601

15p 1k

13.9MHz

R655
R658

R659
R662
R664

R666

R688

0

C611

0.01

IC B/D

00000000000

000

0

0

C641

0.01

C644

0.01

C653

R645

0.01

1M

C650

R740

0.01
R689

R648

33

10k

100
100

33
100
100

100

100

R667

3.3

C647

0.01

2.6

1.6

2.6

1.6
0

1.6

1.7

3.3

1.7
0

1.7

1.6

1.6
0
0
0
0

2.5

2.5
1

R996

4.7k

R997

4.7k

R679 R680

100 100

000

3.3

R994

4.7k

R634

1k

2.5

3.304.700000003.3000002.500000000

18

SIGNAL PROCESSOR

3.304.704.602.6

C670

0.01

R898

10k

IC604

IS61LV6416 -10TLT

0

IC607

CXD9718BQ

DIGITAL AUDIO

3.3

3.3

3.3

3.3

3.3

C672

3.300000000

00000

635
C

0.01

40
C6

42
6
C

3.3

R678R998

0.01

3.3

1

0.0

1

0.0

0

3.302.6

4.7k4.7k

000

C669

0.01

0

S-RAM

C617

0.1

C613

10

0

FL604

0UH

0
0
0
0

0
0
0
0

3.3
0
0
0
0

2.6

2.7
0
0
0
0
0

FL603

0UH

C643

C674

220

10

4V

C651

0.01

C660

0.01

R663

100

100

671
R

47

HCD-SR4W

NO MARK : DVD STOP

48

4646

HCD-SR4W

6-19. SCHEMATIC DIAGRAM — DMB08 BOARD (7/10) —

FL605

0UH

C638

0.1

3.3

5

REG

IC605

NJM2391DL1

-26(TE1)

46

2.5

C639

0.1

• See page 75 for IC Block Diagrams.

IC B/D

C630

10

10V

R621

R622

R624

D/A CONVERTER

L601

C631

0.1

100

100

100

1.6

1.6

0

1.7

4.7

4.7

4.7

3.8

3.3

3.3

1.6

3.3

1.5

2.5

A/D CONVERTER

IC609

PCM1802DBR

IC608

AK4381VT-E2

5

2.5

2.5

IC601

10

C600

0.1

C602C607

1000.1

L600

2.1

2.1

2.1

2.1

2.1

C615

4.8

2.5

C657

0.1

R590

0.1

C614

C625

C618

C655

6.3V

C610

47

6.3V

C619

0.1

1 50V
1 50V

10 16V

10 16V

C622

1k

0.1

C620

R739

4.7k

R683

2.2k

100

R626

1k

1k

R657

R609

470

603
IC

2904V(TE2)
JM

N

R601

R630

LOW-PASS FILTER

R610

4.4

3.1

3.1

10

4.4

3.1

470

0

R599

0

R627

2.2k

2.2k

C628

R612

C624

R613

0.1

4.7k

0.1

R618

4.7k

633
C

3.1

C552

0.1

10

47k

16V

R619

47k

12

IC601

REG

C601

0.1

HCD-SR4W

IC B/D

NO MARK : DVD STOP

48

4747

HCD-SR4W

6-20. SCHEMATIC DIAGRAM — DMB08 BOARD (8/10) — • See page 70 for Waveform. • See page 78 for IC Block Diagram. • See page 100 for IC Pin Function Description.

CN900

46

Q908

DTC124EKA

2.7

Q903

2SC2712-GL-TE85L

3.2

8P

C928

0.1

10k

R949

C916

0.1

X901

R932

R685

20MHz

10k

10k

R991

10k

Q900

DTA114EKA

-T146

SWITCH

JW903

0

4.8

4.7

0

INVERTER

0

R955

10k

D903

1SS355TE-17

R957

10k

k
0

0

1

9

9

5

3

9

9

R

R

4.6

4.6

4.6

4.7

4.6

4.6

4.7

4.7

4.8
0

R929

8.2k

3.3

1.5

1.5

17

4.7

4.7

4.9

4.7

4.6

4.7

4.7
6

4.7

500

4.804.7

R899

10k

R951

10k

k

k

0

0

1

1
8

9

0

0

9

9
R

R

4.7

4.7

4.7

5.100.1000054.6

4.7

4.804.7

1

0
0

.0
0

1
7

3

6

1

9

9
C

R

4.8

0
0
1

8
6
9
R

k

k

.2

.2

2

2

2

1

1

1

9

9

R

R

IC901

uPD703033BYGF-M59-3BA-A

SYSTEM CONTROLLER

4.704.7

4.7

k

0

.3

0

3

1
6

6

2

3

9

9

R

R

k
.2

2
3

1
9
R

4.7

4.704.740

4.8

4.7

4.204.4

k

k

0
0

.2

.2

1

2

2

6

4

5

C901

0.01

4.604.8

k
0
1

2
6
9
R

1

1

1

9

9

9

R

R

R

2
0
9
P
T

4.1

4.1

4.7

4.1

4.804.8

1

k

k

0

0

.0

1

0

1

0

1

4

6

6

1

9

9

9

R

C

R

TP904

TP905

R917

R918

820

820

0

0

0

0

1

1
0

0

R906

0
9

W
J

1
0
9
P
T

4.6

4.6

4.8

3.2

R907

1
9

3.3k

3.3k

R

0
0
0

4.7

4.7

4.7

2.2

4.7

4.6

3.1
5

4.7

3.3

4.8
0
0

4.8

4.8

4.8

4.8

R941

10k

R942

R943

TP903

DTC124EKA

R922

R971

10k

R896

47k

R933

4.7k

2.2k

R919

TP900

R944

10k

C905

330p

C906

10k

330p

10k

C907

0.001

Q908 - Q910

-T146

Q909

-T146

ENABLE
SWITCH

0

2.7
0 0

R992

10k

Q910

-T146

4.7

100

R900

100

R902

10k

R954

R904

100

C900

3.3
5
0
0
0
0

TC74HCT7007AF (EL)

0.1

IC900

FB901

0UH

5
0
0

R901

100

3.3
5

R903

100

0
0

R905

100

LEVEL SHIFT

DIAT_SCOD

IC7004

SN74AHC1G08DCKR

5

5

*

R894

10k

4

IC7004

CSOD

5

1

*

2

3

INVERTER

10k

R945

47k

Q901

2SC2412K-T

4.8

-146-QR

RESET SWITCH

4.7

D902

1SS355TE-17

C909

RESET SIGNAL

0.22

R950

47k

GENERATOR

16V

R964
100k

0

IC907

PST3645NR

C932

0.1

IC B/D

D907

1SS355TE-17

5
5
0

47

FB902

0UH

C927

0.1

C925

0.1

R931

1k

D900

1SR154-400TE-25

D901

1SR154-400TE-25

C911

C910C912

47

0.22

6.3V

R972
10k

R990

2.2k

R895
10k

C926

0.1

5.5V476.3V

HCD-SR4W

Q902

DTA114EKA-T146

MUTING CONTROL

R897
10k

4.8

4.6

0

R963

*2 R981
10K : HK,SP,TW
15K : AUS,EA

1.5K: RU,MX,E41
NO MOUNT : AEP,UK,KR,CH

R981

*2

*1 R963

10K : AEP,UK,KR,CH,MX,E41
47K : AUS,EA

1.5K: RU
NO MOUNT : HK, SP,TW

R935

*1

10K

KEY INPUT

DETECT

4.7

IC903D904

4.74.7

PST3241NL1SS355TE-17

NO MARK : DVD STOP

C922

0.1

R979

47k

Q913

2SA1037AK

-T146-QR

DISC INSERT

DETECT

R987

C917

0.1

47k

2SC2712-GL

Q906, Q907

SIRCS DETECT

-TE85L

00

Q907

R989

0

C918
100p

R980

47k

4.8

R978

1k

0

R977

22k

R986

47k

0.74.8

R985
470k

Q906

2SC2712-GL

-TE85L

4848

6-21. SCHEMATIC DIAGRAM — DMB08 BOARD (9/10) — • See page 70 for Waveforms. • See page 72 for IC Block Diagrams. • See page 81 for IC Pin Function Description.

R232

R248

R250

C201

4.7k

4.7k

220

R249

4V

4.7k

1.600

00*0*

3.3

33

C235

0.01
B

R246

4.7k

4.7k

R245

3.3

0

0

0

000

2.7

FB202

0UH

R238

100

R252

4.7k

4

4.1

3.2

4.7k

R253

0

R202

IC B/D

R239
47k

0

3.3

Q302

DTC114EKA

-T146

INVERTER

CL206

XX

EEPROM

BR9040F

3

3.3

3.3

3.3

B

IC203

C203

0.01

3.3

0
0

R243

FL204

(2012)

C243

0.01
B

C246

0.01
B

C259

0.01
B

C250

0.01
B

R242

10k

1k

1k

R241

R230

33

0UH

CL803

C264

10

2.4

R233

10k

3.3

3.3
0
0
0
0

1.8
0
0
0
0

3.2

5.1

3.2

5.1

2.3

3.1

R226

3.1

4.7k

0
0

R247

0

4.7k

5.1
0

3.1

C255

0.01

3.2

B

3.2

3.3

0.2

CL201

3.2

CL202
CL203

3.2

3.2

CL204

0.1

CL205

4.7

1.8

R229

33

0
0

C261

0.01
B

C265

0.01
B

C266

0.01
B

R231

0

C228

0.01
B

C225

0.1

FB201

0UH

3.3

3.3

1.8

*

*

3.3

2.702.7

0.01
B

1/16W

R203

180

0.5%

3.3

1.3

*

3.3

C268C267

0.01
B

75

0UH

R236

1k

C236

0.01
B

0.5%

R257

R262

0

C229

R206

1.3

3.3

3.3

0.4

11 12 13 14

DVD SYSTEM

PROCESSOR

IC206

ZIVA5X-C2F

2.7

3.2

3.2

3.2

3.2

R244

R256

4.7k

4.7k

75

75

0UH

75

0UH

75

75

0UH

75

0UH

75

75

R207

R263

R258

R208

R259

R264

B

B

B

C230

0.01

3.3

3.2

C231

0.01

0.01

0.4

3.3

0.7

3.3

3.2

1.8

3.3

0.1

C271

C269

0.01

0.01

B

B

75

R210

R260

R209

R261

R234

R265

R266

C233

0.01

B

C232

0.01

0.7

3.3

0.9

3.3

3.2

15

0.1

0.8

0.4

1.1

1.2

1.1

0.6

0.4

33

33

33

33

33

33

33

R215

R216

33

R217

R218

R219

R220

R221

R222

C237

0.01
B

B

3.300

C240

0.01
B

3.3

0.5

0.2

0.3

0.8

C241

3.3

0.01
B

0.4

0.3

0.3

0.4

0.3

0.5

0.3

0.8

0.6

C247

3.2

0.01
B

0.4

1.2

0.5
1

0.7

1.8

0.7

0.8

0.7

0.5

3.3

0.4

0.5
1

0.7

1.2

0.6

0.4

0.9

0.6

3.3

0.4

0.5

0.6

0.9

0.8

1.8

3.3

2.9

3

0.2

3.3

2.1

0.2

C270

33

33

33

0.01
B

R223

R225

R224

3

2.3

1.1

2.5

R227 R228

33 33

C252

0.01
B

C260

0.01
B

R212

22

C262

0.01
B

C251

0.01
B

FL202

0UH

(2012)

1k

R255

128Mbit SD-RAM

C234

0.01
B

C239

0.01
B

C219

0.01
B

C217

0.01
B

C242

0.01
B

C245

0.01
B

C254

10

FL203

0UH

(2012)

HCD-SR4W

IC202

HY57V283220T6

3.3

0.8

3.3

0.9

0.6

0.5

0.6

3.3

0.9

0.4

0.6

3.3

0.4

2.9
3
3

2.5

0.2

1.1

2.3

2.1

0.4

0.4

0.6

0.4

3.3

0.7

1

0.5

3.3

1.2

0.6

0.8

0.3

3.3

0.5

3.3

C249

0.01
B

B

C253

0.01

CL801

C257

C258

0.01

10

B

MBM29PL32BM90TN

0
0
0
0

3.2
0
0
0
0
0

3.2

R213

0

3.3
0

3.3

3.3
0
0

3.2

3.2

3.2

3.2

3.2
0
0

0.7

0.8

0.7

3.3

0.5

0.5

1

0.7

3.3

1.2

C226

0.01
B

C238

0.01
B

0.4

1.8
3

0.1

0.1

0.8

0.4

1.1

1.2

1.0

0.4

0.5

3.3

0.2

0.3

0.8

0.3

3.3

0.3

0.4

C244

0.01 B

C248

0.01 B

0.3

C204

0.01
B

IC205

FR

0

3.3
0
0
0

*
*

0

2.7

*
*

C263

3.3

0.01 B

0
0

2.7

2.7
0

*

0

2.7

3.2

3.2
0

HCD-SR4W

IC B/D

BUS INTERFACE

C314 C315

0.01 0.01

*

2.7*2.703.3*2.7*000

3.2

3.2

C356

0.01

000

3.2

3.2

3.3

3.2

C274

0.01

2.70*0*03.300

IC215

SN74ALVTH16841

0000000

3.2

4949

PROGRAMMABLE ROM

C319

33p

0

*

000

3.3

0.01

C355

NO MARK : DVD STOP

HCD-SR4W

6-22. SCHEMATIC DIAGRAM — DMB08 BOARD (10/10) —

TP001

R024

TP002
TP003
TP004

TP005

TP006
TP007

TP008

TP009

TP010

TP011
TP012
TP013

TP014

TP015
TP016
TP017

TP019

58

CN002

29P

CN003

15P

59

TP020

TP104

TP021

TP022

TP038

TP048

TP018
TP105

TP076

TP023

TP024
TP025

TP026

TP027

TP028
TP029

TP067

0

R022

0

FB001

0UH

R068

100

R030

R064

1k

FB004

0UH

R043

1k

100

DIAT TRANSMIT BOARD

CN801

Y

(Page 63)

1XRST

2SCLK

3XLAT

4SDATA

5DGND

6D2

7BCKO

8LRCKO

9DGND

10CSOD

11DGND

TP036
TP035
TP034
TP033

TP032
TP031

TP030

CN001

9P

DGND

CN010
11P

XRST

XLAT

CSOD

53

k

k

k

k

1

1

1

1

R097

3

R035

R892

5

*

R050
R075

C903

0.1

IC904

TC7W34FUTE12R

0
0

3.3

C019

0.1

100

4.9

4.9

3.3

IC904

BUFFER

4.9

3.3

R890

100

REG

C018

0.1

REG

REG

IC005

3

5

IC004

5

C016 C014

0.1 0.1

6.2

C015C017

0.10.1

IC006

1.8

C020

220

4V

1k

470

R038

470

R040

470

R042

470

R044

470

R045

470

R046

470

R033

470

R027

100

R048

100

R049R891

100100

R101

0

8

9

0

0

9

9

1

1

0

0

R

R

R

R

TP037

TP039

TP040
TP041

TP042

TP043

TP044

TP077
TP045
TP046
TP047

TP049
TP052

k
1

R104

2

1k

10

1k

R

k

k

0

0

1

1

3

7

R072

7

7

0

0

10k

R

R

R087

0

R088

0

R089

0

R091

0

R090

0

C021

0.01

CN007

CN004

17P

53

7P

38

CN005

15P

61

TP062
TP061
TP060

TP059
TP058

TP057
TP056
TP055
TP054

TP053

TP050

FB005

REG

FB006

0UH

0UH

C022

100

4V

IC001

3.3

C008

5

C010

C001

100

6.3V

0.1

IC002

5

0.1

REG

6.2

C011

0.1

FB014

FL006

0UH

0UH

C003
100

FB013

0UH

C005

220 4V

FL005

PWR-EMIS

C004

47
16V

FB010

100 16V

FL004

0UH

0UH

FB011FB012

0UH0UH

FL003

FB007FB008

0UH

C006

FB009

0UH

0UH0UH

CN008

TP063

TP065
TP064

R019

TP066
TP068

2.2k

TP070

TP072
TP071

R059

TP073

0

TP051

12P

NO MARK : DVD STOP

HCD-SR4W

5050

HCD-SR4W

6-23. PRINTED WIRING BOARD — AMP BOARD (SIDE A) —

12

A

B

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

34567

C

D

E

IC110

R146

R138

IC305

IC108

IC101IC102IC105IC106IC107

IC301

IC303

22

(22)

• Semiconductor
Location

Ref. No.

IC101 D-6
IC102 D-5
IC105 D-3
IC106 D-2
IC107 D-1
IC108 E-4
IC110 E-2
IC301 E-6
IC303 C-7
IC305 E-5

Q102 B-6
Q104 B-7
Q110 B-3
Q112 B-3
Q114 B-1
Q301 E-1
Q304 C-1

Location

HCD-SR4W

F

5151

HCD-SR4W

6-24. PRINTED WIRING BOARD — AMP BOARD (SIDE B) —

12

A

B

SWITCHING

REGULATOR

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

345678

K

DIAT SPK

BOARD

CN312

(Page 64)

I

DIAT SPK

BOARD

CN309

(Page 64)

FAN

C

D

E

F

SWITCHING

REGULATOR

H

HP BOARD

CN811

(Page 68)

• Semiconductor
Location

Ref. No.

D101 D-2
D102 D-3
D105 D-5
D106 D-6

L301

1

2

16

17

22

(22)

D107 D-7
D201 D-3
D202 D-3
D205 D-6
D206 D-7
D207 D-7
D208 E-2
D303 D-7
D304 D-7

Q101 B-2
Q103 B-2
Q109 B-6
Q111 B-5
Q113 B-7
Q303 C-7

Location

HCD-SR4W

DMB08
BOARD

C B

CN004

(Page 39)

DMB08
BOARD

CN001

(Page 39)

5252

6-25. SCHEMATIC DIAGRAM — AMP BOARD (1/4) — • See page 70 for Waveform.

CN301

17P

50

TP343

TP342

TP395

TP301
TP302
TP303

TP304
TP305
TP306

TP307
TP308
TP309

TP310

TP361

TP312

TP360

R308

R306

R305
R304

R303

R302
R351
R300

R309

470 1/10W

470 1/10W

470 1/10W
470 1/10W

470 1/10W

470 1/10W
470 1/10W
470 1/10W

0

C402
100p

50V

HCD-SR4W

R345

10k 1/10W

R347
10k

0.1 25V

C323

0.1
25VF560

R380

1/10W

1/10W

C336

16V

R379

C335

47

C337

47

16V

560

47

16V

54

SL303

C325

0.1
25V

F

21

TP331

R317

470 1/10W

R316

470 1/10W

C326

0.1
25V

F

3.3

033.3

3.3

3.3

3.3

1.7

3.3

3.3

1.7

0.4

C324

3.3

1.7

R326

C327

1.7
0
0

0.1
25V

F

0

3.3

0

1.8

STREAM PROCESSOR

IC110

CXD9788AR

1.7

3.3

1.7

1.7

C328

0.1
25V

F

R319

10k

1/10W

R328

C405

0.001
50V

C404C403

B

100p

100p

CH

50V

50V

CH

CH

1.7

0

3.3

3.3

3.3

1.7

C321C320

0.1

0.1

25V

25V

F

F

SL302

C322

0.1
25V

R329

0

F

HCD-SR4W

TP314

TP315
TP316
TP317
TP318

TP368
TP319

C406

0.0047

R310
R311

R312
R313

R314

R315

100 1/10W
100 1/10W

100 1/10W
100 1/10W

100 1/10W

33 1/10W

CN302

9P

50

R138

0

R325

0

NO MARK : DVD STOP

55

5353

HCD-SR4W

6-26. SCHEMATIC DIAGRAM — AMP BOARD (2/4) —

R383R384

560560

R382

560

1/10W

R381

560

53

C178

47p
50V
CH

22k

R119

R176

0

C200

0.1 25V F

R166

0

C146

0.1
25V

R156

F

R146

C136

0.01

R136

0

25V

B

R237

100

R118

R117

C145 R165

0.1
25V

F

R235

100

0

R135

C168

47p 50 V CH

R116

R246
100

1/10W

22k

22k

R175

C199

0.1
25V

F

0

R155

0

R145

C135 C165

0.01
25V

B

1/10W

22k

R245

R239

100

C137

0.01 25V B

R247

IC106

CXD9774M

1.7

3.2

0

0

0

0

0

0

0

3.3

3.3

3.3

1.7

IC105

CXD9774M

1.7

3.2

0

0

0

0

3.3

0

0

3.3

3.3

3.3

100

1.7

12

POWER DRIVE

12

0

15

15

7.9

7.9

7.9

C271

7.9

0.22

15

15

0

12

12

POWER DRIVE

12

12

0

15

15

7.9

7.9

7.9

C209

7.9

0.22

15

15

0

12

12

C116

C186

0.033 50V B

C272

0.22 50V B

C176

0.22 50V B

C166

0.22
50V

50V

B

B

C156

0.033 50V B

C115

C185

0.033 50V B

C210

0.22 50V B

0.22 50V B

0.22
50V

50V

B

B

C155

0.033 50V B

C105

1 16V F

1 16V F

1 16V F

R206

3.3

1/4W

R196

3.3

1/4W

C106

1 16V F

1 16V F

R205

1/4W

R195

3.3

1/4W

C114

R128

22k

C372

1 50V

R139

C385

2.2
16V

F
V

16
1

7
10

C

12

C197
2200

35V

0.0022 50V B

0

F

12

1.7

C157

0.033
50V

TP390

B

C293

0.0022

C255

0.0022

C265

50V

B

50V

B

R431
100k

1/10W

1SS355TE-17

D303

1SS355TE-17

0.0022 50V B

0.0022 50V B

0.0022 50V B

0.0022 50V B

0.0022

0.0022

D304

C292

C266

2.7 1/8W

R216

2.7 1/8W
C256

C291

C290C175

50V

B

R225

2.7

1/8W

R215

2.7

1/8W

C289

50V

B

R226

R430

1/10W

C377

10k

10

50V

C196
2200

35V

TP389

L136

L135

L126

L125

C226

C216

50V

50V

C225

C215

1

1

1

50V

1

50V

D206

P6SMB39AT3

D106

P6SMB39AT3

3.3

D205

P6SMB39AT3

TP388

D105

P6SMB39AT3

C195
2200

35V

4.9

0

C158

R395

47

100k

10V

1/10W

Q301

KTC3875

PROTECT

100

1/10W

0

0

7
47
1

137

R

R

3.3

3.3

3.3

0

15

15

7.9

7.9

C273

0.22
50V

0.22
50V

B

3.3

1/4W

D107

P6SMB39AT3

C217

1

50V

R217

2.7

1/8W

C257

0.0022
50V

B

100k

1/10W

R365
100k

1/10W

C395

2.2
16V

F

7.9 7.9

C147

0.1 25V F

0

0
7

6

5

1

1

R

R

0

3.3

0

k
2
2

C218 C180

0

0.1

12

25V

R

F

0
7

7
1
R

3.2

0

0

1.7

47p
50V

CH

POWER DRIVE

IC107

CXD9774M

0

15

15

12

C187

0.033
50V

B

C117

1

16V

F

L137L127

C294

0.0022 50V B

R366
100k

1/10W

C396

10

10V

1/10W

7.9

12

100k

Q112

2SA1602

TP-1EF

R413
100k

1/10W

R414
100k

R367

1/10W

100k

1/10W

C397

7.9

10

10V

F

7.9 0

1/10W
k

10

481
R

2SA1602

TP-1EF

0W
1/1
k

10

50
4
R

Q114

1/10W
k

10

483
R

W
/10

1

0k
1

52
4
R

TP375

1/10W

10k

84
4
R

TP374

W
0

1/1
k

10

53
4
R

TP373

/10W
1

0k
1

5
8
4
R

TP372

/10W
1

0k
1

54
4
R

1/10W
k

10
6
48

R

TP371

0W
/1

1
k

0
1

5
45

R

TP370

CN313

6P

3.95MM

DIAT SPK

BOARD

CN309

(Page 65)

W

0W
/1

1

1/10
k

0k
1

10

482

451

R

R

7.9

7.9

C274

0.22
50V

B

C177C167

B

0.22
50V

B

R207R197

3.3

1/4W

D207

P6SMB39AT3

C227

1

50V

C267

R227

0.0022

2.7

50V

1/8W

B

R410R409
100k

7.9

R411 R412
100k

1/10W

Q110

2SA1602

TP-1EF

1/10W

0 0

HCD-SR4W

C104

1 16V F

TP387

C194
2200

35V

Q109

0

2SA1602

TP-1EF

7.9 7.9

Q111

2SA1602

TP-1EF

7.97.9

0

Q113

2SA1602

TP-1EF

7.9
0

7.9

OVER LOAD DETECT

NO MARK : DVD STOP

56

5454

HCD-SR4W

6-27. SCHEMATIC DIAGRAM — AMP BOARD (3/4) —

CN300

2P

HEADPHONE AMP

TP320

TP365

TP321

TP322

TP324

CNP303

5P

69

BOARD IN

CNP305

2P

BOARD IN

TP327

CNP304

BOARD IN

TP367

TP392

TP391

TP363

TP328

TP362

4P

R343

TP396

R342

TP340

0UH

TP366

0UH

TP364

TP369

• See page 70 for Waveform.

12

C359

470
10V

C358

470
10V

C366

220
16V

C350

0.1
50V

Q303

2SB1013-TP-34

TP341

1270

IC301

RC4580IDR

R340

33k

1/10W

100p 50V CH

C356

C367

0.1
25V

F

C355

100
16V

B

0

C248

47

16V

C360C361

0.1 2 5V F47 25V

C357

100p 50V CH

33k

R341

4.8

4.8

4.8

4.8

R400
100k

1/10W

C370

C368 C374

0.01

0.1
25V

25V

B

F

R425

R426

R427

12

R428

47k

1/10W

R429

4.7k

1/10W

22k 1/10W

22k 1/10W

C354
100p

50V

C353
100p

50V

IC303

470 1/10W

560 1/10W

560 1/10W

Q303, Q304

FAN DRIVE

CNP309

R337

R336

CH

CH

22k 1/10W

22k 1/10W

3.3

TK11118CSCL-G

0

1/10W

1/10W

R335

REG

R339

R338

R334

0

24k

24k

1/10W

R350

2.7k

1.4

0

Q304

KRC103S

CNP310

R333

22k 1/10W

C352

100p 50V

R332

22k 1/10W

22k 1/10W

R331

100p 50V CH

C371

0.01
25V

B

0

R349

2.2k

1/10W

C363

0.1
25V

F

C351

R330

22k 1/10W

C375

100
16V

10V

100

C362

0.01

53

SL301

C308

0.1
25V

3.3

1.8

1.7

3.3

C302

0.1
25V

3.3

IC305

MC74VHC1GU04DFT1

C384

5p

50V

B

CH

F

1.7

3.3

F

R393

22

1.5

R348

470

1/10W

C309

R323

C310

0.1 25V F

R322

10k

1/10W

TP330

0.1 2 5V F

0

R346

470 1/10W

3.3

0.4

1.7

0

0

3.3

0

1.8

1.7

R320

3.3

033.3

3.3

3.3

3.3

STREAM PROCESSOR

IC108

CXD9788AR

1.7

1.7

1.7

1.7

3.3

1.7

C301

F

25V

0.1

R321

0

0

FB301

0UH

L301

10UH

OSC

C380

220

25V

B

10V

C381

0.01
25V

C306

0.1
25V

F

C305

0.1
25V

C304

0.1
25V

C383

C331

47

16V

F

R373

R372

R371

560

1/10W

F

C329

16V

R374

560 1/10W

C330

47

16V

560

560

47

56

21

1.7

3.3

1.7

1.7

3.3

1.7

1.5

C303

0.1
25V

F

TP325

C382

0.001 50V B

1.5

20

1/10W

R396

100

1M

1/10W

R394

X450

49.152MHZ

L302

10p 50V CH

HCD-SR4W

NO MARK : DVD STOP

5555

HCD-SR4W

6-28. SCHEMATIC DIAGRAM — AMP BOARD (4/4) —

C113

1 16V F

54

TP386

R229

100

R242

1/10W

C103

C182

0.033 50V B

C204

0.22 50V B

C172

0.22 50V B

C203

C162

0.22

0.22
50V

50V

B

B

C152

0.033 50V B

1 16V F

R192

1/4W

3.3

R202

3.3

1/4W

POWER DRIVER

R111

22k

C148

47p
50V

CH

R172

0

0.1 25V F

R162

C142

100

0

0.1
25V

F

R132

C132

0.01

R152

R142

0

25V

B

C189

1.7

3.2

3.3

0

3.3

3.3

0

3.3

1.7

IC102

CXD9774M

12

12

0

0

0

0

15

15

7.9

7.9

0

7.9

7.9

15

15

0

12

C112

C193
2200

35V

Q102

2SA1602

1

16V

F

TP385

D102

P6SMB39AT3

D202

P6SMB39AT3

L132

L122

C222

50V

C212

C284

0.0022
50V

C262

1

0.0022

1

50V

50V

B

R212

1/8W

2.7

C283

0.0022
50V

B

R222

2.7

1/8W

C252

0.0022
50V

B

B

TP-1EF

0

0 0

Q101

2SA1602

TP-1EF

R401
100k

1/10W

7.9

7.9

OVER LOAD DETECT

7.9

7.9

C391

2.2
16V

2SA1602

F

R361

R402

100k

100k

1/10W

1/10W

Q103

TP-1EF

Q104

2SA1602

TP-1EF

7.9

0

R403
100k

1/10W

7.9

V

W

1/10

7.9

k

C392

2.2

7.9

16V

R362
100k

1/10W

10

56
R4

F

R404
100k

1/10W

1/10W

0k
1

487
R

1/10

1/10

1/10

k

0k

10

1

10k

89

488

457
R

R4

R

W

W

W

V

W

1/10W

1/10

1/10W
k

0k

10k

1

10

59

458

490

R4

R

R

50

0.001

C275

50V

0.001

276
C

50V

0.001

277
C

50

1

0.00

278
C

TP382

TP380

TP383

TP381

CN306

4P

EH-S

2.5MM

DIAT SPK

BOARD
CN312

(Page 65)

12

R110

22k

IC101

R109

22k

R171

0

R161

R131

0.1 25V F

0

R151

R141

0

C188

0

0

55

C141

0.1 25V F

100

R129

R241

100

1/10W

C131

0.01 25V B

R108

22k

CXD9774M

12

1.7

3.2

0

0

0

3.3

12

0

15

15

C202

7.9

0.22
50V

7.9

0

3.3

3.3

3.3

7.9

C201

7.9

0.22

15

15

0

C151

0.033 50V B

1.7

12

12

C138

47p 50 V CH

1 16V F

1 16V F

POWER DRIVER

C181

0.033 50V B

C171

0.22
50V

B

B

C161

0.22
50V

50V

B

B

10k

494
R

C101

C102

R201

3.3

1/4W

R191

3.3

1/4W

D208

MA8027-H-TX

C111

C192
2200

35V

1

16V

F

D101

P6SMB39AT3

TP384

10k

10k

10k

495

496

497

R

R

R

C191
2200

35V

L131

D201

P6SMB39AT3

L121

C211

50V

C221

50V

C282

1

R221

2.7

1/8W

R211

2.7

1

1/8W

C261

C251

C281

0.0022 50V B

0.0022 50V B

0.0022 50V B

0.0022 50V B

HCD-SR4W

NO MARK : DVD STOP

5656

HCD-SR4W

6-29. PRINTED WIRING BOARD — IO SECTION —

12

34567

A

AEP,UK,RU

IC101

B

EXCEPT
AEP,UK,RU

C

AEP,UK,RU

D

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

TUNER

UNIT

EXCEPT
AEP,UK,RU

AEP,UK,RU

IC201

EXCEPT
AEP,UK,RU

F

DMB08
BOARD
CN003

(Page 39)

EXCEPT
AEP,UK,RU

AEP,UK,RU

IC603

8 910

AEP,UK,RU

OPTICAL

DIGITAL

IN

EXCEPT
AEP,UK,RU

VIDEO

4

3
1

2

PR/C

S VIDEO

(DVD ONLY)

R

COMPONENT

VIDEO OUT

PB/C

B

Y

MONITOR

OUT

11 12

E

F

E

• Semiconductor Location

Ref. No.

D101 A-3
D201 D-2
D206 D-3

IC101 B-2
IC201 B-6

Location

Ref. No.

IC602 F-2
IC603 A-7
IC605 F-3
IC606 E-6

Q101 A-7

IC602

Location

IC605

Ref. No.

Q102 B-1
Q103 B-6
Q201 D-6
Q202 D-2
Q203 D-2
Q204 D-6

Location

E

DMB08
BOARD

CN002

(Page 39)

Ref. No.

Q205 D-3
Q206 D-2
Q604 F-6
Q605 F-6
Q606 F-3
Q607 F-6

Location

IC606

EXCEPT
AEP,UK,RU

AEP,UK,RU

L R

VIDEO

SAT

SURROUND

BACK

EURO AV

OUTPUT (TO TV)

HCD-SR4W

5757

HCD-SR4W

6-30. SCHEMATIC DIAGRAM — IO SECTION (1/2) — • See page 70 for Waveform. • See page 78, 79 for IC Block Diagrams.

C113

R123

10k

D101

R601 R118

10k 3 3k

3.5

0.1

R120

4.7k

R121
470k

R126

330

C119

0.01

C118

51p

C117

56p

R119

33k

0

4.8

Q103

2SC2412K-T-146-Q

DET AMP

1.4

5.3

R122

0.8

1k

C120

100
16V

UDZSTE-175.1B

5

1.9

2.5

X101

4.332MHz

2.5

27

RDS DECODER

C114
330p

R125

68k

C115
560p

C116

10
50V

R124

47k

IC101

BU1924F-E2

2.7
0

5.1

0.9

2.7

2.5

IC B/D

R621

R633

1.5k

R634

C626

R645

22 25V

1.5k

R635

6.8k

R636

6.8k

0.1

100

C627

R631C612R632 C611

47k220p

47k 220p

50V

R638

6.8k

L602

C610

R630

220p

50V

R639R637

47k6.8k

R629

47k

50V

C614C613

R640

220p220p

47k

C643

220p

J601

4P

C624

1000p

C623
220p

IC603

IC603

OPTICAL RECEIVER

TORX141L

3.3

0.2

J201

3P

J602

1P

10k

06
6

IC

C634

22

25V

R
ID

0
8
5
4
C
R

C633
100p

R649

R602

10k

R603

100

0

Q605

DTC124EK-T146

DTC124EK-T146

C636
220p

1043.5

4

4

R657

33k

Q604, Q605

INVERTER

4.8

Q604

4

10k

C605

22 25V

C606

22 25V

C607

22 25V

C608

22 25V
C609
220p

47k

50V

R622

R624

10k

10k

R623
10k

10555550

R628

R627 R626

10k 10k

R625

10k

10k

.1

IC602

0

C604

100
16V

MC14052 BDR2

3
0
6
C

R604

100

0

55555

C615

22 25V

C616

22

25V

R643R641

10k10k

R644

R642

10k

10k

DTC343TK-T-146

0

C635

0.01

0

0

DTC343TK-T-146

Q606, Q607

MUTE DRIVE

Q607

Q606

R656

47k

INVERTER

R605
100

IC B/D

AMP

0

0

0

1k

R650

R659

1k

CN102

11P

C101

3300p

R103

C102

3300p

C105 C106

6.9

0.9

R113

6.8k

R117

33k

0k

0k

1

1

7

53

4

6

6
R

R

.1
0

1
3
6
C

11

R107
470k

1.5

Q102

2SC2412K

-T-146-QR

AMP AMP

L601

C112

22

25V

R607

1k

C646
220p

R651

4.7k

C637

C625

22

25V

22 25V

1.5

Q101

2SC2412K

-T-146-QR

R608

1k

CONVERTER

P

-T

05

9FP

6

2

IC

4
2
6

M

C109, C110

0.015 : HK,SP

0.018 : EXCEPT HK,SP

0

R106

C107

22

R110

25V

220

R111

220

C111

k
3

22

3

25V

6
11

R

R661

220

R654

220

R655

2.2k

V

p

6

k

1

20

0

2

10k1

0
0

8

1

8

4

52

2

6

6

6

R

C

R

32
6
C

R109

R108

6.9

470k

C108

22

25V

0.9

R112

6.8k

R114

33k

C109

C110

R115

33k

IC B/D

C638

5

0

100p

0

0

C645
100p

R664

4.7k

C103

220

16V

L101

R128

0

R609

10k

R610

10k

.1

C639

0

100

9

16V

62
C

D206

1SS355TE-17

C202

100
16V

0

R101

0

TP101

TP102
TP103
TP104
TP105
TP106

TP107
TP601
TP602

TP603
TP604
TP201
TP605

TP606
TP607
TP608
TP609
TP610

TP611

TP612
TP613

TP614

TP615

TP616

TP617

CN601

29P

0p
0

10
2

1
2
C

50

HCD-SR4W

NO MARK : DVD STOP

59

5858

6-31. SCHEMATIC DIAGRAM — IO SECTION (2/2) — • See page 70 for Waveforms. • See page 79 for IC Block Diagram.

R227

R228

R226

R225

R229

R230

75

75

75

75

75

75

0.001

J202

2P

C230

R224

10k

C234

0.1
C235

1000 6.3V

C238

1000 6.3V

C239

1000 6.3V

C240

1000 6.3V

C241

1000 6.3V

HCD-SR4W

58

TP202
TP203

IC B/D

VIDEO AMP, 75 ohm DRIVER

23

5

22

0

2.4
0

1.5

1.1

2.4

2.3

2.4

25

24

26

R235

5

2.3

4.8

1.7
5

1.5

0
0

2.3

3.5

2.3

4.8

2.3

C225

10k

0.1

C229

0.1

R234

10k

IC201

MM1623BFBE

L209

C224

100
16V

C218
100p

50V

C227

22

25V

C217

0.1

C278

10 50V

C216

10

50V

R203

1k

C222C223

1 10V1 10V

C221

1 10V

TP204
TP205

TP206
TP207
TP208

TP209

L214

0

TP210

R204

TP211
TP212

TP213

1k

CN201

15P

50

Q205

11.4

DTA114EKA-T146

R213

2.2k

R212

3.3k

R211

2.2k

R214

1k

R216

330

R217

330

R218

CNP205 CN205

10P 10P

C231

J203

21P

0.001

330

R219

330

11.4

DTA114EKA-T146

10.5

R215

22k

Q204

Q206

DTA114EKA-T146

0

11.4

0

Q203

DTA114EKA-T146

D201

1SS355TE-17

4.5
5

0

5

Q202

DTA114EKA-T146

0

Q201 - Q203

BLANKOUT SWITCH

R208

47k

0

R202

1k

4.8

R210
220k

Q201

DTC114EKA-T146

NO MARK : DVD STOP

HCD-SR4W

5959

HCD-SR4W

6-32. PRINTED WIRING BOARD — DDCON BOARD —

12

A

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

34567

O

FL

BOARD

CN803

(Page 66)

B

C

D

D

15

14

DMB08
BOARD

CN005

(Page 39)

• Semiconductor
Location

Ref. No.

D810 C-5
D811 C-5
D813 C-5
D814 C-5
D815 C-3

Location

HCD-SR4W

Q802 C-6

6060

HCD-SR4W

6-33. SCHEMATIC DIAGRAM — DDCON BOARD —

CN800

15P

50

• See page 70 for Waveform.

R804

R815

JW

L807

L806

L805

FB806

0UH

0UH

0

R811

JW

R850

3.9k

C818

100
10V

TP835

TP838

TP839

TP840

TP841

TP842

TP843

TP844

TP845

TP846

TP847

TP848

TP849

TP850

TP851

FB808

CN801

17P

R806

TP867

TP866

0

0UH

FB001

0UH

FB002

0UH

FB003

67

L804

19

OSC

0.1

0.1

C830

0.022
50V

5

5

Q802

CPH5504-TL-E

T801

DC-DC CONVERTER

D814

1SS355TE-17

D810

1SS355TE-17

D813

1SS355TE-17

D811

1SS355TE-17

C835

0.01
50V

C836

50V

10

R839

33k

D815

UDZSTE-176.2B

R841

100

C837

0.1
16V

HCD-SR4W

NO MARK : DVD STOP

6161

HCD-SR4W

6-34. PRINTED WIRING BOARD — DIAT TRANSMIT BOARD —

1 2 3 4 5 6 7 8

A

B

C

Y

DMB08
BOARD
CN010

D

E

(Page 39)

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

14

R833

R803

L802

C817

IC802

L805

C850

(SIDE A)

FB801

C802

C801

FB802

L803

C851

C808

R831

R835

D800

L807

C830

C828

R836

C832

33

C833

R816

48

R823

C824

L801

C840

C838

C844

R822

R827

R821

IC804

C820

X801

R826

C819

C806

R802

1732

6449

C837

64

13

C810

L809

C846

16

C834

R815

1

R812

C811

R810

IC801

L804

R830

R829

Q801

R811

E

C816

L808

C823

L806

R813

C825

R814

C818 C839

R824

TP815

(RF AMP OUT)

DIAT TRANSMIT BOARD

C815

R809

C814

C813

8

R805

R834

8

R806

R832

IC803

R807

R808

14

R804

17

17

C809

CN801

JR801

JR806

JR804

JR805

C807

JR803

JR802

C822

C842

C831

C829

C827

C848

R818

C861

RV801

C835

31

45
R825

L811

C836

IC805

R817

R819

R837

FB804

R820

L810

R838

C860

1-862-465-12(12)

DIAT TRANSMIT BOARD

(SIDE B)

F

G

H

I

EB801

CN802

J

(CHASSIS)

C826

1

2

X

C803

DIAT PW

BOARD

CNP812

(Page 64)

C841

C805

C845

C812

CN803

C821

1

2

C847

C849

EB802

L812

Z

DIAT SPK

BOARD

CN301

(Page 64)

• Semiconductor
Location

Ref. No.

D800 B-3
IC801 B-5

IC802 D-3

Location

IC803 C-3
IC804 C-4
IC805 E-6

Q801 C-5

(CHASSIS)

12

1-862-465-

(12)

HCD-SR4W

6262

HCD-SR4W

6-35. SCHEMATIC DIAGRAM — DIAT TRANSMIT BOARD —

FB802

L801

10µH

IN OUT

L803

10µH

10µH

L802

C850

0.1

R803

100

R805

100

16V

0.1

100

C806

C805

C809 R804
100p 100

R834R833

10k10k

10k

R802

R806

100

R835

4.7k

R836

2.7k

JR801

100

JR802

100

JR803

100

C851

0.1

C808
100p

C807
100p

X

DIAT PW

BOARD

CNP812

(Page 65)

Y

DMB08 BARD

(10/10)

CN010

(Page 50)

(CHASSIS)

CN801

EB801

VCC(9V)

P-GND

11P

D-GND

CSOD

D-GND

LRCKO

BCKO

D2 ( SL/SR)

D-GND

SDATA

XLAT

SCLK

XRST

CN802

C803

C802

100

0.1
16V

2P

FB801

C801

0.1

JR804

0

JR805

0

JR806

0

D800

1SS355TE-17

• See page 70 for Waveform. • See page 71 for IC Block Diagrams.

L804

GND

GNDCNT C NP

C810

0.1

LEVEL SHIFT

IC802

TC74VHCT08

AFT(EL)

LEVEL SHIFT

SN74LV125APWR

+2.5V

REGULATOR

IC801

TK11225CMCL-G

IC803

10µH

C812

C821

C811

100

0.1
10V

R807

100

C817
100p

R808

100

C814

C813
100p

100p

C822

100

0.1

10V

L805

10µH

C820

12p

28

X801

24.576MHz

C819

12p

R812

330

C818

0.1

R832

10k

R809

100

C815
100p

L807

10µH

C826

C828

100

0.1

10V

R815

330

C833 C834 C837C838C824

0.1 0.1 0.10.10.1

DTIN

TESTMD

DT2_INF

AUDIO

SMCK

VCOT

D

IFEXM

LRCK

BCK

BCKOUT

LRCKOUT

CK12

CSST

VSS

VDD

OSCI

VSS

OSCO

XTCK4

XSM

MST

XTST

XRST

APAVS

IIFSEL1

O

APAVD

APCP

DIAT SETUP

EXCKSEL

IIFSEL0

R816

2.2k

APS

APVGS

PLL

RF MODULATOR,

D/A CONVERTER

IC804

CXD4016R

DIVCODE

CHNM_BL

VSS

PCMID

VDD

EMPIN

0.0047

L812
10µH

L809
10µH

C832

R831C830

4.7M0.1

C845

100
10V

C844

0.1

C841

2.2
50V

C840

0.1

R821

R823

2.7k

220

R822 R827

150 150

R826 R830

150 10k

C823 R813 R814 L806 L808

0.01 220 100

C816
100p

R829

15k

Q801

10µH

2SC2712G-TE85L

BUFFER

C831C829C827C825R811
100p47p100p47p1k

RV801

470

C846

0.01

10µH

C839

0.1

R820

220

C836

0.1

R819

1k

C835

0.0022

R817

1k

R818

R838

1k

1k

C847

100
16V 0.1

IC805

AD8057ART-REEL7

RF AMP

C861

R825

10k

R824

470

C842
220p

PLVAR

VSS

PLREF

SCLK

CPUIF

TEST7

XSCEN

RF DAC

TEST6

DT

SW

TEST5

DAVRO

DAVREF

DAAVS

DAAVD

DAAOUT

CSOD

R810

TEST4

TEST3

TEST2

TEST1

TEST0

100

VSS

VDD

VSS

VDD

DACK

DAPD

APX

VDD

R837

33

C860

0.1

L810
10µH

(RF AMP OUT)

FB804

C849

100
16V

TP815

C848

0.01 2P

L811

47µH

CN803

EB802

(CHASSIS)

Z

DIAT SPK

BOARD
CN301

(Page 65)

NO MARK : DVD STOP

HCD-SR4W

6363

HCD-SR4W

6-36. PRINTED WIRING BOARD — SPEAKER OUT SECTION —

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

DIAT TRANSMIT BOARD

SWITCHING

REGULATOR

CNP811

CNP812

X

CN802

(Page 62)

IC900

HCD-SR4W

FRONT R

WOOFER

K

AMP BOARD

CN306

(Page 52)

SPEAKER

FRONT LCENTER

WOOFER

I

AMP BOARD

CN313

(Page 52)

WIRELESS

SPEAKER

DIAT TRANSMIT

Z

BOARD
CN803

(Page 62)

6464

6-37. SCHEMATIC DIAGRAM — SPEAKER OUT SECTION —

IC900

KIA7809API

CNP811

2P

C902

0.1
25V

C901
1000

16V

R900

2.2k

16V

L903

R901

47

L900

C900C904

0.11000
CNP812

2P

NO MARK : DVD STOP

63

56

CN312

4P

TP336

50V

0.001

C340

C344

TP337

50V

0.001

C341

0.001 50V

TP338

50V

0.001

C342

TP339

C343

0.001
50V

TP361

TP362

TP340

TP341

TP342

TP343

C481

0.015

0.015

C483

0.001

C484

0.001

C485

0.015

C486

0.015

C482

50V

50V

TB301

TERMINAL BOARD

C492

0.001

C491

0.001
50V

C488

0.001
50V

C487

0.001

50V

50V

TP502

TP504

TP503

TP505

HCD-SR4W

GP307

TERMINAL GND

54

63

J301

1P

CN309

6P

CN301

2P

TP501

C345

0.001 50V

TP344

TP345

TP346

TP348

TP347

TP349

TP500

C502

0.01

C500

0.01

HCD-SR4W

6565

HCD-SR4W

6-38. PRINTED WIRING BOARD — FL BOARD —

12

A

B

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

345678

CONTROL KEY

L

BOARD

CN810

(Page 68)

C

D

E

F

O

DDCON
BOARD

CN801

(Page 60)

IC803

PW KEY

BOARD

CN805

(Page 68)

M

IC801

SONY LAMP

N

BOARD

CN806

(Page 68)

• Semiconductor
Location

Ref. No.

IC801 D-7
IC803 D-5

Location

HCD-SR4W

Q810 D-7

6666

6-39. SCHEMATIC DIAGRAM — FL BOARD —

HCD-SR4W

FL801

CN812

7P

REMOTE CONTROL

RECEIVER

R828

0

IC801

NJL73H400A

4.6

C807

0.01
25V

5.0

C805

10 50V

FB807

0UH

69

5

-22.6

-20.5

-29

-29

-29

-27

-29

-31

-31

-29

-29

-29

-31

-29

-29

-27

-29

-24.8

-31

-31

-27

-31

-29

-29

-26.8

-29

-29

-31

-31

-29

IC803

CN803

17P

61

TP815
TP814
TP811
TP813

TP812
TP816
TP821
TP822

TP823
TP824
TP825
TP826
TP827

TP828
TP829
TP830
TP831

R881

R880

1k

R882

R879

R878

2.2k

2.2k1k

1k

R852

47

100

R853

100

R844

100

R851

FB005 R877

0UH 1k

R849

10k

C841

10

10V

0.6

C848

0.01

C849

0

4.8

4.7

4.7

2.1

2.2

25V

0.015

C847

3.3k

R840

10k

R843

50V

47p

C850

5.0

-31

5.0

0.1
16V

50V

50V

50V

100p

0.001

0.0022

C843

C842

C846

0

Q810

2SC1623

LED DRIVE

CNP807

3P

CNP808

2P

ML9208-03MBZ03B

-29

-29

-29

-29

FL DRIVER

-29

-29

-29

-29

-29

-29

-29

-29

-31

-29

-29

-31

-31

-31

-31

NO MARK : DVD STOP

HCD-SR4W

69

69

6767

HCD-SR4W

6-40. PRINTED WIRING BOARD — POWER/FRONT PANEL SECTION —

12

345678910111213

A

B

AC
IN

C

• See page 28 for Circuit Boards Location. :Uses unleaded solder.

SWITCHING

REGULATOR

FUNCTION

FL

BOARD

CN803

(Page 66)

VOLUME

-

+

D

E

F

G

SONY

FL

BOARD

CN808

(Page 66)

AMP

BOARD

CNP303

(Page 52)

PHONES

FL

BOARD

CNP807

(Page 66)

• Semiconductor
Location

Ref. No.

D800 G-5
D801 G-5
D802 G-9
D819 E-3
D821 D-3

Location

HCD-SR4W

Q800 F-3
Q801 F-3
Q803 G-3
Q804 G-3

6868

6-41. SCHEMATIC DIAGRAM — POWER/FRONT PANEL SECTION —

HCD-SR4W

LF901

CN900 CN901

2P

C903

0.22

CN806

2P

TP834

TP868

C863 C862

0.001 0.001

JW902

JW

JW901

JW

R847

100

D821

SML-512WBC1AR

R861 R860

2.2k 0

2P

C857

1000p

50V

R846

100

D819

SML512WBC1AR

SW. KEY

LS8J3M

C858
820p

50V

S818

TACT SW

LS8J3M

SW. KEY

LS8J3M

R868

S808S809

SW. KEY

LS8J3M

2.2k

S801

SW. KEY

LS8J3M

S816S817

SW. KEY

LS8J3M

R867

0

S815

SW. KEY

LS8J3M

C816

R875R876

22k47k

25V

0.1
25V

S807

SW. KEY

LS8J3M

C851

C852C844

0.1
25V

R874

10k

0.1
25V0.1

TP871

TP872
TP873

TP874

TP875

TP876

67

R866

4.7k

C845

0.1
25V

CN810

7P

67

Q801 - Q804

L803

DTC343TK-T-146

FB803

0UH

CN811

5P

TP818
TP819

TP820

TP817

TP837

C853

C854

47p

FB810

0UH

FB805

0UH

47p

DTC343TK-T-146

FB802

0UH

55

L802

R807

100

Q804

R805

100

Q803

MUTING

0

0

0

0

C804

0.0047

R802

100

Q801

DTC343TK-T-146

Q800

DTC343TK-T-146

R803

100

C806

0.0047

L800

C802

4.7k

0.1

R800

4.7k

0.01

C801

0.01

FB800

0UH

D801

1SS355TE-17

D800

1SS355TE-17

C800

0.001

J800

0

0

0

0

R801

C803

L801

D802

SML-512UWT86

S800

TACT SW

LS8J3M

C811

0.1

R809

TP836
TP853

CN805

0

3P

67

HCD-SR4W

NO MARK : DVD STOP

6969

HCD-SR4W

• Waveforms
– RF Board –

– DDCOM Board –

– AMP Board –

1

IC001 1 (DVDRFP)

800 mVp-p

2

IC001 el (TE)

500 mV/DIV, 1 ms/DIV

– DMB08 Board –

qa

to qg : color bars video signal

5

IC303 8 (XTO)

4.0 Vp-p

37 ns

1 V/DIV, 10 ns/DIV 1 V/DIV, 10 ns/DIV

9

IC303 3 (MO1)

4.5 Vp-p

37 ns

1 V/DIV, 10 ns/DIV

6

IC303 9 (SO1)

q;

IC301 r; (XTAL)

1 V/DIV, 20 ns/DIV

29.5 ns

50 ns

0.5 Vp-p

4.1 Vp-p

4.1 Vp-p

4

3

IC001 r; (FE)

0.3 Vp-p

100 mV/DIV, 1 ms/DIV200 mV/DIV, 100 ns/DIV 500 mV/DIV, 100 ns/DIV

7

IC303 q; (SO2)

4.8 Vp-p

29.5 ns

1 V/DIV, 10 ns/DIV

qa

IC206 <zcz (VDAC_0)

1.4 Vp-p

H

500 mV/DIV, 20 µs/DIV

IC001 tj (RFAC)

8

IC303 qd (SO3)

29.5 ns

1 V/DIV, 10 ns/DIV

qs

IC206 <zx, (VDAC_1)

H

500 mV/DIV, 20 µs/DIV

1.3 Vp-p

4.1 Vp-p

1.1 Vp-p

ql Q802 collector

23.2 Vp-p

10.5 µs

10 V/DIV, 4 µs/DIV

– IO Board –

ws

to wj : color bars video signal

ws

IC201 wd (CVBS OUT)

2.7 Vp-p

H

1 V/DIV, 20 µs/DIV 1 V/DIV, 20 µs/DIV

wg

IC201 qk (CbOUT)

(AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

1.7 Vp-p

H

wd

IC201 wh (COUT)

wg

IC201 qk (CbOUT)

(EXCEPT AEP,UK,RU)

H

500 mV/DIV, 20 µs/DIV

w;

IC305 4

4.7 Vp-p

20.3 ns

1 V/DIV, 10 ns/DIV

wf

IC201 w; (CYOUT)

2.0 Vp-p

H

1.6 Vp-p

(AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

wh

IC201 qh (CrOUT)

(AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

1.7 Vp-p

H

1.7 Vp-p

H

wa

IC108,110 qa (OUTL1)

2.6 µs

1 V/DIV, 1

wf

IC201 w; (CYOUT)

(EXCEPT AEP,UK,RU)

1 V/DIV, 20 µs/DIV

wh

IC201 qh (CrOUT)

(EXCEPT AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

µ

s/DIV

H

H

3.9 Vp-p

2.2 Vp-p

1.6 Vp-p

qd

IC206

<zxb

(VDAC_2)

(AEP,UK,RU)

500m V/DIV, 20 µs/DIV

qg

IC206

(AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

qk

IC607 qs (MCLK2)

1 V/DIV, 40 ns/DIV

930 mVp-p

H

<zz.

(VDAC_4)

H

74.1 ns

920 mVp-p

3.7 Vp-p

qd

IC206

<zxb

H

(VDAC_2)

H

<zz.

(VDAC_4)

800 mVp-p

(EXCEPT AEP,UK,RU)

500 mV/DIV, 20 µs/DIV

qg

IC206

(EXCEPT AEP,UK,RU)

200 mV/DIV, 20 µs/DIV

1.1 Vp-p

qf

IC206

<zxx

(VDAC_3)

(AEP,UK,RU)

H

500 mV/DIV, 20 µs/DIV

qh

IC606 wa (XOUT)

81.4 ns

1 V/DIV, 40 ns/DIV

910 mVp-p

4.5 Vp-p

qf

IC206

<zxx

(VDAC_3)

(EXCEPT AEP,UK,RU)

H

200 mV/DIV, 20 µs/DIV

qj

IC901 ek (X2)

50 ns

1 V/DIV, 20 ns/DIV

800 mVp-p

2.7 Vp-p

wj

IC101 qf (XO)

(AEP,UK,RU)

1 V/DIV, 100 ns/DIV

3.5 Vp-p

231 ns

– DIAT TRANSMIT Board –

wk

IC804 tl (OSCO)

2.8 Vp-p

40.7 ns

1 V/DIV, 20 ns/DIV

HCD-SR4W

7070

• IC Block Diagrams
– DIAT TRANSMIT Board –

HCD-SR4W

IC801 TK11225CMCL-G

IC804 CXD4016R

DTIN48DT2 INF

VCOT46APAVS45APAVD

47

LRCK 49

BCK 50

BCKOUT 51

LRCKOUT 52

CK12 53
CSST

VSS
VDD

OSCI

VSS

OSCO 59

XTCK4

XSM

MST
XTST
XRST

54
55
56
57
58

60
61
62
63
64

INTERFACE

GENERATOR

CONSTANT

CURRENT

SOURCE

PLVAR37PLREF

36

CONTROLLER

8

9

DIVCODE

CHNM BL

BUFFER

10

PCMID

GND

5

GND

RAM

11

EMPIN

OVER HEAT &

OVER CURRENT

PROTECT

CLOCK

SELECTOR

MODULATOR

12

13

VSS

VDD

14

SCLK

15

XSCEN

16

SWDT

CSOD

VIN

6 4

CONTROL

CIRCUIT

BANDGAP

REFERENCE

1 2 3

CONT

APS41VSS40VDD

PLL

SOLOMON

PARITY

GENERATOR

3

IIFSEL14IIFSEL0

IFEXMD

39

READ-

5

APX

6

7

EXCKSEL

43 38

44

AUDIO

CLOCK

1

2

TESTMD

APVGS

APCPO

42

SMCK

VOUT

NP

TEST7

35

D/A

CONVERTER

34

TEST6

33

TEST5

TEST432
TEST331
TEST230
TEST129

28

TEST0

27

VSS

26

VDD
DAVRO25
DAVREF24
DAAVS23
DAAVD22
DAAOUT21
VSS

20

VDD

19

DACK18
DAPD17

71

HCD-SR4W

– DMB08 Board –

IC203 BR9040F-WE2

R/B

1

2

VCC

INSTRUCTION DECODE

3

CS

SK

4

CONTROL AND CLOCK

GENERATOR

DETECT
SUPPLY

VOLTAGE

WRITE

DISABLE

HIGH

VOLTAGE

GENERATOR

8

WC

7

GND

IC215 SN74ALVCH16841DGGR

56

1OE

1Q1
1Q2

GND

1Q3
1Q4

VCC

1Q5
1Q6

1Q7

GND

1Q8
1Q9

1Q10

OE

1

2
3

4

5
6

7

8
9

10

11
12
13
14

LATCH

1LELE

1D1

55

1D2

54

GND

53

1D3

52

1D4

51

VCC

50

1D5

49

1D6

48

1D7

47

GND

46

1D8

45

1D9

44

1D10

43

INSTRUCTION

REGISTER

IC302 BR24L16F-WE2

VCC

8

WP

7

SCL

6

ADDRESS

BUFFER

DATA

REGISTER

8bit

16bit

11 bit

ADDRESS
DECODER

ADDRESS
DECODER

CONTROL CIRCUIT

R/W

AMPS

11 bit

8bit

16bit

16 K bit EEPROM ARRAY

4,096bit

EEPROM

SLAVE WORD

ADDRESS REGISTER

STOPSTART

6

DO

5

DI

A0

1

8 bit

A1

2

A2

3

ACK

DATA

REGISTER

2Q10

72

2Q1
2Q2
2Q3

GND

2Q4
2Q5
2Q6

VCC

2Q7
2Q8

GND

2Q9

2OE

SDA

15
16
17

18

19
20
21

22

23
24

25

26
27

28

OE

LATCH

LE

2D1

42

2D2

41

2D3

40

GND

39

2D4

38

2D5

37

2D6

36

VCC

35

2D7

34

2D8

33

GND

32

2D9

31

2D10

30

29

2LE

5

HIGHT VOLTAGE

GENERATOR

POWER SUPPLY

VOLTAGE DETECTION

GND

4

IC303 SM8707GV-G-E2

1

VDD1

2

VSS1

X'tal

OSC

REF

Div.1

MO1

VDD2

VSS2

XTO

XTI

3

4

NC

5

6

7

8

PHASE

DETECTOR1

LOOP

Div.1

PHASE

PUMP1

LPF

VCO

CONTROL

LOGIC

HCD-SR4W

16

NC

NC

15

NC

14

13

SO3

VDD3

12

11

VSS3

SO2

10

SO1

9

IC401 CXD3068Q

DVDD2

61

ASYE

62

MD2

63

DOUT

LRCK

PCMD

BCK

EMPH

XTSL

DVSS2

XTAI

XTAO

SOUT
SOCK

XOLT

SQSO
SQCK

SCSY

SBSO

EXCK

DIGITAL

64

OUT

65
66
67

68
69
70
71
72

73
74
75

76
77
78
79
80

D/A DIGITAL

INTERFACE

60

CLOCK

GENERATOR

CPU

INTERFACE

VPCO

32K

RAM

SERVO INTERFACE

SERVO

AUTO

SEQUENCER

AVDD0

IGEN

FOCUS
SERVO

DSP

TRACKING

SERVO

DSP

SLED

SERVO

DSP

AVSS0

AVSS1

RFAC

ASYI

ASYMMETRY
CORRECTOR

ASYO

BIAS

AVDD1

PCO

FILI

FILO

DIGITAL

PLL

EFM

CLTV

V16M

VCTL

59 58 57 56 55 54 53 52 51 50 49 48 474645 44 43 42 41

OSC

DEMODULATOR

ERROR

CORRECTOR

SUBCODE

PROCESSOR

ADIO

RFDCCETE

A/D

CONVERTER

GENERATOR

GENERATOR

GENERATOR

PROCESSOR

MIRR, DFCT,

AMPLIFIER &

OPERATIONAL

ANALOG SWITCH

FOCUS

PWM

TRACKING

PWM

SLED
PWM

DIGITAL

CLV

FOK

DETECTOR

40

SE

39

TE

38

VC

37

TES1

36

TEST1

35

DVSS1
FRDR

34

FFDR

33

TRDR

32

TFDR

31

SRDR

30
29

SFDR

DVDD1

28

FSTO

27

SSTP

26

MDP

25

LOCK

24

PWMI

23

FOK

22

DFCT

21

1 2 3 4 5 6 7 8 9

XLAT

DVDD0

XRST

MUTE

DATA

CLOK

SENS

SCLK

12 13 14 15 16 17 18 19 20

10 11

WFCK

XUGF

XPCK

GFS

C2PO

ATSK

SCOR

C4M

WDCK

DVSS0

COUT

MIRR

73

HCD-SR4W

IC604 IS61LV6416-10TLT

A4

1
2

A3

3

A2

4

A1

5

A0

CHIP ENABLE

6

CS

I/O 0
I/O 1
I/O 2
I/O 3

VDD

VSS
I/O 4
I/O 5
I/O 6
I/O 7

WE

A15

A14

A13

A12

NC

7
8

9
10
11
12
13
14
15
16

WRITE ENABLE

17

18
19
20
21
22

BUFFER

BUFFER

LOW
BYTE

I/O

BUFFER

ROW/COLUMN

DECODER

64K x 16

MEMORY

ARRAY

SENSE AMP

&

WRITE

PRIVER

HIGH
BYTE

I/O

BUFFER

OUTPUT ENABLE

BUFFER

BYTE ENABLE

BUFFER

44

A5
A6

43

A7

42

OE

41

BHE

40

BLE

39
38

I/O 15

37

I/O 14

36

I/O 13

35

I/O 12

34

VSS

33

VDD

32

I/O 11

31

I/O 10

30

I/O 9

29

I/O 8

28

NC

27

A8

26

A9

25

A10

24

A11

23

NC

IC606 LC89056W-E

37

CE

38

CL

MICROCOMPUTER

INTERFACE

39XSEL

MODE0
MODE1

DOSEL0
DOSEL1

CKSEL0

CKSEL1

XMODE

40
41
42DGND
43DVDD
44
45

46
47

48

MODE

SELECT

SYSTEM

RESET

1 2 3 4

DISEL

36

DI

35

DOUT

DO

ERROR

3334

DEMODULATOR

DINO

DGND

AUTO

BPSYNC

31

SAMPLING

FREQUENCY

LOCK

DETECT

DATA

INPUT

CIRCUIT

DINI

5

30

DIN2

DVDD

F2/P2/C2

VF/P3/C3

C BIT

DETECT

TIMING

6

7

DGND

F0/P0/C0

F1/P1/C1

CLOCK

8 9 10

R

DVDD

252627282932

PLL

CSFLAG

PA/PB

DETECT

VIN

LPF

11

12

AVDD

AGND

AUDIO

24
23

EMPHA

22

XIN

21

XOUT

20

XMCK
19 DVDD
18 DGND
17

XSTATE
16

DATAO

LRCK

15

BCK

14

CKOUT

13

74

IC608 AK4381VT-E2

MCLK

1

BICK

2

SDTI

3
4

LRCK

PDN

5

CSN

6

CCLK

7
8

INTERFACE

CDTI

IC609 PCM1802DBR

µP

AUDIO

DATA

INTERFACE

CLOCK

DIVIDER

INTERPOLATOR

INTERPOLATOR

8x

8x

DE–EMPHASIS

CONTROL

∆∑

MODULATOR

∆∑

MODULATOR

SCF

SCF

16
15

14
13

12
11

10

9

HCD-SR4W

DZFL
DZFR

VDD
VSS

AOUTL+
AOUTL–

AOUTR+
AOUTR–

VINL

1

VINR

2

3

VREF1

4

VREF2

VCC

5

AGND

6

PDWN

7

BYPAS

8

FSYNC

9

LRCK

10

IC612 CXD9742Q

VDDL

DSBCK 38

DSIFL
DSIFR
DSICT

DSISW

DSISL

DSISR

DIRDSCK

SYNC

INIT

VSS

SINGLE-END/

DIFFERENTIAL

CONVERTER

REFERENCE

SINGLE-END/

DIFFERENTIAL

CONVERTER

37

39
40
41
42
43
44

45
46
47

48

POWER
SUPPLY

VSS

35

36

FIR FILTER

&

DOWN

SAMPLING

UNIT

5TH ORDER

DELTA-SIGMA

MODULATOR

5TH ORDER

DELTA-SIGMA

MODULATOR

EXIFLR

EXICSW

EXISLR

34

33

CLOCK

GENERATOR

&

TIMING

CONTROL

EXILRCK

32

31

PCM

MUTE

ROM
24 bit

720 word

EXIBCK

VDDH

30

x16 1/64
(x1/128)

DECIMATION

FILTER

WITH

DC CUT

FILTER

CLOCK & TIMING CONTROL

EXIMCK

VSS

28

PCM

I/F

27

29

SERIAL

INTERFACE

MODE/FORMAT

CONTROL

MCK

TOUT2

26

TEST

CONTROL

&

25

VDDL

INT/EXT

DATA

SELECT

INT/EXT

CLOCK

SELECT

24

22
21

20
19

18

17

16

15
14

13

VSS

POFLR23
POCSW
POSLR

PLRCK
PBCK

VDDH

MCKOUT

VSS

FMTPCM
DIRPCK

VDDL

20

MODE1

19

MODE0

18

FMT1

17

FMT0

16

OSR

15

SCKI

14

VDD

13

DGND

12

DOUT

11

BCK

1

VDDL

2

SEL1FS

3

SEL4FS

4

SELEXT

5

DSGAIN

6

XMTPCM

7

VDDH

8

TEST1

9

10

TEST2

TEST3

11

TOUT1

12

VSS

75

HCD-SR4W

IC703 NJM3404AV (TE2)

A OUTPUT

A-INPUT

A+INPUT

1

2

A

3

V-

4

B

V+

8

B OUTPUT

7

B-INPUT

6

B+INPUT

5

IC704 TK11125CSCL-G

VIN VOUT

5 4

BANDGAP

OVER HEAT &

OVER CURRENT

PROTECTION

CONTROL

CIRCUIT

REFERENCE

1 2 3

VCONT GND NP

IC706 M51V18165M-60TS-KR1

VSS

DQ16

DQ15

DQ14

DQ13

VSS

DQ12

DQ11

DQ10

DQ9

4950 4748 4546 4344 4142 35

CONTROLLER

OUTPUT

BUFFER

OUTPUT

BUFFER

VDD

1 43 65 87 109

VDD

DQ1

INPUT

BUFFER

INPUT

BUFFER

VCC VDD

DQ3

DQ4

VCC

DQ5

DQ2

DQ6

DQ7

CONTROLLER

DQ8

NC

40 – 36

I/O

I/O

11 – 16

NC

I/O

SELECTOR

LCAS34UCAS33OE

17 18

WE

RAS

TIMING

GENERATOR

SENSE

AMPLIFIER

MEMORY

CELLS

VBB GENERATOR

IVCC GENERATOR

ON CHIP

ON CHIP

REFRESH

CONTROL

CLOCK

COLUMN

ADDRESS

BUFFERS

COLUMN

DECODERS

WORD

DRIVERS

A9A8A7A6A5A4VSS

3132 2930 262728

INTERNAL

ADDRESS
COUNTER

ROW

ADDRESS

BUFFERS

ROW

DECODERS

VDD

VDD

2019 2221 24 25232

NC

NC

A0A1A2

A3

VDD

76

IC808 MSM56V16160F-8TK7R1

VSS

DQ15

DQ14

VSSQ

DQ13

DQ12

VCCQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

4950 4648 4447 45 4243 3940 36

41

38

TIMING

REGISTER

NC

37

UDQM35CLK34CKE33NC

HCD-SR4W

A9A8A7A6A5A4VSS

3132 2930 262728

VDD

DQ0

DQ1

OUTPUT
BUFFERS

READ

REGISTER

INPUT

REGISTER

INPUT

BUFFERS

VSSQ

DATA

DATA

DQ2

DQ3

VCCQ

DQ4

DQ5

VSSQ

PROGRAMING

REGISTER

LATENCY

BURST

CONTROLLER

CONTROLLER

DQ6

DQ7

&

I/O

CONTROLLER

VDDQ

BANK

14

LDQM

16WE15 17CS18

RAS

CAS

SENSE

AMPLIFIER

MEMORY

CELLS

INTERNAL

COLUMN

ADDRESS

COUNTOR

WORD

DRIVERS

COLUMN

ADDRESS

BUFFERS

COLUMN

DECODERS

ROW

DECODERS

ROW

ADDRESS

BUFFERS

INTERNAL

ROW

ADDRESS

COUNTOR

A10/AP

A11-BA

212019 2322 252421 43 65 87 109 11 1312

A0A1A2

A3

VDD

IC812, 813 SN74LV245APWR

G

CC

V

20 19 18 17

12345678910

DIR

ENABLE

A1

B1

B2

B3

B4

B5

15 14 13 12

16

A2

A3

A4

A5

B6

A6

A7

IC814 TC7WH157FK (TE85R)

8

B7

B8

11

1

A

2

B

3

Y

4

GND

A8

GND

EN G

A

Y

B

Y

VCC

117

ST

116

SELECT

5

Y

77

HCD-SR4W

IC907 PST3645NR

OUT

1

VDD

2

5

CD

– DRIVER Board –

VREF

GND

3

IC701 BA6956AN

TSD

CONTROL LOGIC

1 2 3 4 5 6 7 8 9

VREF

OUT2

RNF

OUT1

VM

VCC

FIN

GND

RIN

4

NC

– IO Board –

IC101 BU1924F-E2

RCLK

PLL

1187.5Hz

BIPHASE

DECODER

DEFFERENTIAL

DECODER

1 43 65 872

QUAL

RDAT

VREF

NC

PLL 57kHz

RDS/ARI

COMPARATOR

8th SWITCHED

CAPACITOR

FILTER

ANTI-ALIASING

FILTER

MUX

VDD2

XO

141516 13 121110 9

CLOCK

ANALOG

VSS1

VDD1

VSS3

VSS2

XI

DIGITAL

CMP

T1

TEST

T2

78

IC201 MM1623BFBE

HCD-SR4W

S-DC OUT

S1/S2

150kΩ

1VCC1

BIAS

CLAMP

CLAMP

BIAS

CLAMP

150kΩ

BIAS

150kΩ

BIAS

6dB

6dB

6dB

6dB

6dB

6dB

+

150kΩ

BIAS

6dB–6dB

2C IN

3MUTE 1

4CVBS IN

5YC MIX

6Y IN

7GND

8BIAS

9I/P

10CY IN

11CLP

12CB IN

13MUTE2

14CR IN

LOW-PASS

LOW-PASS

LOW-PASS

6.75MHz

LOW-PASS

FILTER

LOW-PASS

FILTER

13.5MHz

6.75MHz

LOW-PASS

FILTER

LOW-PASS

FILTER

13.5MHz

6.75MHz

LOW-PASS

FILTER

LOW-PASS

FILTER

13.5MHz

6.75MHz

FILTER

6.75MHz

FILTER

6.75MHz

FILTER

75Ω

DRIVER

75Ω

DRIVER

75Ω

DRIVER

75Ω

DRIVER

75Ω

DRIVER

75Ω

DRIVER

28 VCC2

27 S-DC OUT

26 C OUT

25 S1

24 S2

23 CVBS OUT

22 GND2

21 Y OUT

20 CY OUT

19 GND2

18 CB OUT

17 GND2

16 CR OUT

15 GND2

IC602 MC14052 BDR2 IC605 M62429FP-TP

VIN2 VOUT2 VCC CLOCK

8

VR 2

VOL AMP 2

VOL AMP 1

VR 1

1

VIN1 VOUT1 GND DATA

7

REF AMP

2 3 4

6

VREF

5

LOGIC

CONTROL

79

HCD-SR4W

– RF Board –

IC001 CXD1881AR

RFDC

RFSIN

64 63 62 61 60 59 58 57 5156

ATOP

ATON

AIN

AIP

VPA

RFAC

BYP

DIN

DIP

55 54 53 52 50 49

FNP

FNN

VNA

MEV

RX

DVDRFP
DVDRFN

CD D

CD C

CD B

CD A

CONTROL

SIGNALS
TO EACH

BLOCK

CE ATT

CEPOL

GCA

GCA

GCA

GCA

GCA

GCAGCA

FROM

S-PORT

HOLDEN

COMPA-

RATOR

–
+

INPUT

IMPEDANCE

FROM S-PORT

INPUT

BUFFER

FAST ATTACK

AGC CHARGE

PUMP

3

LPF ATT
POL SEL

BUFFER

3

SEL

SINK CURRENT

2

FROM S-PORT

REGISTER

V33 FOR
OUTPUT

V25

V125

V25/3

TE

RST

FOR SERVO

OUTPUT

V25/2

LINKEN

AGCO

SERIAL

PORT

BUFFER

PI
FE
TE
CE

MNTR

CONTROL

GCASEL

2

AGC

HOLD

PH

BOTTOM

ENVELOPE

PH

MUX

SDEN

48

SDATA

47

SCLK

46

V33

45

LPC

44

LCN

43

MNTR

42

41

CE

FE

40

TE

39

PI

38

37

V25

36

V125

35

TPH

34

DFT

33

LINK

INPUT

SEL

ATT

4

PROGRAMMABLE

DETECTOR

DETECTOR

–
+

DUAL APC

INPUT

BIAS

INPUT

IMPEDANCE

SEL

+
–

SIGDET

PHASE

PHASE

A+D

+
+

+
+

B+C

B+D

+
+

SUM

AMP

+
+

A+C

2

CLAMP &

ENVELOPE

2

LEVEL

+
+

AGC

DAC

APC SEL

DVD/CD

1
2

A2

3

B2

4

C2

5

D2

6

CP

7

CN

8

D

9

C

10

B

11

A

12

13

14

15

16

BUFFER

GCA

FROM

S-PORT

MUX

CD/DVD

MUX ATT

2

INPUT

IMPEDANCE

SEL

EQ

3

FROM

S-PORT

D

C

B

A

S-PORT

COMPARATOR

3

VC

GCA

3

FROM

S-PORT

GCA

W/LPF

3

FROM

S-PORT

GCA

GCA

4

3

FROM

FROM

S-PORT

VCI FOR SERVO INPUT

VC = VPB/2

LD H/L

FROM S-PORT

––

GCA

FROM

S-PORT

CD/DVD

+
+

+
–

4

INTERNAL

FDGHG

EQUALIZER

FILTER

DIFFERENTIATOR

AGCO

TOPHOLD

TOPHOLD

–
+

CP/CN

LOW

IMPEDANCE

GCALPF

HYSTERESISTER

& OFFSET

FROM S-PORT

FROM S-PORT

OFFSET

CANSEL

FROM

S-PORT

BCA
DET

MIRR
COMPARATOR

PEAK/BOTTOM

HOLD

OUTPUT

INHIBIT

–
+

GCALPF

SUBGCAMUX GCALPF

CEFDB

5

FULL WAVE

RECTIFER

OFFSET

CANSEL

FROM

S-PORT

OFFSET

CANSEL

FROM

S-PORT

OFFSET

CANSEL

FROM

S-PORT

TOP

HOLD

2

FROM

S-PORT

INPUT GAIN

FROM S-PORT

4

5

6

DAC

2

80

17

18 19 20 21 22 24 2523 26 27 28 29 31 3230

CD F

CD E

VPB

VC

CDLD

DVDLD

DVDPD

CDPD

VNB

LDON

MIRR

MP

MB

MLPF

MIN

MEVO

• IC Pin Function Description
DMB08 BOARD IC206 ZIVA5X-C2F (DVD SYSTEM PROCESSOR)

Pin No. Pin Name I/O Description

1 VDDP — Power supply terminal (+3.3V) (I/O signal)
2 HA1 I/O Address bus
3 HD15 I/O Data bus (address signal multiplexed)
4 HD14 I/O Data bus (address signal multiplexed)
5 HD13 I/O Data bus (address signal multiplexed)
6 HD12 I/O Data bus (address signal multiplexed)
7 HD11 I/O Data bus (address signal multiplexed)
8 HD10 I/O Data bus (address signal multiplexed)

9 HD9 I/O Data bus (address signal multiplexed)
10 HD8 I/O Data bus (address signal multiplexed)
11 HD7 I/O Data bus (address signal multiplexed)
12 VDDP — Power supply terminal (+3.3V) (I/O signal)
13 GNDP — Ground terminal (I/O signal)
14 HD6 I/O Data bus (address signal multiplexed)
15 HD5 I/O Data bus (address signal multiplexed)
16 HD4 I/O Data bus (address signal multiplexed)
17 HD3 I/O Data bus (address signal multiplexed)
18 HD2 I/O Data bus (address signal multiplexed)
19 HD1 I/O Data bus (address signal multiplexed)
20 VDDP — Power supply terminal (+3.3V) (I/O signal)
21 GNDP — Ground terminal (I/O signal)
22 HD0 I/O Data bus (address signal multiplexed)
23 HDTACK I/O Acknowledge signal input/output for host data transfer (not used)
24 HIRQ0 I Interrupt signal input for Medusa (not used)
25 WEH.UDS I/O Host upper data strobe signal output
26 WEL.LDS I/O Host lower data strobe signal output (not used)
27 HREAD I/O Read/write strobe signal output
28 GPIO0 I/O Jig detection port (pull-up)
29 GND — Ground terminal (inside core)
30 VDD — Power supply terminal (+1.8V) (inside core)
31 GND25 — Ground terminal (SDRAM I/O signal)
32 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
33 MA9 O SDRAM address bus
34 MA8 O SDRAM address bus
35 MA7 O SDRAM address bus
36 MA6 O SDRAM address bus
37 MA5 O SDRAM address bus
38 MA4 O SDRAM address bus
39 MA3 O SDRAM address bus
40 MA2 O SDRAM address bus
41 MA1 O SDRAM address bus
42 MA0 O SDRAM address bus
43 GND25 — Ground terminal (SDRAM I/O signal)
44 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
45 MA10 O SDRAM address bus
46 MA11 O SDRAM address bus
47 BA1 O SDRAM bank select 1 signal output

HCD-SR4W

81

HCD-SR4W

Pin No. Pin Name I/O Description

48 BA0 O SDRAM bank select 0 signal output
49 MCS0 O SDRAM chip select 0 signal output
50 MCS1 O Not used
51 MRAS O SDRAM row address strobe signal output
52 MCAS O SDRAM column address strobe signal output
53 MWE O SDRAM write enable signal output (“H” : read, “L” : write)
54 GND25 — Ground terminal (SDRAM I/O signal)
55 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
56 MCLK O SDRAM Clock output
57 MD0 I/O SDRAM data
58 MD1 I/O SDRAM data
59 MD2 I/O SDRAM data
60 MD3 I/O SDRAM data
61 GND25 — Ground terminal (SDRAM I/O signal)
62 MDQM0 O Byte read /write mask signal 0 output
63 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
64 MD4 I/O SDRAM data
65 MD5 I/O SDRAM data
66 MD6 I/O SDRAM data
67 MD7 I/O SDRAM data
68 MD8 I/O SDRAM data
69 MD9 I/O SDRAM data
70 MD10 I/O SDRAM data
71 MD11 I/O SDRAM data
72 GND25 — Ground terminal (SDRAM I/O signal)
73 MDQM1 O Byte read /write mask signal 1 output
74 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
75 MD12 I/O SDRAM data
76 MD13 I/O SDRAM data
77 MD14 I/O SDRAM data
78 MD15 I/O SDRAM data
79 GND — Ground terminal (inside core)
80 VDD — Power supply terminal (+1.8V) (inside core)
81 MD16 I/O SDRAM data
82 MD17 I/O SDRAM data
83 MD18 I/O SDRAM data
84 MD19 I/O SDRAM data
85 GND25 — Ground terminal (SDRAM I/O signal)
86 MDQM2 O Byte read /write mask signal 2 output
87 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
88 MD20 I/O SDRAM data
89 MD21 I/O SDRAM data
90 MD22 I/O SDRAM data
91 MD23 I/O SDRAM data
92 MD24 I/O SDRAM data
93 MD25 I/O SDRAM data
94 MD26 I/O SDRAM data

82

Pin No. Pin Name I/O Description

95 MD27 I/O SDRAM data
96 GND25 — Ground terminal (SDRAM I/O signal)
97 MDQM3 O Byte read /write mask signal 3 output
98 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
99 MD28 I/O SDRAM data

100 MD29 I/O SDRAM data
101 MD30 I/O SDRAM data
102 MD31 I/O SDRAM data
103 GND25 — Ground terminal (SDRAM I/O signal)
104 VDD25 — Power supply terminal (+3.3V) (SDRAM I/O signal)
105 VCLK I/O System clock (not used)
106 I2C_CTRL — Not used
107 VS O S1 signal output
108 I/P SW O Progressive/interlace switch signal output (not used)
109 GPIO1 (5) — Not used
110 GPIO1 (4) — Not used
111 VDDP — Power supply terminal (+3.3V) (I/O signal)
112 GNDP — Ground terminal (I/O signal)
113 GPIO1 (3) — Not used
114 GPIO1 (2) — Not used
115 GPIO1 (1) — Not used
116 HIRQ2_ I Busy signal input from the EEPROM (IC203)
117 VDAC_4B — Video DAC bias bit 4 (connected to the ground)
118 VDAC_VDD4 — Power supply terminal (+3.3V) (Video DAC 4)
119 VDAC_4 O VDAC output 4
120 VDAC_3B — Video DAC bias bit 3 (connected to the ground)
121 VDAC_VDD3 — Power supply terminal (+3.3V) (Video DAC 3)
122 VDAC_3 O VDAC output 3
123 VDAC_2B — Video DAC bias bit 2 (connected to the ground)
124 VDAC_VDD2 — Power supply terminal (+3.3V) (Video DAC 2)
125 VDAC_2 O VDAC output 2
126 VDAC_1B — Video DAC bias bit 1 (connected to the ground)
127 VDAC_VDD1 — Power supply terminal (+3.3V) (Video DAC 1)
128 VDAC_1 O VDAC output 1
129 VDAC_0B — Video DAC bias bit 0 (connected to the ground)
130 VDAC_VDD0 — Power supply terminal (+3.3V) (Video DAC 0)
131 VDAC_0 O VDAC output 0
132 VDAC_DVSS — Ground terminal (Video DAC digital system)
133 VDAC_DVDD — Power supply terminal (+3.3V) (Video DAC digital system)
134 VDAC_REFVDD — Power supply terminal (Video DAC reference)
135 VDAC_REF I Reference voltage input terminal(for Video DAC)
136 VDAC_REFVSS — Ground terminal (Video DAC reference)
137 XVSS — Ground terminal (crystal oscillator)
138 XOUT O Crystal oscillation signal output
139 XIN I Crystal oscillation signal input
140 XVDD — Power supply terminal (crystal oscillator)
141 AVSS2 — Ground terminal (analog PLL)

HCD-SR4W

83

HCD-SR4W

Pin No. Pin Name I/O Description

142 AVDD2 — Power supply terminal (+3.3V) (analog PLL)
143 AVDD1 — Power supply terminal (+3.3V) (analog PLL)
144 AVSS1 — Ground terminal (analog PLL)
145 VDD — Power supply terminal (+1.8V) (inside core)
146 GND — Ground terminal (inside core)
147 XCK O Audio system clock output (not used)
148 LRCK O LRCK signal output for audio (not used)
149 BCK O BCK signal output for audio (not used)
150 GPIO4 (1) — Not used (pull-up)
151 GPIO4 (2) — Not used (pull-up)
152 VDDP — Power supply terminal (+3.3V) (I/O signal)
153 GNDP — Ground terminal (I/O signal)
154 GPIO4 (3) — Not used (pull-down)
155 GPIO4 (4) — Not used (pull-down)
156 IEC958 O S/PDIF signal
157 DAI_DATA I Data input from ADC (not used)
158 DAI_BCK I BCK signal input from ADC (not used)
159 DAI_LRCK I LRCK signal input from ADC (not used)
160 I2C_CL I/O I2C clock bus
161 I2C_DA I/O I2C data bus
162 CS(ZIVA_E2P) O Chip select signal output to the EEPROM (IC203)
163 RXD1 I Serial data input for check jig
164 TXD1 O Serial data output for check jig
165
166 GNDP — Ground terminal (I/O signal)
167 VDDP — Power supply terminal (+3.3V) (I/O signal)
168 SDDATA7 I SDBus data7 input
169 SDDATA6 I SDBus data6 input
170 SDDATA5 I SDBus data5 input
171 SDDATA4 I SDBus data4 input
172 GND — Ground terminal (inside core)
173 VDD — Power supply terminal (+1.8V) (inside core)
174 SDDATA3 I SDBus data3 input
175 SDDATA2 I SDBus data2 input
176 SDDATA1 I SDBus data1 input
177 SDDATA0 I SDBus data0 input
178 SDREQ O SDBus data request signal output
179 SDEN I SDBus data enable signal input
180 GNDP — Ground terminal (I/O signal)
181 VDDP — Power supply terminal (+3.3V) (I/O signal)
182 SDERROR I SDBus data error signal input
183 SDCLK I SDBus data clock input
184 HIRQ1 I Interrupt signal input from the mechanism controller (IC301)
185 DRVCLK I Serial data clock input from the mechanism controller (IC301)
186 DRVTX I
187 DRVRX O Serial data output to the mechanism controller (IC301) and the EEPROM (IC203)
188 DRVRDY I Ready signal input from the mechanism controller (IC301)

WRITE_CTRL(ZIVA_E2P)

OWrite control signal output to the EEPROM (IC203)

Serial data input from the mechanism controller (IC301) and the EEPROM (IC203)

84

Pin No. Pin Name I/O Description

189 VNW — Power supply for 5V tolerance voltage input
190 ALE O Latch enable signal output for address data demux
191 RST_SPC O Reset signal output to the mechanism controller (IC301)
192 HCS3 O Not used
193 HCS2 O Chip select signal output for Medusa (not used)
194 HCS1 I/O Not used
195 HCS0 O Chip select signal output to the external ROM (IC205)
196 VDDP — Power supply terminal (+3.3V) (I/O signal)
197 TRST I Reset signal input
198 TDO O Data output
199 TDI I Data input
200 TMS I TMS signal input
201 TCK I TCK signal input
202 RESET I ZIVA reset input
203 BUS CLK I/O Not used
204 GND — Ground terminal (inside core)
205 VDD — Power supply terminal (+1.8V) (inside core)
206 HA3 I/O Address bus 3
207 HA2 I/O Address bus 2
208 GNDP — Ground terminal (I/O signal)

HCD-SR4W

85

HCD-SR4W

DMB08 BOARD IC301 CXP973064-245R (MECHANISH CONTROLLER)

Pin No. Pin Name I/O Description

1 EEP SO O Not used
2 SDEN O Serial data enable signal output to DVD/CD RF amplifier

3 DOCTRL/ISBTEST O
4 XRST DSD O Reset signal output to the DSD decoder “L”: reset

5 EEP SI I/O Two-way data bus with the EEPROM
6 EEP RDY I EEPROM ready signal input from the DVD decoder
7 FCS JMP 1 O Focus jump 1 signal output to the motor/coil driver
8 FCS JMP 2 O Focus jump 2 signal output to the motor/coil driver

9 SENS CD I Internal status (SENSE) signal input from the digital signal processor
10 CDSP2 O Clock selection signal output to the digital signal processor
11 CDSP4 — Not used
12 XCS DVD O Chip select signal output to the DVD decoder
13 VSS — Ground terminal (digital system)

14 to 21 D0 to D7 I/O Two-way data bus with the DVD decoder

22 INIT0 DVD I Interrupt signal input from the DVD decoder
23 INIT1 DVD I Interrupt signal input from the DVD decoder
24 SCK DSD O Serial data transfer clock signal output to the DSD decoder
25 XRST DVD O Reset signal output to the DVD decoder “L”: reset
26 SCOR I Subcode sync (S0+S1) detection signal input from the digital signal processor
27 LAT CD O Serial data latch pulse signal output to the digital signal processor

28 LD ON O
29 MIRR I Mirror signal input from the digital signal processor

30 COUT CD I Numbers of track counted signal input from the digital signal processor

31 INLIM I
32 CS ZIVA O Chip select signal output to the DVD system processor

33 SI ZIVA I Serial data input from the DVD system processor
34 SO ZIVA O Serial data output to the DVD system processor
35 SCK ZIVA O Serial data transfer clock signal output to the DVD system processor
36 DRVIRQ O Interrupt request signal output to the DVD system processor
37 DRVRDY O Ready signal output to the DVD system processor
38 RST I System reset signal input from the DVD system processor “L”: reset
39 VSS — Ground terminal (digital system)
40 XTAL I System clock input terminal (20 MHz)
41 EXTAL O System clock output terminal (20 MHz)
42 VDD — Power supply terminal (+3.3V) (digital system)

43, 44 SLED A, SLED B O Sled motor drive signal output

45 JIT OFFSET O Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
46 SDOUT DSD O Serial data output to the DSD decoder
47 SDIN DSD I Serial data input from the DSD decoder
48 READY DSD I Ready signal input from the DSD decoder “L”: ready
49 DATA CD O Serial data output to the digital signal processor
50 CLOK CD O Serial data transfer clock signal output to the digital signal processor
51 XMSLAT O Serial data latch pulse signal output to the DSD decoder
52 SQSO I Subcode Q data input from the digital signal processor

Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on

Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on

Detection signal input from limit in switch The optical pick-up is inner position
when “H”

86

HCD-SR4W

Pin No. Pin Name I/O Description

53 MUTE DSD O Muting on/off control signal output to the DSD decoder “H”: muting on
54 SQCK O Subcode Q data reading clock signal output to the digital signal processor
55 VSS — Ground terminal (digital system)
56 TRAY IN I Disc tray in detection signal input terminal Not used
57 TRAY OUT I Disc tray out detection signal input terminal Not used
58 GFS DVD I Guard frame sync signal input from the DVD decoder
59 MUTE CD O Muting on/off control signal output to the digital signal processor “H”: muting on
60 MUTE 2D O Muting on/off control signal output to the motor/coil driver “H”: muting on
61 SLED I Sled motor servo drive PWM signal input terminal
62 FG I Spindle motor control signal input
63 SP ON O Muting on/off control signal output to the motor/coil driver “H”: muting on
64 JIT I Jitter signal input
65 TE I Tracking error signal input from the DVD/CD RF amplifier
66 PI I Pull in signal input from the DVD/CD RF amplifier
67 FE I Focus error signal input from the DVD/CD RF amplifier
68 AVSS — Ground terminal (for A/D converter)
69 AVREF I Reference voltage input terminal (for A/D converter)
70 AVDD — Power supply terminal (+3.3V) (for A/D converter)
71 GFS CD I Guard frame sync signal input from the digital signal processor
72 SCLK CD O SENSE serial data reading clock signal output to the digital signal processor
73 TSD-M O Thermal shut down signal output to the motor/coil driver
74 FOK CD I Focus OK signal input from the digital signal processor
75 LOCK CD I GFS is sampled by 460 Hz “H” input when GFS is “H”
76 LDSEL O Laser diode selection signal output
77 SACD/DVD O SACD/DVD selection signal output “L”: DVD, “H”: SACD
78 I2C SIO I/O Communication data bus with the DVD system processor and system controller

79 IIC-CLK I/O
80 RXD I Serial data input from the RS-232C (for check)

81 TXD O Serial data output to the RS-232C (for check)
82 SDCLK RF O Serial data transfer clock signal output to the DVD/CD RF amplifier
83 SDATA RF I/O Two-way data bus with the DVD/CD RF amplifier
84 XWR O Write strobe signal output to the DVD decoder
85 XRD O Read strobe signal output to the DVD decoder
86 (PWE) — Not used
87 VDD — Power supply terminal (+3.3V) (digital system)
88 VSS — Ground terminal (digital system)

89 to 96 A0 to A7 O Address signal output to the DVD decoder

97 A8 O Motor/coil driver power save control signal output terminal Not used
98 XDRST O Reset signal output to the digital signal processor “L”: reset
99 EEP WP O Write protect signal output to the EEPROM

100 EEP CLK I Clock signal output to the EEPROM

Communication data reading clock signal input or transfer clock signal output
with the DVD system processor and system controller

87

HCD-SR4W

DMB08 BOARD IC401 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)

Pin No. Pin Name I/O Description

1DVDD0 — Power supply terminal (+3.3V) (digital system)

2 XRST I Reset signal input from the mechanism controller “L”: reset

3 MUTE I Muting on/off control signal input from the mechanism controller “H”: muting on

4DATAISerial data input from the mechanism controller

5 XLAT I Serial data latch pulse signal input from the mechanism controller

6 CLOK I Serial data transfer clock signal input from the mechanism controller

7 SENS O Internal status (SENSE) signal output to the mechanism controller

8 SCLK I SENSE serial data reading clock signal input from the mechanism controller

9ATSK I/O Input/output terminal for anti-shock Not used
10 WFCK O Write frame clock signal output to the DVD decoder
11 RFCK O RFCK signal output terminal Not used
12 XPCK O XPCK signal output terminal Not used
13 GFS O Guard frame sync signal output to the mechanism controller
14 C2PO O C2 pointer signal output to the DVD decoder

15 SCOR O
16 C4M O 4.2336 MHz clock signal output terminal Not used

17 WDCK O Guard subcode sync (S0+S1) detection signal output to the DVD decoder
18 DVSS0 — Ground terminal (digital system)
19 COUT O Numbers of track counted signal output to the mechanism controller
20 MIRR O Mirror signal output to the mechanism controller
21 DFCT I/O Defect signal input/output terminal Not used
22 FOK O Focus OK signal output to the mechanism controller
23 PWMI I Spindle motor external control signal input terminal Not used
24 LOCK O GFS is sampled by 460 Hz “H” output when GFS is “H”
25 MDP O Spindle motor servo drive signal output to the DVD decoder

26 SSTP I
27 FSTO O 2/3 divider output terminal Not used

28 DVDD1 — Power supply terminal (+3.3V) (digital system)
29 SFDR O Sled servo drive PWM signal (+) output
30 SRDR O Sled servo drive PWM signal (–) output
31 TFDR O Tracking servo drive PWM signal (+) output
32 TRDR O Tracking servo drive PWM signal (–) output
33 FFDR O Focus servo drive PWM signal (+) output
34 FRDR O Focus servo drive PWM signal (–) output
35 DVSS1 — Ground terminal (digital system)
36 TEST I Input terminal for the test
37 TES1 I Input terminal for the test
38 VC I Middle point voltage (+1.65V) input terminal
39 FE I Focus error signal input from the DVD/CD RF amplifier
40 SE I Sled error signal input from the DVD/CD RF amplifier
41 TE I Tracking error signal input from the DVD/CD RF amplifier
42 CE I Middle point servo analog signal input
43 RFDC I RF signal input from the DVD/CD RF amplifier
44 ADIO O Output terminal for the test Not used
45 AVSS0 — Ground terminal (analog system)

Subcode sync (S0+S1) detection signal output to the DVD decoder and
mechanism controller

Detection signal input from limit in switch The optical pick-up is inner position
when “H”

88

HCD-SR4W

Pin No. Pin Name I/O Description

46 IGEN I Stabilized current input for operational amplifiers
47 AVDD0 — Power supply terminal (+3.3V) (analog system)
48 ASYO O EFM full-swing output terminal
49 ASYI I Asymmetry comparator voltage input terminal
50 RFAC I EFM signal input from the DVD/CD RF amplifier
51 AVSS1 — Ground terminal (analog system)
52 CLTV I Internal VCO control voltage input terminal
53 FILO O Filter output for master PLL
54 FILI I Filter input for master PLL
55 PCO O Charge pump output for master PLL
56 AVDD1 — Power supply terminal (+3.3V) (analog system)
57 BIAS I Asymmetry circuit constant current input terminal
58 VCTL I VCO control voltage input terminal for the wideband EFM PLL Not used
59 V16M O VCO oscillation output terminal for the wideband EFM PLL Not used
60 VPCO O Charge pump output terminal for the wideband EFM PLL Not used
61 DVDD2 — Power supply terminal (+3.3V) (digital system)
62 ASYE I Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used

63 MD2 I
64 DOUT O Digital audio signal output to the digital audio interface IC

65 LRCK O L/R sampling clock signal (44.1 kHz) output to the DVD decoder
66 PCMD O Serial data output to the DVD decoder
67 BCLK O Bit clock signal (2.8224 MHz) output to the DVD decoder

68 EMPH O

69 XTSL I
70 DVSS2 — Ground terminal (digital system)

71 XTAI I System clock input terminal (33.8688 MHz)
72 XTAO O System clock output terminal (33.8688 MHz) Not used
73 SOUT O Serial data output terminal Not used
74 SOCK O Serial data reading clock signal output terminal Not used
75 XOLT O Serial data latch pulse signal output terminal Not used
76 SQSO O Subcode Q data output to the mechanism controller
77 SQCK I Subcode Q data reading clock signal input from the mechanism controller
78 SCSY I Input terminal for resynchronism of guard subcode sync (S0+S1) Not used
79 SBSO O Subcode serial data output to the DVD decoder
80 EXCK I Subcode serial data reading clock signal input to the DVD decoder

Digital out on/off control signal input from the mechanism controller
“L”: digital out off, “H”: digital out on

“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz

89

HCD-SR4W

DMB08 BOARD IC607 CXD9618BQ (AUDIO DIGITAL SIGNAL PROCESSOR)

Pin No. Pin Name I/O Description

1 VSS — Ground terminal

2 XRST I Reset signal input from the system controller “L”: reset

3 EXTIN I Master clock signal input terminal Not used

4 FS2 I Sampling frequency selection signal input terminal Not used

5 VDDI — Power supply terminal (+2.6V)

6 FS1 I Sampling frequency selection signal input terminal Not used

7 PLOCK O Internal PLL lock signal output terminal Not used

8 VSS — Ground terminal

9 MCLK1 I System clock signal input terminal (13.5 MHz)
10 VDDI — Power supply terminal (+2.6V)
11 VSS — Ground terminal
12 MCLK2 O System clock signal output terminal (13.5 MHz)

13 MS I
14 SCKOUT O Internal system clock signal output to the D/A converter and stream processor

15 LRCKI1 I L/R sampling clock signal (44.1 kHz) input from the digital audio processor
16 VDDE — Power supply terminal (+3.3V)
17 BCKI1 I Bit clock signal (2.8224 MHz) input from the digital audio processor
18 SDI1 I Front L-ch and R-ch audio serial data input from the digital audio processor

19 LRCKO O
20 BCKO O Bit clock signal (2.8224 MHz) output to the D/A converter and stream processor

21 VSS — Ground terminal
22 KFSIO I Audio clock signal (11.2896 MHz) input from the digital audio processor
23 SDO1 O Front L-ch and R-ch audio serial data output to the stream processor
24 SDO2 O Center and woofer audio serial data output to the stream processor
25 SDO3 O Rear L-ch and R-ch audio serial data output to the stream processor
26 SDO4 O Audio serial data output to the D/A converter
27 SPDIF O S/PDIF signal output terminal Not used
28 LRCKI2 I L/R sampling clock signal (44.1 kHz) input from the A/D converter
29 BCKI2 I Bit clock signal (2.8224 MHz) input from the A/D converter
30 SDI2 I Center and woofer audio serial data input from the digital audio processor
31 VSS — Ground terminal
32 HACN O Acknowledge signal output to the system controller
33 HDIN I Write data input from the system controller
34 HCLK I Clock signal input from the system controller
35 HDOUT O Read data output to the system controller
36 HCS I Chip select signal input from the system controller
37 SDCLK O Clock signal output terminal Not used
38 CLKEN O Clock enable signal output terminal Not used
39 RAS O Row address strobe signal output terminal Not used
40 VDDI — Power supply terminal (+2.6V)
41 VSS — Ground terminal
42 CAS O Column address strobe signal output terminal Not used
43 DQM/OE0 O Output terminal of data input/output mask Not used
44 CS0 O Chip select signal output to the S-RAM
45 WE0 O Write enable signal output to the S-RAM

Master/slave selection signal input terminal
“L”: slave, “H”: master (fixed at “L” in this set)

L/R sampling clock signal (44.1 kHz) output to the D/A conv erter and stream
processor

90

HCD-SR4W

Pin No. Pin Name I/O Description

46 VDDE — Power supply terminal (+3.3V)
47 WMD1 I S-RAM wait mode setting terminal Fixed at “H” in this set
48 VSS — Ground terminal
49 WMD0 I S-RAM wait mode setting terminal Fixed at “H” in this set
50 PAGE2 O Page selection signal output terminal Not used
51 VSS — Ground terminal

52, 53 PAGE1, PAGE0 O Page selection signal output terminal Not used

54 BOOT I Boot mode control signal input terminal Not used
55 BTACT O Boot mode state display signal output terminal Not used
56 BST I Boot strap signal input from the system controller

57 MOD1 I

58 MOD0 I
59 EXLOCK I PLL lock error and data error flag input from the digital audio interface IC

60 VDDI — Power supply terminal (+2.6V)
61 VSS — Ground terminal

62, 63 A17, A16 O Address signal output terminal Not used

64 to 66 A15 to A13 O Address signal output to the S-RAM

67 GP10 O
68 GP9 O Decode signal output to the system controller

69 GP8 I Bit 1 input terminal of channel status from the digital audio interface IC
70 VDDI — Power supply terminal (+2.6V)
71 VSS — Ground terminal

72 to 75 D15 to D12 I/O Two-way data bus with the S-RAM

76 VDDE — Power supply terminal (+3.3V)

77 to 80 D11 to D8 I/O Two-way data bus with the S-RAM

81 VSS — Ground terminal

82 to 85 A9, A12 to A10 O Address signal output to the S-RAM

86 TDO O Simple emulation data output terminal Not used
87 TMS I Simple emulation data input start/end detection signal input terminal Not used
88 XTRST I Simple emulation asychronous break input terminal Not used
89 TCK I Simple emulation clock signal input terminal Not used
90 TDI I Simple emulation data input terminal Not used
91 VSS — Ground terminal

92 to 97 A8 to A3 O Address signal output to the S-RAM

98, 99 D7, D6 I/O Two-way data bus with the S-RAM

100 VDDI — Power supply terminal (+2.6V)
101 VSS — Ground terminal

102 to 105 D5 to D2 I/O Two-way data bus with the S-RAM

106 VDDE — Power supply terminal (+3.3V)
107, 108 D1, D0 I/O Two-way data bus with the S-RAM
109, 110 A2, A1 O Address signal output to the S-RAM

111 VSS — Ground terminal

112 A0 O Address signal output to the S-RAM

113 PM I PLL reset signal input from the system controller “L”: reset

PLL input frequency selection signal input terminal
“L”: 384fs, “H”: 256fs (fixed at “H” in this set)
Mode setting terminal
“L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)

L/R sampling clock signal (44.1 kHz) output to the D/A conv erter and stream
processor

91

HCD-SR4W

Pin No. Pin Name I/O Description

114 SDI3 I Rear L-ch and R-ch audio serial data input from the digital audio processor
115 SDI4 I Audio serial data input terminal Not used

116 SYNC I

117 to 119 VSS — Ground terminal

120 VDDI — Power supply terminal (+2.6V)

Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)

92

HCD-SR4W

DMB08 BOARD IC701 TMC57929PGF-RDP (DVD DECODER)

Pin No. Pin Name I/O Description

1, 2 D5, D6 I/O Two-way data bus with the mechanism controller

3 VSS — Ground terminal (digital system)
4D7I/O Two-way data bus with the mechanism controller
5A0IAddress signal input from the mechanism controller
6 VDD — Power supply terminal (+3.3V) (digital system)
7A1IAddress signal input from the mechanism controller
8 VDD5V — Power supply terminal (+5V)

9 to 14 A2 to A7 I Address signal input from the mechanism controller

15 VSS — Ground terminal (digital system)
16 XWAIT O Wait signal output terminal Not used
17 XRD I Read strobe signal input from the mechanism controller
18 XWR I Write strobe signal input from the mechanism controller
19 XCS I Chip select signal input from the mechanism controller

20, 21 XINT0, XINT1 O Interrupt signal output to the mechanism controller

22 VDD — Power supply terminal (+3.3V) (digital system)
23 XHRS I Not used
24 HDB7 O Stream data signal output to the DSD decoder and DVD system processor
25 VSS — Ground terminal (digital system)
26 HDB8 O Error flag signal output to the DSD decoder and DVD system processor
27 HDB6 O Stream data signal output to the DSD decoder and DVD system processor
28 VDDS — Power supply terminal (+5V) (digital system)
29 HDB9 O Not used
30 HDB5 O Stream data signal output to the DSD decoder and DVD system processor
31 HDBA O Not used
32 HDB4 O Stream data signal output to the DSD decoder and DVD system processor
33 VSS — Ground terminal (digital system)
34 HDBB O Not used
35 HDB3 O Stream data signal output to the DSD decoder and DVD system processor
36 VDD — Power supply terminal (+3.3V) (digital system)
37 HDBC O Not used
38 VDDS — Power supply terminal (+5V) (digital system)
39 HDB2 O Stream data signal output to the DSD decoder and DVD system processor
40 HDBD O Not used
41 HDB1 O Stream data signal output to the DSD decoder and DVD system processor
42 VSS — Ground terminal (digital system)
43 HDBE O Not used
44 HDB0 O Stream data signal output to the DSD decoder and DVD system processor
45 HDBF O Not used

46 XDRQ O
47 VDDS — Power supply terminal (+5V) (digital system)

48 XHWR O
49 XHRD O Header flag signal output to the DSD decoder

50 VDD — Power supply terminal (+3.3V) (digital system)
51 REDY O Not used
52 VSS — Ground terminal (digital system)

Serial data effect flag signal output to the DSD decoder and DVD system
processor

Serial data transfer clock signal output to the DSD decoder and DVD system
processor

93

HCD-SR4W

Pin No. Pin Name I/O Description

53 XHAC I
54 HINT O Not used

55 XS16 O Not used
56 HA1 I Not used
57 XPDI I/O Not used
58 VDDS — Power supply terminal (+5V) (digital system)

59, 60 HA0, HA2 I Not used

61 VSS — Ground terminal (digital system)

62, 63 HCS0, HCS1 I Not used

64 VDD — Power supply terminal (+3.3V) (digital system)
65 DASP I/O Not used

66 to 69 MDB0 to MDB3 I/O Two-way data bus with the D-RAM

70 VSS — Ground terminal (digital system)
71 MDB4 I/O Two-way data bus with the D-RAM
72 VDD5V — Power supply terminal (+5V)

73 to 75 MDB5 to MDB7 I/O Two-way data bus with the D-RAM

76 XMWR O Write enable signal output to the D-RAM
77 VDD — Power supply terminal (+3.3V) (digital system)
78 XRAS O Row address strobe signal output to the D-RAM

79, 80 MA0, MA1 O Address signal output to the D-RAM

81 VSS — Ground terminal (digital system)

82 to 87 MA2 to MA7 O Address signal output to the D-RAM

88 VDD — Power supply terminal (+3.3V) (digital system)
89 MA8 O Address signal output to the D-RAM
90 VSS — Ground terminal (digital system)
91 MA9 O Address signal output to the D-RAM
92 MNT1 O EEPROM ready signal output to the mechanism controller

93 MNT2 O
94 XMOE O Output enable signal output to the D-RAM

95 XCAS O Column address strobe signal output to the D-RAM

96, 97 MDB8, MDB9 I/O Two-way data bus with the D-RAM

98 VSS — Ground terminal (digital system)
99 MDBA I/O Two-way data bus with the D-RAM

100 VDD — Power supply terminal (+3.3V) (digital system)

101, 102 MDBB, MDBC I/O Two-way data bus with the D-RAM

103 VDD5V — Power supply terminal (+5V)

104 to 106 MDBD to MDBF I/O Two-way data bus with the D-RAM

107 GFS O Guard frame sync signal output to the mechanism controller
108 VSS — Ground terminal (digital system)
109 APEO O Absolute phase error signal output
110 VDD — Power supply terminal (+3.3V) (digital system)
111 DASYO O RF binary signal output
112 GNDA5 — Ground terminal (analog system)

113, 114 ASF1, AFS2 — Filter connected terminal for selection the constant asymmetry compensation

115 DASYI I Analog signal input after integrated from the RF binary signal

DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder

Operation clock signal output for PSP physical disc mark detection to DSD
decoder

94

HCD-SR4W

Pin No. Pin Name I/O Description

116 RFDCC I Input terminal for adjusting DC cut high-pass filter for RF signal Not used

117 RFIN I RF signal input from the DVD/CD RF amplifier
118, 119 VCCA5, VCCA4 — Power supply terminal (+3.3V) (analog system)

120 VCOR1 — VCO oscillating range setting resistor connected terminal

121 VCOIN I VCO input terminal
122, 123 GNDA4, GNDA3 — Ground terminal (analog system)

124 LPF5 O Signal output from the operation amplifier from PLL loop filter

125 VC1 I Middle point voltage (+1.65V) input terminal
126, 127 LPF2, LPF1 I Inverted signal input to the operation amplifier from PLL loop filter
128, 129 VCCA3, VCCA2 — Power supply terminal (+3.3V) (analog system)

130 PDO O Signal output from the charge pump for phase comparator

131 PDHVCC I Middle point voltage input terminal for RF PLL

132 FDO O Signal output from the charge pump for frequency comparator
133, 134 GNDA2, GNDA1 — Ground terminal (analog system)

135 SPO O Spindle motor control signal output

136 VC2 I Middle point voltage (+1.65V) input terminal

137 MDIN2 I Spindle motor servo drive signal input

138 MDIN1 I MDP input terminal

139 VCCA1 — Power supply terminal (+3.3V) (analog system)

140 CLVS O Control signal output for selection the spindle control filter constant at CLVS

141 VSS — Ground terminal (digital system)

142 MDSOUT O Frequency error output terminal of internal CLV circuit

143 VDD — Power supply terminal (+3.3V) (digital system)

144 MDPOUT O Phase error output terminal of internal CLV circuit

145 DFCT I Defect signal input terminal Not used

146 GSCOR I

147 EXCK O Subcode serial data reading clock signal output to the digital signal processor

148 SBIN I Subcode serial data input from the digital signal processor

149 VSS — Ground terminal (digital system)

150 SCOR I Sucode sync (S0+S1) detection signal input from the digital signal processor

151 WFCK I Write frame clock signal input from the digital signal processor

152 VDD5V — Power supply terminal (+5V)

153 XRCI I RAM overflow signal input terminal Not used

154 VDDS — Power supply terminal (+5V) (digital system)

155 C2PO I C2 pointer signal input from the digital signal processor

156 VDD — Power supply terminal (+3.3V) (digital system)

157 DBCK O Bit clock signal (2.8224 MHz) output terminal Not used

158 BCLK I Bit clock signal (2.8224 MHz) input from the digital signal processor

159 DDAT O PCM data output terminal Not used

160 MDAT I Serial data input from the digital signal processor

161 VSS — Ground terminal (digital system)

162 DLRC O L/R sampling clock signal (44.1 kHz) output terminal Not used

163 LRCK I L/R sampling clock signal (44.1 kHz) input from the digital signal processor

164 XRST I Reset signal input from the mechanism controller “L”: reset

165 IFS0 I Interface selection signal input terminal Fixed at “L” in this set

166 IFS1 I Interface selection signal input terminal Fixed at “H” in this set

Guard subcode sync (S0+S1) detection signal input from the digital signal
processor

95

HCD-SR4W

Pin No. Pin Name I/O Description

167 XTAL I 33.8688 MHz clock signal input terminal
168 VSS — Ground terminal (digital system)
169 XTL2 O System clock output terminal (33.8688 MHz)
170 XTL1 I System clock input terminal (33.8688 MHz)
171 VDD — Power supply terminal (+3.3V) (digital system)

172 to 176 D0 to D4 I/O Two-way data bus with the mechanism controller

96

HCD-SR4W

DMB08 BOARD IC801 CXD2753R (DSD DECODER)

Pin No. Pin Name I/O Description

1 VSCA0 — Ground terminal (for core)
2 XMSLAT I Serial data latch pulse signal input from the mechanism controller
3 MSCK I Serial data transfer clock signal input from the mechanism controller
4 MSDATI I Serial data input from the mechanism controller
5 VDCA0 — Power supply terminal (+2.5V) (for core)
6MSDATO O Serial data output to the mechanism controller
7 MSREADY O Ready signal output to the mechanism controller “L”: ready
8 XMSDOE O Serial data output enable signal output terminal Not used
9 XRST I Reset signal input from the mechanism controller “L”: reset

10 SMUTE I
11 MCKI I Master clock signal (33.8688 MHz) input

12 VSIOA0 — Ground terminal (for I/O)
13 EXCKO1 O Master clock signal (33.8688 MHz) output to the digital audio processor
14 EXCKO2 O External clock 2 signal output terminal Not used
15 LRCK O L/R sampling clock signal (44.1kHz) output terminal Not used
16 F75HZ O Not used
17 VDIOA0 — Power supply terminal (+3.3V) (for I/O)

18 to 25 MNT0 to MNT7 O Monitor signal output terminal Not used

26 TCK I Clock signal input from the DVD system processor
27 TDI I Serial data input from the DVD system processor
28 VSCA1 — Ground terminal (for core)
29 TDO O Serial data output to the DVD system processor
30 TMS I TMS signal input from the DVD system processor
31 TRST I Reset signal input from the DVD system processor “L”: reset

32 to 34 TEST1 to TEST3 I Input terminal for the test (normally: fixed at “L”)

35 VDCA1 — Power supply terminal (+2.5V) (for core)
36 UBIT O Not used
37 XBIT O Not used

38 to 41 SUPDT0 to SUPDT3 O Supplementary data output terminal Not used

42 VSIOA1 — Ground terminal (for I/O)

43, 44 SUPDT4, SUPDT5 O Supplementary data output terminal Not used

45 VDIOA1 — Power supply terminal (+3.3V) (for I/O)

46, 47 SUPDT6, SUPDT7 O Supplementary data output terminal Not used

48 SUPEN O Supplementary data enable signal output terminal Not used
49 VSCA2 — Ground terminal (for core)
50 NC O Not used

51, 52 TEST4, TEST5 I Input terminal for the test (normally: fixed at “L”s)

53 NC O Not used
54 VDCA2 — Power supply terminal (+2.5V) (for core)

55, 56 NC O Not used

57 BCKASL I
58 VSDSD0 — Ground terminal (for DSD data output)

59 BCKAI I Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used
60 BCKAO O Bit clock signal (2.8224 MHz) output terminal for DSD data output
61 PHREFI I Bit clock signal (2.8224 MHz) input terminal for DSD data output Not used

Soft muting on/off control signal input from the mechanism controller
“H”: muting on

Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for
DSD data output “L”: input (slave), “H”: output (master) Fixed at “H” in this set

97

HCD-SR4W

Pin No. Pin Name I/O Description

62 PHREFO O Bit clock signal (2.8224 MHz) output to the digital audio processor Not used
63 ZDFL O Front L-ch Zero data flag detection signal output terminal Not used
64 DSAL O Front L-ch DSD data output to the digital audio processor
65 ZDFR O Front R-ch Zero data flag detection signal output terminal Not used
66 DSAR O Front R-ch DSD data output to the digital audio processor
67 VDDSD0 — Power supply terminal (+3.3V) (for DSD data output)
68 ZDFC O Center zero data flag detection signal output terminal Not used
69 DSAC O Center DSD data output to the digital audio processor
70 ZDFLFE O Woofer zero data flag detection signal output terminal Not used
71 DSALFE O Woofer DSD data output to the digital audio processor
72 VSDSD1 — Ground terminal (for DSD data output)
73 ZDFLS O Rear L-ch zero data flag detection signal output terminal Not used
74 DSALS O Rear L-ch DSD data output to the digital audio processor
75 ZDFRS O Rear R-ch zero data flag detection signal output terminal Not used
76 DSARS O Rear R-ch DSD data output to the digital audio processor
77 VDDSD — Power supply terminal (+3.3V) (For DSD data output)

78, 79 IOUT0, IOUT1 O Data output terminal for IEEE 1394 link chip interface Not used

80 VSCB0 — Ground terminal (for core)

81, 82 IOUT2, IOUT3 O Data output terminal for IEEE 1394 link chip interface Not used

83 VDCB0 — Power supply terminal (+2.5V) (for core)

84, 85 IOUT4, IOUT5 O Data output terminal for IEEE 1394 link chip interface Not used

86 VSIOB0 — Ground terminal (for I/O)

87 IANCO O

88 IFULL I

89 IEMPTY I
90 VDIOB0 — Power supply terminal (+3.3V) (for I/O)

91 IFRM O Frame reference signal output terminal for IEEE 1394 link chip interface Not used
92 IOUTE O Enable signal output terminal for IEEE 1394 link chip interface Not used

93 IBCK O
94 VSCB1 — Ground terminal (for core)

95 IERR I Not used
96 IANCI I Not used
97 IPLAN I Not used
98 IHOLD O Not used
99 VDCB1 — Power supply terminal (+2.5V) (for core)

100 IVLD I Not used

101 to 105 IDIN0 to IDIN4 I Not used

106 VSIOB1 — Ground terminal (for I/O)

107 to 109 IDIN5 to IDIN7 I Not used

110 VDIOB1 — Power supply terminal (+3.3V) (for I/O)

111 to 114 WAD0 to WAD3 I External A/D data input terminal for PSP physical disc mark detection Not used

115 TESTI I Input terminal for the test (normally: fixed at “L”)
116 VSCB2 — Ground terminal (for core)

Transmission information data output terminal for IEEE 1394 link chip interface
Not used
Data transmission hold request signal input terminal for IEEE 1394 link chip
interface Not used
High speed transmission request signal input terminal for IEEE 1394 link chip
interface Not used

Data transmission clock signal output terminal for IEEE 1394 link chip interface
Not used

98

HCD-SR4W

Pin No. Pin Name I/O Description

117 to 120 WAD4 to WAD7 I External A/D data input terminal for PSP physical disc mark detection Not used

121 VDCB2 — Power supply terminal (+2.5V) (for core)

122 WRFD I Not used

123 WCK I
124, 125 WAVDD0, WAVDD1 — A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)

126 WARFI I

127 WAVRB I A/D bottom reference terminal for PSP physical disc mark detection
128, 129 WAVSS0, WAVSS1 — A/D ground terminal (for PSP physical disc mark detection)

130 VSIO — Ground terminal (for I/O)

131 to 134 DQ7 to DQ4 I/O Two-way data bus with the SD-RAM

135 VDIOA2 — Power supply terminal (+3.3V) (for I/O)

136 to 139 DQ3 to DQ0 I/O Two-way data bus with the SD-RAM

140 VSIOA3 — Ground terminal (for I/O)

141 DCLK O Clock signal output to the SD-RAM

142 DCKE O Clock enable signal output to the SD-RAM

143 XWE O Write enable signal output to the SD-RAM

144 XCAS O Column address strobe signal output to the SD-RAM

145 XRAS O Row address strobe signal output to the SD-RAM

146 VDIOA3 — Power supply terminal (+3.3V) (for I/O)

147 NC O Not used
148, 149 A11, A10 O Address signal output to the SD-RAM

150 VSCA3 — Ground terminal (for core)
151, 152 A9, A8 O Address signal output to the SD-RAM

153 VDCA3 — Power supply terminal (+2.5V) (for core)

154 to 157 A7 to A4 O Address signal output to the SD-RAM

158 VSIOA4 — Ground terminal (for I/O)

159 to 162 A3 to A0 O Address signal output to the SD-RAM

163 VDIOA4 — Power supply terminal (+3.3V) (for I/O)

164 XSRQ O Serial data request signal output to the DVD decoder

165 XSHD I Header flag signal input from the DVD decoder

166 SDCK I Serial data transfer clock signal input from the DVD decoder

167 XSAK I Serial data effect flag signal input from the DVD decoder

168 SDEF I Error flag signal input from the DVD decoder

169 to 176 SD0 to SD7 I Stream data signal input from the DVD decoder

Operation clock signal input for PSP physical disc mark detection from the DVD
decoder

Analog RF signal input for PSP physical disc mark detection from the DVD/CD
RF amplifier

99

HCD-SR4W

DMB08 BOARD IC901 uPD703033BYGF-M59-3BA-A (SYSTEM CONTROLLER)

Pin No. Pin Name I/O Description

1DAMP-DATA O Serial data output to the stream processors
2DAMP-CLK O Serial data transfer clock signal output to the stream processors

3 I2C-DATA I/O
4 CQ-RST O Reset signal output to the DVD system processor “L”: reset

5 I2C-CLK I/O
6 DSP-DO I Write data input from the audio digital signal processor

7 DIG-DI O

8DIG-CLK O

9 EVDD — Power supply terminal (+5V)
10 EVSS — Ground terminal
11 P-PWM O PWM voltage control signal output
12 DSP-RST O Reset signal output to the audio digital signal processor “L”: reset
13 DSP-PM O PLL reset signal output to the audio digital signal processor “L”: reset
14 DSP-CS O Chip select signal output to the audio digital signal processor
15 DSP-HACN I Acknowledge signal input from to the audio digital signal processor
16 DSP-BST O Boot strap signal output to the audio digital signal processor
17 DSP-GP9 I Decode signal input from to the audio digital signal processor
18 DIR-ZERO I Audio serial data input from the digital audio interface IC
19 DIR-ERR I PLL lock error and data error flag input from the digital audio interface IC
20 DIR-CE O Chip enable signal output to the digital audio interface IC
21 VPP — Power supply terminal (for programming) Not used
22 DIR-XST I Source clock switching monitor input from the digital audio interface IC
23 DIR-AD O Muting signal output
24 DIR-XMODE O System reset signal output to the digital audio interface IC “L”: reset
25 DIRDO I Write data input from the digital audio interface IC
26 DAMP-RST O Reset signal output to the stream processors “L”: reset
27 GP12 — Not used (fixed at “L”)
28 DAMP-MUTEN O Muting on/off control signal output to the stream processors “H”: muting on
29 CS1 O Chip select signal output to the stream processor (for front L-ch and R-ch)
30 CS2 O Chip select signal output to the stream processor (for center and woofer)
31 CS3 O Chip select signal output to the stream processor (for rear L-ch and R-ch)
32 DAC-CS O Chip select signal output to the D/A converter
33 AD-RST O Reset signal output to the A/D converter and D/A converter “L”: reset

34 RESET I For several hundreds msec. after the power supply rises, “L” is input, then it

35 XT1 I Sub system clock input terminal Not used (open)
36 XT2 O Sub system clock output terminal Not used (open)
37 REGC — Capacitance connection terminal
38 X2 O Main system clock output terminal (20 MHz)
39 X1 I Main system clock input terminal (20 MHz)
40 VSS — Ground terminal
41 VDD — Power supply terminal (+5V)

Communication data bus with the DVD system processor and mechanism
controller

Communication data reading clock signal input or transfer clock signal output
with the DVD system processor and mechanism controller

Read data output to the digital audio interface IC, audio digital signal processor
and D/A converter
Clock signal output to the digital audio interface IC, audio digital signal processor
and D/A converter

System reset signal input “L”: reset

changes to “H”

100