Sipex Corporation SP690RCN, SP690RCP, SP690REN, SP690REP, SP690SCN Datasheet

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SP690T/S/R, SP802T/S/R,

SP804T/S/R, and SP805T/S/R

3.0V/3.3V Low P o wer Micropr ocessor

Supervisory with Battery Switch-Over

The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices are a family of

microprocessor (µP) supervisory circuits that integrate a myriad of components involved in

discrete solutions to monitor power-supply and battery-control functions in µP and digital

systems. The series will significantly improve system reliability and operational efficiency

when compared to discrete solutions. The features of the SP690T/S/R, SP802T/S/R,

SP804T/S/R and SP805T/S/R devices include a watchdog timer, a µP reset and backup-

battery switchover, and power-failure warning; a complete µP monitoring and watchdog

solution. The series is ideal for 3.0V or 3.3V applications in portable electronics, computers,

controllers, and intelligent instruments and is a solid match for designs where it is critical to

monitor the power supply to the µP and it’s related digital components. Refer to Sipex's

SP690A/692A/802L/802M/805L/805M series for similar devices designed for +5V systems.

■ RESET and RESET Outputs

■ Reset asserted down to V

= 1V

■ Reset Time Delay - 200ms

■ Watchdog Timer - 1.6 sec timeout

■ 40µA Maximum V

Supply Current

■ 1µA Maximum Battery Supply Current

■ Power Switching

50mA Output in V

Mode (1.5Ω)

10mA Output in Battery Mode (15Ω)

■ Battery Can Exceed V

in Normal Operation

■ Precision Voltage Monitor for Power-Fail

or Low-Battery Warning

■ Available in 8 pin SO and DIP packages

■ Pin Compatible Upgrades to

MAX690T/S/R, MAX802T/S/R,

MAX804T/S/R, MAX805T/S/R

DESCRIPTION

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ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation

sections of the specifications below is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect

reliability and cause permanent damage to the device.

..................................................................................-0.3V to 6.0V

BATT

................................................................................-0.3V to 6.0V

All Other Inputs (NOTE 1).................................-0.3V to the higher of V

or V

BATT

Continuous Input Current:

..................................................................................100mA

BATT

..................................................................................20mA

GND..................................................................................20mA

WDI, PFI...........................................................................20mA

Continuous Output Current:

RESET, RESET, PFO.........................................................20mA

OUT

......................................................................................100mA

Power Dissipation per Package:

8pin NSOIC (derate 6.14mW/°C above +70°C)..............500mW

8pin PDIP (derate 11.8mW/°C above +70°C)..............1,000mW

Storage Temperature........................................-65°C to +160°C

Lead Temperature(soldering,10sec).............................................+300°C

ESD Rating........................................................4KV Human Body Model

SPECIFICATIONS

= 3.17V to 5.50V for the SP690T/SP80_T, V

= 3.02V to 5.50V for the SP690S/SP80_S, V

= 2.72V to 5.50V for the SP690R/SP80_R, V

BATT

= 3.60V, and

= T

MIN

to T

MAX

unless otherwise noted. Typical values taken at T

AMB

= +25

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SPECIFICATIONS (continued)

= 3.17V to 5.50V for the SP690T/SP80_T, V

= 3.02V to 5.50V for the SP690S/SP80_S, V

= 2.72V to 5.50V for the SP690R/SP80_R, V

BATT

= 3.60V, and

= T

MIN

to T

MAX

unless otherwise noted. Typical values taken at T

AMB

= +25

SPECIFICATIONS (continued)

= 3.17V to 5.50V for the SP690T/SP80_T, V

= 3.02V to 5.50V for the SP690S/SP80_S, V

= 2.72V to 5.50V for the SP690R/SP80_R, V

BATT

= 3.60V, and

= T

MIN

to T

MAX

unless otherwise noted. Typical values taken at T

AMB

= +25

NOTE 1: The following are tested at V

BATT

= 3.6V and V

= 5.5V: V

supply current, watchdog

functionality, logic input leakage, PFI functionality, and the RESET and RESET states. The state of

RESET or RESET and PFO is tested at V

= V

(min).

NOTE 2: Tested V

BATT

= 3.6V, V

= 3.5V and 0V.

NOTE 3: Leakage current into the battery is tested under the following worst-case conditions: V

= 5.5V, V

BATT

= 1.8V and at V

= 1.5V, V

BATT

= 1.0V.

NOTE 4: "-" equals the battery-charging current, "+" equals the battery-discharging current.

NOTE 5: When V

> V

BATT

, V

OUT

remains connected to V

until V

drops below V

BATT

. The

-to-V

BATT

comparator has a small 25mV typical hysteresis to prevent oscillation.

NOTE 6: When V

BATT

> V

, V

OUT

remains connected to V

until V

drops below the battery

switch threshold, V

NOTE 7: V

OUT

switches from V

BATT

to V

when V

rises above the reset threshold, independent of

BATT

. Switchover back to V

occurs at the exact voltage that causes RESET to go HIGH (on the

SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset.

NOTE 8: The reset threshold tolerance is wider for V

rising than for V

falling to accommodate the

10mV typical hysteresis, which prevents internal oscillation.

NOTE 9: SP690_ and SP802_ devices only.

NOTE 10: SP804_ and SP805_ devices only.

NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET

output high impedance).

INTERNAL BLOCK DIAGRAM

1.25V

BATTERY

SWITCHOVER

CIRCUIT

PFI

WATCHDOG

TIMER

RESET

GENERATOR

BATTERY

SWITCHOVER

COMPARATOR

RESET

COMPARATOR

1.25V

WDI

BATT

PFO

RESET / RESET*

SP690T/S/R

SP802T/S/R

SP804T/S/R

SP805T/S/R

*SP804T/S/R and SP805T/S/R only

POWER-FAIL

COMPARATOR

OUT

GND

PIN ASSIGNMENTS

Pin 1 —V

OUT

— Output Supply Voltage for

CMOS RAM. When V

is above the

reset threshold, V

OUT

connects to V

through a P-channel MOSFET switch.

When V

falls below the V

and

BATTERY

, V

BATTERY

connects to V

OUT

Connect to V

if no battery is used.

Pin 2 — V

— +5V Supply Input

Pin 3 — GND — Ground reference for all

signals

Pin 4 — PFI — Power-Fail Comparator Input.

When PFI is less than 1.25V or when V

falls below the V

, PFO goes LOW,

otherwise PFO remains HIGH. Connect

to GND if unused.

Pin 5 — PFO — Power-Fail Comparator

Output. Leave open if unused.

Pin 6 — WDI — Watchdog Input. If WDI

remains HIGH or LOW for 1.6 seconds,

the internal watchdog timer triggers a

reset. The internal watchdog timer clears

when reset is asserted or WDI sees a

rising or falling edge. The watchdog

function cannot be disabled.

Pin 7 for SP690_/802_ only — Active-LOW

Reset Output. — Whenever RESET is

triggered by a watchdog timeout, it goes

LOW for 200ms. It stays LOW whenever

is below the reset threshold and re-

mains LOW for 200ms after V

rises

above the reset threshold or when the

watchdog triggers a reset.

Pin 7 for SP804_/805_ only — Active-HIGH

Open-Drain Reset Output. — The

inverse operation of RESET.

Pin 8 — V

BATTERY

— Backup-Battery Input.

When V

falls below V

and V

BATTERY

OUT

switchesfrom V

to V

BATTERY

When V

rises above the reset threshold,

OUT

reconnects to V

. V

BATTERY

may

exceed V

. Connect to V

if no battery

is used.

OUT

GND

PFI

BATTERY

RESET / RESET*

WDI

PFO

*SP804T/S/R and SP805T/S/R only

SP690T/S/R

SP802T/S/R

SP804T/S/R

SP805T/S/R

PINOUT

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