Siemens SAB-C501G-L24N, SAB-C501G-L24P, SAB-C501G-L40M, SAB-C501G-L40N, SAB-C501G-L40P Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C501

Data Sheet 04.97

C501 Data Sheet
Revision History :

1997-04-01
Previous Releases : 11.92, 11.93, 08.94, 08.95, 10.96
Page

(previous
version)

Page
(new
version)

Subjects (changes since last revision)

general C501G-1E OTP version included
4

5
5-7
11
8, 9, 10

4
5
5-7
11
8, 9, 10

Ordering information resorted and C501G-1E types added
Table with literature hints added
Pin configuration logic symbol for pins EA
Pin description for ALE/PROG and EA/Vpp completed
Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi-

bidirectional”
13
14

­15-18
17

-

­41

-

13
14
15
16-18
17
25-28
31
41
43, 44

Block diagram updated for C501G-1E

New design of register (PSW) description

“Memory organization” added

Actualized design of the SFR tables

Reset value of T2CON corrected

Description for the C501-1E OTP version added

DC characteristics for C501-1E added

Timing “External Clock Drive” now behind “Data Memory Cycle”

AC characteristics for C501-1E added

/Vpp and ALE/PROG updated

Edition 1997-04-01
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

©

Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Preliminary

Fully compatible to standard 8051 microcontroller

•

Versions for 12/24/40 MHz operating frequency

•

Program memory : completely external (C501-L)

•

8K × 8 ROM (C501-1R)
8K × 8 OTP memory (C501-1E)

256 × 8 RAM

•

Four 8-bit ports

•

Three 16-bit timers / counters (timer 2 with up/down counter feature)

•

USART

•

Six interrupt sources, two priority levels

•

Power saving modes

•

Quick Pulse programming algorithm (C501-1E only)

•

2-Level program memory lock (C501-1E only)

•

P-DIP-40, P-LCC-44, and P-MQFP-44 package

•

Temperature ranges : SAB-C501

•

SAF-C501

: 0 ˚C to 70 ˚C

T

A

: – 40 ˚C to 85 ˚C

T

A

C501

C501

Power
Saving
Modes

T2

Figure 1
C501G Functional Units

RAM

256 x 8

T0

CPU

T1

8K x 8 ROM (C501-1R)
8K x 8 OTP (C501-1E)

USART

Port 0

Port 1

Port 2

Port 3

Ι

/O

Ι

/O

Ι

/O

Ι

/O

MCA03238

Semiconductor Group 3 1997-04-01

C501

The C501-1R contains a non-volatile 8K × 8 read-only program memory, a volatile 256 × 8 read/
write data memory, four ports, three 16-bit timers counters, a seven source, two priority level
interrupt structure and a serial port. The C501-L is identical, except that it lacks the program
memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip.
The term C501 refers to all versions within this specification unless otherwise noted. Further, the
term C501 refers to all versions which are available in the different temperature ranges, marked with

SAB-C501... or SAF-C501.... .

Ordering Information
Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C501G-LN
SAB-C501G-LP
SAB-C501G-LM

SAB-C501G-L24N
SAB-C501G-L24P
SAB-C501G-L24M

SAB-C501G-L40N
SAB-C501G-L40P
SAB-C501G-L40M

SAF-C501G-L24N
SAF-C501G-L24P

SAB-C501G-1RN
SAB-C501G-1RP
SAB-C501G-1RM

SAB-C501G-1R24N
SAB-C501G-1R24P
SAB-C501G-1R24M

SAB-C501G-1R40N
SAB-C501G-1R40P
SAB-C501G-1R40M

Q67120-C969
Q67120-C968
Q67127-C970

Q67120-C1001
Q67120-C999
Q67127-C1014

Q67120-C1002
Q67120-C1000
Q67127-C1009

Q67120-C1011
Q67120-C1010

Q67120-DXXX
Q67120-DXXX
Q67127-DXXX

Q67120-DXXX
Q67120-DXXX
Q67127-DXXX

Q67120-DXXX
Q67120-DXXX
Q67127-DXXX

P-LCC-44
P-DIP-40
P-MQFP-44

P-LCC-44
P-DIP-40
P-MQFP-44

P-LCC-44
P-DIP-40
P-MQFP-44

P-LCC-44
P-MQFP-44

P-LCC-44
P-DIP-40
P-MQFP-44

P-LCC-44
P-DIP-40
P-MQFP-44

P-LCC-44
P-DIP-40
P-MQFP-44

for external memory (12 MHz)

for external memory (24 MHz)

for external memory (40 MHz)

for external memory (24 MHz)
ext. temp. – 40 ˚C to 85 ˚C

with mask-programmable ROM (12 MHz)

with mask-programmable ROM (24 MHz)

with mask-programmable ROM (40 MHz)

SAF-C501G-1R24N
SAF-C501G-1R24P

SAB-C501G-1EN
SAB-C501G-1EP

SAF-C501G-1EN
SAF-C501G-1EP

SAB-C501G-1E24N
SAB-C501G-1E24P

SAF-C501G-1E24N
SAF-C501G-1E24P

Semiconductor Group 4 1997-04-01

Q67120-DXXX
Q67120-DXXX

Q67120-C1054
Q67120-C1056

Q67120-C2002
Q67120-C2003

Q67120-C2005
Q67120-C2006

Q67120-C2008
Q67120-C2009

P-LCC-44
P-DIP-40

P-LCC-44
P-DIP-40

P-LCC-44
P-DIP-40

P-LCC-44
P-DIP-40

P-LCC-44
P-DIP-40

with mask-programmable ROM (24 MHz)
ext. temp. – 40 ˚C to 85 ˚C

with OTP memory (12 MHz)

with OTP memory (12 MHz))
ext. temp. – 40 ˚C to 85 ˚C

with OTP memory (24 MHz)

with OTP memory (24 MHz))
ext. temp. – 40 ˚C to 85 ˚C

Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request.

The ordering number of ROM types (DXXX extensions) is defined after program release
(verification) of the customer.

Additional Literature

For further information about the C501 the following literature is available :

Title Ordering Number

C501 8-Bit CMOS Microcontroller User’s Manual B158-H6723-X-X-7600

C501

C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

CC

P0.1/AD1

P1.3

P1.4

6 5 4 3 2 1 44 43 42 41 40

P1.5
P1.6
P1.7

RESET P0.7/AD7

RxD/P3.0

N.C.

TxD/P3.1
INT0/P3.2
INT1/P3.3

T0/P3.4
T1/P3.5

8
9

10

11
12
13
14
15
16
17

P1.2

P1.1/T2EX

N.C

P1.0/T2

C501

P0.0/AD0

V

P0.3/AD3

P0.2/AD2

397
38
37
36
35
34
33
32

31
30
29

2827262524232221201918

P0.4/AD4
P0.5/AD5
P0.6/AD6

EA/

V

PP

N.C.
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13

MCP03214

XTAL2

RD/P3.7

WR/P3.6

SS

V

XTAL1

N.C.

P2.1/A9

P2.0/A8

P2.3/A11

P2.2/A10

P2.4/A12

Figure 2
Pin Configuration P-LCC-44 Package (Top view)

Semiconductor Group 5 1997-04-01

C501

T2/P1.0

T2EX/P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RxD/P3.0

TxD/P3.1

INT0/P3.2

1
2
3
4
5
6
7
8
9
10
11
12

C501

40
39
38
37
36
35
34
33
32

31
30
29

V

CC

P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7RESET
EA/

V

PP

ALE/PROG
PSEN

INT1/P3.3

13
14

T1/P3.5

15
16

RD/P3.7

XTAL2

XTAL1

17
18
19
20

V

SS

Figure 3
Pin Configuration P-DIP-40 Package (top view)

28
27
26
25
24
23
22

21

MCP03215

P2.7/A15
P2.6/A14T0/P3.4
P2.5/A13
P2.4/A12WR/P3.6
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8

Semiconductor Group 6 1997-04-01

P0.6/AD6

P0.5/AD5

P0.4/AD4

PP

V

EA/

N.C.

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

C501

P0.3/AD3

33

P0.2/AD2

P0.1/AD1

P0.0/AD0

V

CC

N.C.

C501

P1.0/T2

P1.1/T2EX

P1.2
P1.3
P1.4 WR/P3.6

44 12

P1.5

P1.6

P1.7

N.C.

RESET P0.7/AD7

RxD/P3.0

Figure 4
Pin Configuration P-MQFP-44 Package (top view)

10987654321

TxD/P3.1

INT0/P3.2

INT1/P3.3

23242526272829303132

2234

2135
2036
1937
1838
1739
1640
1541
1442
1343

11

T0/P3.4

T1/P3.5 P2.5/A13

P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
N.C.

V

SS

XTAL1
XTAL2
RD/P3.7

MCP03216

VV

CC

XTAL1
XTAL2

SS

Port 0
8-Bit Digital

Ι/O

Port 1

/OΙ8-Bit Digital

RESET
EA

/

V

PP

C501

Port 2

/OΙ8-Bit Digital

ALE/PROG

Port 3

PSEN

MCL03217

/OΙ8-Bit Digital

Figure 5
Logic Symbol

Semiconductor Group 7 1997-04-01

Table 1
Pin Definitions and Functions

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

C501

P1.0 – P1.7 2–9

2
3

*) I = Input

O = Output

1–8

1
2

40–44,
1–3,

40
41

I/O Port 1

is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 1 pins that
have 1s written to them are pulled high by
the internal pullup resistors, and in that
state can be used as inputs. As inputs,
port 1 pins being externally pulled low will
source current (
istics) because of the internal pull-up
resistors. Port 1 also contains the timer 2
pins as secondary function. The output
latch corresponding to a secondary
function must be pro-grammed to a one
(1) for that function to operate.
The secondary functions are assigned to
the pins of port 1, as follows:
P1.0 T2 Input to counter 2
P1.1 T2EX Capture - Reload trigger of

I

, in the DC character-

IL

timer 2 / Up-Down count

Semiconductor Group 8 1997-04-01

Table 1
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

C501

P3.0 – P3.7 11,

13–19

11

13

14

15

16
17
18

19

10–17

10

11

12

13

14
15
16

17

5, 7–13

5

7

8

9

10
11
12

13

I/O Port 3

is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 3 pins that
have 1s written to them are pulled high by
the internal pull-up resistors, and in that
state they can be used as inputs. As
inputs, port 3 pins being externally pulled
low will source current (
characteristics) because of the internal
pull-up resistors. Port 3 also contains the
interrupt, timer, serial port 0 and external
memory strobe pins which are used by
various options. The output latch
corresponding to a secondary function
must be programmed to a one (1) for that
function to operate.
The secondary functions are assigned to
the pins of port 3, as follows:
P3.0 R × D receiver data input (asyn-

P3.1 T × D transmitter data output

P3.2 INT

P3.3 INT1 interrupt 1 input/timer 1

P3.4 T0 counter 0 input
P3.5 T1 counter 1 input
P3.6 WR the write control signal lat-

P3.7 RD the read control signal

I

, in the DC

IL

chronous) or data input
output (synchronous) of
serial interface 0

(asynchronous) or clock
output (synchronous) of
the serial interface 0

0 interrupt 0 input/timer 0

gate control

gate control

ches the data byte from
port 0 into the external
data memory

enables the external data
memory to port 0

*) I = Input

O = Output

Semiconductor Group 9 1997-04-01

Table 1
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

C501

XTAL2 20 18 14 –

XTAL2

Output of the inverting oscillator
amplifier.

XTAL1 21 19 15 –

XTAL1

Input to the inverting oscillator amplifier
and input to the internal clock generator
circuits.
To drive the device from an external
clock source, XTAL1 should be driven,
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, since the input
to the internal clocking circuitry is divided
down by a divide-by-two flip-flop.
Minimum and maximum high and low
times as well as rise fall times specified
in the AC characteristics must be
observed.

P2.0 – P2.7 24–31 21–28 18–25 I/O Port 2

is a quasi-bidirectional I/O port with
internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high
by the internal pull-up resistors, and in
that state they can be used as inputs. As
inputs, port 2 pins being externally pulled
low will source current (
characteristics) because of the internal
pull-up resistors. Port 2 emits the high­order address byte during fetches from
external program memory and during
accesses to external data memory that
use 16-bit addresses (MOVX @DPTR).
In this application it uses strong internal
pull-up resistors when issuing 1s. During
accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port
2 issues the contents of the P2 special
function register.

, in the DC

I

IL

*) I = Input

O = Output

Semiconductor Group 10 1997-04-01

Table 1
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

C501

PSEN

32 29 26 O

RESET 10 9 4 I

ALE/PROG

33 30 27 I/O The Address Latch Enable

The Program Store Enable

output is a control signal that enables the
external program memory to the bus
during external fetch operations. It is
activated every six oscillator periods
except during external data memory
accesses. Remains high during internal
program execution.

RESET

A high level on this pin for two machine
cycles while the oscillator is running
resets the device. An internal diffused
resistor to
using only an external capacitor to

permits power-on reset

V

SS

.

V

CC

output is used for latching the low-byte of
the address into external memory during
normal operation. It is activated every six
oscillator periods except during an
external data memory access.
For the C501-1E this pin is also the
program pulse input (PROG) during OTP
memory programming.

EA

/

V

PP

35 31 29 I

External Access

Enable

When held at high level, instructions are
fetched from the internal ROM (C501-1R
and C501-1E) when the PC is less than
2000H. When held at low level, the C501
fetches all instructions from external
program memory. For the C501-L this
pin must be tied low.
This pin also receives the programming
supply voltage

V

during OTP memory

PP

programming (C501-1E) only).

*) I = Input

O = Output

Semiconductor Group 11 1997-04-01

Table 1
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-LCC-44 P-DIP-40 P-MQFP-44

P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0

is an 8-bit open-drain bidirectional I/O
port. Port 0 pins that have 1s written to
them float, and in that state can be used
as high-impedance inputs. Port 0 is also
the multiplexed low-order address and
data bus during accesses to external
program or data memory. In this
application it uses strong internal pull-up
resistors when issuing 1s.
Port 0 also outputs the code bytes during
program verification in the C501-1R and
C501-1E. External pull-up resistors are
required during program verification.

C501

V

SS

V

CC

22 20 16 – Circuit ground potential
44 40 38 – Supply terminal for all operating modes

N.C. 1, 12,

23, 34

*) I = Input

O = Output

– 6, 17,

28, 39

– No connection

Semiconductor Group 12 1997-04-01

C501

Functional Description

The C501 is fully compatible to the standard 8051 microcontroller family.
It is compatible with the 80C32/52/82C52. While maintaining all architectural and operational

characteristics of the 8051microcontroller family, the C501 incorporates some enhancements in the
timer 2 unit.

Figure 6 shows a block diagram of the C501.

V

CC

V

SS

XTAL1
XTAL2

RESET
ALE/PROG
PSEN

EA/

V

PP

C501

OSC & Timing

Serial Channel

CPU

Timer 0

Timer 1

Timer 2

Interrupt Unit

(USART)

RAM

256 x 8

C501-1R : ROM

C501-1E : OTP

8K x 8

Port 0

Port 1

Port 2

Port 3

Port 0

8-Bit Digit.

Port 1
8-Bit Digit.

Port 2
8-Bit Digit.

Port 3
8-Bit Digit.

Ι/O

Ι/O

Ι/O

/OΙ

MCB03219

Figure 6
Block Diagram of the C501

Semiconductor Group 13 1997-04-01

C501

CPU

The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs
24 MHz: 500 ns, 40 MHz : 300 ns).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H
H
H
H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-04-01

Memory Organization

The C501 CPU manipulates data and operands in the following four address spaces:

– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128 byte special function register area

Figure 7 illustrates the memory address spaces of the C501.

C501

External

Internal

"Code Space"

FFFF

2000

External
(EA = 0)(EA = 1)

H

H

1FFF

0000

FFFF

H

External

Indirect

Address

FF

H

Internal

RAM

80

H

H

0000

H

"Data Space" "Internal Data Space"

H

Internal

RAM

Direct

Address

Special
Function
Register

7F

H

00

H

MCD03224

FF

80

H

H

Figure 7
C501 Memory Map

Semiconductor Group 15 1997-04-01