Siemens HYB314265BJ-45, HYB314265BJ-50, HYB314265BJL-45, HYB314265BJL-50, HYB514265BJ-400 Datasheet

256K x 16-Bit EDO-Dynamic RAM

Preliminary Information

HYB 514265BJ-400/40/-45/-50

HYB 314265BJ(L)-45/-50

• 262 144 words by 16-bit organization

• 0 to 70 °C operating temperature

• EDO - Hyper Page Mode

• Performance:

-400 -40 -45 -50

t

rc

t

rac

t

cac

t

aa

t

hpc

t

hpc

• Low Power dissipation

69 69 79 89 ns
40 40 45 50 ns
10 10 12 13 ns
20 20 22 25 ns

12,5 15 18 20 ns

80 66 55 50 MHz

- Active(max.):
120mA / 120mA / 105mA / 95 mA

- Standby : TTL Inputs (max.) 2.0 mA

- Standby: CMOS Inputs (max.) 1.0 mA

- Standby (L-version) 200 µA

• Power Supply:

HYB 514265BJ-400 +5 V ±5%
HYB 514265BJ-40 +5 V ±10%
HYB 514265BJ-45 +5 V ±10%
HYB 514265BJ-50 +5 V ±10%
HYB 314265BJ(L)-45 +3.3 V ±0.3 V
HYB 314265BJ(L)-50 +3.3 V ±0.3 V

• Read, write, read-modify-write, CAS -before

RAS refresh, RAS only refresh, hidden refresh
mode

• Low Power Version (L) with Self Refresh

and 250 µA self refresh current

• 2 CAS / 1 WE control

• All inputs and outputs TTL-compatible

• 512 refresh cycles / 16 ms

512 refresh cycles / 128 ms (L-version)

• Plastic Packages: P-SOJ-40-3 400 mil width

The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process
as well as advanced circuit techniques to provide wide operation margins, both internally and for the
system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a
standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit
densities and is compatible with commonly used automatic testing and insertion equipment.

The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh.

Semiconductor Group 1

6.96

Ordering Information

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Type Ordering

Package Description

Code

5 V versions:

HYB 514265BJ-400 Q67100-3033 P-SOJ-40-3 5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-40 Q67100-3039 P-SOJ-40-3 5 V 40 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-45 Q67100-3035 P-SOJ-40-3 5 V 45 ns 256 K x 16 EDO-DRAM
HYB 514265BJ-50 Q67100-3036 P-SOJ-40-3 5 V 50 ns 256 K x 16 EDO-DRAM

3.3 V versions:

HYB 314265BJ-45 on request P-SOJ-40-3 3.3 V 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJ-50 on request P-SOJ-40-3 3.3 V 50 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-45 on request P-SOJ-40-3 3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM
HYB 314265BJL-50 on request P-SOJ-40-3 3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM

Truth Table
RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation

H
L
L
L
L
L
L
L
L

H
H
L
H
L
L
H
L
L

H
H
H
L
L
H
L
L
L

H
H
H
H
H
L
L
L
H

H
H
L
L
L
H
H
H
H

High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z

High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z

Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write

Pin Names

A0-A8 Address Inputs
RAS Row Address Strobe
UCAS, LCAS Column Address Strobe
WE Read/Write Input
OE Output Enable
I/O1 – I/O16 Data Input/Output

V

CC

Power Supply:
+ 5 V for HYB 514265,
+ 3.3 V for HYB 314265

V

SS

Ground (0 V)

N.C. No Connection

Semiconductor Group 2

Pin Configuration

(top view)

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

P-SOJ-40-3

Semiconductor Group 3

Block Diagram

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Semiconductor Group 4

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Absolute Maximum Ratings

Operating temperature range ........................................................................................ 0 to + 70 °C

Storage temperature range..................................................................................... – 55 to + 150 °C

Input/output voltage for HYB 514265................................................ – 0.5 to min. (VCC + 0.5, 7.0) V

Power supply voltage for HYB 514265...........................................................................– 1 to + 7 V

Input/output voltage for HYB 314265................................................ – 0.5 to min. (VCC + 0.5, 4.6) V

Power supply voltage for HYB 314265.....................................................................– 0.5 to + 4.6 V

Data out current (short circuit) ................................................................................................ 50 mA

Note:

Stresses above those listed under“Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

DC Characteristics for HYB514265

T

= 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 % (± 5 % for -400 version) , tT = 2 ns

A

Parameter Symbol Limit Values Unit Notes

min. max.

Input high voltage V
Input low voltage V
Output high voltage (I
Output low voltage (I

= – 5.0 mA) V

OUT

= 4.2 mA) V

OUT

Input leakage current, any input

IH

IL

OH

OL

I

I(L)

2.4 VCC + 0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V
– 10 10 µA

1
1
1
1
1

(0 V < VIN < 7 V, all other inputs = 0 V)
Output leakage current

(DO is disabled, 0 V < V

OUT

< VCC)

Average VCC supply current:

-400 version

-40 version

-45 version

-50 version

Standby VCC supply current

(RAS = LCAS = UCAS = WE = VIH)

Average VCC supply current during RAS-only
refresh cycles: -400 version

-40 version

-45 version

-50 version

I

I

I

I

O(L)

CC1

CC2

CC3

– 10 10 µA

–

120

mA
120
105
95

– 2 mA –

–

120

mA
120
105
95

1

2, 3, 4

2, 4

Semiconductor Group 5

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Parameter Symbol Limit Values Unit Notes

min. max.

Average VCC supply current during
hyper page mode (EDO) operation: -400 version

-40 version

-45 version

-50 version

Standby VCC supply current

(RAS = LCAS = UCAS = WE = VCC – 0.2 V)

Standby VCC supply current (L-version only)

(RAS = LCAS = UCAS = WE = VCC – 0.2 V)

Average VCC supply current during
CAS-before-RAS refresh mode: -400 version

-40 version

-45 version

-50 version

I

I

I

I

CC4

CC5

CC5

CC6

–

110

mA

2, 3, 4

90
75
65

–1 mA

– 200 µA

1

1

–

120

mA

2, 4

120
105
95

DC Characteristics for 314265

T

= 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 2 ns

A

Parameter Symbol Limit Values Unit Test

Condition

1
1
1
1
1
1
1

1

2, 3, 4

Input high voltage
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
CMOS Output high voltage (I
CMOS Output low voltage (I

= – 2.0 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

= 100 µA) V

OUT

Input leakage current, any input

(0 V < VIN < VCC + 0.3 V, all other inputs = 0 V)

Output leakage current

(DO is disabled, 0 V < V

< VCC+ 0.3 V)

OUT

Average VCC supply current:

-45 version

-50 version

V

I

I

I

IH

IL

OH

OL

OH

OL

I(L)

O(L)

CC1

min. max.

2.0 VCC + 0.5 V
– 0.5 0.8 V

2.4 – V
– 0.4 V

2.4 – V
– 0.4 V
– 10 10 µA

– 10 10 µA

–

105

mA

95

Standby VCC supply current

(RAS = LCAS = UCAS = WE = VIH)

Semiconductor Group 6

I

CC2

– 2 mA –

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Parameter Symbol Limit Values Unit Test

min. max.

Condition

Average VCC supply current during
RAS-only refresh cycles:

-45 version

-50 version

Average VCC supply current during hyper page
mode (EDO) operation:

-45 version

-50 version

Standby VCC supply current

(RAS = LCAS = UCAS = WE = VCC – 0.2 V)

Standby VCC supply current (L-version only)

(RAS = LCAS = UCAS = WE = VCC – 0.2 V)

Average VCC supply current during CAS­before-RAS refresh mode:

-45 version

-50 version

I

I

I

I

I

CC3

CC4

CC5

CC5

CC6

–

mA

2, 4

105
95

–

mA

2, 3, 4

75
65

–1mA

– 200 µA

1

1

–

mA

2, 4

105
95

Self Refresh Current (L-version only)

CBR cycle with RAS >trasss(min), CAS held low;
WE = VCC– 0.2 V,

V

Addresses and Din =

– 0.2 V or 0.2 V

CC

I

CC7

– 250 µA

Capacitance

T

= 0 to 70 °C; f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A8)
Input capacitance (

RAS, UCAS, LCAS, WE, OE) C

Output capacitance (l/O1 to l/O16)

C

C

I1

I2

IO

–5pF
–7pF
–7pF

Semiconductor Group 7

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

AC Characteristics

T

= 0 to 70 °C, tT = 2 ns

A

5) 6)

Parameter

Common Parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
CAS precharge time t
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delaytime t
RAS to column address delay time t
RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time(rise and fall)
Refresh period t

Symbol

RC

RP

RAS

CAS

CP

t

ASR

t

RAH

t

ASC

t

CAH

RCD

RAD

RSH

CSH

CRP

t

T

REF

Limit Values

Unit Note

-400 -40

min. max. min. max.

69 – 69 – ns
25 – 25 – ns
40 10k 40 10k ns

4.5 10k 6 10k ns
4–5–ns
0–0–ns
5–5–ns
0–0–ns
5–5–ns
9 30 9 30 ns
7 20 7 20 ns
6–6–ns
32 – 32 – ns
5–5–ns
1 50 1 50 ns

7

16 – 16 – ms

Read Cycle

Access time from RAS t
Access time from CAS t
Access time from column address t
OE access time t
Column address to
Read command setup time
Read command hold time

RAS lead time t

t
t

Read command hold time ref. to RAS t
CAS to output inlow-Z t
Output buffer turn-off delay from CAS t

Semiconductor Group 8

RAC

CAC

AA

OEA

RAL

RCS

RCH

RRH

CLZ

OFF

– 40 – 40 ns
– 10 – 10 ns
– 17 – 20 ns

8, 9
8, 9
8,10

– 10 – 10 ns
20 – 20 – ns
0–0–ns
0–0–ns
0–0–ns
0–0–ns
0–010ns

11
11
8
12

HYB 5(3)14265BJ(L)-400/-40/-45/-50

256K x 16 EDO-DRAM

Parameter

Output buffer turn-off delay from OE t
Data to OE low delay t
CAS high to data delay t
OE high to data delay t
Data to CAS low delay t

Write Cycle

Write command hold time t
Write command pulse width
Write command setup time
Write command to RAS lead time t
Write command to

CAS lead time t
Data setup time
Data hold time t
Data to CAS low delay t

Symbol

OEZ

DZO

CDD

ODD

DZC

WCH

t

WP

t

WCS

RWL

CWL

t

DS

DH

DZC

Limit Values

Unit Note

-400 -40

min. max. min. max.

0 10 0 10 ns
0–0 ns
8–8–ns
8–8–ns
0–0–ns

12
13
14
14
13

5–5–ns
5–5–ns
0–0–ns

15

10 – 10 – ns
10 – 10 – ns
0–0–ns
5–5–ns
0–0–ns

16
16
13

Read-modify-Write Cycle

Read-write cycle time t
RAS to WE delay time t
CAS to WE delay time t
Column address to WE delay time t
OE command hold time t

Hyper Page Mode (EDO) Cycle

Hyper page mode cycle time t
Access time from

CAS precharge t
Output data hold time t
RAS pulse width in hyper page mode t
RAS hold time from CAS precharge t

RWC

RWD

CWD

AWD

OEH

HPC

CPA

COH

RAS

RHCP

93 – 93 – ns
52 – 52 – ns
22 – 22 – ns
32 – 32 – ns

15
15
15

5–5–ns

12.5 – 15 – ns
– 17 – 21 ns

7

3–3–ns
40 200k 40

200k

ns

17 – 21 – ns

Semiconductor Group 9