Siemens HYB314100BJ-50, HYB314100BJ-60, HYB314100BJ-70, HYB314100BJL-50, HYB314100BJL-60 Datasheet

4M x 1-Bit Dynamic RAM
Low Power 4M x 1-Bit Dynamic RAM

dvanced Information

• 4 194 304 words by 1-bit organization

• 0 to 70 ˚C operating temperature

• Fast Page Mode Operation

• Performance:

HYB 314100BJ/BJL -50/-60/-70

-50 -60 -70

t

RAC

t

CAC

t

AA

t

RC

t

PC

• Single + 3.3 V (± 0.3 V ) supply with a built-in V

• Low power dissipation

RAS access time 50 60 70 ns
CAS access time 13 15 20 ns
Access time from address 25 30 35 ns
Read/Write cycle time 95 110 130 ns
Fast page mode cycle time 35 40 45 ns

generator

bb

max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
max. 198 mW active (-70 version)

• Standby power dissipation:

7.2 mW max. standby (TTL)

3.6 mW max. standby (CMOS)
720 µW max. standby (CMOS) for Low Power Version

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,

hidden refresh and test mode capability

• All inputs and outputs TTL-compatible

• 1024 refresh cycles / 16 ms

• 1024 refresh cycles / 128 ms Low Power Version

• Plastic Packages: P-SOJ-26/20-5 with 300 mil width

Semiconductor Group 1 4.96

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by
1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20
package. This package size provides high system bit densities and is compatible with commonly
used automatic testing and insertion equipment. System oriented features include single + 3.3 V
(± 0.3 V) power supply, direct interfacing with high performance logic device families.

Ordering Information
Type Ordering Code Package Descriptions

HYB 314100BJ-50 Q67100-Q2035 P-SOJ-26/20-5 3.3 V DRAM

(access time 50 ns)

HYB 314100BJ-60 Q67100-Q2037 P-SOJ-26/20-5 3.3 V DRAM

(access time 60 ns)

HYB 314100BJ-70 Q67100-Q2039 P-SOJ-26/20-5 3.3 V DRAM

(access time 70 ns)

HYB 314100BJL-50 on request P-SOJ-26/20-5 3.3 V Low Power DRAM

(access time 50 ns)

HYB 314100BJL-60 on request P-SOJ-26/20-5 3.3 V Low Power DRAM

(access time 60 ns)

HYB 314100BJL-70 on request P-SOJ-26/20-5 3.3 V Low Power DRAM

(access time 70 ns)

Semiconductor Group 2

Pin Configuration

(top view)

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

P-SOJ-26/20-5

Pin Names

A0-A10 Address Input
RAS Row Address Strobe
CAS Column Address Strobe
WE Read/Write Input
DI Data In
DO Data Out

V

CC

V

SS

Power Supply (+ 3.3 V)
Ground (0 V)

N.C. No Connection

Semiconductor Group 3

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Block Diagram

Semiconductor Group 4

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 ˚C

Storage temperature range......................................................................................– 55 to + 150 ˚C

Input/output voltage ...........................................................................– 1 to + min (VCC + 0.5, 4.6) V

Power Supply voltage..................................................................................................– 1 to + 4.6 V

Data out current (short circuit) ................................................................................................50 mA

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

DC Characteristics

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns

A

Parameter Symbol Limit Values Unit Test

Condition

1)

1)

1)

1)

1)

1)

2) 3)4)

Input high voltage
Input low voltage V
TTL Output high voltage (I
TTL Output low voltage (I
CMOS Output high voltage (I
CMOS Output low voltage (

= – 2 mA) V

OUT

= 2 mA) V

OUT

= – 100 µA) V

OUT

I

100 µA

OUT =

)

Input leakage current, any input
(0 V <

V

< VCC + 0.3 V, all other input = 0 V)

in

Output leakage current
(DO is disabled, 0 V < V

OUT

< VCC)

Average VCC supply current

-50 version

-60 version

-70 version

V

V
I

I

I

IH

IL

OH

OL

OH

OL

I(L)

O(L)

CC1

min. max.

2.0 VCC + 0.5 V
– 1.0 0.8 V

2.4 – V
– 0.4 V

V

– 0.2 – V

CC

– 0.2 V
– 10 10 µA

– 10 10 µA

mA
_
–
–

70
60
55

Standby VCC supply current
(RAS = CAS = WE = VIH)

V

Average

supply current during RAS-only

CC

refresh cycles -50 version

-60 version

-70 version

Average VCC supply current during fast page
mode operation -50 version

-60 version

-70 version

Standby VCC supply current
(RAS = CAS = WE = VCC – 0.2 V)

Semiconductor Group 5

I

I

I

I

CC2

CC3

CC4

CC5

–2mA–

mA
_
–
–

70
60
55

mA
–
–

50
45

2)4)

2) 3)4)

40

–1

200

mA

µA1)L-version

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

DC Characteristics (cont’d)

T

= 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns

A

Parameter Symbol Limit Values Unit Test

Condition

2)4)

Average VCC supply current during
CAS before RAS refresh mode

-50 version

-60 version

-70 version

I

CC6

min. max.

–
–
–

70
60
55

mA

For Low Power Version only:

I

CC7

– 250 µA–

Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE = VCC – 0.2 V or 0.2 V,
A0 to A10 = VCC – 0.2 V or 0.2 V;
DI = VCC – 0.2 V or 0.2 V or open,

t

= 125 µs, t

RC

RAS

= t

min = 1 µs)

RAS

Capacitance

T

= 0 to 70 ˚C; VCC = 3.3 V ± 0.3 V; f = 1 MHz

A

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A10, DI)
Input capacitance (

RAS, CAS, WE) C

Output capacitance (DO)

C

C

I1

I2

IO

–5pF
–7pF
–7pF

Semiconductor Group 6

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

AC Characteristics

T

= 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns

A

Parameter

5)6)

Symbol

Common Parameters

Random read or write cycle time t
RAS precharge time t
RAS pulse width t
CAS pulse width t
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time t
RAS to column address delay

t
t
t
t

t

RC

RP

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

time

Limit Values

Unit Note

-50 -60 -70

min. max. min. max. min. max.

95 – 110 – 130 – ns
35 – 40 – 50 – ns
50 10k 60 10k 70 10k ns
13 10k 15 10k 20 10k ns
0–0–0–ns
8–10–10–ns
0–0–0–ns
10 – 15 – 15 – ns
18 37 20 45 20 50 ns
13 25 15 30 15 35 ns

RAS hold time t
CAS hold time t
CAS to RAS precharge time t
Transition time (rise and fall)
Refresh period
Refresh period for L-version

Read Cycle

Access time from RAS t
Access time from

CAS t

Access time from column
address

Column addr. to

RAS lead time t
Read command setup time
Read command hold time
Read command hold time

referenced to

RAS

t
t
t

t

t
t
t

RSH

CSH

CRP

T

REF

REF

RAC

CAC

AA

RAL

RCS

RCH

RRH

13 15 – 20 – ns
50 60 – 70 – ns
5–5–5–ns
350350350ns7
–16–16–16ms
– 128 – 128 – 128 ms

– 50 – 60 – 70 ns 8, 9
– 13 – 15 – 20 ns 8, 9
– 25 – 30 – 35 ns 8,10

25 – 30 – 35 – ns
0–0–0–ns
0–0–0–ns11
0–0–0–ns11

CAS to output in low-Z t

CLZ

0–0–0–ns8

Semiconductor Group 7