Samsung S3C821A, S3P821A Datasheet

S3C821A/P821A PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLES

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.

S3C821A/P821A MICROCONTROLLER

The S3C821A/P821A single-chip CMOS
microcontroller is fabricated using the highly
advanced CMOS process, based on Samsung’s
newest CPU architecture.

The S3C821A is a microcontroller with a 48-Kbyte
mask-programmable ROM embedded.

The S3P821A is a microcontroller with a 48-Kbyte
one-time-programmable ROM embedded.

Using a proven modular design approach, Samsung
engineers have successfully developed the
S3C821A/P821A by integrating the following
peripheral modules with the powerful SAM8 core:

— Six programmable I/O ports, including five 8-bit

ports and one 7-bit port, for a total of 47 pins.

— Twelve bit-programmable pins for external

interrupts.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.
— Watch timer for real time.
— 4-input A/D converter
— Serial I/O interface

The S3C821A/P821A is versatile microcontroller for
cordless phone, pager, etc. They are currently
available in 80-pin TQFP and 80-pin QFP package.

OTP

The S3P821A is an OTP (One Time Programmable) version of the S3C821A microcontroller. The S3P821A
microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of a masked ROM. The
S3P821A is comparable to the S3C821A, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW S3C821A/P821A

FEATURES

CPU

• SAM8 CPU core

Memory

• Data memory: 1040-byte of internal register file
(Excluding LCD RAM)

• Program memory: 48-Kbyte internal program
memory (ROM)

External Interface

• 64-Kbyte external data memory area

Instruction Execution Time

• 750 ns at 8 MHz (minimum, Main oscillator)

• 183 µs at 32,768 Hz (minimum, Sub oscillator)

Interrupts

• 7 interrupt levels and 19 interrupt sources

• 19 vectors

• Fast interrupt processing feature (for one
selected interrupt level)

I/O Ports

• Five 8-bit I/O ports (P0–P4) and one 7-bit I/O
port (P5) for a total of 47 bit-programmable pins

8-Bit Basic Timer

• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function

Watch Timer

• Time internal generation: 3.91 ms, 0.5 s at
32,768 Hz

• Four frequency outputs to BUZ pin

• Clock source generation for LCD

Timers and Timer/Counters

LCD Controller/Driver

• Up to 32 segment pins

• 3, 4, and 8 common selectable

• Choice of duty cycle

• All dots can be switched on/off

• Internal resistor circuit for LCD bias

Serial Port

• One synchronous SIO

A/D Converter

• 8-bit conversion resolution × 4 channel

• 34 µs conversion time (4 MHz CPU clock, fxx/4)

Oscillation Sources

• Crystal, ceramic, or RC for main system clock

• Crystal or external oscillator for subsystem clock

• Main system clock frequency: 8 MHz

• Subsystem clock frequency: 32.768 kHz

Power-down Modes

• Main idle mode (only CPU clock stops)

• Sub idle mode

• Stop mode (main/sub system oscillation stops)

Operating Temperature Range

• – 40 °C to + 85 °C

Operating Voltage Range

• 2.0 V to 5.5 V at 32 kHz (sub clock)-6 MHz
(main clock)

• 2.2 V to 5.5 V at 8 MHz

Package Type

• 80-pin TQFP, 80-pin QFP

• One 8-bit timer/counter (Timer 0) with three
operating modes: Interval, Capture, and PWM

• One 16-bit timer/counter (Timer 1) with two 8-bit
timer/counter modes

1-2

S3C821A/P821A PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

OUT

X

X

OUT

T1CK

TA
TB

T0CK

T0/T0CAP/

T0PWM

IN

IN

RESET

MAIN

OSC

SUB

OSC

TIMER 1

A and B

TIMER 0

P0.0-P0.7

PORT 0

P1.0-P1.7

PORT 1

INTERNAL BUS

I/O PORT and INTERRUPT

CONTROL

SAM8 CPU

48-KB ROM

1-KBYTE

REGISTER

FILE

P2.0-P2.7

PORT 2

PORT 3

PORT 4

PORT 5

P3.0-P3.7

P4.0-P4.7

P5.0-P5.6

SCK

SI

SO

AV

SIO

AV

SS

REF

A/D

CONVERTER

VDD1 (INTERNAL)
VSS1 (INTERNAL)
VDD2 (EXTERNAL)

WATCH

TIMER

VSS2 (EXTERNAL)

ADC0-ADC3

Figure 1-1. S3C821A Simplified Block Diagram

LCD

DRIVER

BUZ

COM0-COM3
SEG0-SEG3/
COM4-COM7
SEG4-SEG31
VLC1

1-3

PRODUCT OVERVIEW S3C821A/P821A

PIN ASSIGNMENTS

P1.0/SEG24/AD0

P0.7/SEG23/A15

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

P2.0/AS

P2.1/DR

VDD1(INT)

VSS1

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

80797877767574737271706968676564636261

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

AVREF

P2.6/INT2/TA

P2.7/INT3/TB

P2.5/INT1/T1CK

S3C821A

(80-TQFP)

P3.0/ADC0

P3.1/ADC1

P3.2/ADC2

P3.3/ADC3

AVSS

P3.4

P3.5

P3.6

P4.0/INT4

P4.1/INT5

P4.2/INT6

P4.3/INT7

60

40

P4.4/INT8

P4.5/INT9

P4.6/INT10

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11

1-4

P3.7/T0/T0PWM/T0CAP

Figure 1-2. S3C821A Pin Assignments (80-TQFP-1212)

S3C821A/P821A PRODUCT OVERVIEW

P0.6/SEG22/A14

P0.5/SEG21/A13

P0.4/SEG20/A12

P0.3/SEG19/A11

P0.2/SEG18/A10

P0.1/SEG17/A9

P0.0/SEG16/A8

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

P0.7/SEG23/A15
P1.0/SEG24/AD0
P1.1/SEG25/AD1
P1.2/SEG26/AD2
P1.3/SEG27/AD3
P1.4/SEG28/AD4
P1.5/SEG29/AD5
P1.6/SEG30/AD6
P1.7/SEG31/AD7

P2.0/AS

P2.1/DR

VDD1(INT)

VSS1

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM
P2.4/INT0/T0CK
P2.5/INT1/T1CK

P2.6/INT2/TA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

807978777675747372717069686766

S3C821A

(80-QFP)

65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG6
SEG5
SEG4
SEG3/COM7
SEG2/COM6
SEG1/COM5
SEG0/COM4
COM3
COM2
COM1
COM0
VDD2 (EXT)
VSS2
VLC1
P5.6
P5.5
P5.4
P5.3/BUZ
P5.2/SO
P5.1/SI
P5.0/SCK
P4.7/INT11
P4.6/INT10
P4.5/INT9

252627282930313233343536373839

P3.4

P3.5

AVREF

P3.0/ADC0

P3.1/ADC1

P2.7/INT3/TB

P3.2/ADC2

AVSS

P3.3/ADC3

P3.6

P4.0/INT4

P4.1/INT5

P3.7/T0/T0PWM/T0CAP

40

P4.2/INT6

P4.3/INT7

P4.4/INT8

Figure 1-3. S3C821A Pin Assignments (80-QFP-1420C)

1-5

PRODUCT OVERVIEW S3C821A/P821A

PIN DESCRIPTIONS

Table 1-1. S3C821A Pin Descriptions

Pin

Names

Pin

Type

Pin

Description

P0.0–P0.7 I/O 4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. Configurable as LCD segments/
external interface address and data lines

P1.0–1.7 I/O 4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. Configurable as LCD segments/
external interface address and data lines

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

P3.0–P3.3

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output
pins. P2.0–P2.3 can alternately be used
as external interface lines. P2.4–P2.7 are
configurable as alternate functions or
external interrupts at falling edge with
noise filters.

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output

P3.4–P3.6

pins. P3.0–P3.3 can alternately be used
as ADC. P3.7 is configurable as an
alternate function.

P3.7

P4.0–P4.7 I/O 1-bit-programmable I/O port.

Pull-up resistors and open-drain outputs
are software assignable. Pull-up resistors
are automatically disabled for output
pins. P4.0–P4.7 are configurable as
external interrupts at a selectable edge
with noise filters.

P5.0
P5.1
P5.2
P5.3

P5.4–P5.6

I/O 1-bit-programmable I/O port.

Pull-up resistors are software assignable,
and automatically disabled for output
pins.
P5.0–P5.3 are configurable as alternate
functions. If SCK and SI are used as
input, these pins have noise filters.

Circuit

Type

Pin

Numbers

H-32 72–79

(74-80, 1)

H-32 80, 1–7

(2-9)

D-4 8 (10)

9 (11)
18 (20)
19 (21)
20 (22)
21 (23)
22 (24)
23 (25)

F-16

25–28

(27–30)

D-4

30–32

(32–34)

D-4

33 (35)

E-4 34–41

(36–43)

D-4 42 (44)

43 (45)
44 (46)
45 (47)

46–48

(48–50)

(note)

Share

Pins

SEG16/A8

–

SEG23/A15

SEG24/AD0

–

SEG31/AD7

AS

DR
DW
DM

INT0/T0CK
INT1/T1CK

INT2/TA
INT3/TB

ADC0–ADC3

T0/T0PWM/

T0CAP

INT4–INT11

SCK

SI

SO

BUZ

NOTE: Parentheses indicate pin number for 80-QFP package.

1-6

S3C821A/P821A PRODUCT OVERVIEW

Table 1-1. S3C821A Pin Descriptions (Continued)

Pin

Names

V

, V

SS1

DD1

X

X

,

OUT

IN

TEST – Chip test input pin

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

(note)

– Power input pins for internal power block – 10, 11 (12, 13) –

– Main oscillator pins – 12, 13 (14, 15) –

– 14 (16) –

Share

Pins

Hold GND when the device is operating

XTIN, XT

RESET

OUT

– Sub oscillator pins for sub-system clock – 15, 16 (17,18) –

I

RESET signal input pin. Schmitt trigger

B 17 (19) –

input with internal pull-up resistor.

INT0–INT3 I/O External interrupts input with noise filter. D-4 20–23 (22–25) P2.4–P2.7

T0CK I/O 8Bit Timer 0 external clock input. D-4 20 (22) P2.4
T1CK I/O Timer 1/A external clock input. D-4 21 (23) P2.5

TA I/O Timer 1/A clock output D-4 22 (24) P2.6
TB I/O Timer B clock output D-4 23 (25) P2.7

T0 I/O Timer 0 clock output D-4 33 (35) P3.7

T0PWM I/O Timer 0 PWM output D-4 33 (35) P3.7

T0CAP I/O Timer 0 capture input D-4 33 (35) P3.7

ADC0–ADC3 I/O Analog input pins for A/D converts

F-16 25–28 (27–30) P3.0–P3.3

module

AV

REF

, AV

SS

– A/D converter reference voltage and

– 24, 29 (26, 31) –

ground

INT4–INT11 I/O External interrupts input with noise filter. E-4 34–41 (36–43) P4.0–P4.7

BUZ I/O Buzzer signal output D-4 45 (47) P5.3

SCK, SI, SO I/O Serial clock, serial data input, serial data

D-4 42–44 (44–46) P5.0–P5.2

output

V

SS2

V

LC1

, V

DD2

– LCD bias voltage input pins – 49 (51) –
– Power input pins for external power block – 50, 51 (52, 53) –

COM0–COM3 O LCD Common signal output H-30 52–55 (54–57) –

SEG0–SEG3

O LCD Common or Segment signal output H-31 56–59 (58–61) –

(COM4–COM7)

SEG4–SEG15 O LCD segment signal output H-29 60–71 (62–73) –

NOTE: Parentheses indicate pin number for 80-QFP package.

1-7

PRODUCT OVERVIEW S3C821A/P821A

Table 1-1. S3C821A Pin Descriptions (Continued)

Pin

Names

SEG16–

Pin

Type

Pin

Description

Circuit

Type

Pin

Numbers

I/O LCD segment signal output H-32 72–79 (74–80, 1) P0.0–P0.7

SEG23

SEG24–

I/O LCD segment signal output H-32 80, 1–7 (2–9) P1.0–P1.7

SEG31

A8–A15 I/O External interface address lines H-32 72–79 (74–80, 1) P0.0–P0.7

AD0–AD7 I/O External interface address/data lines H-32 80, 1–7 (2–9) P1.0–P1.7

AS

DR
DW
DM

NOTE: Parentheses indicate pin number for 80-QFP package.

I/O Address strobe D-4 8 (10) P2.0
I/O Data read D-4 9 (11) P2.1
I/O Data write D-4 18 (20) P2.2
I/O Data memory select D-4 19 (21) P2.3

Share

Pins

1-8

S3C821A/P821A PRODUCT OVERVIEW

PIN CIRCUITS

V

V

DD

DATA

DD

INPUT

Figure 1-4. Pin Circuit Type A

V

DD

PULL-UP
RESISTOR

RESET

P-CHANNEL

N-CHANNEL

Noise Filter

OUTPUT

DISABLE

PULL-UP

ENABLE

OUTPUT

DISABLE

V

SS

Figure 1-6. Pin Circuit Type C

V

DD

DATA

CIRCUIT

TYPE C

OUTPUT

I/O

Figure 1-5. Pin Circuit Type B

SCHMITT TRIGER

Figure 1-7. Pin Circuit Type D-4

1-9

PRODUCT OVERVIEW S3C821A/P821A

V

DD

PULL-UP

RESISTOR

PULL-UP
ENABLE

V

DD

OPEN-DRAIN EN

DATA

OUTPUT

DISABLE

PULL-UP

ENABLE

DATA

OUTPUT

DISABLE

V

SS

Figure 1-8. Pin Circuit Type E-4

CIRCUIT

TYPE C

I/O

V

DD

I/O

1-10

ADEN

ADSELECT

DATA

T0 ADC

Figure 1-9. Pin Circuit Type F-16