Samsung S3C820B Datasheet

S3C820B PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C-SERIES MICROCONTROLLERS

Samsung’s S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3C820B MICROCONTROLLER

The S3C820B single-chip CMOS microcontroller is
fabricated using a highly advanced CMOS process
and is based on Samsung’s newest CPU
architecture.

The S3C820B is the microcontroller which has
64K-byte mask-programmable ROM and 192K-byte
mask ROM for font data.

Using a proven modular design approach, Samsung
engineers developed the S3C820B by integrating
the following peripheral modules with the powerful
SAM87 core:

— Four programmable I/O ports, excluding one

BUZ pin, for a total of 32 pins.

— Eight bit-programmable pins for external

interrupts.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.

— Watch timer for real time.

The S3C820B is a versatile microcontroller for data
bank or dictionary. It is currently available in a 128­pin QFP package.

1-1

PRODUCT OVERVIEW S3C820B

FEATURES

CPU

• SAM87 CPU core

Memory

• 64K-byte internal program memory (ROM)

• 192K-byte internal memory (ROM) for font data

• 272-byte internal register file
(Excluding LCD RAM)

• 6144-byte data RAM

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for
power-down modes

Instruction Execution Time

• 1.5 µs at 4 MHz fx (minimum)

• 183 µs at 32,768 Hz fxt

Interrupts

LCD Controller/Driver

• 65 segments and 18 common terminals

• Internal resistor circuit for LCD bias

• Voltage doubler

• All dot can be switched on/off

Timers and Timer/Counters

• One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function

• One 8-bit timer/counter (Timer 0) with three
operating modes; Interval, Capture and PWM

• One 16-bit timer/counter (Timer 1) with two 8-bit
timer/counter modes; Interval

Power-Down Modes

• Idle mode (CPU clock stops)

• Stop mode (main oscillation and CPU clock
stops)

• Five interrupt levels and 15 interrupt sources

• 15 vectors (15 sources have a dedicated vector
address)

• Fast interrupt processing feature (for one
selected interrupt level)

I/O Ports

• Four 8-bit I/O ports (P0–P3) for a total of 32-bit
programmable pins

• Eight input pins for external interrupts

• One output only pin for BUZ

Watch Timer

• Interval time: 3.91 ms, 1s at 32,768 Hz

• Four frequency outputs to BUZ pin and BUZ pin

• Clock source generation for LCD

Operating Temperature Range

• – 40 °C to + 85 °C

Operating Voltage Range

• 2.2 V to 4.5 V at 1 MHz fx

• 2.7 V to 4.5 V at 4 MHz fx

Package Type

• 128-pin QFP

1-2

S3C820B PRODUCT OVERVIEW

BLOCK DIAGRAM

XIN

XOUT

XTIN

XTOUT

BUZ

BUZ

T0

T0CK

Basic
Timer

Main
OSC

Sub

OSC

Watch

Timer

Timer 0

P0.0-P0.7

(A8-A15)

(AD0-AD7)

Port 0

Internal Bus

I/O Port and Interrupt Control

SAM8 CPU

64K-byte

ROM

314-Byte

Register

P1.0-P1.7

Port 1

File

RESET

TEST

Controller

Port 2

Port 3

LCD

Driver/

Voltage
Doubler

Timer 1

P2.0-P2.3
(AS, DW, DR, DM)
P2.4-P2.7
(T0, T0CK, CLO, BUZ)

P3.0/TB/INT0
P3.1/TA/INT1
P3.2/T1CK/INT2
P3.3/INT3
P3.4/INT4
P3.5/INT5
P3.6/INT6
P3.7/INT7
COM0-COM8
COM9-COM17
SEG0-SEG64
VLC0

BIAS
CA
CB

TA
TB
T1CK

192K-byte
Font ROM

Figure 1-1. Block Diagram

6144-Byte
Data RAM

1-3

PRODUCT OVERVIEW S3C820B

PIN ASSIGNMENTS

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0

COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17

VDD
VSS

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10

P0.1/A9

P0.0/A8
P1.7/AD7
P1.6/AD6
P1.5/AD5

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39404142434445464748495051525354555657585960616263

S3C820B

(128-QFP-1420)

103

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

1-4

CA

CB

BUZ

P1.4/AD4

P1.3/AD3

P1.2/AD2

P1.1/AD1

P1.0/AD0

P3.0/TB/INT0

P3.3/INT3

P3.4/INT4

P3.5/INT5

P3.1/TA/INT1

P3.2/T1CK/INT2

P2.0/AS

P3.6/INT6

P3.7/INT7

P2.1/DW

P2.2/DR

P2.4/T0

P2.3/DM

P2.7/BUZ

P2.6/CLO

P2.5/T0CK

Figure 1-2. Pin Assignment (128-Pin QFP Package)

VLC0

BIAS

S3C820B PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Pin

Names

P0.0–P0.7 I/O I/O port with nibble-programmable pins; schmitt

P1.0–P1.7 I/O Same general characteristics as port 0; also

P2.0–P2.3 I/O I/O port with bit-programmable pins; schmitt

P2.4–P2.7 I/O P2.4/capture input, interval/PWM output (T0)

P3.0–P3.7 I/O I/O port with bit-programmable pins; schmitt

T1CK I/O Timer A external clock input pins. 4 46 P3.2/INT2
TB

TA

AS, DW, DR,
DM

T0 I/O Capture input or interval/PWM output. 6 56 P2.4
T0CK I/O Timer 0 clock input. 6 57 P2.5

Pin

Type

trigger input or push-pull, open-drain output and
software assignable pull-up; also configurable
as external interface address lines A8–A15.

configurable as external interface address/data
lines AD0–AD7.

trigger input or push-pull output and software
assignable pull-ups. Lower nibble pins 0–3 are
configurable for external interface signals.

P2.5/timer 0 clock input (T0CK)
P2.6/system clock output (CLO)
P2.7/buzzer signal output (BUZ)

trigger input or push-pull output and software
assignable pull-up; P3.0–P3.7 are alternately
used for external interrupt input (noise filters,
interrupt enable and pending control);
P3.0/timer B clock output (TB)/INT0
P3.1/timer 1/A clock output (TA)/INT1
P3.2/timer 1/A clock input (T1CK)/INT2

I/O Timer B and 1/A clock output pins. 4 44

I/O Output pins for external interface control

signals.

AS: address strobe
DW: data memory write
DR: data memory read
DM: data memory select

Pin

Description

Circuit

Type

3 35–28 A8–A15

3 43–36 AD0–AD7

5 52–55

6 56–59 T0, T0CK,

4 44–51 TB/INT0,

5 52–55 P2.0–P2.3

Pin No. Shared

45

Functions

AS, DW,

DR, DM

CLO, BUZ

TA/INT1,

T1CK/INT2,

INT3–INT7

P3.0/INT0
P3.1/INT1

1-5

PRODUCT OVERVIEW S3C820B

Table 1-1. Pin Descriptions (Continued)

Pin

Names

Pin

Type

Pin

Description

Circuit

Type

Pin No. Shared

Functions

CLO I/O Clock output 6 58 P2.6
BUZ I/O Output pin for buzzer signal. 6 59 P2.7

BUZ

O Inverted buzzer signal output. – 60 –

INT0–INT7 I/O External interrupt input pins. 4 44–51 P3.0/TB,

P3.1/TA,

P3.2/T1CK,

P3.3–P3.7
AD0–AD7 I/O Address low and data ports. 3 43–36 P1.0–P1.7
A8–A15 I/O Address high output ports. 3 35–28 P0.0–P0.7
COM0–COM8 O LCD common signal output. 7 73–65 –
COM9–

O LCD common signal output. 7 11–19 –

COM17
SEG0–

SEG64

O LCD seg signal output. 8 10–1

128–74

–

CA, CB – Capacitor terminal for voltage doubling. – 61, 62 –
V

LC0

– LCD power supply. – 63 –

BIAS O Bias voltage level for LCD driving. – 64 –

RESET

XTIN, XT

OUT

TEST I Test signal input (must be connected to

I System reset pin 2 27 –

– Crystal oscillator pins for sub clock. – 25, 26 –

– 24 –

VDD).
XIN, X
VDD, V

1-6

OUT

SS

– Main oscillator pins – 23, 22 –
– Power input pins – 20, 21 –

S3C820B PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

P-Channel

In

N-Channel

Figure 1-3. Pin Circuit Type 1

Pull-up

Enable

VDD

Pull-up

Resistor

In

Schmitt Trigger

Figure 1-4. Pin Circuit Type 2 (RESETRESET)

VDD

Pull-up
Resistor

VDD

Data

Open-drain

Output

Disable

Input

Figure 1-5. Pin Circuit Type 3 (Ports 0, 1)

I/O

VSS

1-7