Samsung S3C80A4, S3C80A5, S3C80A8, S3C80B4, S3C80B5 Datasheet

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S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 MICROCONTROLLER

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture.

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is the microcontroller which has mask-programmable ROM. The S3P80A4/P80A8/P80A5/P80B4/P80B8/P80B5 is the microcontroller which has one-time-programmable

EPROM. Using a proven modular design approach, Samsung engineers developed the

S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 by integrating the following peripheral modules with the powerful SAM87 RC core:

— Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins. — Internal LVD circuit and eight bit-programmable pins for external interrupts. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). — One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. — One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP package.

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PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

FEATURES

CPU

• SAM87RC CPU core

Memory

• Program memory (ROM)

– S3C80A4/C80B4: 4-Kbyte (0000H–0FFFH)

– S3C80A8/C80B8: 8-Kbyte (0000H–1FFFH)

– S3C80A5/C80B5: 15,872 byte (0000H–3E00H)

• Data memory: 256-byte RAM

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power-

down modes

Instruction Execution Time

• 500 ns at 8-MHz f

(minimum)

OSC

Timers and Timer/Counters

• One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer function

• One 8-bit timer/counter (Timer 0) with two

operating modes; Interval mode and PWM mode.

• One 16-bit timer/counter with one operating

modes; Interval mode

Low Voltage Detect Circuit

• Low voltage detect for reset or Back-up mode.

• Low level detect voltage

– S3C80A4/C80A8/C80A5:

2.20 V (Typ) ± 200 mV – S3C80B4/C80B8/C80B5:

1.90 V (Typ) ± 200 mV

Auto Reset Function

• Reset occurs when stop mode is released by P0.

• When a falling edge is detected at Port 0 during

Stop mode, system reset occurs.

Interrupts

• 13 interrupt sources with 10 vector.

• 5 level, 10 vector interrupt structure

I/O Ports

• Two 8-bit I/O ports (P0-P1) and one 3-bit port

(P2) for a total of 19 bit-programmable pins

• Eight input pins for external interrupts

Carrier Frequency Generator

• One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Back-up mode

• When V

is lower than V

, the chip enters

LVD

Back-up mode to block oscillation and reduce the current consumption.

Operating Temperature Range

• –40°C to + 85°C

Operating Voltage Range

• 1.7 V to 3.6 V at 4 MHz f

• 2.0 V to 3.6 V at 8 MHz f

OSC OSC

Package Type

• 24-pin SOP/SDIP

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S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-P0.7/INT0-INT4 P1.0-P1.7

XIN

XOUT

LVD

TEST

Main OSC

8-bit Basic Timer

8-bit

Timer/

Counter

16-bit

Timer/

Counter

Port 0(INTR) Port 1

Internal Bus

Port I/O and Interrupt

Control

SAM87RI CPU

15-Kbyte ROM

256-Byte

Port 2

Carrier

Generator

(Counter A)

P2.0/T0PWM P2.1/REM P2.2

Figure 1-1. Block Diagram

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PRODUCT OVERVIEW S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5

PIN ASSIGNMENTS

VDD

VSS

XIN

XOUT

TEST P0.0/INT0/INTR P0.1/INT1/INTR

RESETRESET/P0.2/INT2/INTR

P0.3/INT3/INTR P0.4/INT4/INTR P0.5/INT4/INTR P0.6/INT4/INTR P0.7/INT4/INTR

1 2 3 4

S3C80A4/C80A8/C80A5

5 6

C80B4/C80B8/C80B5

7 8 9 10 11 12

24-SOP/SDIP

(TOP VIEW)

P2.2

P2.1/REM/SCLK

P2.0/T0PWN/T0CK/SDAT

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)

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S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Names

Type

Description

P0.0–P0.7 I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. Interrupt with Reset(INTR) is assigned to Port 0.

P1.0–P1.7 I/O I/O port with bit-programmable pins.

Configurable to input mode or output mode. Pin circuits are either push-pull or nchannel open-drain type. Pull-up resistors are assignable by software.

P2.0 P2.1 P2.2

I/O 3-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors are assignable by software. The two pins of port 2 have high current drive capability.

Circuit

Type

24-Pin

Number

Shared

Functions

1 5–12 INT0 – INT4/INTR

2 13–20

21–23 REM/T0CK 4 5

XIN, X

OUT

– System clock input and output pins – 2, 3 –

TEST I Test signal input pin (for factory use only;

must be connected to VSS).

– Power supply input pin – 24 – – Ground pin – 1 –

– 4 –

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