Samsung PS42P2SDX Circuit Descriptions

Circuit Operation Description

Samsung Electronics 5-1

5. Circuit Description

5-1 Power supply

5-1-1 Outline(PDP SMPS)

Considering various related conditions, the switching regulator with good efficiency and allowing for its small size and lightweight was used as the power supply for PDP. Most of the power supply components used forward converter, and Vsamp and Vsb used simple flyback converter. To comply with the international harmonics standards and improve the power factor, active PFC (Power Factor Correction) was used to rectify AC input into +400V DC output, which in turns used as input to the switching regulator.

5-1-2 42"SD SMPS SPECIFICATION

5-1-2(A) INPUT

PDP-42PS board is designed so that input power can be used within AC 90 VAC to 264 VAC with 50/60Hz ± 3Hz.

5-1-2(B) OUTPUT

PDP-42PS board provides 13 output switching power supplies for PDP 50inch (+165Vs, +220Set, +185Ve, +75Va, +80Scan, +18Vg, +5Vsb, +5V(D), +5V(A), +12V. +9V, +12Vfan, and +12Vsamp). The output voltage, and current requirements for continuous operation are stated below (Table 3).

Table1. Specifications of Output Power Supplies for PDP SMPS

Output Name

Vscan

Vset

Vfan

V5(A)

V5(D)

Vsb

V12

Vsamp

Output Voltage

+165V

+75V

+80V

+220V

+185V

+18.3V

+12V

+9V

+5V

+5.3V

+5V

+12V

Output Current

1.4A

0.5A

0.05A

0.3A

0.8A

0.3A

1.0A

3.5A

0.4

1.2A

1.5A

Using in PDP driving

Sustain Voltage of Drive Board

Address Voltage of Drive Board

Analog IC Drive Voltage of Video Board

IC Drive Voltage of Logic Board

Stand-by for Remote Control

Circuit Operation Description

5-2 Samsung Electronics

Table 2. Specifications to Protect PDP SMPS

Division

+5V

OCP Current

10A

OVP Voltage

195V

90V

6.2V

Short Circuit

O.K

5-1-2(C) FUNCTION OF BOARD

(1) Remote control

Using 250V/ 10A relay, the board makes remote control available.

(2) Free voltage

The board designed so that input voltage can be used within 90 VAC to 264VAC.

(3) Embedded thermal sensor

The board is equipped with thermal sensor to detect the internal temperature of the unit, and to short relay when the internal temperature is higher than specified temperature so as to shutdown the unit.

(4) Improvement of power factor

The board is designed using PFC circuit so that PF (Power Factor) can be over 0.95, because low PF can be a problem in high voltage power.

(5) Protection

The OCP (Over Current Protection), the OVP (Over voltage Protection), and the Short Circuit Protection functions are added against system malfunction.

Circuit Operation Description

Samsung Electronics 5-3

5-1-2(D) PDP-PS-42 BLOCK DIAGRAM

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(1) AC-DC Converter

PDP-42PS outputs +400V DC from the common AC power supply using the active PFC booster converter. This converter is designed for improving the power factor and preventing the noise with high frequency and finally becomes the input power system for the switching regulator on the output side.

(2) Auxiliary Power Supply

The auxiliary power supply is a block generating power of •Ï-com for remote controlling. Once the power plug is inserted, this block always comes into operation, causing •Ï-com to get into the standby state for the output. Thus, this output is called the stand-by voltage. And with the relay ON signal inputted through the remote controller, this block turns the mechanical switch of relay to ON for driving the main power supply.

(3) Implementation of Sustain Voltage

As the main part of a SMPS for PDP, sustain voltage must supply a high power, +165V/ 1.4A. It is designed using forward converter basically. At the output stage two 90V converters are connected serially for high efficiency and reduction of system size against a single 180V converter.

(4) Implementation of Small Power Output (Va, V(D), V(A), Vfan, V9, Vsamp, Ve, Vset, Vscan, V12, and

Vg)Vset, Ve, and Vscan used DC-DC module. V(D), Va, V12, and Vfan used forward converter, and Vsamp used flyback converter. V(A), V9, and Vg are simply implemented using switching regulator.

5-1-3 Requirements of PDP SMPS

Since SMPS does not operate alone, but it operates with the load of the whole system, it should be designed carefully considering the load of the system. In addition, it should be designed considering emerging issues such as EMC, and protection against heat as well as system stability especially.

5-1-3(A) SAFETY AND REMOTE CONTROL CAPABILITY

Stability is one of the most important requirements for SMPS. SMPS should be designed to prevent abnormal status due to abnormal load variation so as to keep the system stable, and guarantee customer safety. The protection circuits of SMPS include over-current protection (OCP), over voltage protection (OVP), and under voltage lock-out (UVLO), and short circuit protection circuit. Although each circuit can be implemented by various procedures, the most popular is implementing with comparator that compares current value with that of standard and determine abnormality of the circuit. In addition, surge current protection, insulation management, and static electricity protection circuit should be added, because it uses commercial power source as an input. PDP SMPS should be designed using auxiliary power and relay to provide remote control capability.

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5-1-3(B) THE RELATION BETWEEN POWER CONSUMPTION AND POWER CONVERSION Efficiency

The power consumption and the power conversion efficiency of SMPS affect protection against heat and system operation much. [ If the power conversion efficiency of 100W SMPS is 70%, is the power loss of internal circuit 30W? ] Output power consumption Po is determined by the multiplication of DC output voltage Vo and output current Io. Input power consumption Pi is determined by the addition of output power consumption Po and internal power loss of SMPS Pl. Provided that the power conversion efficiency is _,

If the power conversion efficiency of 100W SMPS is 70%, the internal power loss is about 42.8W by Equation (1). If the power conversion efficiency of 400W SMPS for 42"SD is 82%, the internal power loss is 87.8W by Equation (1). Table 4 shows internal power loss as a function of output power for various power conversion efficiencies.

Table 4. Power Conversion Efficiency vs. Internal Power Loss

100

120

140

160

180

200

120 140 160 180 200 240220 260 280 300

50%

60%

90%

70%

80%

Internal

Power

Loss ( W)

Direct Current Output Power (W)

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5-1-3(C) PFC (Power Factor Correction) Circuit Descriptions

The current electric devices use DC power supply and require a rectifier circuit converting AC into DC. As most rectifier circuits apply a capacitor input type, the rectifier circuit becomes the core of the occurrence of harmonics with lower reverse rate.If various electronic and electric devices are connected to a power system, high-frequency current will occur due to a power rectifier circuit, a phase control circuit with power input current of non-sine wave, or components with non-linear load characteristics, such as capacitor, inductor, etc. As the result, the disturbance of voltage occurs, and finally a power capacitor or a transformer generates heat, fire or noise occurs, controls malfunction, or the accessed devices abnormally operate or their lives are shortened.To prevent those symptoms, IEC (International Electrotechnical Commission) regulated standards for Power Supply Harmonics. (Refer to IEC 1000-3-2.)Figure 8 shows the basic structure of Active Boost PFC and waveforms.

Standards for Power Supply Harmonics

Scale: Devices accessed to 220V/380V, 230V/400V, 240V/425V and lower than 16A (IEC 100-3-2) Devices with AC 230V and lower than 16A (IEC 555-2)

Applied Classes :

♣ Class A: Devices not included in another class ♣ Class B : Portable tools ♣ Class C : Lighting devices ♣ Class D : Devices with special current waveforms

Application Schedule : Except the devices less than rating input of 75W (1996~1999)

Except the devices less than rating input of 50W (2000 and after)

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5-1-3(D) CONCLUSION

Although SMPS (Switching Mode Power Supply) enables small lightweight high-power consumption power design, it is hard to be used when stability and precise control are required. Power stage for PDP can be designed using the lightweight SMPS feature. It is important to design SMPS considering system load, stability, and related international standards.

The architecture and the pulse of active boost PFC

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5-2 Driver Circuit

5-2-1 Driver Circuit Overview

5-2-1(A) WHAT IS THE DEFINITION OF DRIVE CIRCUIT?

It is a circuit generating an appropriate pulse (High voltage pulse) and then driving the panel to implement images in the external terminals (X electrode group, Y electrode group and address electrode), and this high voltage switching pulse is generated by a combination of MOSFET’s.

5-2-1(B) PANEL DRIVING PRINCIPLES

In PDP, images are implemented by impressing voltage on the X electrode, Y electrode and address electrode, components of each pixel on the panel, under appropriate conditions. Currently, ADS (Address & Display Separate: Driving is made by separating address and sustaining sections) is most widely used to generate the drive pulse. Discharges conducted within PDP pixels using this method can largely be classified into 3 types, as follows:

(1) Address discharge : This functions to generate wall voltage within pixels to be lighted by addressing

information to them (i.e., impressing data voltage)

(2) Sustain discharge : This means a display section where only pixels with wall voltage by the address

discharge display self-sustaining discharge by the support of such wall voltage. (Optic outputs realizing images are generated.)

(3) Erase discharge : To have address discharge occur selectively in pixels, all pixels in the panel must

have the same conditions (i.e., the same state of wall and space electric discharges). The ramp reset discharge section, therefore, is important to secure the drive margin, and methods most widely used to date include wall voltage controlling by ramp pulse.

Circuit Operation Description

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5-2-1(C) TYPES AND DETAILED EXPLANATION OF DRIVE DISCHARGES

(1 ) Sustaining discharge

Sustaining discharge means a self-sustaining discharge generated by the total of the sustaining pulse voltage (usually, 160~170V) alternately given to X and Y electrodes during the sustaining period and the wall voltage that varies depending upon pixels' previous discharge status. It is operated by the memory function (through this, the current status is defined by previous operation conditions) AC PDP basically possesses. That is, when there is existing wall voltage in pixels (in other words, when pixels remain ON), the total of wall voltage and a sustaining voltage to be impressed subsequently impresses a voltage equal to or above the discharge start voltage, thereby generating discharge again, but when there is no existing wall voltage in pixels (in other words, when pixels remain OFF), the sustaining voltage only does not reach the discharge start voltage, thus causing no discharge. The sustaining discharge is a section generating actual optic outputs used in displaying images.

(2) Address discharge

This means a discharge type generated by the difference between positive voltage of the address electrode (normally 70~75V determined by supplied Va voltage + positive wall charge) and the negative potential of Y electrode (supplied GND level voltage + negative wall charge). The address discharge serves to generate wall voltage in pixels where images are to be displayed (that is, discharge is to be generated) prior to the sustaining discharge section. Namely, pixels with wall voltage by the address discharge will generate sustaining discharge by the following sustaining pulses.

(3) Erase discharge

The purpose of resetting or erase discharge is to make even wall voltage in all pixels on the panel. Wall voltage, which may vary depending upon the previous sustaining discharge status, must be made even. That is, wall voltage generated by the sustaining discharge must surely be removed, by making discharges and then supplying ions or electrons. Wall voltage can be removed by making discharges and then setting a limitation on time for opposite polarity charging of the wall voltage or generating weak discharge (Low voltage erasing) to supply an appropriate quantity of ions or electrons and keep polarities from being charged oppositely. The weak discharge (Low voltage erasing) methods, which have been known to date, can largely be into two types: 1) the log pulse adopted by most companies including F Company, and 2) the ramp pulse adopted by Matsushita. In both two methods, impression is made with a slow rising slope of the erasing pulse. Because the total of the existing wall voltage and a voltage on the rising pulse must be at least the drive start voltage to generate discharges, external impressed voltage is adjusted based on the difference in wall voltage between pixels. And, weak discharge is generated because of a small impressed voltage.

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5-2-2 SPECIFICATION OF DRIVE PULSES

5-2-2(A) DRIVE PULSES

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5-2-2(B) FUNCTIONS OF PULSES

(1) X rising ramp pulse

Just before X rising ramp pulse is impressed, the last Y electrode sustain pulse of previous sub field is impressed. The pulse causes sustain discharge. Consequently, positive wall charge is accumulated in X electrode, and negative wall charge is accumulated in Y electrode. X rising ramp erases wall charge produced by the last sustain discharge pulse using weak-discharge.

(2) Y rising ramp pulse

During Y rising ramp period, weak-discharge begins when external voltage of about 390V~400V is impressed to Y electrode, and each gap voltage is equal to discharge start voltage. Sustaining the weak-discharge, positive wall charge is accumulated in X electrode and address electrode, and negative wall charge is accumulated in Y electrode of the entire panel.

(3) Y falling ramp pulse

During Y falling ramp period, the negative wall charge in Y electrode accumulated by 200V of X bias is used to erase positive wall charge in X electrode. Address electrode (0V) sustains most of the positive electric charge accumulated during rising ramp period so that it can maintain wall charge distribution beneficial to the upcoming address discharge.

(4) Y scan pulse

This is called the scan pulse, selecting each of Y electrodes on a one-line-at-a-time basis. In this case, Vscan means the scan bias voltage. About 70 V (Vscan) voltage is impressed on the selected electrode lines, while 0 V (GND) voltage is impressed on the other lines. In the cells the address pulse (70V~75V) is impressed on, address discharge is occurred because negative wall charge is accumulated in Y electrode, positive wall charge is accumulated in address electrode by the applied ramp pulse, and the sum of impressed voltage is greater than discharge start voltage. Thus, because scan pulse and data pulse are impressed line by line, very long time is taken for PDP addressing.

(5) 1st sustain pulse

The sustaining pulse always begins with the Y electrode. This is because when address discharge is generated, positive wall voltage is generated on the Y electrodes. Because wall electric charge generated by address discharge is generally smaller than wall voltage generated by sustaining discharge, initial discharges have small discharge strength, and stabilization is usually obtained after 5~6 times discharges, subject to variations depending on the structure and environment of electrodes. The purpose of impressing the initial sustaining pulses long is to obtain stable initial discharges and generate wall electric charges as much as possible.

5-2-3(A) FUNCTIONS OF EACH BOARD

(1) X board

X board is connected to the panel’s X-electrode blocks, 1) generates sustain voltage pulse (including ERC), 2) generates X rising ramp pulse, and 3) sustains Ve bias during scan period.

(2) Y board

Y board is connected to the Y-electrode blocks of panel, 1) generates sustain voltage pulse (including ERC), 2) generates Y rising and falling ramp pulse, and 3) sustains Vscan bias.

(3) Y buffer board (upper and lower)

Y buffer board impresses scan pulse to Y electrodes, and consists of upper and lower sub-boards. In case of SD class, one board is equipped with 4 scan driver IC’s (STMicroelectronics STV7617 with 64 or 65 outputs).

(4) COF

Impresses Va pulse on address electrodes in the address section and generates address discharge based on a difference between such Va pulse and scan pulse impressed on Y electrodes. It is in the form of COF, and a COF is equipped with 4 data drive IC’s (STMicroelectronics STV7610A with 96 outputs). For a single scan, 7 COF’s are required.

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5-2-3 Configuration and Operation Principles of Driver Circuit

Y-Buffer (Upper)

Y Drive board

- Sustain pulse (Energy recovery)

- Rising ramp pulse

- Falling ramp pulse

X Drive board

- Sustain pulse (Energy recovery)

- Rising ramp pulse

- Ve bias

- Vscan pulse

Y-Buffer (Lower)

Y-electrode blocks

COF X-electrode blocks

(6 blocks)

(3 blocks)

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5-2-3(B) DRIVING BOARD'S BLOCK DIAGRAM

(1) Y

(2) X

17V

170V

POWER

220V

75V

POWER

220V

17V

170V

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➣ Components of driving board's operations

1. Power supply

1) Supplied from the power supply board

- For sustaining discharge: 180V;

- For logic signaling buffer: 5V; and

- For gate driver IC: 15V.

2) Generated by the internal DC/DC part

- For generating Vw pulse: 180V.

2. Logic signal

1) Supplied from the logic board

- Gate signals for FETs.

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5-2-3(C) PRINCIPLES OF FET’S OPERATION AND HIGH VOLTAGE SWITCHIng

❏ FET’s operation principles

❏ FET’s high voltage switching principles

(1) With no signal impressed on G1, FET1 gets

open-circuited, and with signal impressed on G2, FET2 gets short-circuited, thereby causing GND to be outputted to output terminals.

(2) With signal impressed on G1, FET1 gets short-

circuited, and with no signal impressed on G2, FET2 gets open-circuited, thereby causing 180V to be outputted to output terminals.

(1) With signal impressed on the gate (Positive voltage),

FET gets short-circuited (a conducting wire of zero (0) resistance); and

(2) With no signal impressed on the gate (GND), FET gets

open-circuited (a non-conducting wire of ∞ resistance).

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5-2-3 (D) DRIVER CIRCUIT DIAGRAM

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5-2-3(E) DRIVER BOARD CONNECTOR LAYOUT

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