Rockwell Automation 1785 PLC-5, 1785 Quick Reference

1785 PLC-5 Programmable Controllers
Quick Reference

Addressing Instruction SetHardware Components Switch Settings Troubleshooting

Front Panels ........................ 1-1

Processor Comparison......... 1-6

1771 I/O Chassis ...............1-10

Power Supplies.................. 1-11

Keyswitch..........................1-13

Processor Status File ......... 1-14

I/O Status File .................... 1-30

Data Table Files ...................2-1

Program Files ......................2-4

I/O Image Addressing...........2-5

Logical Addressing...............2-6

Indexed Addressing..............2-7

Indirect Addressing ..............2-7

I/O Addressing Modes ..........2-8

I/O Placement ......................2-8

Concept Summary................2-9

Status Bits........................... 3-1

Relay................................... 3-2

Timer .................................. 3-5

Counter ............................... 3-7

Compare ............................. 3-9

Compute ........................... 3-12

Logical .............................. 3-22

Conversion ........................ 3-24

Bit Modify and Move.......... 3-26

File.................................... 3-28

Diagnostic ......................... 3-30

Shift Register..................... 3-32

Sequencer......................... 3-35

Program Control ................ 3-36

Processor Control and

Message ........................... 3-41

Block and ControlNet

Transfer ............................ 3-43

ASCII ................................. 3-47

Chassis Backplane............... 4-1

Chassis Configuration ..........4-3

Complementary I/O .............. 4-4

Enhanced and

Ethernet PLC-5 ....................4-7

ControlNetwork Address ....4-11

Classic PLC-5 ....................4-12

Ethernet Jumper ................ 4-21

Enhanced and Ethernet PLC-5

General .........................5-1

Communication.............5-3

PLC-5/40L and PLC-5/60L

Communication ....................5-5

Ethernet

Status and Transmit .............5-7

ControlNet

Status Indicators ..................5-8

Classic PLC-5

General ..............................5-12

Adapter Mode .............5-14

Scanner Mode.............5-15

Remote I/O .........................5-17

Extended Local I/O .............5-25

Flex I/O ControlNet .............5-28

1771 I/O ControlNet............5-29

ControlNet I/O Status..........5-30

ControlNet Errors................5-35

Fault Codes ........................5-45

Using this Manual

This Quick Reference provides information frequently needed for using and maintaining your Allen-Bradley
PLC-5 processor.
It is intended for reference purposes only, and not as the sole source of information.

For more specific information on any topic in this Quick Reference, see:

• Enhanced and Ethernet PLC-5 Family Programmable Controllers User Manual, publication 1785-6.5.12

• Classic PLC-5 User Manual, publication 1785-6.2.1

• ControlNet PLC-5 Programmable Controllers Phase 1.5 User Manual, publication 1785-6.5.22

Important User Information

Because of the variety of uses for the products described in this publication, those responsible for the application
and use of this control equipment must satisfy themselves that all necessary steps have been taken to assure that
each application and use meets all performance and safety requirements, including any applicable laws,
regulations, codes and standards.

The illustrations, charts, sample programs and layout examples shown in this guide are intended solely for
purposes of example. Since there are many variables and requirements associated with any particular installation,
Allen-Bradley does not assume responsibility or liability (to include intellectual property liability) for actual use
based upon the examples shown in this publication.

The Safety Guidelines for the Application, Installation, and Maintenance of Solid State Control, publication
SGI-1.1 (available from your local Allen-Bradley office), describes some important differences between
solid-state equipment and electromechanical devices which should be taken into consideration when applying
products such as those described in this publication.

Reproduction of the contents of this copyrighted publication, in whole or in part, without written permission of
Allen-Bradley Company, Inc. is prohibited.

Summary of Changes

In this release of the PLC-5 Quick Reference, we have altered the way we reference software documentation.
Rather than show specific screens and key sequences which may vary according to the software package you
are using, we refer you instead to the programming software documentation that accompanies your particular
software package. Of course, we still provide the essential reference information you need to quickly accomplish
your tasks, but if you have specific questions about software procedures, you should refer to your programming
software documentation set.

To help you find new information, we included change bars as shown to the left of this paragraph.

Conventions

The table below describes the naming conventions used in this manual:

☞ You see this symbol in the lower right-hand corner of the page when information is continued on the next page.

© 1999 Rockwell Automation
PLC, PLC-2, PLC-3, PLC-5, PLC-5/10, PLC-5/11, PLC-5/12, PLC-5/15, PLC-5/20, PLC-5/25, PLC-5/30, PLC-5/40, PLC-5/40L, PLC-5/60, PLC-5/60L, PLC-5/80, PLC-5/20E, PLC-5/40E, PLC-5/80E, PLC-5/250,
PLC-5/20C, PLC-5/40C, PLC-5/80C, Ethernet, and DH+ are trademarks of Rockwell Automation.

This name: Represents these processors:

Enhanced

PLC-5/11™PLC-5/40

™

PLC-5/20™PLC-5/60

™

PLC-5/30™PLC5/80

™

PLC-5/40L™PLC-5/60L

™

Ethernet

PLC-5/20E™PLC-5/40E

™

PLC5/80E

™

ControlNet
Phase 1.5

PLC-5/20C15™ 5/40C15

™

5/80C15

™

Classic

PLC-5/10™PLC-5/15

™

PLC-5/12™PLC-5/25

™

Hardware Components

Front Panel 1-1

Front Panel – Enhanced
PLC-5 Processors

Channel 1A
fixed DH+ port

Keyswitch

Channel 0 - on-board

serial port

Channel 1A status
indicator (green/red)

Connect programming terminal
here when channel 1A is configured
for DH+ communications

Channel 1A communication port

Install memory
module here

Battery holder

Channel 1B status
indicator (green/red)

Channel 1B
communication port

PLC-5/11 Processor PLC-5/20 Processor

Battery (red)
Processor RUN/FAULT (green/red)
Force (amber)
Channel 0 communication

status (green)

Indicators:

Hardware Components

Front Panel 1-2

PLC-5/30, -5/40, -5/60,

-5/80 Processor

PLC-5/40L, -5/60L Processor

Keyswitch

Battery holder

Channel 2A status
indicator (green/red)

Connect programming terminal here
when channel 2A is configured for
DH+ communications

Channel 2A communication port

Channel 2B communication port

Channel 1A status
indicator (green/red)

Channel 1A communication port

Channel 1B communication port

Channel 2 status
indicator (green/red)

Channel 2
extended-local I/O
communication port

Channel 2B
status indicator
(green/red)

Install memory
module here

Channel 1B
status indicator
(green/red)

Channel 0 - on-board
serial port

The PLC-5/30 processor has 2 communication ports and 1 serial port

Battery (red)
Processor RUN/FAULT (green/red)
Force (amber)
Communication ACTIVE/FAULT

status (green/red)

Indicators:

Labels to write information
about the channel
communication mode,
station addresses, etc.

Connect programming terminal here
when channel 1A is configured for
DH+ communications

Hardware Components

Front Panel 1-3

Front Panel – Ethernet
PLC-5 Processors

PLC-5/20E Processor

Keyswitch

Channel 0 - on-board
serial port

Channel 1A status
indicator (green/red)

Connect programming
terminal here

Channel 1A

Battery (red)
Processor RUN/FAULT (green/red)
Force (amber)
Channel 0 communication

status (green)

Install memory
module here

Battery holder

Channel 1B status
indicator (green/red)

Channel 1B

Channel 2 Ethernet
status indicators

Channel 2

Indicators:

Battery (red)
Force (amber)

Communication
ACTIVE/FAULT (green/red)

Channel 0 - on-board
serial port

Labels to write information
about the channel
communication mode,
station addresses, etc.

Keyswitch

Channel 1A

Channel 1B

Battery holder

Channel 2

Indicators:

PLC-5/40E, -5/80E Processor

Channel 1A status
indicator (green/red)

Connect programming
terminal here

Channel 2 Ethernet
status indicators

Processor RUN/FAULT
(green/red)

Install memory
module here

Channel 1B status
indicator (green/red)

Hardware Components

Front Panel 1-4

Channel 2 Status Indicators

PLC-5/20C15 Processor

Keyswitch

I/O Status Indicator

Network Access Port

Channel 2

Channel 0

Channel 1 Status Indicators

DH+ Programming Terminal
Connection to Channel 1A

Channel 1A

Battery

Processor RUN/FAULT
Force

Channel 0 Communication
ACTIVE/FAULT

Memory Module Space

Battery Holder

Channel 1B

Keyswitch

I/O Status Indicator

Channel 2 Status Indicators

Network Access Port

Channel 2

Channel 1 Status Indicators

DH+ Programming Terminal
Connection to Channel 1A

Channel 1A

Channel 1B

Battery

Processor RUN/FAULT
Force

Channel 0 Communication
ACTIVE/FAULT

Channel 0 - on-board serial port

Memory Module Space

Battery Holder

PLC-5/40C15, -5/80C15 Processor

Front Panel – ControlNet PLC-5 Processors

ControlNet PLC-5 Processors

Phase Catalog Number

1.0/1.25 1785L20C, -L40C, -L80C

1.5 1785L20C15, -L40C15, -L80C15

Hardware Components

Front Panel 1-5

Hardware Components

REM I/O indicator
ACTIVE/FAULT
(green/red)

P
R
O
G

PLC-5/10 Processor PLC-5/12, -5/15, -5/25 Processor

Keyswitch

DH+ communication
indicator ACTIVE/FAULT
(green/red)

Connect programming
terminal here

Connect DH+
link here

Adapter indicator
(green)

Connect remote
I/O link here

Battery holder

Write the DH+
network station
number on this label

12373

Battery (red)
Processor RUN/FAULT (green/red)
Force (amber)

Indicators:

Front Panel – Classic
PLC-5 Processors

Hardware Components

Processor Comparison 1-6

Comparison Chart for

PLC-5 Family Processors

Processor Memory

(Words)

Local
Chassis

Remote Chassis
(I/O Racks)

I/O Capacity Communication

PLC-5/10 6K 1 resident none

128 (8-pt) 1, 256 (16-pt) 1, 512 (32-pt)

1

DH+ link

PLC-5/12 6K 1 resident none

128 (8-pt) 1, 256 (16-pt) 1, 512 (32-pt)

1

adapter, DH+ link

PLC-5/15 6K

(expands to
14K)

1 resident 12

(3 I/O racks)

• 512

1

• 512 inputs and 512 outputs using 16- or
32-pt modules

2

adapter/remote I/O scanner, DH+ link

PLC-5/25 13K

(expands to
21K)

1 resident 28

(7 I/O racks)

• 1024

1

• 1024 inputs and 1024 outputs using 16­or 32-pt modules

2

adapter/remote I/O scanner, DH+ link

PLC-5/11 8K 1 resident 4

(1 I/O rack)
rack must be
addressed as rack
3

• 256 (8-pt), 384 (16-pt), or 512 (16-pt)

1

• 512(16-pt) or 768 (32-pt)

2

• 1 channel (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

1 Any mix of I/O
2 Maximum I/O possible using 16-pt modules with 2-slot addressing or 32-pt modules with 1-slot addressing. Modules must alternate input/output in the chassis slots.

Hardware Components

Processor Comparison 1-7

PLC-5 comparison chart continued...

Processor Memory

(Words)

Local
Chassis

Remote Chassis
(I/O Racks)

I/O Capacity Communication

PLC-5/20 16K 1 resident 12

(3 I/O racks)

• 512

1

• 512 inputs and 512 outputs using 16- or
32-pt modules

• 1 channel (remote I/O scanner, adapter, DH+ link)

• 1 channel DH+ link

• 1 RS-232, RS-422, RS-423 serial port

PLC-5/20E 16K 1 resident 12

(3 I/O racks)

• 512

1

• 512 inputs and 512 outputs using 16- or
32-pt modules

• 1 channel (remote I/O scanner, adapter, DH+ link)

• 1 channel DH+ link

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel Ethernet

PLC-5/20C15 16K 1 resident 12 (3 I/O racks)

• 512

1

• 512 inputs and 512 outputs using 16- or
32-pt modules

• 1 channel (remote I/O scanner, adapter, DH+ link)

• 1 channel DH+ link

• 1 RS-232, RS-422, RS-423 serial port

• ControlNet

PLC-5/30 32K 1 resident 28

(7 I/O racks)

• 1024

1

• 1024 inputs and 1024 outputs using16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

1

Any mix of I/O

Hardware Components

Processor Comparison 1-8

PLC-5 comparison chart continued...

Processor Memory

(Words)

Local
Chassis

Remote Chassis
(I/O Racks)

I/O Capacity Communication

PLC-5/40

48K

3

1 resident

60

2

(15 I/O racks)

• 2048

1

• 2048 inputs and 2048 outputs using 16­or 32-pt modules

• 4 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

PLC-5/40L

48K

3

1 resident up
to 16
extended

60

2

(15 I/O racks)

• 2048

1

• 2048 inputs and 2048 outputs using 16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel extended local I/O scanner

PLC-5/40E

48K

3

1 resident
(16 rack
addressing
capability)

60
(15 I/O racks)

• 2048

1

• 2048 inputs and 2048 outputs using 16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel Ethernet

PLC-5/40C15

48K

3

1 resident 60

15 I/O racks

• 2048

1

• 2048 inputs and 2048 outputs using 16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel ControlNet

PLC-5/60

3

64K 1 resident

92

2

(23 I/O racks)

• 3072

1

• 3072 inputs and 3072 outputs using 16­or 32-pt modules

• 4 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

1

Any mix of I/O

2

Maximum of 32 physical devices/channel

3

Maximum of 57K words per program file and 32K words per data table file

Hardware Components

Processor Comparison 1-9

PLC-5 comparison chart continued...

PLC-5 ControlNet Processors - Maximum I/O Map Entries

Processor Memory

(Words)

Local
Chassis

Remote Chassis
(I/O Racks)

I/O Capacity Communication

PLC-5/60L

3

64K 1 resident up

to 16
extended

64

2

(23 I/O racks)

• 3072

1

• 3072 inputs and 3072 outputs using16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel extended local I/O scanner

PLC-5/80

3.4

100K 1 resident

92

2

(23 I/O racks)

• 3072

1

• 3072 inputs and 3072 outputs using 16­or 32-pt modules

• 4 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

PLC-5/80E

3,4

100K 1 resident

92

2

(23 I/O racks)

• 3072

1

• 3072 inputs and 3072 outputs using 16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel Ethernet

PLC-5/80C15

3.4

100K 1 resident

92

2

(23 I/O racks)

• 3072

1

• 3072 inputs and 3072 outputs using 16­or 32-pt modules

• 2 channels (remote I/O scanner, adapter, DH+ link)

• 1 RS-232, RS-422, RS-423 serial port

• 1 channel ControlNet

1

Any mix of I/O

2

Maximum of 32 physical devices/channel

3

Maximum of 57K words per program file and 32K words per data table file

4

Maximum of 64K words total data table space

Phase 1.0/1.25 Phase 1.5

Processor Number of

Mappings:

Number of
DIF
Files:

Number of
DIF
Words:

Number of
DOF
Files:

Number of
DOF
Words:

Processor Number of

Mappings:

Number of
DIF
Files:

Number of
DIF
Words:

Number of
DOF
Files:

Number of
DOF
Words:

PLC-5/20C 64 1 1000 1 1000 PLC-5/20C 64 2 2000 2 2000
PLC-5/40C 64 1 1000 1 1000 PLC-5/40C 96 3 3000 3 3000
PLC-5/80C 64 1 1000 1 1000 PLC-5/80C 128 4 4000 4 4000

Hardware Components

1771 I/O Chassis 1-10

1771 I/O Chassis for PLC-5 Family

Processors

7KH3/&SURFHVVRUVDUHDOVRFRPSDWLEOHZLWK$$DQG$FKDVVLVZLWKVORWSRZHUVXSSOLHVRQO\

Catalog Number Chassis Size Mounting

Backpanel 19” Rack

Power Supply Socket

1771-A1B 4-slot X left
1771-A2B 8-slot X left
1771-A3B 12-slot X X top

1771-A3B1 12-slot X left

1771-A4B 16-slot X left

When using these processors with the
1771-A1, A2, and A4 chassis:

Only this mode of addressing is
supported:

Classic PLC-5 processors 2-slot and 1-slot in the local rack

Enhanced and Ethernet PLC-5 processors 2-slot addressing

ControlNet PLC-5 processors 2-slot addressing

Hardware Components

Power Supply Modules 1-11

Power Supply Modules in a Chassis

(containing a PLC-5 processor)

Output
Current

Output Current (in amps) when Parallel with: Power Supply

Power Supply Input Power (in Amps) P3 P4 P4S P4S1 P5 P6S P6S1 Location

1771-P3 120V ac 3 6 11 11 slot

1771-P4 120V ac 8 11 16 16 slot

1771-P4S 120V ac 8 11 16 16 slot

1771-P4S1 100V ac 8 16 slot

1771-P4R 120V ac

8, 16, 24

2

slot

1771-P5 24V dc 8 16 slot

1771-P6S 220V ac 8 16 slot

1771-P6S1 200V ac 8 16 slot

1771-P6R 220V ac

8, 16, 24

2

slot

1771-P7 120/220V ac 16

external

1

1771-PS7 120/220V ac 16

external

1

1

You cannot use an external power supply and a power supply module to power the same chassis; they are not compatible.

2

See publication 1771-2.166 for more information.

Hardware Components

Power Supplies 1-12

Power Supplies in a Remote Chassis (1771-ASB)

or an Extended Local I/O Chassis (1771-ALX)

Output Current Output Current (in amps) when Parallel with: Power Supply

Power Supply Input Power (in Amps) P3 P4 P4S P4S1 P5 P6S P6S1 Location

1771-P3 120V ac 3 6 11 11 slot

1771-P4 120V ac 8 11 16 16 slot

1771-P4S 120V ac 8 11 16 16 slot

1771-P4S1 100V ac 8 16 slot

1771-P4R 120V ac 8, 16, 24

2

slot

1771-P5 24V dc 8 16 slot

1771-P6S 220V ac 8 16 slot

1771-P6S1 200V ac 8 16 slot

1771-P6R 220V ac 8, 16, 24

2

slot

1771-P1 120/220V ac 6.5 external

1

1771-P2 120/220V ac 6.5 external

1

1771-P7 120/220V ac 16 external

1

1771-PS7 120/220V ac 16 external

1

1777-P2 120/220V ac 9 external

1

1777-P4 24V dc 9 external

1

1

You cannot use an external power supply and a power supply module to power the same chassis; they are not compatible.

2

See publication 1771-2.166 for more information.

Hardware Components

Keyswitch 1-13

Front Panel Keyswitch

Keyswitch Position

Operation RUN PROG REM

RUN PROG

Execute programs (with outputs enabled) X X
Execute programs (with outputs disabled)
Save program to disk X X X X
Restore programs X X X
Create or delete: ladder files, SFC files, data table files X X
Edit online: ladder files and SFC files

(program files already exist)

X X X

Force live outputs X X
Prohibit processor from scanning program X X
Change operating mode using a programming device X X
Download to/from EEPROM X X
Automatically configure remote I/O X X
Edit data table values

(data table files already exist)

X X X X

Establish ControlNet connections and exchange data X X X X

Hardware Components

Processor Status File 1-14

Processor Status File

This word of the status file: Stores:

S:0 Arithmetic flags

• bit 0 = carry

• bit 1 = overflow

• bit 2 = zero

• bit 3 = sign

S:1 Processor status and flags

Bit

Description
0 RAM checksum is invalid at power-up
1 processor in RUN mode
2 processor in TEST mode
3 processor in PROG mode
4 processor burning EEPROM
5 processor in download mode
6 processor has test edits enabled
7 mode select switch in REMOTE position
8 forces enabled
9 forces present
10 processor successfully burned EEPROM
11 performing online programming
12 not defined
13 user program checksum calculated
14 last scan of ladder or SFC step
15 processor running first program scan or the first scan of the next step

in an SFC

Hardware Components

Processor Status File 1-15

processor status file continued

This word of the status file: Stores:

S:7 Global status bits:

• S:7/0-7 - - rack fault bits for racks 0-7

• S:7/8-15 - - rack queue-full bits for racks 0-7
See also S:27, S:32, S:33, S:34, and S:35

S:8 Last program scan (in ms)
S:9 Maximum program scan (in ms)
S:2 Switch setting information

• bits 0 - 6 DH+ station number

• bit 11-12 are set based on the I/O chassis backplane switches

• bit 12

bit 11 = I/O chassis addressing

0 0 illegal
1 01/2-slot
0 11-slot
1 12-slot

• bit 13: 1 = load from EEPROM

• bit 14: 1 = RAM backup not configured

• bit 15: 1 = memory unprotected

S:3 to S:6 Active Node table for channel 1A

Word Bits DH+ Station #
3 0-15 00-17
4 0-15 20-37
5 0-15 40-57
6 0-15 60-77

Hardware Components

Processor Status File 1-16

processor status file continued...

This word of the status file: Stores:

S:10 Minor fault (word 1)

Bit Description
0 battery is low (replace in 1-2 days)
1 DH+ active node table has changed
2 STI delay too short, interrupt program overlap
3 EEPROM memory transfer at power-up
4 edits prevent SFC continuing; data table size changed

during program mode; reset automatically in run mode
5 invalid I/O status file
6 not defined
7 no more command blocks exist
8 not enough memory on the memory module to upload the program from the processor
9 no MCP is configured to run
10 MCP not allowed
11 PII word number not in local rack
12 PII overlap
13 no command blocks exist to get PII
14 arithmetic overflow
15 SFC action overlap

See also S:17

Hardware Components

Processor Status File 1-17

processor status file continued...

This word of the status file: Stores:

S:11 Major fault

Bit Description
0 corrupted program file (codes 10-19)
1 corrupted address in ladder file (codes 20-29)
2 programming error (codes 30-49)
3 SFC fault (codes 71-79)
4 error while assembling program (code 70); duplicate LBLs found
5 start-up protection fault; processor sets this bit when powering up in run mode if bit S:26/1 is
set
6 peripheral device fault
7 jumped to fault routine (codes 0-9)
8 watchdog faulted
9 system configured wrong (codes 80-89)
10 recoverable hardware error
11 MCP does not exist or is not ladder or SFC file
12 PII does not exist or is not ladder
13 STI does not exist or is not ladder
14 fault routine does not exist or is not ladder
15 fault occurred in a non-ladder file

Hardware Components

Processor Status File 1-18

processor status file continued...

This word of the status file: Stores:

S:12 Fault codes

Code Description
0-9 user-defined
10 failed data table check
11 bad user program checksum
12 bad integer operand type
13 bad mixed mode operand type
14 not enough operands for instruction
15 too many operands for instruction
16 bad instruction found
17 no expression end in a CPT math expression
18 missing end of edit zone
19 download aborted
20 indirect address out of range (high)
21 indirect address out of range (low)
22 attempt to access undefined file
23 file number less than 0 or greater than number of defined files; or,

indirect reference to file 0, 1, 2; or bad file number24

indirect reference to wrong file type
25 reserved
26 reserved
27 reserved
28 reserved
29 reserved
30 subroutine jump nesting level exceeded

Hardware Components

Processor Status File 1-19

processor status file continued...

This word of the status file: Stores:

S:12 continued... Fault codes

Code Description
31 too few subroutine parameters
32 jump to non-ladder file
33 CAR routine not 68000 code
34 bad timer parameters entered
35 bad PID delta time entered
36 PID setpoint out of range
37 invalid I/O specified in an immediate I/O instruction
38 invalid use of return instruction
39 FOR loop missing NXT
40 control file too small
41 NXT instruction with no FOR
42 jump target does not exist or JMP missing LBL
43 file is not an SFC
44 error using SFR
45 invalid channel number entered
46 IDI or IDO instruction length operand too long (> 64 words)
46-69 reserved

Hardware Components

Processor Status File 1-20

processor status file continued...

This word of the status file: Stores:

S:12 continued... Fault codes

Code Description
70 duplicate labels
71 SFC subchart is already executing
72 tried to stop an SFC that is not running
73 maximum number of SFC subcharts exceeded
74 SFC file error
75 SFC contains too many active steps
76 SFC step loops back to itself
77 SFC references a step, transition, subchart, or SC file that is

missing, empty or too small
78 SFC could not continue after power loss
79 error in downloading an SFC to a processor that cannot run

SFCs or this specific PLC processor does not support this

Enhanced SFC
80 I/O configuration error
81 illegal setting of I/O chassis backplane switch
82 illegal cartridge type
83 user watchdog fault
84 error in user-configured adapter mode block transfers
85 bad cartridge
86 cartridge incompatible with host
87 rack addressing overlap (includes any adapter channel)

Hardware Components

Processor Status File 1-21

processor status file continued...

This word of the status file: Stores:

S:12 continued... Fault codes

Code Description
88 scanner channels are overloading the remote I/O buffer; too much data for the

processor to process
90 Sidecar module extensive memory test failed
91 Sidecar module undefined message type
92 Sidecar module requesting undefined pool
93 Sidecar module illegal maximum pool size
94 Sidecar module illegal ASCII message
95 Sidecar module reported fault, which may be the result of a bad

program that corrupts memory or of a hardware failure
96 Sidecar module not physically connected to the PLC-5 processor
97 Sidecar module requested a pool size that is too small for PCCC command (occurs at power-up)
98 Sidecar module first/last 16 bytes RAM test failed
99 Sidecar module-to-processor data transfer faulted
100 Processor-to-sidecar module data transfer failed
101 Sidecar module end of scan data transfer failed
102 The file number specified for raw data transfer through the sidecar

module is an illegal value
103 The element number specified for raw data transfer through the

sidecar module is an illegal value
104 The size of the raw data transfer requested through the sidecar module is an illegal size
105 The offset into the raw data transfer segment of the sidecar module is an illegal value

Hardware Components

Processor Status File 1-22

processor status file continued...

This word of the status file: Stores:

S:12 continued... Fault codes

Code Description
106 Sidecar module transfer protection violation; for PLC-5/26, -5/46,

and -5/86 processors only
200 ControlNet scheduled output data missed
201 ControlNet input data missed
202 Not used
203 Reserved
204 ControlNet configuration is too complex
205 ControlNet configuration exceeds bandwidth

206 Reserved
207 Reserved
208 Too many pending ControlNet I/O connections

S:13 Program file where fault occurred
S:14 Rung number where fault occurred
S:15 VME status file
S:16 I/O Status File

Hardware Components

Processor Status File 1-23

processor status file continued...

This word of the status file: Stores:

S:17 Minor fault (word 2)

Bit Description
0 BT queue full to remote I/O
1 queue full – channel 1A; maximum remote block transfers used
2 queue full – channel 1B; maximum remote block transfers used
3 queue full – channel 2A; maximum remote block transfers used
4 queue full – channel 2B; maximum remote block transfers used
5 no modem on serial port
6 remote I/O rack in local rack table; or, remote I/O rack is greater than the image size
7 firmware revision for channel pairs 1A/1B or 2A/2B does not

match processor firmware revision
8 ASCII instruction error
9 duplicate node address
10 DF1 master poll list error
11 protected processor data table element violation
12 protected processor file violation
13 using all 32 ControlNet MSGs
14 using all 32 ControlNet 1771 READ and/or 1771 WRITE CIOs
15 using all 8 ControlNet Flex I/O CIOs

See also S:10.

S:18 Processor clock year
S:19 Processor clock month
S:20 Processor clock day
S:21 Processor clock hour
S:22 Processor clock minute
S:23 Processor clock second

Hardware Components

Processor Status File 1-24

processor status file continued...

This word of the status file: Stores:

S:24 Indexed addressing offset
S:25 Reserved
S:261. User control bits

Bit

Description
0 Restart/continuous SFC: when reset, processor restarts at first step in SFC.

When set, processor continues with active step after power loss or change to RUN
1 Start-up protection after power loss: when reset, no protection.

When set, processor sets major fault bit S:11/5 when powering up in run mode
2 Define the address of the local rack: when reset, local rack

address is 0. When set, local rack address is 1
3 Set complementary I/O: when reset, complementary I/O is not

enabled. When set, complementary I/O is enabled
4 Local block transfer compatibility bit: when reset, normal

operation. When set, eliminates frequent checksum errors to

certain BT modules
5 PLC-3 scanner compatibility bit: when set (1), adapter channel

response delayed by 1 ms; when reset (0), operate in

normal response time
6 Data table-modification inhibit bit. When set (1), user cannot edit

the data table while processor is in run mode

S:27 Rack control bits:

• S:27/0-7 - - I/O rack inhibit bits for racks 0-7

• S:27/8-15 - - I/O rack reset bits for racks 0-7
See also S:7, S:32, S:33, S:34, and S:35.

S:28 Program watchdog setpoint

Hardware Components

Processor Status File 1-25

processor status file continued...

This word of the status file: Stores:

S:29 Fault routine file
S:30 STI setpoint
S:31 STI file number
S:32 Global status bits:

• S:32/0-7 - - rack fault bits for racks 10-17 (octal)

• S:32/8-15 - - rack queue-full bits for racks 10-17
See also S:7, S:27, S:33, S:34, and S:35.

S:33 Rack control bits:

• S:33/0-7 - - I/O rack inhibit bits for racks 10-17 (octal)

• S:33/8-15 - - I/O rack reset bits for racks 10-17
See also S:7, S:27, S:32, S:34, and S:35.

S:34 Global status bits:

• S:34/0-7 - - rack fault bits for racks 20-27 (octal)

• S:34/8-15 - - rack queue-full bits for racks 20-27
See also S:7, S:27, S:32, S:33, and S:35.

S:35 Rack control bits:

• S:35/0-7 - - I/O rack inhibit bits for racks 20-27 (octal)

• S:35/8-15 - - I/O rack reset bits for racks 20-27
See also S:7, S:27, S:32, S:33, and S:34.

S:36 Reserved
S:37 Reserved

Hardware Components

Processor Status File 1-26

processor status file continued...

This word of the status file: Stores:

Classic PLC-5 processors use only 37 words for the status file. Therefore, the following descriptions apply only to
Enhanced, Ethernet, and ControlNet processors.

S:38 - S:45 Reserved
S:46 PII program file number
S:47 PII module group
S:48 PII bit mask
S:49 PII compare value
S:50 PII down count
S:51 PII changed bit
S:52 PII events since last interrupt
S:53 STI scan time (in ms)
S:54 STI maximum scan time (in ms)
S:55 PII last scan time (in ms)
S:56 PII maximum scan time (in ms)
S:57 User program checksum
S:58 Reserved
S:59 Extended-local I/O channel discrete transfer scan (in ms)
S:48 PII bit mask

Hardware Components

Processor Status File 1-27

processor status file continued...

This word of the status file: Stores:

S:60 Extended-local I/O channel discrete maximum scan (in ms)
S:61 Extended-local I/O channel block-transfer scan (in ms)
S:62 Extended-I/O channel maximum block-transfer scan (in ms)
S:63 Protected processor data table protection file number
S:64 The number of remote block transfer command blocks being used by channel pair 1A/1B.
S:65 The number of remote block transfer command blocks being used by channel 2A/2B or by channel 2 (ControlNet)
S:66 Reserved
S:72* ControlNet node of this processor
S:73* ControlNet PLC-2 compatibility file
S:74* Time in msec between itemations of ControlNet subsystem diagnostics
S:75* Maximum of S:74
S:76 Number of slots in processor-resident local chassis
S:77 Communication time slice for communication housekeeping functions (in ms)
S:78 MCP I/O update disable bits

Bit 0 for MCP A
Bit 1 for MCP B, etc.

* Applies only to ControlNet phase 1.5 PLC-5 processors.

Hardware Components

Processor Status File 1-28

processor status file continued...

This word of the status file: Stores:

S:79 MCP inhibit bits

Bit 0 for MCP A
Bit 1 for MCP B
etc.

S:80-S:127 MCP file number

MCP scan time (in ms)
MCP max scan time (in ms)

The above sequence applies to each MCP; therefore, each MCP has 3 status words.
For example, word 80: file number for MCP A

word 81: scan time for MCP A

word 82: maximum scan time for MCP A

word 83: file number for MCP B

word 84: scan time for MCP B

etc.

Hardware Components

I/O Status File 1-29

I/O Status File Format

(N:15 is defined in word S:16 of the processor status file.)

Defined I/O status file

N15:0

N15:1

N15:14

N15:15

rack 0

rack 7 (maximum for PLC-5/25, -5/30 processors)

Word in integer file

N15:30

N15:31

rack 17 (maximum for PLC-5/40, -5/40L, -5/40E, -5/40C processors)

N15:46

N15:47

rack 27 (maximum for PLC-5/60, -5/60L, -5/80, -5/80E, -5/80C processors)

rack 3 (maximum for PLC-5/11, -5/15, -5/20, -5/20E, and -5/20C) processors

Hardware Components

I/O Status File 1-30

Word 1 in the I/O Status File

This bit: Corresponds to:

Fault bits 00 first 1/4 rack starting I/O group 0

01 second 1/4 rack starting I/O group 2

02 third 1/4 rack starting I/O group 4

03 fourth1/4 rack starting I/O group 6

Present bits 08 first 1/4 rack starting I/O group 0

09 second 1/4 rack starting I/O group 2

10 third 1/4 rack starting I/O group 4

11 fourth1/4 rack starting I/O group 6

00010203040506070809101112131415

Not Used

Not Used

Fault Bits

Present Bits

N15:14

Hardware Components

I/O Status File 1-31

Word 2 in the I/O Status File

This bit: Corresponds to:

Inhibit bits 00 first 1/4 rack starting I/O group 0

01 second 1/4 rack starting I/O group 2
02 third 1/4 rack starting I/O group 4
03 fourth1/4 rack starting I/O group 6

Reset bits 08 first 1/4 rack starting I/O group 0

09 second 1/4 rack starting I/O group 2
10 third 1/4 rack starting I/O group 4
11 fourth1/4 rack starting I/O group 6



ATTENTION: When you use a ladder program or the software to inhibit and reset an I/O rack, you must set or
clear the reset and inhibit bits that correspond to each quarter rack in a given chassis. Failure to set all the appropriate
bits could cause unpredictable operation due to scanning only part of the I/O chassis.

00010203040506070809101112131415

Not Used

Not Used

Inhibit Bits

Reset Bits

N15:15

Addressing

Data Table Files 2-1

Addressing Data Table Files
(Enhanced, Ethernet, and ControlNet Processors) Series E and Later –

File Type

File-Type
Identifier

File

Number

Maximum Size of File

16-bit words and structures

c

Memory Used in

Overhead for each

File

(in 16-bit words)

Memory Used

(in 16-bit words) per

Word, Character, or

Structure

PLC-5/11, -5/20 PLC-5/30 PLC-5/40 PLC-5/60, -5/80

Output image O 0 32 64 128 192 6 1/word
Input image I 1 32 64 128 192 6 1/word
Status S 2 128 128 128 128 6 1/word
Bit (binary) B

3

a

D7KLVLVWKHGHIDXOWILOHQXPEHUDQGW\SH)RUWKLVILOHW\SH\RXFDQDVVLJQDQ\ILOHQXPEHUIURPWKURXJK

2000 words 6 1/word

Timer T

4

a

6000 words/2000 structures 6 3/structure

Counter C

5

a

6000 words/2000 structures 6 3/structure

Control R

6

a

6000 words/2000 structures 6 3/structure

Integer N

7

a

2000 words 6 1/word

Floating-point F

8

a

4000 words/2000 structures 6 2/structure

ASCII A 3-999 2000 words 6 1/2 per character
BCD D 3-999 2000words 6 1/word
Block-transfer BT 3-999 12000 words/2000 structures 6 6/structure
CIO CT 3-999 12000 words/2000 structures 6 6/structure
Message MG 3-999

32760 words/585 structures

b

E7KHPD[LPXPVL]HRIDGDWDWDEOHILOHLV.ZRUGV7KHPD[LPXPVL]HRIWKHHQWLUHGDWDWDEOHLV.ZRUGV
F&RQWURO1HW3/&VGRQRWVXSSRUWHOHPHQWVILOH7KHPD[LPXPVL]HRIDGDWDWDEOHILOHLV.ZRUGV7KHPD[LPXPVL]HRIWKHHQWLUHGDWDWDEOHLV.ZRUGV
G&RQWURO1HW3/&VRQO\



6 56/structure

PID PD 3-999

32718 words/399 structures

b

6 82/structure

SFC status SC 3-999 6000 words/2000 structures 6 3/structure
ASCII string ST 3-999

32760 words/780 structures

b

6 42/structure

Unused -- 9-999 6 6 0

Addressing

Data Table Files 2-2

File Type

File-Type
Identifier

File

Number

Maximum Size of File

16-bit words and structures

Memory Used in

Overhead for each File

(in 16-bit words)

Memory Used

(in 16-bit words) per Word,

Character, or Structure

PLC-5/11, -5/20 PLC-5/30 PLC-5/40 PLC-5/60, -5/80

Output image O 0 32 64 128 192 6 1/word
Input image I 1 32 64 128 192 6 1/word
Status S 2 128 128 128 128 6 1/word
Bit (binary) B

3

a

1000 words 6 1/word

Timer T

4

1

3000 words/1000 structures 6 3/structure

Counter C

5

1

3000 words/1000 structures 6 3/structure

Control R

6

1

3000 words/1000 structures 6 3/structure

Integer N

7

1

1000 words 6 1/word

Floating-point F

8

1

2000 words/1000 structures 6 2/structure

ASCII A 3-999 1000 words 6 1/2 per character
BCD D 3-999 1000words 6 1/word
Block-transfer BT 3-999 6000 words/1000 structures 6 6/structure
Message MG 3-999

32760 words/585 structures

b

6 56/structure

PID PD 3-999

32718 words/399 structures

2

6 82/structure

SFC status SC 3-999 3000 words/1000 structures 6 3/structure
ASCII string ST 3-999

32760 words/780 structures

2

6 42/structure

Unused -- 9-999 6 6 0

D7KLVLVWKHGHIDXOWILOHQXPEHUDQGW\SH)RUWKLVILOHW\SH\RXFDQDVVLJQDQ\ILOHQXPEHUIURPWKURXJK
E7KHPD[LPXPVL]HRIDGDWDWDEOHILOHLV.ZRUGV7KHPD[LPXPVL]HRIWKHHQWLUHGDWDWDEOHLV.ZRUGV
F&RQWURO1HW3/&VGRQRWVXSSRUWHOHPHQWVILOH

Addressing

Data Table Files 2-3

Data Table Files - Classic Processors

File Description

Number
(Default
File)

Maximum Size of File
(16-bit words and
structures)

Memory Used

PLC-5/10,

-5/12, -5/15

PLC-5/25

Output Image O 0 32 64 2/file + 1/word

Input Image I 1 32 64 2/file + 1/word

Status S 2 32 32 2/file + 1/word

Bit (binary) B 3-999 (3) 1000 words 2/file + 1/word

Timer T 3-999 (4) 3000 words/1000 structures 2/file + 3/structure

Counter C 3-999 (5) 3000 words/1000 structures 2/file + 3/structure

Control R 3-999 (6) 3000 words/1000 structures 2/file + 3/structure

Integer N 3-999 (7) 1000 words 2/file + 1/word

Floating Point F 3-999 (8) 1000 words 2/file + 2/structure

ASCII A 3 - 999 1000 words 2/file + 1/2 per

character

BCD D 3 - 999 1000 words 2/file + 1/word

Extra Storage 3 - 999

PLC-5 Memory

Data Table

program

Addressing

Program Files 2-4

Program Files

Program File Number Program File Number

Description Classic

PLC-5 Processors

Enhanced, Ethernet, and ControlNet
PLC-5 Processors

System 0 0

Sequential Function 1

1 - 1999

2

Ladder 2 - 999

2 - 1999

2

Structured Text

1

2 - 1999

2

Assigned as needed:

Subroutines
Fault Routines
Selectable Timed Interrupts

Processor Input Interrupts

1

SFC Step/Transition
SFC Actions

1

3 - 999 2 - 1999

1

Enhanced, Ethernet, and ControlNet PLC-5 processors only.

2

Enhanced, Ethernet, and ControlNet PLC-5 processors can have up to 16 main control programs (in any combination of SFC,
ladder, and structured text).

PLC-5 Memory

Data Table

program

Addressing

I/O Images/Symbolic 2-5

I/O Image Addressing

a:bbc/dd

a I/O data type identifier

I - input device

O - output device

bb I/O rack number

00 - 03 (octal) PLC-5/10, -5/11, -5/12, -5/15, -5/20, -5/20E, -5/20C15

00 - 07 (octal) PLC-5/25, -5/30

00 - 17 (octal) PLC-5/40, -5/40L, -5/40E, -5/40C15

00 - 27 (octal) PLC-5/60, -5/60L, -5/80, -5/80E, -5/80C15

c I/O group number 0 - 7 (octal)

dd terminal (bit) number 00 - 17 (octal)

Examples: I:001/07 input device, rack 00, group 1, terminal (bit) 7

O:074/10 output device, rack 07, group 4, terminal (bit) 10

Addressing

Logical 2-6

Logical Addressing

Where: Is the:

# File address identifier. Omit for bit, word, and structure addresses (also indicates indexed addressing, see next

page)

X

File type: B - binary N - integer T - timer MG - message 1 CT - ControlNet Transfer

2

C - counter O - output A - ASCII PD - PID

1

ST - ASCII string

1

F - floating point R - control D - BCD SC - SFC status

1

I - input S - status BT - block transfer

1

F File number: 0 - output 1 - input 2 - status 3 - 999 any other type

: Colon delimiter separates file and structure/word numbers

e Structure/word number: 0 - 277

octal for input/output files

0 - 31 decimal for the status file (Classic PLC-5 processors)

up to: 0 - 127 decimal for the status file

0 - 999 for all the file types except MG, PD, and ST files

. Period delimiter is used only with structure-member mnemonics in counter, timer and control files

s Structure-member mnemonic is used only with timer, counter, control, BT, MG, PD, SC, and ST files

/ Bit delimiter separates bit number

b Bit number: 00 - 07 or 10 - 17 for input/output files

00 - 15 for all other files
00 - 15,999 for binary files when using direct bit address

1

Enhanced, Ethernet, and ControlNet PLC-5 processors only.

2

ControlNet only.

bit number

bit delimiter

structure-member

delimiter

structure/word number

delimiter

file number

file type

file address

mnemonic

identifier

# X F: 3. s / b

Addressing

Indexed/Indirect 2-7

Indexed Addressing

Indexed addressing offsets an address by the number of elements you select. You store the offset value in an offset word in word 24 of the status
file S:24. The processor starts operation at the base address plus the offset. You can manipulate the offset word in your ladder logic.

The indexed address symbol is the # character. Place the # character immediately before the file-type identifier in a logical a ddress.

Important: File instructions manipulate the offset value stored at S:24. Make sure that you monitor or load the offset value you want prior to

using an indexed address. Unpredictable machine operation could occur.

Indirect Addressing

• You can indirectly address the following: file number; element number; bit number

• Substitute address must be of type: N, T, C, R, B, I, O, S.

• Enter the address in brackets [ ]

Examples: Indirect Address Variable

N[N7:0] file number

N7:[C5:7.ACC] element number

B3:/[I:017] bit number

Addressing

Module Placement 2-8

I/O Addressing Modes

Discrete I/O Module Placement for Addressing Modes

Addressing Concept Summary

2-slot addressing 1-slot addressing 1/2-slot addressing

• two I/O module slots = 1 group

• each physical 2-slot I/O group corresponds to one
word (16 bits) in the input image table and one
word (16 bits) in the output image table

• one I/O module slot = 1 group

• each physical slot in the chassis corresponds to
one word (16 bits) in the input image table and one
word (16 bits) in the output image table

• one half of an I/O module slot = 1 group

• each physical slot in the chassis corresponds to
two words (32 bits) in the input image table and
two words (32 bits) in the output image table

I/O 2-slot addressing 1-slot addressing 1/2-slot addressing

8-pt
modules

no restriction on module placement no restriction on module placement, but does

not make best use of I/O image and available
I/O addresses

no restriction on module placement, but does
not make best use of I/O image and available
I/O addresses

16-pt
modules

must use 1 input and 1 output module per even/odd
slot pair

no restriction on module placement no restriction on module placement, but does

not make best use of I/O image and available
I/O addresses

32-pt
modules

not allowed must use 1 input and 1 output module per

even/odd slot pair

no restriction on module placement

If you are using this chassis size: 2-slot addressing 1-slot addressing 1/2-slot addressing

4-slot 1/4 rack 1/2 rack 1 rack

8-slot 1/2 rack 1 rack 2 racks

12-slot 3/4 rack 1 1/2 racks 3 racks

16-slot 1 rack 2 racks 4 racks

Instruction Set

Status Bits 3-1

Instruction Set

Instruction Set – Status Bits

Category Mnemonic

Word 0

Word 1 Word 2

15 14 13 12 11 10 09 08

TIMER (T4:

n

)

2

TON TOF RTO EN TT DN .PRE .ACC

COUNTER (C5:

n

)

2

CTU CTD CU CD DN OV UN .PRE .ACC

FILE (R6:

n

)

2

FAL EN DN ER .LEN .POS

FSC

EN DN ER IN FD .LEN .POS

FFL FFU

EN EU DN EM .LEN .POS

LFL

1

LFU

1

EN EU DN EM .LEN .POS

BSL BSR

EN DN ER UL .LEN .POS

FBC DDT

EN DN ER IN FD .LEN .POS

SQI SQO SQL EN

DN ER .LEN .POS

ASCII (R6:

n

)

2

ARL 1AWT 1AWA 1EN EU DN EM ER UL .LEN .POS

AHL

1

EN DN EM ER FD

ACB 1ABL

1

EN EU DN EM ER FD

COMPUTE (R6:n)

2

AVE 1SRT 1STD 1EN DN ER .LEN .POS

1

Enhanced, Ethernet, and ControlNet PLC-5 processors only

2

n

= starting structure number 0-999

Status Bits:

.EN – enable
.TT – timing
.DN – done
.OV – overflow
.UN – underflow
.EU – unload

enable
.FD – found
.UL – unload
.ER – error
.EM – empty
.CD – count down

enable
.CU – count up

enable
.IN – inhibit
.EU – queue

Instruction Set

Relay 3-2

Relay Instructions

Instruction Description

Examine On
XIC

Examine data table bit I:012/07, which corresponds to terminal 7 of an input module in I/O
rack 1, I/O group 2. If this data table bit is set (1), the instruction is true.

Examine Off
XIO

Examine data table bit I:012/07, which corresponds to terminal 7 of an input module in I/O
rack 1, I/O group 2. If this data table bit is reset (0), the instruction is true.

Output Energize
OTE

If the input instructions preceding this output instruction on the same rung go true, set (1) bit
O:013/01, which corresponds to terminal 1 of an output module in I/O rack 1, I/O group 3.

Output Latch
OTL

If the input conditions preceding this output instruction on the same rung go true, set (1) bit
O:013/01, which corresponds to terminal 1 of an output module in I/O rack 1, I/O group 3. This
data table bit remains set until an OTU instruction resets the bit.

Output Unlatch
OTU

If the input conditions preceding this output instruction on the same rung go true, reset (0) bit
O:013/01, which corresponds to terminal 1 of an output module in I/O rack 1, I/O group 3. This
is necessary to reset a bit that has been latched on.

I:012

] [

07

I:012

] / [

07

O:013

()

01

O:013

(L)
01

O:013

(U)

01

Instruction Set

Relay 3-3

relay instructions continued...

Instruction Description

Immediate Input
IIN

This instruction updates a word of input–image bits before the next normal input-image update.
For a local chassis, program scan is interrupted while the inputs of the addressed I/O group are
scanned; for a remote or ControlNet chassis, program scan is interrupted only to update the
input image with the latest states as found in the remote I/O or ControlNet buffer.

Immediate Output
IOT

This instruction updates a word of output–image bits before the next normal output-image
update. For a local chassis, program scan is interrupted while the outputs of the addressed I/O
group are scanned; for a remote or ControlNet chassis, program scan is interrupted only to
update the remote I/O or ControlNet buffer with the latest states as found in the output image.

01

(IIN)

01

(IOT)

Instruction Set

Relay 3-4

relay instructions continued...

Instruction Description

Immediate Data
Input
IDI
for ControlNet
processors only

If the input conditions are true, an immediate data input is initiated that updates the destination
file from the private ControlNet buffers before the next normal input-image update. The Data file
offset (232) is where the data is stored. The Length (10) identifies the number of words in the
transfer – it can be an immediate value ranging from 1 to 64 or a logical address that specifies
the number of words to be transferred. The Destination (N11:232) is the destination of the
words to be transferred. The Destination should be the matching data-table address in the Data
Input File (DIF) except when you use the instruction to ensure data-block integrity in the case of
Selectable Timed Interrupts (STIs).

Immediate Data
Output
IDO
for ControlNet
processors only

If the input conditions are true, an immediate data output is initiated that updates the private
ControlNet output buffers from the source file before the next normal output-image update. The
Data file offset (175) is the offset into the buffer where the data is stored. The Length (24)
identifies the number of words in the transfer-it can be an immediate value ranging from 1 to 64
or a logical address that specifies the number of words to be transferred. The Source (N12:175)
is the source of the words to be transferred. The Source should be the matching data-table
address in the Data Output File (DOF) except when you use the instruction to ensure data-block
integrity in the case of Selectable Timed Interrupts (STIs).

IMMEDIATE DATA INPUT

Data file offset 232

Length 10

Destination N11:232

IDI

IMMEDIATE DATA OUTPUT

Data file offset 175

Length 24

Source N12:175

IDO

Instruction Set

Timer 3-5

Timer Instructions

Instruction Description

Timer On Delay
TON

Status Bits:
EN – Enable
TT – Timer Timing
DN – Done

If the input conditions go true, timer T4:1 starts incrementing in 1-second intervals. When
the accumulated value is greater than or equal to the preset value (15), the timer stops
and sets the timer done bit.

Timer Off Delay
TOF

Status Bits:
EN – Enable
TT – Timer Timing
DN – Done

If the input conditions are false, timer T4:1 starts incrementing in 10 ms intervals as long as the
rung remains false. When the accumulated value is greater than or equal to the preset value
(180), the timer stops and resets the timer done bit.

TIMER ON DELAY

Timer T4:1

Time Base 1.0

Preset 15

Accum 0

TON

Rung
ConditionEN15TT14DN13

ACC
Value

TON
Status

False 0000 Reset

True 1 1 0 increase Timing

True 1 0 1 >=preset Done

TIMER OFF DELAY

Timer T4:1

Time Base .01

Preset 180

Accum 0

TOF

Rung
ConditionEN15TT14DN13

ACC
Value

TOF
Status

True 1010 Reset

False 0 1 1 increase Timing

False 0 0 0 >=preset Done

Instruction Set

Timer 3-6

timer instructions continued...

Instruction Description

Retentive Timer On
RTO

Status Bits:
EN - Enable
TT - Timer Timing
DN - Done

If the input conditions go true, timer T4:10 starts incrementing in 1-second intervals as long as
the rung remains true. When the rung goes false, the timer stops. If the rung goes true again,
the timer continues. When the accumulated value is greater than or equal to the preset (10), the
timer stops and sets the timer done bit.

Timer Reset
RES

If the input conditions go true, timer T4:1 is reset. This instruction resets timers
and counters, as well as control blocks. This is necessary to reset the RTO
accumulated value.

RETENTIVE TIMER ON

Timer T4:10

Time Base 1.0

Preset 10

Accum 0

RTO

Rung
ConditionEN15TT14DN13

ACC
Value

RTO
Status

False 0000 Reset

True 1 1 0 increase Timing

False 0 0 0 maintains Disabled

True 1 0 1 >=preset Done

T4:1

(RES)

Instruction Set

Counter 3-7

Counter Instructions

Instruction Description

Count Up
CTU

Status Bits:
CU-Count Up
CD-Count Down
DN-Count Done
OV-Overflow
UN-Underflow

If the input conditions go true, counter C5:1 starts counting, incrementing by 1 every time the
rung goes from false-to-true. When the accumulated value is greater than or equal to the preset
value (10), the counter sets the counter done bit.

COUNT UP

Counter C5:1

Preset 10

Accum 0

CTU

Rung
Condition

CU15DN13OV12ACC

Value

CTU
Status

False 0000 Reset

Toggle True 1 0 0 incr by 1 Counting

True 1 1 0 >=preset Done

True 1 1 1 >32767 Overflow

Instruction Set

Counter 3-8

counter instructions continued...

Instruction Description

Count Down
CTD

Status Bits:
CU-Count Up
CD-Count Down
DN-Count Done
OV-Overflow
UN-Underflow

If the input conditions go true, counter C5:1 starts counting, decrementing by 1 every time the
rung goes from false-to-true. When the accumulated value is less than or equal to the preset
value (10), the counter resets the counter done bit.

Counter Reset
RES

If the input conditions go true, counter C5:1 is reset. This instruction resets timers and counters,
as well as control blocks.

COUNT DOWN

Counter C5:1

Preset 10

Accum 35

CTD

Rung
Condition

CD14DN13UN11ACC

Value

CTD
Status

False 0000 Reset

False 0 1 0 >=preset Preload

Toggle True 1 1 0 decr by 1 Counting

True 1 0 0 <preset Done

True 1 0 1 <-32768 Underflow

C5:1

(RES)

Instruction Set

Compare 3-9

Compare Instructions

Instruction Description

Compare
CMP

If the expression is true, this input instruction is true. The CMP instruction can perform these
operations: equal (=), less than (<), less than or equal (<=), greater than (>), greater than or
equal (>=), not equal (<>). Complex expressions (up to 80 characters) are valid with Enhanced
and ControlNet PLC–5 processors only.

Limit Test
LIM

If the Test value (N7:15) is >= the Low Limit (N7:10) and <= the High Limit (N7:20), this
instruction is true.

COMPARE

Expression
N7:5 = N7:10

CMP

LIMIT TEST (CIRC)

Low limit N7:10

3

Test N7: 1 5

4

High limit N7:20

22

LIM

Low Limit Test High Limit LIM

0010T

–5510T

51110F

1000T

10 5 –5 F

10 11 5 T

Instruction Set

Compare 3-10

compare instructions continued...

Instruction Description

Mask Compare Equal
MEQ

The processor takes the value in the Source (D9:5) and passes that value through the Mask
(D9:6). Then the processor compares the result to the Compare value (D9:10). If the result and
this comparison values are equal, the instruction is true.

MASKED EQUAL

Source D9:5

0000

Mask D9:6

0000

Compare D9:10

0000

MEQ

Source Mask Compare MEQ

0008 0008 0009 F

0008 0001 0001 F

0087 000F 0007 T

0087 00F0 0007 F

Instruction Set

Compare 3-11

compare instructions continued...

Instruction Description

Equal to
EQU

If the value in Source A (N7:5) is = to the value in Source B (N7:10), this instruction is true.

Greater than or Equal GEQ If the value in Source A (N7:5) is > or = to the value in Source B (N7:10), this instruction is true.
Greater than

GRT

If the value in Source A (N7:5) is > the value in Source B (N7:10), this instruction is true.

Less than or Equal
LEQ

If the value in Source A (N7:5) is < or = to the value in Source B (N7:10), this instruction is true.

Less than
LES

If the value in Source A (N7:5) is < the value in Source B (N7:10), this instruction is true.

Not Equal
NEQ

If the value in Source A (N7:5) is not equal to the value in Source B (N7:10), this instruction is true.

xxxxxxxxxxxxx

Source A N7:5

3

Source B N7:10

1

xxx

Source A Source B EQU GEQ GRT LEQ LES NEQ

10 10 T T F T F F

5 6 FFFTTT

21 20 F T T F F T

–30 –31 FTTFFT

–15 –14 FFFTTT

Instruction Set

Compute 3-12

Compute Instructions

Instruction Description

Compute
CPT

If the input conditions go true, evaluate the Expression N7:4 – (N7:6 * N7:10) and store the
result in the Destination (N7:3). The CPT instruction can perform these operations: add (+),
subtract (–), multiply (*), divide (|), convert from BCD (FRD), convert to BCD (TOD), square root
(SQR), logical and (AND), logical or (OR), logical not (NOT), exclusive or (XOR), negate (–), clear
(0), and move. In addition, Enhanced PLC-5 processors can do: X to the power of Y (**), radians
(RAD), degrees (DEG), log (LOG), natural log (LN), sine (SIN), cosine (COS), tangent (TAN), inverse
sine (ASN), inverse cosine (ACS), inverse tangent (ATN). Complex expressions (up to 80
characters) are valid with Enhanced and ControlNet PLC-5 processors only.

Arc Cosine
ACS
(Enhanced, Ethernet, and

ControlNet PLC-5
processors only)

When the input conditions are true, take the arc cosine of the Source (F8:19) and store the
result in the Destination (F8:20). The Source must be greater than or equal to –1 and less than
or equal to 1.

COMPUTE

Dest N7:3

3

Expression
N7:4 – (N7:6 * N7:10)

CPT

ARCCOSINE

Source F8:19

0.7853982

Destination F8:20

0.6674572

ACS

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

Salways resets

Instruction Set

Compute 3-13

compute instructions continued...

Instruction Description

Addition
ADD

When the input conditions are true, add the value in Source A (N7:3) to the value in Source B
(N7:4) and store the result in the Destination (N7:12).

Arc Sine
ASN
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

When the input conditions are true, take the arc sine of the Source (F8:17) and store the result
in the Destination (F8:18). The Source is interpreted as radians and must be greater than or
equal to -1 and less than or equal to 1.

ADD

Source A N7:3

3

Source B N7:4

1

Dest N7:12

4

ADD

Status Bit Description

C sets if carry is generated; otherwise resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

ARCSINE

Source F8:17

0.7853982

Destination F8:18

0.9033391

ASN

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

Salways resets

Instruction Set

Compute 3-14

compute instructions continued...

Instruction Description

Arc Tangent
ATN
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the arc tangent of the Source (F8:21) and store the
result in the Destination (F8:22). The Source is interpreted as radians.

Average
AVE
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
EN-Enable
DN-Done Bit
ER-Error Bit

When the input conditions go from false-to-true, add N7:1, N7:2, N7:3, and N7:4. Divide the
sum by 4 and store the result in N7:0.

ARCTANGENT

Source F8:21

0.7853982

Destination F8:22

0.6657737

ATN

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

AVERAGE FILE

File #N7:1

Dest N7:0

Control R6:0

Length 4

Position 0

AVE

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-15

compute instructions continued...

Instruction Description

Clear
CLR

When the input conditions are true, clear BCD file 9, word 34 (set to zero).

Cosine
COS
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the cosine of the Source (F8:13) and store the result in
the Destination (F8:14). The Source is interpreted as radians.

CLR

Dest D9:34

0000

CLR

Status Bit Description

Calways reset

Valways reset

Zalways set

Salways reset

COSINE

Source F8:13

0.7853982

Destination F8:14

0.7071068

COS

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-16

compute instructions continued...

Instruction Description

Division
DIV

When the input conditions are true, divide the value in Source A (N7:3) by the value in Source B
(N7:4) and store the result in the Destination (N7:12).

Natural Log
LN
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the natural log of the Source (N7:0) and store the result
in the Destination (F8:20). The Source must be positive (greater than 0).

DIVIDE

Source A N7:3

3

Source B N7:4

1

Dest N7:12

3

DIV

Status Bit Description

Calways resets

V sets if division by zero or overflow; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

NATURAL LOG

Source N7:0

5

Destination F8:20

1.609438

LN

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-17

compute instructions continued...

Instruction Description

Log to the Base 10
LOG
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the log base 10 of the Source (N7:2) and store
the result in the Destination (F8:3). The Source must be positive (greater than 0).

Multiply
MUL

When the input conditions are true, multiply the value in Source A (N7:3) by the value in
Source B (N7:4) store the result in the Destination (N7:12).

LOG BASE 10

Source N7:2

5

Destination F8:3

0.6989700

LOG

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

MULTIPLY

Source A N7:3

3

Source B N7:4

1

Dest N7:12

3

MUL

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-18

compute instructions continued...

Instruction Description

Negate
NEG

When the input conditions are true, take the opposite sign of the Source (N7:3) and store the
result in the Destination (N7:12). This instruction turns positive values into negative values and
negative values into positive values.

Sine
SIN
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the sine of the Source (F8:11) and store the result in
the Destination (F8:12). The Source is interpreted as radians.

NEGATE

Source N7:3

3

Destination N7:12

–3

NEG

Status Bit Description

C sets if the operation generates a carry; otherwise resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

SINE

Source F8:11

0.7853982

Destination F8:12

0.7071068

SIN

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-19

compute instructions continued...

Instruction Description

Square Root
SQR

When the input conditions are true, take the square root of the Source (N7:3) and store the
result in the Destination (N7:12).

Sort
SRT
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit

When the input conditions go from false-to-true, the elements in N7:1, N7:2, N7:3.and N7:4 are
sorted into ascending order.

SQUARE ROOT

Source N7:3

25

Destination N7:12

5

SQR

Status Bit Description

Calways resets

V sets if overflow occurs during floating point to integer

conversion; otherwise resets

Z sets if the result is zero; otherwise resets

Salways resets

SORT

File #N7:1

Control R6:0

Length 4

Position 0

SRT

Instruction Set

Compute 3-20

compute instructions continued...

Instruction Description

Standard Deviation
STD
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit

When the input conditions go from false-to-true, the elements in N7:1, N7:2, N7:3 and N7:4 are
used to calculate the standard deviation of the values and store the result in the Destination
(N7:0). The result is stored in N7:0.

Subtract
SUB

When the input conditions are true, subtract the value in Source B (N7:4) from the value in
Source A (N7:3) and store the result in the Destination (N7:12).

STANDARD DEVIATION

File #N7:1

Dest N7:0

Control R6:0

Length 4

Position 0

STD

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

SUBTRACT

Source A N7:3

3

Source B N7:4

1

Dest N7:12

2

SUB

Status Bit Description

C sets if borrow is generated; otherwise resets

V sets if underflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Compute 3-21

compute instructions continued...

Instruction Description

Tangent
TAN
(Enhanced, Ethernet and

ControlNet PLC-5 processors
only)

When the input conditions are true, take the tangent of the Source (F8:15) and store the result in the
Destination (F8:16). The Source must be greater than or equal to –102943.7 and less than or equal to

102943.7. The Source is interpreted as radians.

TANGEN T

Source F8:15

0.7853982

Destination F8:16

1.0000000

TAN

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Logical 3-22

Logical Instructions

Instruction Description

AND When the input conditions are true, the processor evaluates an AND operation (bit-by-bit)

between Source A (D9:3) and Source B (D9:4) and stores the result in the Destination (D9:5).
The truth table for an AND operation is:

Source A Source B Result

000
100
010
111

NOT Operation When the input conditions are true, the processor performs a NOT (takes the opposite of)

operation (bit-by-bit) on the Source (D9:3) and stores the result in the Destination (D9:5). The
truth table for a NOT operation is:

Source Destination

01
10

BITWISE AND

Source A D9:3

3F37

Source B D9:4

00FF

Dest D9:5

0037

AND

NOT

Source A D9:3

00FF

Destination D9:5

FF00

NOT

Status Bit Description

Calways resets

Valways resets

Z sets if the result is zero; otherwise resets

S sets if the most significant bit (bit 15 for decimal or bit 17 for octal) is set (1); otherwise resets

Instruction Set

Logical 3-23

logical instructions continued...

Instruction Description

OR When the input conditions are true, the processor evaluates an OR operation (bit-by-bit)

between Source A (D9:3) and Source B (D9:4) and stores the result in the Destination (D9:5).
The truth table for an OR operation is:

Source A Source B Result

000
101
011
111

Exclusive OR
XOR

When the input conditions are true, the processor evaluates an exclusive OR operation
(bit-by-bit) between Source A (D9:3) and Source B (D9:4) and stores the result in the Destination
(D9:5). The truth table for an XOR operation is:

Source A Source B Result

000
101
011
110

BITWISE INCLUS OR

Source A D9:3

3F37

Source B D9:4

00FF

Dest D9:5

3FFF

OR

BITWISE EXCLUS OR

Source A D9:3

3F37

Source B D9:4

3F37

Dest D9:5

0000

XOR

Status Bit Description

Calways resets
Valways resets
Z sets if the result is zero; otherwise resets
S sets if the most significant bit (bit 15 for decimal or bit 17 for octal) is set (1); otherwise resets

Instruction Set

Conversion 3-24

Conversion Instructions

Instruction Description

Convert from BCD
FRD

When the input conditions are true, convert the value in the Source (D9:3) to an integer value
and store the result in the Destination (N7:12). The source must be in the range of 0-9999
(BCD).

Convert to BCD
TOD

When the input conditions are true, convert the value in Source (N7:3) to a BCD format and store
the result in the Destination (D9:5).

FROM BCD

Source D9:3

0037

Destination N7:12

37

FRD

Status Bit Description

Calways resets

Valways resets

Z sets if the destination value is zero; otherwise resets

Salways resets

TO BCD

Source N7:3

44

Destination D9:5

0044

TOD

Status Bit Description

Calways resets

V sets if the source value is negative or greater than

9999 (i.e., outside of the range of 9999)

Z sets if the destination value is zero; otherwise resets

Salways resets

Instruction Set

Conversion 3-25

conversion instructions continued...

Instruction Description

Convert to Degrees
DEG

(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

Converts radians (the value in Source A) to degrees and stores the result in the Destination
(Source times 180/π).

Convert to Radians
RAD

(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

Converts degrees (the value in Source A) to radians and stores the result in the Destination
(Source times π/180).

RADIANS TO DEGREE

Source F8:7

0.7853982

Destination F8:8

45

DEG

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

DEGREES TO RADIAN

Source N7:9

45

Destination F8:10

0.7853982

RAD

Status Bit Description

Calways resets

V sets if overflow is generated; otherwise resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Bit Modify and Move 3-26

Bit Modify and Move Instructions

Instruction Description

Bit Distribute
BTD

When the input conditions are true, the processor copies the number of bits specified by Length,
starting with the Source bit (3) of the Source (N7:3), and placing the values in the Destination
(N7:4), starting with the Destination bit (10).

Move
MOV

When the input conditions are true, move a copy of the value in Source (N7:3) to the Destination
(N7:12). This overwrites the original value in the Destination.

BIT FIELD DISTRIB

Source N7:3

0
Source bit 3
Dest N7:4

0
Dest bit 10
Length 6

BTD

MOVE

Source N7:3

0

Destination N7:12

0

MOV

Status Bit Description

Calways resets

V sets if overflow is generated during floating

point-to-integer conversion; otherwise resets

Z sets if the destination value is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

Bit Modify and Move 3-27

bit modify and move instructions continued...

Instruction Description

Masked Move
MVM

When the input conditions are true, the processor passes the value in the Source (D9:3) through
the Mask (D9:5) and stores the result in the Destination (D9:12). This overwrites the original
value in the Destination.

MASKED MOVE

Source D9:3

478F

Mask D9:5

00FF

Dest bit D9:12
Length 008F

MVM

Status Bit Description

Calways resets

Valways resets

Z sets if the result is zero; otherwise resets

S sets if the result is negative; otherwise resets

Instruction Set

File Instructions 3-28

File Instructions

Instruction Description

File Arithmetic and Logic
FAL

Status Bits:
EN – Enable
DN – Done Bit
ER – Error Bit

When the input conditions go from false-to-true, the processor reads 8 elements of N14:0, and
subtracts 256 (a constant) from each element. This example shows the result being stored in
the eight elements beginning with N15:10. The control element R6:1 controls the operation. The
Mode determines whether the processor performs the expression on all elements in the files
(ALL) per program scan, one element in the files (INC) per scan, or a specific number of
elements (NUM) per scan.

The FAL instruction can perform these operations: add (+), subtract (–), multiply (*), divide (|),
convert from BCD (FRD), convert to BCD (TOD), square root (SQR), logical and (AND), logical or
(OR), logical not (NOT), exclusive or (XOR), negate (–), clear (0), move, and the new math
instructions (see the CPT list).

File Fill
FLL

When the input conditions are true, the processor copies the value in Source (N10:6) to the
elements in the Destination file (#N12:0). The FLL instruction only fills as many elements in the
destination as specified in the Length.

FILE ARITH/LOGICAL

Control R6:1
Length 8
Position 0
Mode ALL
Dest #N15:10
Expression #N14:0 – 256

FAL

FILL FILE

Source N10:6

Destination #N12:0

Length 5

FLL

Instruction Set

File Instructions 3-29

file instructions continued...

Instruction Description

File Search and Compare
FSC

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
IN - Inhibit Bit
FD - Found Bit

When the input conditions go from false-to-true, the processor performs the not-equal-to
comparison on 10 elements per scan for 9 scans (numeric mode) between files B4:0 and B5:0.
The Mode determines whether the processor performs the expression on all elements in the
files (ALL) per program scan, one element in the files (INC) per scan, or a specific number of
elements (number) per scan. The control element R9:0 controls the operation.

When the corresponding source elements are not equal (element B4:4 and B5:4 in this
example), the processor stops the search and sets the found.FD and inhibit.IN bits so your
ladder program can take appropriate action. To continue the search comparison, you must reset
the.IN bit.

To see a list of the available comparisons, see the comparisons listed under the CMP
instruction.

File Copy
COP

When the input conditions are true, the processor copies the contents of the Source file (#N7:0)
into the Destination file (#N12:0). The source remains unchanged. The COP instruction copies
the number of elements from the source as specified by the Length.

FILE SEARCH/COMPARE

Control R9:0
Length 90
Position 0
Mode 10
Expression #B4:0 <>#B5:0

FSC

COPY FILE

Source #N7:0

Destination #N12:0

Length 5

COP

Instruction Set

Diagnostic 3-30

Diagnostic Instructions

Instruction Description

File Bit Compare
FBC

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
IN - Inhibit Bit
FD - Found Bit

When the input conditions go from false-to-true, the processor compares the number of bits
specified in the Cmp Control Length (48) of the Source file (#I:031) with the bits in the Reference
file (#B3:1). The processor stores the results (mismatched bit numbers) in the Result file
(#N7:0). File R6:4 controls the compare and file R6:5 controls the file that contains the results.
The file containing the results can hold up to 10 (the number specified in the Length field)
mismatches between the compared files.

FILE BIT COMPARE

Source #I:031
Reference #B3:1
Result #N7:0
Cmp Control R6:4
Length 48
Position 0
Result Control R6:5
Length 10
Position 0

FBC

Instruction Set

Diagnostic 3-31

diagnostic instructions continued...

Instruction Description

Diagnostic Detect
DDT

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
IN - Inhibit Bit
FD - Found Bit

When the input conditions go from false-to-true, the processor compares the number of bits
specified in the Cmp Control Length (20) of the Source file (#I:031) with the bits in the Reference
file (#B3:1). The processor stores the results (mismatched bit numbers) in the Result file
(#N10:0). File R6:0 controls the compare and file R6:1 controls the file that contains the results
(#N10:0). The file containing the results can hold up to 5 (the number specified in the Length
field) mismatches between the compared files. The processor copies the source bits to the
reference file for the next comparison.

The difference between the DDT and FBC instruction is that each time the DDT instruction finds
a mismatch, the processor changes the reference bit to match the source bit. You can use the
DDT instruction to update your reference file to reflect changing machine or process conditions.

Data Transition
DTR

The DTR instruction compares the bits in the Source (I:002) through a Mask (0FFF) with the bits
in the Reference (N63:11). When the masked source is different than the reference, the
instruction is true for only 1 scan. The source bits are written into the reference address for the
next comparison. When the masked source and the reference are the same, the instruction
remains false.

DIAGNOSTIC DETECT

Source #I:030
Reference #B3:1
Result #N10:0
Cmp Control R6:0
Length 20
Position 0
Result Control R6:1
Length 5
Position 0

DDT

DATA TRANSITION

Source I:002

Mask 0FFF

Reference N63:11

DTR

Instruction Set

Shift Register 3-32

Shift Register Instructions

Instruction Description

Bit Shift Left
BSL

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload Bit

If the input conditions go from false-to-true, the BSL instruction shifts the number of bits
specified by Length (5) in File (B3), starting at bit 16 (B3:1/0 = B3/16), to the left by one bit
position. The source bit (I:022/12) shifts into the first bit position, B3:1/0 (B3/16). The fifth bit,
B3:1/4 (B3/20), is shifted into the UL bit of the control structure (R6:53).

Bit Shift Right
BSR

Status Bits:
EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload Bit

If the input conditions go from false-to-true, the BSR instruction shifts the number of bits
specified by Length (3) in File (B3), starting with B3:2/0 (=B3/32), to the right by one bit
position. The source bit (I:023/06) shifts into the third bit position B3/34. The first bit (B3/32)
is shifted into the UL bit of the control element (R6:54).

BIT SHIFT LEFT

File #B3:1

Control R6:53

Bit Address I:022/12

Length 5

BSL

BIT SHIFT RIGHT

File #B3:2

Control R6:54

Bit Address I:023/06

Length 3

BSR

Instruction Set

Shift Register 3-33

shift register instructions continued...

Instruction Description

FIFO Load
FFL

Status Bits:
EN - Enable Load
DN - Done Bit
EM - Empty Bit

When the input conditions go from false-to-true, the processor loads N60:1 into the next
available element in the FIFO file, #N60:3, as pointed to by R6:51. Each time the rung goes from
false-to-true, the processor loads another element. When the FIFO file (stack) is full, (64 words
loaded), the DN bit is set.

FIFO Unload
FFU

Status Bits:
EU - Enable Unload
DN - Done Bit
EM - Empty Bit

When the input conditions go from false-to-true, the processor unloads an element from N60:3
into N60:2. Each time the rung goes from false-to-true, the processor unloads another element.
All the data in file #N60:3 is shifted one position toward N60:3. When the file is empty, the EM
bit is set.

FIFO LOAD

Source N60:1

FIFO #N60:3

Control R6:51

Length 64

Position 0

FFL

FIFO UNLOAD

FIFO #N60:3

Dest N60:2

Control R6:51

Length 64

Position 0

FFU

Instruction Set

Shift Register 3-34

shift register instructions continued...

Instruction Description

LIFO Load
LFL
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

Status Bits:
EN - Enable Load
DN - Done Bit
EM - Empty Bit

When the input conditions go from false-to-true, the processor loads N70:1 into the next
available element in the LIFO file #N70:3, as pointed to by R6:61. Each time the rung goes from
false-to-true, the processor loads another element. When the LIFO file (stack) is full (64 words
have been loaded), the DN bit is set.

LIFO Unload
LFU
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
EN - Enable Load
EU - Enable Unload
DN - Done Bit
EM - Empty Bit

When the input conditions go from false-to-true, the processor unloads the last element from
#N70:3 and puts it into N70:2. Each time the rung goes from false-to-true, the processor
unloads another element. When the LIFO file is empty, the EM bit is set.

LIFO LOAD

Source N70:1

LIFO #N70:3

Control R6:61

Length 64

Position 0

LFL

LIFO UNLOAD

LIFO #N70:3

Dest N70:2

Control R6:61

Length 64

Position 0

LFU

Instruction Set

Sequencer 3-35

Sequencer Instructions

Instruction Description

Sequencer Input
SQI

The SQI instruction compares the Source (#I:031) input image data through a Mask (FFF0) to
Reference data (#N7:11) to see if the two files are equal. The operation is controlled by the
information in the control file R6:21. When the status of all unmasked bits of the word pointed to
by control element R6:21 matches the corresponding reference bits, the rung instruction goes
true.

Sequencer Load
SQL

Status Bits:
EN – Enable
DN – Done Bit
ER - Error Bit

The SQL instruction loads data into the sequencer File (#N7:20) from the source word (I:002) by
stepping through the number of elements specified by Length (5) of the Source (I:002), starting
at the Position (0). The operation is controlled by the information in the control file R6:22. When
the rung goes from false-to-true, the SQL instruction increments the next step in the sequencer
file and loads the data into it for every scan that the rung remains true.

Sequencer Output
SQO

Status Bits:
EN – Enable
DN – Done Bit
ER - Error Bit

When the rung goes from false-to-true, the SQO instruction increments to the next step in the
sequencer File (#N7:1). The data in the sequencer file is transferred through a Mask (0F0F) to
the Destination (O:014) for every scan that the rung remains true.

SEQUENCER INPUT
File #N7:11

Mask FFF0
Source #I:031
Control R6:21
Length 4
Position 0

SQI

SEQUENCER LOAD
File #N7:20

Source I:002
Control R6:22
Length 5
Position 0

SQL

SEQUENCER OUTPUT
File #N7:1

Mask 0F0F
Dest O:014
Control R6:20
Length 4
Position 0

SQO

Instruction Set

Program Control 3-36

Program Control Instructions

Instruction Description

Master Control Reset
MCR

If the input conditions are true, the program scans the rungs between MCR instruction rungs
and processes the outputs normally. If the input conditions are false, all non-retentive outputs
between the MCR-instruction rungs are reset.

Jump
JMP

If the input conditions are true, the processor skips rungs by jumping to the rung identified by
the label (10).

Label
LBL

When the processor reads a JMP instruction that corresponds to label 10, the processor jumps
to the rung containing the label and starts executing. (Must be the first instruction on a rung.)

FOR Loop
FOR

The processor executes the rungs between the FOR and the NXT instruction repeatedly in one
program scan, until it reaches the terminal value (10) or until a BRK instruction aborts the
operation. Step size is how the loop is incremented.

(MCR)

10

(JMP)

10

[LBL]

FOR

Label Number 0

Index N7:0

Initial Value 0

Terminal Value 10

Step Size 1

FOR

Instruction Set

Program Control 3-37

program control instructions continued...

Instruction Description

Next
NXT

The NXT instruction returns the processor to the corresponding FOR instruction, identified by the
label number specified in the FOR instruction. NXT must be programmed on an unconditional
rung that is the last rung to be repeated in a For-Next loop.

Break
BRK

When the input conditions go true, the BRK instruction aborts a For-Next loop.

Jump to Subroutine
JSR

If the input conditions are true, the processor starts running a subroutine Program File (90).
The processor uses the Input Parameters (N16:23, N16:24, 231) in the subroutine and passes
Return Parameters (N19:11, N19:12 back to the main program, where the processor
encountered the JSR instruction.

NEXT

Label Number 0

NXT

[BRK]

JUMP TO SUBROUTINE

Program File 90
Input par N16:23
Input par N16:24
Input par 231
Return par N19:11
Return par N19:12

JSR

Instruction Set

Program Control 3-38

program control instructions continued...

Instruction Description

Subroutine
SBR

The SBR instruction is the first instruction in a subroutine file. This instruction identifies Input
Parameters (N43:0, N43:1, N43:2) the processor receives from the corresponding JSR
instruction. You do not need the SBR instruction if you do not pass input parameters to the
subroutine.

Return
RET

The RET instruction ends the subroutine and stores the Return Parameters (N43:3, N43:4) to be
returned to the JSR instruction in the main program.

Temporary End
TND

The TND instruction stops the processor from scanning the rest of the program (i.e., this
instruction temporarily ends the program).

Always False
AFI

The AFI instruction disables the rung (i.e., the rung is always false).

One Shot
ONS

If the input conditions preceding the ONS instructions on the same rung go from false-to-true,
the ONS instruction conditions the rung so that the output is true for one scan. The rung is false
on successive scans.

SUBROUTINE

Input par N43:0
Input par N43:1
Input par N43:2

SBR

RETURN ()

Return par N43:3
Return par N43:4

RET

(TND)

[AFI]

B3

[ONS]

110

Instruction Set

Program Control 3-39

program control instructions continued...

Instruction Description

One Shot Falling
OSF
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
OB - Output Bit

1

SB - Storage Bit

1

The OSF instruction triggers an event to occur one time. Use the OSF instruction whenever an
event must start based on the change of state of a rung from true-to-false, not on the resulting
rung status. The output bit (N7:0/15) is set (1) for one program scan when the rung goes from
true-to-false.

One Shot Rising
OSR
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits:
OB - Output Bit

1

SB - Storage Bit

1

The OSR instruction triggers an event to occur one time. Use the OSR instruction whenever an
event must start based on the change of state of a rung from false-to-true, not on the resulting
rung status. The output bit (N7:0/15) is set (1) for one program scan when the rung goes from
false-to-true.

1

These bits are for display purposes only; there is no logical address for them.

ONE SHOT FALLING

Storage Bit B3/0
Output Bit 15
Output Word N7:0

OSF

ONE SHOT RISING

Storage Bit B3/0
Output Bit 15
Output Word N7:0

OSR

Instruction Set

Program Control 3-40

Program control instructions continued...

Instruction Description

SFC Reset
SFR
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

The SFR instruction resets the logic in a sequential function chart. When the SFR
instruction goes true, the processor performs a lastscan/postscan on all active
steps and actions in the selected file, and then resets the logic in the SFC on the
next program scan. The chart remains in this reset state until the SFR instruction
goes false.

End of Transition
EOT

The EOT instruction should be the last instruction in a transition file. If you do not
use an EOT instruction, the processor always evaluates the transition as true.

User Interrupt Disable
UID
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

The UID instruction temporarily disables an interrupt-driven ladder program (such
as an STI or PII) from interrupting the currently executing program.

User Interrupt Enable
UIE
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

The UIE instruction re-enables the interrupt-driven ladder program to interrupt the
currently executing ladder program.

SFC Reset

Prog File Number 3

SFR

(EOT)

(UID)

(UIE)

Instruction Set

Processor and Message 3-41

Processor Control and Message Instructions

Instruction Description

Proportional, Integral,
and Derivative

PID

Status Bits:
EN - Enable
DN - Done Bit

If the input conditions go false-to-true, the processor performs PID calculations and calculates a
new control output (for Classic PLC-5 processors). The control block (N10:0) contains the
instruction information for the PID. The PID gets the process variable from N15:13 and sends
the PID output to N20:21. The tieback stored in N15:14 handles the manual control station.

For Enhanced, Ethernet, and ControlNet PLC-5 processors, you can use the PD control block. (If
you use PD control block, then there is no done bit.) Also, the rung input conditions only need to
be true for these processors.

Message
MSG

If the input conditions are true, the data is transferred according to the instruction parameters
you set when you entered the message instruction. The Control Block (N7:10) contains status
and instruction parameters.

For Enhanced, Ethernet, and ControlNet PLC-5 processors, you can use the MG control block.

PID

Control Block N10:0
Proc Variable N15:13
Tieback N15:14
Control Output N20:21

PID

SEND/RECEIVE MSG

Control Block N7:10

MSG

Bit # Status Bits
15 EN - Enable

14 ST - Start Bit
13 DN - Done Bit
12 ER - Error Bit
11 CO - Continuous
10 EW - Enabled-Waiting
9NR - No Response
8 TO - Time Out Bit

Instruction Set

Processor and Message 3-42

Processor control and message instructions continued...

☞

Instruction Description

Message
MSG

Status Bits
TO - Time-Out Bit
EW - Enabled-Waiting Bit
CO - Continuous Bit
ER - Error Bit
DN - Done Bit
ST - Start Bit
EN - Enable Bit

If the input conditions go from false to true, the data is transferred according to the instruction
parameters you set when you enter the message instruction. The Control Block (MG10:10)
contains status and instruction parameters.

You cannot use N (integer) control blocks on the ControlNet network.

For continuous MSGs, condition the rung to be true for only one scan.

SEND/RECEIVE MESSAGE

Control block MG10:10

MSG

Instruction Set

Block Transfer 3-43

Block and
ControlNet

Transfer Instructions

☞

Integer (N) control block

Word Offset Description

0 status bits (see below)

1 requested word count

2 transmitted word count

3 file number

4 element number

Block Transfer (BT) control block

Word Mnemonic Description

.EN thru.RW status bits

.RLEN requested length

.DLEN transmitted word length/error code

.FILE file number

.ELEM element number

.RGS rack/group/slot

Word 0

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

EN ST DN ER CO EW NR TO RW ** rack ** ** group ** slot

Instruction Set

Block Transfer 3-44

block transfer instructions continued...

PLC-5/25, -5/30, -5/40, -5/40L, -5/40C, -5/60,

-5/60L, -5/80, -5/40E, -5/80E, -5/80C processors

PLC-5/40, -5/40C, 5/60, -5/60L,

-5/60C, -5/80, -5/40E, -5/80E, -5/80C
processors

PLC-5/60, -5/80, -5/80E, -5/80C

processors

S:7

bit #

BT queue

full for rack

S:32
bit #

BT queue

full for rack

S:34
bit #

BT queue

full for rack

08

1

0 08100820

09

1

1 09110921

10

1

2 10121022

11

1

3 11131123

12 4 12141224

13 5 13151325

14 6 14161426

15 7 15171527

1

PLC-5/10, -5/11 -5/12, -5/15, -5/20, -5/20E, -5/20C processors also

Instruction Set

Block Transfer 3-45

block transfer instructions continued...

Instruction Description

Block Transfer
Read
BTR

If the input conditions go from false-to-true, a block transfer read is initiated for the I/O module
located at rack 1, group 0, module 0. The Control Block (N10:100 – 5-word file) contains status
for the transfer. The Data File (N10:110) is where the data read from the module is stored. The
BT Length (40) identifies the number of words in the transfer. A non-continuous block transfer is
queued and run only once on a false-to-true rung transition; a continuous block transfer is
repeatedly requeued. For Enhanced, Ethernet, and ControlNet PLC-5 processors, you can use
the BT control block.

Block Transfer Write
BTW

If the input conditions go from false-to-true, the block transfer write is initiated for the I/O
module located at rack 1, group 0, module 0. The Control Block (N10:0 - 5-word file) contains
status for the transfer. The Data File contains the data to write to the module (N10:10). The BT
Length (40) identifies the number of words in the transfer. A non-continuous block transfer is
queued and run only once on a false-to-true rung transition; a continuous block transfer is
repeatedly requeued. For Enhanced, Ethernet, and ControlNet PLC-5 processors, you can use
the BT control block.

BLOCK TRNSFR READ

Rack 1
Group 0
Module 0
Control Block N10:100
Data File N10:110
Length 40
Continuous Y

BTR

BLOCK TRNSFR WRITE

Rack 1
Group 0
Module 0
Control Block N10:0
Data File N10:10
Length 40
Continuous Y

BTW

Instruction Set

Block Transfer 3-46

block transfer instructions continued...

Instruction Description

ControlNet I/O Transfer
CT

Status Bits
TO - Time-Out Bit
EW - Enabled-Waiting Bit
CO - Continuous Bit
ER - Error Bit
DN - Done Bit
ST - Start Bit
EN - Enable Bit

If the input conditions go from false to true, the data is transferred according to the
instruction parameters you set when you enter the ControlNet I/O transfer instruction.
The Control Block (CT21:50) contains status and instruction parameters.

You cannot use N (integer) control blocks on the ControlNet network.

For continuous CIOs, condition the rung to be true for only
one scan.

CNET I/O TRANSFER

Control block CT21:50

CIO

Instruction Set

ASCII Instructions 3-47

ASCII Instructions

Instruction Description

ASCII Test for Line
ABL
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

If input conditions go from false–to–true, the processor reports the number of characters in the
buffer, up to and including the end–of–line characters and puts this value into the position word
of the control structure (R6:32.POS). The processor also displays this value in the characters
field of the display.

ASCII Characters in Buffer
ACB
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

If input conditions go from false–to–true, the processor reports the total number of characters in
the buffer and puts this value into the position word (.POS) of the control structure. The
processor also displays this value in the characters field of the display.

Convert ASCII String to Integer
ACI
(Enhanced, and Ethernet and

ControlNet PLC-5 processors
only)

If input conditions are true, the processor converts the string in ST38:90 to an integer and stores
the result in N7:123.

En – Enable
DN – Done Bit
ER – Error Bit

EM – Empty Bit
EU – Queue
FD – Found Bit

Status Bits:

ASCII TEST FOR LINE

Channel 0
Control R6:32
Characters

ABL

ASCII CHARS IN BUFFER

Channel 0
Control R6:32
Characters

ACB

ASCII STRING TO INT

Source ST38:90
Dest N7:123

75

ACI

Status Bit Description

C set if source is negative; otherwise resets
V set if source is >= 32,768 or <= –32,768, otherwise resets
Z sets if source is zero; otherwise resets
S set if destination is negative; otherwise resets

Instruction Set

ASCII Instructions 3-48

ASCII instructions continued...

Instruction Description

ASCII String Concatenate ACN
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

If input conditions are true, the processor concatenates the string in ST38:90 with the string in
ST37:91 and stores the result in ST52:76.

ASCII String Extract
AEX
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

If input conditions are true, the processor extracts 10 characters starting at the 42nd character
of ST38:40 and stores the result in ST52:75.

Convert Integer to ASCII String
AIC
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

If input conditions are true, the processor converts the value 876 to a string and stores the
result in ST38:42.

STRING CONCATENATE

Source A ST38:90
Source B ST37:91
Dest ST52:76

ACN

STRING EXTRACT

Source ST38:40
Index 42
Number 10
Dest ST52:75

AEX

INTEGER TO STRING

Source 876
Dest ST38:42

AIC

Instruction Set

ASCII Instructions 3-49

ASCII instructions continued...

Instruction Description

ASCII Handshake Lines
AHL
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

If input conditions go from false-to-true, the processor uses the AND and OR masks to
determine whether to set or reset the DTR (bit 0) and RTS (bit 1) lines, or leave them
unchanged. Bit 0 and 1 of the AND mask cause the line(s) to reset if 1 and leave the line(s)
unchanged if 0. BIt 0 and 1 of the OR mask cause the line(s) to set if 1 and leave the line(s)
unchanged if 0.

ASCII Read
ARD
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits
EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload
EM - Empty
EU - Queue

If input conditions go from false-to-true, read 50 characters from the buffer and move them to
ST52:76. The number of characters read is stored in R6:32.POS and displayed in the Characters
Read Field of the instruction display.

ASCII HANDSHAKE LINE

Channel 0
AND Mask 0001
OR Mask 0003
Control R6:23
Channel Status

AHL

ASCII READ

Channel 0
Dest ST52:76
Control R6:32
String Length 50
Characters Read

ARD

Instruction Set

ASCII Instructions 3-50

ASCII instructions continued...

Instruction Description

ASCII Read Line
ARL
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

Status Bits
EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload
EM - Empty
EU - Queue

If input conditions go from false-to-true, read 18 characters (or until end-of-line) from the
buffer and move them to ST50:72. The number of characters read is stored in R6:30.POS and
displayed in the Characters Read Field of the instruction display.

ASCII String Search
ASC
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

If input conditions are true, search ST52:80 starting at the 35th character, for the string found in
ST38:40. In this example, the string was found at index 42. If the string is not found, the ASCII
instruction minor fault bit S:17/8 is set and the result is zero.

ASCII READ LINE

Channel
Dest ST50:72
Control R6:30
String Length 18
Characters Read

ARL

STRING SEARCH

Source ST38:40
Index 35
Search ST52:80
Result 42

ASC

Instruction Set

ASCII Instructions 3-51

ASCII instructions continued...

Instruction Description

ASCII String Compare
ASR
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

If the string in ST37:42 is identical to the string in ST38:90, the instruction is true. Note that this
is an input instruction. An invalid string length causes the ASCII instruction error minor fault bit
S:17/8 to be set, and the instruction is false.

ASCII Write Append
AWA
(Enhanced, Ethernet, and

ControlNet PLC-5 processors
only)

Status Bits

EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload
EM - Empty
EU - Queue

If input conditions go from false-to-true, read 50 characters from ST52:76 and write it to
channel 0 and append the two character configuration in the channel configuration (default
CR/LF). The number of characters sent is stored in R6:32.POS and displayed in the characters
sent field of the instruction display.

ASCII STRING COMPARE

Source A ST37:42
Source B ST38:90

ASR

ASCII WRITE APPEND

Channel 0
Source ST52:76
Control R6:32
String Length 50
Characters Sent

AWA

Instruction Set

ASCII Instructions 3-52

ASCII instructions continued...

Instruction Description

ASCII Write
AWT
(Enhanced, Ethernet, and
ControlNet PLC-5 processors
only)

Status Bits
EN - Enable
DN - Done Bit
ER - Error Bit
UL - Unload
EM - Empty
EU - Queue

If input conditions go from false-to-true, write 40 characters from ST37:40 to channel 0. The
number of characters sent is stored in R6:23.POS and displayed in the characters sent field of
the instruction display.

ASCII WRITE

Channel 0
Source ST37:40
Control R6:23
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AWT

Switch Settings

Chassis Backplane 4-1

Switch Assembly Settings for I/O Chassis Backplane
PLC-5 Processor in the I/O Chassis

Always
Off

Pressed in at bottom
Open (OFF)

Switches

Switch

Switch

Pressed in at top
Closed (ON)

Switches

Last State

Addressing

EEPROM transfer

Processor memory protection

Outputs of this I/O chassis remain in their
last state when a hardware failure occurs.

1

Outputs of this I/O chassis are turned off
when a hardware failure occurs.

1

1

ON

OFF

4

ON

ON

ON ON

ON ON

ON

ON

OFF OFF

OFF

OFF

OFF OFF

OFF

OFF

2-slot

1-slot

1/2-slot

Not allowed

EEPROM memory transfers to processor memory at powerup.

2

EEPROM memory transfers to processor memory if processor memory not valid.

EEPROM memory does not tranfer to processor memory.

3

Processor memory protection disabled.

Processor memory protection enabled.

4

1

Regardless of this switch
setting, outputs are reset when
either of the following occurs:

l

processor detects a
runtime error

l

an I/O chassis backplane
fault occurs

l

you select program or test
mode

l

you set a status file bit to
reset a local rack

2

If an EEPROM module is not
installed, the processor's
PROC LED indicator blinks,
and the processor sets S:11/9,
in the major fault status word.

3

A processor fault occurs if
processor memory is not valid.

4

You cannot clear processor
memory when this switch
is ON.

76

8

5

Switch Settings

Chassis Backplane 4-2

Switch 1

Switch 2

56

ON

OFF

Last State

Switches

Processor Restart Lockout

Addressing

ATTENTION: We recommend that you set switch 1 to the OFF position to de-energize outputs wired to this

chassis when a fault is detected. Also, if outputs are controlled by inputs in a different rack and a remote I/O rack
fault occurs (in the inputs rack), the inputs are left in their last non-faulted state. The outputs may not be properly
controlled and potential personnel and machine damage may result. If you want your inputs to be anything other
than their last non-faulted state, then you need to program a fault routine.

Outputs of this I/O chassis are turned off when a comunication fault is detected by this I/O adapter.

Processor can restart the I/O chassis after a communication fault.
Set this switch to ON if you plan to use I/O rack auto-configuration.

You must manually restart the I/O chassis with a switch wired to the
1771-AS or -ASB, or with the pushbutton mounted in the 1771-ALX.

ON

ON

ON ON

ON

OFF

OFF OFF

OFF

OFF

2-slot

1-slot

1

1/2-slot

1,2

Not allowed

1

The 1771-AS adapter does not support 1-slot or 1/2-slot addressing.
When you use this adapter, set switches 5 and 6 to the OFF position.

2

The 1771-ASB series A adapter does not support 1/2-slot addressing.

Always
Off

Pressed in at bottom
Open (OFF)

Pressed in at top
Closed (ON)

Always
Off

Outputs of this I/O chassis remain in their last state when a communication fault is detected by this I/O adapter.

Switch A

ssembly Se

tti

ngs for

I/O Ch

assis Backplane –

1771-ASB R

emote

I/O Adapt

er Module,

1771-ACN(R)

and -

ACN(R)15 ControlNet Adapt

er or

1771-ALX Extended Local I/O Adapter Module in the I/O Chassis

Switch Settings

Chassis Configuration 4-3

1771 I/O Chassis Configuration Plug Settings

NYYN

Important: You cannot power a single I/O chassis with both a
power supply module and an external power supply.

Set Y when you install a
power supply module in
the chassis.

Using
Power Supply
Module in
the Chassis?

YN

Set N when you use an
external power supply.

Switch Settings

Complementary I/O 4-4

Switch Assemblies without Complementary I/O in a
Remote I/O Adapter Module (1771-ASB series C and series D)

1234

O

N
O

F
F

12345678

O
N

O
F
F

56

Switch

12

ON

OFF

OFF

ON

OFF

OFF

ON

ON

57.6 Kbps - 10,000 ft. (3048m)

115.2 Kbps - 5,000 ft. (1524m)

230.4 Kbps - 2,500 ft. (762m)

not used

I/O Rack Number
(see next page)

First I/O Group Number
(see below)

Link Response: ON - for series B emulation

OFF - for unrestricted

Scan: ON - for all but last 4 slots

OFF - for all slots

SW-1

SW-2

Max chassis

distance

on = closed
off = open

Pressed in at bottom
Open (OFF)

Pressed in at top
Closed (ON)