AG35-Quecopen
Hardware Design
LTE Module Series
Rev. AG35-Quecopen_Hardware_Design_V1.3
Date: 2018-12-12
Status: Released
www.quectel.com
LTE Module Series
AG35-Quecopen
Hardware Design
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About the Document
History
Revision Date Author Description
Eden LIU/
1.0 2017-10-19
Dominic GONG/
Jun WU
Initial
Hardware Design
1.1 2018-03-19
Eden LIU/
Dominic GONG
1. Updated the variants and/or frequency bands of
AG35-Quecopen in Table 1.
2. Changed pins 132 and 133 into RESERVED
pins (Table 4, Table 8 and Figure 2).
3. Deleted SIM IC in Figure 1.
4. Updated transmitting power and GSM features in
Table 2.
5. Updated SD card interface into SDIO interface to
support both eMMC and SD card.
6. Added the description of eCall temperature
range in Table 2 and Chapter 6.3.
7. Updated GNSS data update rate into 10Hz in
Chapter 4.1.
8. Updated the description of PCM interface in
primary and auxiliary modes, and the auxiliary
mode timing (Figure 23) of PCM interface.
9. Updated antenna gain in Table 42, and added a
note for GNSS antenna.
10. Updated current consumption in Chapter 6.4.
11. Updated RF receiving sensitivity in Chapter 6.6.
12. Updated part of the description of thermal
consideration (Chapter 6.8).
1. Added variants and updated bands of the module
1.2 2018-08-27
AG35-QuecOpen_Hardware_Design 2 / 137
Eden LIU/
Dominic GONG
(Table 1).
2. Updated the PAM power supply diagram in the
functional diagram (Figure 1).
LTE Module Series
AG35-Quecopen
Hardware Design
3. Enabled SHDN_N, and added the description of
the pin in Table 4 and Chapter 3.7.2.3.
4. Changed the name of pin 143 from
OTG_PWR_EN to GPIO8 (Table 4).
5. Updated the description of alternate functions of
multiplexing pins (Table 5).
6. Enabled the analog audio interface, and added
the description of the interface in Table 4 and
Chapter 3.12.
7. Enabled UART4 and UART5 interfaces (Chapter
3.11).
8. Added a note for I2C1 interface (Chapter 3.13).
9. Updated the power domain and the reference
circuit with PHY application of SGMII interface
(Chapter 3.16).
10. Updated the pin definition of wireless connectivity
interfaces (Table 26) and the reference circuit for
connection with AF20 module (Figure 30).
11. Added ADC sample rate in Table 28.
12. Updated the reference circuit of USB_BOOT
interface (Figure 33).
13. Added the description of RTC function (Chapter
3.22).
14. Updated the frequency of Galileo and QZSS
(Table 49).
15. Updated current consumption values of the
module (Chapter 6.4).
16. Added RF output power of AG35-E (Chapter 6.5).
17. Added RF receiving sensitivity of AG35-E
(Chapter 6.6).
18. Updated the reflow soldering thermal profile and
related parameters (Chapter 8.2).
1. Updated supported bands of the module (Table
1).
2. Updated the functional diagram (Figure 1).
3. Updated the pin assignment (Figure 2).
4. Updated the drive current of STATUS pin (Table
4) and its reference circuit design (Figure 34).
5. Updated alternate functions of multiplexing pins
(Table 5).
1.3 2018-12-12
Eden LIU/
Dominic GONG/
Ethan SHAN
6. Updated the drive circuit of SHDN_N interface
(Figure 14).
7. Added a note relating to PCM interface (Chapter
3.13). Added GNSS performance values of
AG35-QuecOpen_Hardware_Design 3 / 137
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Hardware Design
AG35-NA and AG35-J (Chapter 4.2).
8. Updated the maximum clock frequency of SPI2
interface into 38MHz (Chapter 3.15).
9. Updated current consumption values of the
module (Chapter 6.4).
10. Completed the RF output power values of the
module (Chapter 6.5).
11. Added the RF receiving sensitivity of AG35-E,
AG35-NA and AG35-J (Chapter 6.6).
1.4 2019-02-01 Eden 1. Updated the description of the notes (table 5).
AG35-QuecOpen_Hardware_Design 4 / 137
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Hardware Design
Contents
About the Document ................................................................................................................................ 2
Contents .................................................................................................................................................... 5
Table Index ............................................................................................................................................... 8
Figure Index ............................................................................................................................................ 10
1 Introduction ..................................................................................................................................... 12
1.1. Safety Information .................................................................................................................. 13
2 Product Concept ............................................................................................................................. 14
2.1. General Description ................................................................................................................ 14
2.2. Key Features .......................................................................................................................... 15
2.3. Functional Diagram ................................................................................................................ 19
2.4. Evaluation Board .................................................................................................................... 20
3 Application Interfaces ..................................................................................................................... 21
3.1. General Description ................................................................................................................ 21
3.2. Pin Assignment ....................................................................................................................... 21
3.3. Pin Description ....................................................................................................................... 23
3.4. Operating Modes .................................................................................................................... 40
3.5.
Power Saving ......................................................................................................................... 40
3.5.1. Sleep Mode.................................................................................................................. 40
3.5.1.1. USB Application with USB Remote Wakeup Function ...................................... 41
3.5.1.2. USB Application without USB Remote Wakeup Function ................................. 42
3.5.1.3. USB Application without USB Suspend Function .............................................. 42
3.5.2. Airplane Mode .............................................................................................................. 43
3.6. Power Supply ......................................................................................................................... 44
3.6.1. Power Supply Pins ....................................................................................................... 44
3.6.2. Decrease Voltage Drop ................................................................................................ 44
3.6.3. Reference Design for Power Supply ............................................................................ 45
3.6.4. Monitor the Power Supply ............................................................................................ 46
3.7. Turn on and off Scenarios ...................................................................................................... 46
3.7.1. Turn on Module Using PWRKEY ................................................................................. 46
3.7.2. Turn off Module ............................................................................................................ 48
3.7.2.1. Turn off Module Using the PWRKEY Pin .......................................................... 48
3.7.2.2. Turn off Module Using AT Command or API Interface .............
.......................... 49
3.7.2.3. Turn off Module Using SHDN_N ....................................................................... 49
3.8. Reset The Module .................................................................................................................. 51
3.9. (U)SIM Interface ..................................................................................................................... 52
3.10. USB Interface ......................................................................................................................... 55
3.11. UART Interfaces ..................................................................................................................... 56
3.12. Audio Interface (Optional) ....................................................................................................... 60
3.13. PCM and I2C Interfaces ......................................................................................................... 61
3.14. SDIO Interfaces ...................................................................................................................... 64
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3.14.1. SDIO1 Interface ........................................................................................................... 64
3.14.2. SDIO2 Interface ........................................................................................................... 64
3.14.2.1. Reference Design for SD Card Application ....................................................... 65
3.14.2.2. Reference Design for eMMC Application .......................................................... 67
3.15. SPI Interfaces ......................................................................................................................... 68
3.16. SGMII Interface (Optional) ...................................................................................................... 70
3.17. Wireless Connectivity Interfaces ............................................................................................ 72
3.17.1. WLAN Interface ........................................................................................................... 75
3.17.2. BT Interface* ................................................................................................................ 75
3.18. ADC Interfaces ....................................................................................................................... 75
3.19. Network Status Indication ....................................................................................................... 76
3.20. STATUS .................................................................................................................................. 77
3.21. USB_BOOT Interface ............................................................................................................. 78
3.22. RTC ........................................................................................................................................ 79
4 GNSS Receiver ................................................................................................................................ 80
4.1. General Description ...........................................
..................................................................... 80
4.2. GNSS Performance ................................................................................................................ 80
4.3. Layout Guidelines ................................................................................................................... 83
5 Antenna Interfaces .......................................................................................................................... 84
5.1. Main/Rx-diversity Antenna Interface ....................................................................................... 84
5.1.1. Pin Definition ................................................................................................................ 84
5.1.2. Operating Frequency ................................................................................................... 84
5.1.3. Reference Design of RF Antenna Interface ................................................................. 88
5.1.4. Reference Design of RF Layout ................................................................................... 89
5.2. GNSS Antenna Interface ........................................................................................................ 91
5.3. Antenna Installation ................................................................................................................ 92
5.3.1. Antenna Requirements ................................................................................................ 92
5.3.2. Recommended RF Connector for Antenna Installation ................................................ 93
6 Electrical, Reliability and Radio Characteristics .......................................................................... 95
6.1. Absolute Maximum Ratings .................................................................................................... 95
6.2. Power Supply Ratings ..........................................
.................................................................. 96
6.3. Operation and Storage Temperatures .................................................................................... 96
6.4. Current Consumption ............................................................................................................. 97
6.5. RF Output Power ................................................................................................................... 111
6.6. RF Receiving Sensitivity ........................................................................................................ 115
6.7. Electrostatic Discharge .......................................................................................................... 119
6.8. Thermal Consideration .......................................................................................................... 119
7 Mechanical Dimensions................................................................................................................ 122
7.1. Mechanical Dimensions of the Module ................................................................................. 122
7.2. Recommended Footprint ...................................................................................................... 124
7.3. Design Effect Drawings of the Module .................................................................................. 125
8 Storage, Manufacturing and Packaging ...................................................................................... 126
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8.1. Storage ................................................................................................................................. 126
8.2. Manufacturing and Soldering ................................................................................................ 127
8.3. Packaging ............................................................................................................................. 128
9 Appendix A References ................................................................................................................ 130
10 Appendix B GPRS Coding Schemes ........................................................................................... 134
11 Appendix C GPRS Multi-slot Classes .......................................................................................... 135
12 Appendix D EDGE Modulation and Coding Schemes ................................................................ 137
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Table Index
TABLE 1: FREQUENCY BANDS OF AG35-QUECOPEN MODULES .............................................................. 15
TABLE 2: KEY FEATURES OF AG35-QUECOPEN MODULES ...................................................................... 15
TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 23
TABLE 4: PIN DESCRIPTION ........................................................................................................................... 24
TABLE 5: ALTERNATE FUNCTIONS OF MULTIPLEXING PINS ..................................................................... 35
TABLE 6: PULL-UP/PULL-DOWN RESISTANCE OF GPIOS .......................................................................... 39
TABLE 7: OVERVIEW OF OPERATING MODES ............................................................................................. 40
TABLE 8: VBAT AND GND PINS ....................................................................................................................... 44
TABLE 9: PWRKEY PIN DESCRIPTION .......................................................................................................... 46
TABLE 10: PIN DEFINITION OF SHDN_N ....................................................................................................... 50
TABLE 11: RESET_N PIN DESCRIPTION ....................................................................................................... 51
TABLE 12: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 53
TABLE 13: PIN DESCRIPTION OF USB INTERFACE ..................................................................................... 55
TABLE 14: PIN DEFINITION OF UART1 INTERFACE ..................................................................................... 57
TABLE 15: PIN DEFINITION OF UART2 INTERFACE ..................................................................................... 57
TABLE 16: PIN DEFINITION OF UART3 INTERFACE (MULTIPLEXED FROM SPI) ...................................... 57
TABLE 17: PIN DEFINITION OF UART4 INTERFACE (MULTIPLEXED FROM SDIO1) ................................. 58
TABLE 18: PIN DEFINITION OF UART5 INTERFACE (MULTIPLEXED FROM SDIO1) ................................. 58
TABLE 19: PIN DEFINITION OF DEBUG UART INTERFACE ......................................................................... 58
TABLE 20: LOGIC LEVELS OF DIGITAL I/O .................................................................................................... 59
TABLE 21: PIN DEFINITION OF ANALOG AUDIO INTERFACE ...................................................................... 60
TABLE 22: PIN DEFINITION OF PCM INTERFACE ......................................................................................... 63
TABLE 23: PIN DEFINITION OF I2C INTERFACES ......................................................................................... 63
TABLE 24: PIN DEFINITION OF SDIO2 INTERFACE ...................................................................................... 65
TABLE 25: PIN DEFINITION OF SPI1 INTERFACE ......................................................................................... 68
TABLE 26: PIN DEFINITION OF SPI2 INTERFACE (MULTIPLEXED FROM UART1) .................................... 68
TABLE 27: PIN DEFINITION OF SPI3 INTERFACE (MULTIPLEXED FROM UART2) .................................... 68
TABLE 28: PARAMETERS OF SPI INTERFACE TIMING ................................................................................ 69
TABLE 29: PIN DEFINITION OF SGMII INTERFACE ...................................................................................... 70
TABLE 30: PIN DEFINITION OF WIRELESS CONNECTIVITY INTERFACES ................................................ 72
TABLE 31: PIN DEFINITION OF ADC INTERFACES ....................................................................................... 76
TABLE 32: CHARACTERISTIC OF ADC INTERFACES ................................................................................... 76
TABLE 33: PIN DEFINITION OF THE NETWORK STATUS INDICATOR (NET_STATUS ) .............................. 77
TABLE 34: WORKING STATE OF THE NETWORK STATUS INDICATOR (NET_STATUS) ........................... 77
TABLE 35: PIN DEFINITION OF STATUS ........................................................................................................ 78
TABLE 36: PIN DEFINITION OF USB_BOOT INTERFACE ............................................................................. 79
TABLE 37: AG35-CE GNSS PERFORMANCE ................................................................................................. 80
TABLE 38: AG35-E GNSS PERFORMANCE .................................................................................................... 81
TABLE 39: AG35-NA GNSS PERFORMANCE ................................................................................................. 81
TABLE 40: AG35-LA GNSS PERFORMANCE .................................................................................................. 82
TABLE 41: AG35-J GNSS PERFORMANCE .................................................................................................... 82
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TABLE 42: PIN DEFINITION OF THE RF ANTENNA INTERFACES ............................................................... 84
TABLE 43: AG35-CE OPERATING FREQUENCIES ........................................................................................ 84
TABLE 44: AG35-E OPERATING FREQUENCIES ........................................................................................... 85
TABLE 45: AG35-NA OPERATING FREQUENCIES ........................................................................................ 86
TABLE 46: AG35-LA OPERATING FREQUENCIES ......................................................................................... 86
TABLE 47: AG35-J OPERATING FREQUENCIES ........................................................................................... 87
TABLE 48: PIN DEFINITION OF GNSS ANTENNA INTERFACE ..................................................................... 91
TABLE 49: GNSS FREQUENCY ....................................................................................................................... 91
TABLE 50: ANTENNA REQUIREMENTS .......................................................................................................... 92
TABLE 51: ABSOLUTE MAXIMUM RATINGS .................................................................................................. 95
TABLE 52: POWER SUPPLY RATINGS ........................................................................................................... 96
TABLE 53: OPERATION AND STORAGE TEMPERATURES .......................................................................... 96
TABLE 54: AG35-CE CURRENT CONSUMPTION (25°C, 3.8V POWER SUPPLY) ........................................ 97
TABLE 55: AG35-E CURRENT CONSUMPTION ............................................................................................. 99
TABLE 56: AG35-NA CURRENT CONSUMPTION ......................................................................................... 102
TABLE 57: AG35-LA CURRENT CONSUMPTION ......................................................................................... 104
TABLE 58: AG35-J CURRENT CONSUMPTION ............................................................................................ 108
TABLE 59: AG35-CE GNSS CURRENT CONSUMPTION ............................................................................. 109
TABLE 60: AG35-E GNSS CURRENT CONSUMPTION ................................................................................. 110
TABLE 61: AG35-NA GNSS CURRENT CONSUMPTION .............................................................................. 110
TABLE 62: AG35-LA GNSS CURRENT CONSUMPTION ............................................................................... 110
TABLE 63: AG35-J GNSS CURRENT CONSUMPTION.................................................................................. 111
TABLE 64: AG35-CE RF OUTPUT POWER .................................................................................................... 111
TABLE 65: AG35-E RF OUTPUT POWER ....................................................................................................... 112
TABLE 66: AG35-NA RF OUTPUT POWER .................................................................................................... 113
TABLE 67: AG35-LA RF OUTPUT POWER ..................................................................................................... 113
TABLE 68: AG35-J RF OUTPUT POWER ....................................................................................................... 114
TABLE 69: AG35-CE RF RECEIVING SENSITIVITY ...................................................................................... 115
TABLE 70: AG35-E RF RECEIVING SENSITIVITY ......................................................................................... 116
TABLE 71: AG35-NA RF RECEIVING SENSITIVITY ....................................................................................... 117
TABLE 72: AG35-LA RF RECEIVING SENSITIVITY ....................................................................................... 117
TABLE 73: AG35-J RF RECEIVING SENSITIVITY .......................................................................................... 118
TABLE 74: ELECTROSTATIC DISCHARGE CHARACTERISTICS ................................................................ 119
TABLE 75: RECOMMENDED THERMAL PROFILE PARAMETERS ............................................................. 127
TABLE 76: RELATED DOCUMENTS .............................................................................................................. 130
TABLE 77: TERMS AND ABBREVIATIONS .................................................................................................... 130
TABLE 78: DESCRIPTION OF DIFFERENT CODING SCHEMES ................................................................ 134
TABLE 79: GPRS MULTI-SLOT CLASSES .................................................................................................... 135
TABLE 80: EDGE MODULATION AND CODING SCHEMES ......................................................................... 137
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Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 20
FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 22
FIGURE 3: SLEEP MODE CURRENT CONSUMPTION DIAGRAM ................................................................ 41
FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 41
FIGURE 5: SLEEP MODE APPLICATION WITHOUT USB REMOTE WAKEUP ............................................. 42
FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION ................................................ 43
FIGURE 7: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ...................................................... 45
FIGURE 8: STAR STRUCTURE OF THE POWER SUPPLY ............................................................................ 45
FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 46
FIGURE 10: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................. 47
FIGURE 11: TURN ON THE MODULE USING KEYSTROKE .......................................................................... 47
FIGURE 12: TIMING OF TURNING ON MODULE ........................................................................................... 48
FIGURE 13: TIMING OF TURNING OFF MODULE ......................................................................................... 49
FIGURE 14: SHUT DOWN THE MODULE USING DRIVING CIRCUIT ........................................................... 50
FIGURE 15: TIMING OF TURNING OFF MODULE VIA SHDN_N ................................................................... 50
FIGURE 16: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 51
FIGURE 17: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 52
FIGURE 18: TIMING OF RESETTING MODULE ............................................................................................. 52
FIGURE 19: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 53
FIGURE 20: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR . 54
FIGURE 21: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 55
FIGURE 22: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 59
FIGURE 23: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 60
FIGURE 24: PRIMARY MODE TIMING ............................................................................................................ 62
FIGURE 25: AUXILIARY MODE TIMING .......................................................................................................... 62
FIGURE 26: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC .................................... 64
FIGURE 27: REFERENCE CIRCUIT DESIGN FOR SD CARD APPLICATION ............................................... 66
FIGURE 28: REFERENCE CIRCUIT DESIGN FOR EMMC APPLICATION .................................................... 67
FIGURE 29: SPI TIMING ................................................................................................................................... 69
FIGURE 30: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION ............................................. 71
FIGURE 31: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY APPLICATION .............................. 71
FIGURE 32: REFERENCE CIRCUIT FOR CONNECTION WITH AF20 MODULE .......................................... 74
FIGURE 33: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR ........................................... 77
FIGURE 34: REFERENCE CIRCUITS OF STATUS ......................................................................................... 78
FIGURE 35: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 79
FIGURE 36: REFERENCE CIRCUIT OF RF ANTENNA INTERFACES ........................................................... 88
FIGURE 37: MICROSTRIP DESIGN ON A 2-LAYER PCB ............................................................................... 89
FIGURE 38: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB ........................................................... 89
FIGURE 39: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)
................................................................................................................................................................... 90
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FIGURE 40: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)
................................................................................................................................................................... 90
FIGURE 41: REFERENCE CIRCUIT OF GNSS ANTENNA ............................................................................. 91
FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ................................................ 93
FIGURE 43: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 93
FIGURE 44: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ........................................................... 94
FIGURE 45: REFERENCED HEATSINK DESIGN (HEATSINK AT THE TOP OF THE MODULE) ................ 120
FIGURE 46: REFERENCED HEATSINK DESIGN (HEATSINK AT THE BACKSIDE OF CUSTOMERS’ PCB)
................................................................................................................................................................. 121
FIGURE 47: MODULE TOP AND SIDE DIMENSIONS ................................................................................... 122
FIGURE 48: MODULE BOTTOM DIMENSIONS (TOP VIEW) ....................................................................... 123
FIGURE 49: RECOMMENDED FOOTPRINT (TOP VIEW) ............................................................................ 124
FIGURE 50: TOP VIEW OF THE MODULE .................................................................................................... 125
FIGURE 51: BOTTOM VIEW OF THE MODULE ............................................................................................ 125
FIGURE 52: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE .............................................. 127
FIGURE 53: TAPE SPECIFICATIONS ............................................................................................................ 128
FIGURE 54: REEL SPECIFICATIONS ............................................................................................................ 129
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1 Introduction
This document defines the AG35-Quecopen module and describes its air interface and hardware
interface which are connected with customers’ applications.
This document can help customers quickly understand module interface specifications, electrical and
mechanical details, as well as other related information of the module. Associated with application notes
and user guides, customers can use AG35-Quecopen module to design and set up automotive industry
mobile applications easily.
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1.1. Safety Information
The following safety precautions must be observed during all phases of the operation, such as usage,
service or repair of any cellular terminal or mobile incorporating AG35-Quecopen module. Manufacturers of
the cellular terminal should send the following safety information to users and operating personnel, and
incorporate these guidelines into all manuals supplied with the product. If not so, Quectel assumes no
liability for customers’ failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If the device offers an Airplane Mode, then it should be
enabled prior to boarding an aircraft. Please consult the airline staff for more
restrictions on the use of wireless devices on boarding the aircraft.
Wireless devices may cause interference on sensitive medical equipment, so
please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, please remember using emergency call. In order to make or receive a
call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.
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2 Product Concept
2.1. General Description
Quecopen
of communication technology and the ever-changing market demands, more and more customers have
realized the advantages of Quecopen
greatly valued by customers. With Quecopen
hardware design will be simplified. Main features of Quecopen
Simplifies the development of embedded applications, and shortens product development cycle
Simplifies circuit design, and reduces product cost
Decreases the size of terminal products
Reduces power consumption
Supports remote upgrade of firmware wirelessly
Improves products’ cost-performance ratio, and enhances products’ competitiveness
AG35-Quecopen module is a baseband processor platform based on ARM Cortex A7 kernel. The
maximum dominant frequency is up to 1.2GHz. Customers can use AG35-Quecopen modules as the
basis for development of Quecopen® applications.
AG35-Quecopen is a series of automotive-grade LTE-FDD/LTE-TDD/WCDMA/TD-SCDMA/EVDO/
CDMA/GSM wireless communication module with receive diversity, and provides data connectivity on
LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA, TD-SCDMA, EVDO, CDMA,
EDGE and GPRS networks. It also provides GNSS and voice functionalities to meet customers’ specific
application demands.
Engineered to meet the demanding requirements in automotive applications and other harsh operating
conditions, AG35-Quecopen offers a premium solution for high performance automotive and intelligent
transportation system (ITS) applications, such as fleet management, onboard vehicle telematics, in-car
entertainment systems, emergency calling, and roadside assistance.
With a compact profile of 33.0mm × 37.5mm × 3.0mm, AG35-Quecopen can meet almost all
requirements for automobile application. It is an SMD type module which can be embedded into
applications through its 299-pin LGA pads.
®
is an application solution where the module acts as a main processor. With the development
®
solution. Especially, its advantage in reducing the product cost is
®
solution, development flow for wireless application and
®
solution are listed below:
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Table 1: Frequency Bands of AG35-Quecopen Modules
Hardware Design
Network
Typ e
LTE-FDD
(with
Rx-diversity)
LTE-TDD
(with
Rx-diversity)
WCDMA
(with
Rx-diversity)
AG35-CE AG35-E AG35-NA AG35-LA* AG35-J*
B1/B3/
B5/B8
B1/B3/B5/
B7/B8/B20/
B28
B2/B4/B5/
B7/B12/B13/
B17/B28
1)
B1/B2/B3/
B4/B5/B7/
B8/B28
B1/B3/B5/B8/
B9/B19/B21/
B28/
B34/B38/
B39/B40/
B38/B40 N/A N/A B41
B41
B1/B8 B1/B5/B8 B2/B4/B5
B1/B2/B3/
B4/B5/B8
B1/B3/B5/
B6/B8/B19
TD-SCDMA B34/B39 N/A N/A N/A N/A
EVDO/CDMA BC0 1) N/A N/A N/A N/A
GSM 900/1800MHz 900/1800MHz 850/1900MHz
GPS,
GLONASS,
BeiDou/
Compass,
Galileo, QZSS
GNSS
GPS,
GLONASS,
BeiDou/
Compass,
Galileo, QZSS
GPS,
GLONASS,
BeiDou/
Compass,
Galileo, QZSS
850/900/
1800/1900MHz
GPS,
GLONASS,
BeiDou/
Compass,
Galileo, QZSS
N/A
GPS,
GLONASS,
BeiDou/
Compass,
Galileo, QZSS
NOTES
1)
1.
EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional.
2. “*” means under development.
2.2. Key Features
The following table describes the detailed features of AG35-Quecopen module.
Table 2: Key Features of AG35-Quecopen Modules
Feature Details
Power Supply
Supply voltage: 3.3V~4.3V
Typical supply voltage: 3.8V
AG35-QuecOpen_Hardware_Design 15 / 137
LTE Module Series
AG35-Quecopen
Transmitting Power
LTE Features
Class 4 (33dBm±2dB) for GSM850
Class 4 (33dBm±2dB) for EGSM900
Class 1 (30dBm±2dB) for DCS1800
Class 1 (30dBm±2dB) for PCS1900
Class E2 (27dBm±3dB) for GSM850 8-PSK
Class E2 (27dBm±3dB) for EGSM900 8-PSK
Class E2 (26dBm±3dB) for DCS1800 8-PSK
Class E2 (26dBm±3dB) for PCS1900 8-PSK
Class 3 (24dBm+2/-1dB) for EVDO/CDMA BC0
Class 3 (24dBm+1/-3dB) for WCDMA bands
Class 2 (24dBm+1/-3dB) for TD-SCDMA bands
Class 3 (23dBm±2dB) for LTE-FDD bands
Class 3 (23dBm±2dB) for LTE-TDD bands
Support up to non-CA Cat 4 LTE FDD and TDD
Support 1.4 to 20MHz RF bandwidth
Support Multiuser MIMO in DL direction
FDD: Max 150Mbps (DL)/50Mbps (UL)
TDD: Max 130Mbps (DL)/30Mbps (UL)
Hardware Design
UMTS Features
TD-SCDMA Features
CDMA2000 Features
GSM Features
Support 3GPP R8 DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA
Support QPSK, 16-QAM and 64-QAM modulation
DC-HSDPA: Max 42Mbps (DL)
HSUPA: Max 5.76Mbps (UL)
WCDMA: Max 384Kbps (DL)/384Kbps (UL)
Support CCSA Release 3 TD-SCDMA
Max 4.2Mbps (DL)/2.2Mbps (UL)
Support 3GPP2 CDMA2000 1X Advanced, CDMA2000 1x EV-DO Rev.A
EVDO: Max 3.1Mbps (DL)/1.8Mbps (UL)
1X Advanced: Max 307.2Kbps (DL)/307.2Kbps (UL)
GPRS:
Support GPRS multi-slot class 33 (33 by default)
Coding scheme: CS-1, CS-2, CS-3 and CS-4
Max 107Kbps (DL)/85.6Kbps (UL)
EDGE:
Support EDGE multi-slot class 33 (33 by default)
Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
Downlink coding schemes: CS 1-4 and MCS 1-9
Uplink coding schemes: CS 1-4 and MCS 1-9
Max 296Kbps (DL)/236.8Kbps (UL)
Support TCP/UDP/PPP/FTP/HTTP/NTP/PING/QMI/HTTPS/SMTP/MMS/
Internet Protocol Features
FTPS/SMTPS/SSL protocols
Support the protocols PAP (Password Authentication Protocol) and CHAP
(Challenge Handshake Authentication Protocol) usually used for PPP
AG35-QuecOpen_Hardware_Design 16 / 137
LTE Module Series
AG35-Quecopen
connections
Text and PDU modes
SMS
Point to point MO and MT
SMS cell broadcast
SMS storage: ME by default
(U)SIM Interface Support USIM/SIM card: 1.8V, 3.0V
Built-in audio codec with two microphone inputs and one stereo output or
two mono outputs
Audio Features
(Optional)
GSM: HR/FR/EFR/AMR/AMR-WB
WCDMA: AMR/AMR-WB
LTE: AMR/AMR-WB
Support echo cancellation and noise suppression
Used for audio function with external codec
Support 16-bit linear data format
PCM Interface
Support long frame synchronization and short frame synchronization
Support master and slave modes, but must be the master in long frame
synchronization
Hardware Design
USB Interface
UART Interfaces
Compliant with USB 2.0 specification (support USB HOST) and the data
transfer rate can reach up to 480Mbps
Used for AT command communication, data transmission, GNSS NMEA
output, software debugging and firmware upgrade
Support USB serial driver under Windows 7/8/8.1/10, Windows CE
5.0/6.0/7.0*, Linux 2.6/3.x/4.1~4.14, Android 4.x/5.x/6.x/7.x/8.x
UART1:
Baud rate reach up to 921600bps, 115200bps by default
Support RTS and CTS hardware flow control
UART2:
Baud rate reach up to 921600bps, 115200bps by default
Support RTS and CTS hardware flow control
UART3 (Multiplexed from SPI):
Baud rate reach up to 921600bps, 115200bps by default
Support RTS and CTS hardware flow control
UART4 (Multiplexed from SDIO1):
Baud rate reach up to 921600bps, 115200bps by default
Support RTS and CTS hardware flow control
UART5 (Multiplexed from SDIO1):
Baud rate reach up to 921600bps, 115200bps by default
Debug UART:
Used for Linux console and log output, 115200bps baud rate
SDIO1:
SDIO Interfaces
Compliant with SD 3.0 protocol
Used for WLAN function
AG35-QuecOpen_Hardware_Design 17 / 137
LTE Module Series
AG35-Quecopen
SDIO2:
Compliant with SD 3.0 protocol
Support eMMC and SD card
SPI Interfaces
Support master mode only
Maximum clock frequency rate: 50MHz
I2C1:
Compliant with I2C specification version 5.0
Multi-master is not supported
I2C Interfaces
Used for codec configuration by default
I2C2:
Compliant with I2C specification version 5.0
Multi-master is not supported
SGMII Interface (Optional) Support 10/100Mbps
Hardware Design
Wireless Connectivity
Interfaces
Support SDIO1 interface for WLAN and UART & PCM interfaces for
Bluetooth*
Rx-diversity Support LTE/WCDMA Rx-diversity
GNSS Features
AT Commands
Gen8C-Lite of Qualcomm
Protocol: NMEA 0183
3GPP TS 27.007/3GPP TS 27.005 AT commands and Quectel enhanced
AT commands
Network Indication NET_STATUS is used to indicate network connectivity status
Antenna Interface
Physical Characteristics
Temperature Range
Including main antenna interface (ANT_MAIN), Rx-diversity antenna
interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS)
Size: (33.0±0.15)mm × (37.5±0.15 )mm × (3.0±0.2)mm
Weight: approx. 8.1g
2)
1)
Operation temperature range: -35°C ~ +75°C
Extended temperature range: -40°C ~ +85°C
eCall temperature range: -40°C ~ +90°C 3)
Storage temperature range: -40°C ~ +95°C
Firmware Upgrade
USB interface
DFOTA
RoHS All hardware components are fully compliant with EU RoHS directive
NOTES
1. 1) Within operation temperature range, the module is 3GPP compliant, and emergency call can be
dialed out with a maximum power and data rate.
2. 2) Within extended temperature range, the module remains fully functional and retains the ability to
establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no
unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio
network. Only one or more parameters like P
might reduce in their value and exceed the specified
out
AG35-QuecOpen_Hardware_Design 18 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
tolerances. When the temperature returns to normal operation temperature levels, the module will
meet 3GPP specifications again.
3. 3) Within eCall temperature range, the emergency call function must be functional until the module is
broken. When the ambient temperature is between 75°C and 90°C and the module temperature has
reached the threshold value, the module will trigger protective measures (such as reduce power,
decrease throughput, unregister the device, etc.) to ensure the full function of emergency call.
4. “*” means under development.
2.3. Functional Diagram
The following figure shows a block diagram of AG35-Quecopen and illustrates the major functional parts.
Power management
Baseband
DDR+NAND flash
Radio frequency
Peripheral interfaces
AG35-QuecOpen_Hardware_Design 19 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
Figure 1: Functional Diagram
2.4. Evaluation Board
In order to help customers develop applications conveniently with AG35-Quecopen module, Quectel
supplies the evaluation board (EVB), USB data cable, earphone, antenna and other peripherals to control
or test the module. For more details, please refer to document [4].
AG35-QuecOpen_Hardware_Design 20 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
3 Application Interfaces
3.1. General Description
AG35-Quecopen is equipped with 299-pin LGA pads that can be connected to cellular application
platform. Sub-interfaces included in these pads are described in detail in the following sub-chapters:
Power supply
(U)SIM interface
USB interface
UART interfaces
Audio interface (optional)
PCM and I2C interfaces
SDIO interfaces
SPI interfaces
SGMII interface (optional)
Wireless connectivity interfaces
ADC interfaces
Status indication interfaces
USB_BOOT interface
3.2. Pin Assignment
The following figure shows the pin assignment of AG35-Quecopen module.
AG35-QuecOpen_Hardware_Design 21 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
GND
SPK2_P
SPK1_P
MICBIAS
MIC2_P
MIC_P
GND
GPIO 4
COEX_UART_RX
GND
WAKEUP_I N
MCLK
GND
VBAT_BB
GND
WLAN_WAKE
RESERVED
UART2_CTS
UART2_RTS
VDD_EXT
NET_STATUS
ADC2
GND
SHDN_N
GND
SPK2_N
SPK1_N
MIC2_N
MIC1_N
AGND
GPIO 8
COEX_UAR T_TX
GPIO 5
WLAN_EN
RESERVED
GND
VBAT_BB
GND
GPIO 7
RESERVED
UART2_TXD
UART2_RXD
GND
WLAN_SLP_CLK
STATUS
ADC0
ADC1
ANT_DI V
129
127
299
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
296
125
128
126
124
214
213
224
233
242
251
260
269
278
287
178
177
6
4
2
5
3
1
ANT_GNSS
RESERVED
RESERVED
123
121
119
117
115
113
122
120
118
116
114
112
212
211
210
209
208
207
216 217 218215 219 220 221 222 223
225
226
227
234
235
236
244
253
262
271
280
289
183
182
14
12
13
15
245 246 247
254 255 256
263 264 265
272
281
290
184
18
16
17
243
252
261
270
279
288
181
180
179
8
10
9
7
11
ANT_MAIN
111
109
107
110
108
206
205
204
228
237
273
282
291
187
186
185
22
20
23
21
19
RESERVED
99
105
103
106
104
102
203
202
229
238
274
283
292
189
188
28
26
24
27
97
101
98
100
201
200
199
230
231
239
240
248
249
257
258
266
267
275
276
284
285
293
294
192
191
190
32
30
33
31
29
RESERVED
95
93
91
89
298
96
94
92
90
198
197
196
232
241
250
259
268
277
286
295
195
194
193
36
34
39
37
35
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
402538
41
RESERVED
72
RESERVED
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
297
VBAT_RF
VBAT_RF
GND
GND
SPI_CS
SPI_MOSI
GND
GND
PCM_CLK
PCM_SYNC
GND
GPIO 2
GPIO 1
UART1_RTS
GND
SDC2_CL K
SDC2_CM D
SDC2_DATA0
SDC2_DATA2
GND
I2C1_SCL
VBAT_RF
VBAT_RF
GND
GND
SPI_CL K
SPI_MISO
GND
RESERVED
RESERVED
GND
PCM_OUT
PCM_IN
GND
GPIO 3
UART1_TXD
UART1_RXD
UART1_CTS
GND
SDC2_INS_DET
SDC2_DATA1
SDC2_DATA 3
SDC2_VDD
GND
I2C1_SDA
GND
GND
VDD_MDIO
EPHY_RST_N
PWRKEY
BT_EN
RESET_N
PM_ENABLE
Powe r Pin s GND Pins Signa l Pins RESV RVED P ins
MDIO Pins
ADC Pins
COEX_UART Pins SGMII Pins
GND
RESERVED
RESERVED
SGMII_R X_P
GND
SGMII_MD ATA
SGMII_MC LK
EPHY_IN T_N
SGMII_R X_M
SDIO Pin s
UART2 Pins
RESERVED
GND
GND
RESERVED
SDC1_CMD
SGMII_T X_P
GND
SGMII_T X_M
GND
RESERVED
SDC1_DATA0
SDC1_CLK
(U)SI M Pins
UART1 Pins
SPI Pins
RESERVED
SDC1_DATA1
GND
RESERVED
SDC1_DATA2
USIM_GND
USIM_VDD
SDC1_DATA3
USIM_PRESENCE
RESERVED
USIM_RST
USIM_CLK
GND
RESERVED
USB_VBUS
GND
GND
USIM_DATA
USB Pins
Debug UART Pins
Audio Pins
RESERVED
USB_DM
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GND
IIC Pi ns
SD Pin s
GPIO Pi ns
PCM Pins
RESERVED
USB_DP
GND
Figure 2: Pin Assignment (Top View)
NOTES
1. Pins 59, 65, 67, 144~147, 149 and 159 cannot be pulled up before power-up. Pin 80 cannot be pulled
down before power-up.
2. PWRKEY (pin 2) output voltage is 0.8V because of the diode drop in the Qualcomm chipset.
AG35-QuecOpen_Hardware_Design 22 / 137
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AG35-Quecopen
Hardware Design
3. GND pins 215~299 should be connected to ground in the design.
4. Keep all RESERVED pins and unused pins unconnected.
3.3. Pin Description
The following tables show the pin definition of AG35-Quecopen module, as well as the alternate functions
of multiplexing pins.
Table 3: I/O Parameters Definition
Typ e Description
AI Analog input
AO Analog output
B Bidirectional digital with CMOS input
BH High-voltage tolerant bidirectional digital with CMOS input
DI Digital input
DO Digital output
H High level
IO Bidirectional
L Low level
OC Open collector
OD Open drain
PD Pull down
PI Power input
PO Power output
PU Pull up
AG35-QuecOpen_Hardware_Design 23 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
Table 4: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
VBAT_BB 155, 156 PI
VBAT_RF
85, 86,
87, 88
PI
VDD_EXT 168 PO
10, 13, 16,
17, 30, 31,
35, 39, 44,
45, 54, 55,
63, 64, 69,
70, 75, 76,
81~84,
89~94,
96~100,
102~106,
108~112,
GND
114,
Ground
116~118,
120~126,
128~131,
142, 148,
153, 154,
157, 158,
167, 174,
177, 178,
181, 184,
187, 191,
196~299
Power supply for
module’s baseband
part
Power supply for
module’s RF part
Provide 1.8V for
external circuit
Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V
Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V
Vnorm=1.8V
I
max=50mA
O
It must be able to
provide sufficient
current up to 0.8A.
It must be able to
provide sufficient
current up to 1.8A in a
transmitting burst.
Power supply for
external GPIO’s pull up
circuits.
Turn on/off
Pin Name Pin No. I/O Description DC Characteristics Comment
PWRKEY 2 DI
Turn on/off the
module
V
max=2.1V
IH
V
min=1.3V
IH
The output voltage is
0.8V because of the
AG35-QuecOpen_Hardware_Design 24 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
VILmax=0.5V diode drop in the
Qualcomm chipset.
max=2.1V
V
RESET_N 1 DI Reset the module
Emergency
SHDN_N 176 DI
shutdown for the
module
IH
V
min=1.3V
IH
V
max=0.5V
IL
max=2.1V
V
IH
V
min=1.3V
IH
V
max=0.5V
IL
Internally pulled up to
1.8V. Active low.
(U)SIM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
USIM_GND 24
USIM_
PRESENCE
25 DI
USIM_VDD 26 PO
USIM_CLK 27 DO
USIM_RST 28 DO
USIM_DATA 29 IO
Specified ground for
(U)SIM card
(U)SIM card
insertion detection
Power supply for
(U)SIM card
Clock signal of
(U)SIM card
Reset signal of
(U)SIM card
Data signal of
(U)SIM card
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
For 1.8V (U)SIM:
Vmax=1.9V
Vmin=1.7V
For 3.0V (U)SIM:
Vmax=3.05V
Vmin=2.7V
IOmax=50mA
For 1.8V (U)SIM:
V
max=0.45V
OL
V
min=1.35V
OH
For 3.0V (U)SIM:
max=0.45V
V
OL
V
min=2.55V
OH
For 1.8V (U)SIM:
V
max=0.45V
OL
V
min=1.35V
OH
For 3.0V (U)SIM:
max=0.45V
V
OL
V
min=2.55V
OH
For 1.8V (U)SIM:
VILmax=0.6V
V
min=1.2V
IH
Connect to ground of
(U)SIM card
connector.
1.8V power domain.
If unused, keep it
open.
Either 1.8V or 3.0V is
supported by the
module automatically.
AG35-QuecOpen_Hardware_Design 25 / 137
LTE Module Series
AG35-Quecopen
Hardware Design
VOLmax=0.45V
VOHmin=1.35V
For 3.0V (U)SIM:
max=1.0V
V
IL
V
min=1.95V
IH
V
max=0.45V
OL
V
min=2.55V
OH
USB Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
USB_VBUS 32 PI
USB_DM 33 IO
USB_DP 34 IO
USB connection
detection
USB differential data
bus (-)
USB differential data
bus (+)
Vmax=5.25V
Vmin=3.0V
Vnorm=5.0V
Compliant with USB
2.0 standard
specification.
Compliant with USB
2.0 standard
specification.
Maximum current:
1mA.
Require differential
impedance of 90Ω.
Status Indication
Pin Name Pin No. I/O Description DC Characteristics Comment
STATUS 171 OD
NET_
STATUS
170 DO
Indicate the
module’s operation
status
Indicate the
module’s network
activity status
The drive current
should be less than
0.15mA.
V
min=1.35V
OH
V
max=0.45V
OL
Require external
pull-up. If unused,
keep it open.
1.8V power domain.
If unused, keep it
open.
UART1 Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
UART1_CTS 56 DO DTE clear to send
UART1_RTS 57 DI DTE request to send
UART1_RXD 58 DI Receive data
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
min=-0.3V
V
IL
V
max=0.6V
IL
V
min=1.2V
IH
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AG35-Quecopen
Hardware Design
VIHmax=2.0V
1.8V power domain.
If unused, keep it
open.
UART1_TXD 60 DO Transmit data
V
max=0.45V
OL
V
min=1.35V
OH
UART2 Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
UART2_TXD 163 DO Transmit data
UART2_CTS 164 DO DTE clear to send
UART2_RXD 165 DI Receive data
UART2_RTS 166 DI DTE request to send
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
Debug UART Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
DBG_TXD 71 DO Transmit data
DBG_RXD 72 DI Receive data
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
ADC Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
ADC0 173 AI
ADC1 175 AI
General purpose
analog to digital
converter interface
General purpose
analog to digital
converter interface
Voltage range:
0.3V to VBAT_BB
Voltage range:
0.3V to VBAT_BB
If unused, keep it
open.
If unused, keep it
open.
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LTE Module Series
AG35-Quecopen
Hardware Design
ADC2 172 AI
General purpose
analog to digital
converter interface
Voltage range:
0.1V to 1.7V
If unused, keep it
open.
Audio Interface (Optional)
Pin Name Pin No. I/O Description DC Characteristics Comment
SPK2_P 132 AO
SPK2_N 133 AO
SPK1_P 134 AO
SPK1_N 135 AO
MICBIAS 136 AO
MIC2_N 137 AI
Earphone analog
output 2 (+)
Earphone analog
output 2 (-)
Earphone analog
output 1 (+)
Earphone analog
output 1 (-)
Bias voltage output
for microphone
Microphone analog
input 2 (-)
Vmax=1.55V
Vmin=1.5V
Vnorm=1.525V
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
MIC2_P 138 AI
MIC1_N 139 AI
MIC1_P 140 AI
Microphone analog
input 2 (+)
Microphone analog
input 1 (-)
Microphone analog
input 1 (+)
AGND 141 Analog ground
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
PCM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
In master mode, it is
an output signal. In
slave mode, it is an
input signal.
If unused, keep it
open.
PCM_SYNC 65 IO
PCM data frame
synchronization
signal
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
PCM_IN 66 DI PCM data input
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
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AG35-Quecopen
Hardware Design
1.8V power domain.
In master mode, it is
an output signal. In
slave mode, it is an
input signal.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
PCM_CLK 67 IO PCM clock
PCM_OUT 68 DO PCM data output
MCLK 152 DO Output 12.288MHZ
VOLmax=0.45V
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
I2C1 Interface (for Codec Configuration by Default)
Pin Name Pin No. I/O Description DC Characteristics Comment
V
max=0.45V
I2C1_SDA 42 IO
I2C1 serial data.
Used for external
codec.
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
External pull-up
resistor is required.
1.8V only.
If unused, keep it
open.
External pull-up
resistor is required.
1.8V only.
If unused, keep it
I2C1_SCL 43 DO
I2C1 serial clock.
Used for external
codec.
V
max=0.45V
OL
V
min=1.35V
OH
open.
I2C2 Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
V
max=0.45V
OL
External pull-up
resistor is required.
1.8V only. If unused,
keep it open.
I2C2_SDA 73 IO I2C2 serial data
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
External pull-up
I2C2_SCL 74 DO I2C2 serial clock
max=0.45V
OL
V
min=1.35V
OH
resistor is required.
1.8V only. If unused,
V
keep it open.
SDIO2 Interface (for eMMC & SD Card)
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AG35-Quecopen
Hardware Design
Pin Name Pin No. I/O Description DC Characteristics Comment
SD card
1.8V/2.85V
configurable power
output.
If unused, keep it
open.
VDD_SDIO 46 PO
application: SDIO
pull up power
source.
eMMC application:
Keep it open when
IOmax=50mA
used for eMMC.
SDC2_
DATA2
SDC2_
DATA3
SDC2_
DATA0
SDC2_
DATA1
47 IO
48 IO
49 IO
50 IO
SDC2_CMD 51 IO
SDIO data signal
(bit 2)
SDIO data signal
(bit 3)
SDIO data signal
(bit 0)
SDIO data signal
(bit 1)
SDIO command
signal
DI: Insertion
DI/
SD_INS_
DET
52
detection for SD
DO
card.
DO: Reset eMMC
SDC2_CLK 53 DO SDIO bus clock
For 1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
For 3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
For 1.8V signaling:
max=0.45V
V
OL
V
min=1.4V
OH
For 3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
SDIO signal level can
be selected
according to the one
supported by SD
card.
1.8V power domain
for eMMC.
Please refer to SD
3.0 protocol for more
details.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
eMMC resetting is
currently not
supported.
SDIO signal level can
be selected
according to the one
supported by SD
card.
1.8V power domain
for eMMC.
Please refer to SD
3.0 protocol for more
details.
If unused, keep it
open.
SPI Interface
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LTE Module Series
AG35-Quecopen
Hardware Design
Pin Name Pin No. I/O Description DC Characteristics Comment
SPI_MOSI 77 DO
SPI_MISO 78 DI
SPI master out slave
in
SPI master in slave
out
SPI_CS_N 79 DO SPI chip selection
SPI_CLK 80 DO SPI serial clock
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
MDIO Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V/2.85V
VDD_MDIO 4 PO
SGMII_MDATA
pull-up power source
configurable power
output. If unused,
keep it open.
EPHY_RST_
N
6 DO Ethernet PHY reset
SGMII_MCLK 7 DO
SGMII_
MDATA
8 IO
SGMII MDIO
(Management Data
Input/Output) clock
SGMII MDIO
(Management Data
Input/Output) data
1.8V：
V
OLmax=0.45V
V
OHmin=1.35V
2.85V：
V
OLmax=0.35V
V
OHmin=2.14V
1.8V：
V
OLmax=0.45V
V
OHmin=1.35V
2.85V：
V
OLmax=0.35V
V
OHmin=2.14V
1.8V：
V
ILmax=0.58V
V
IHmin=1.27V
V
OLmax=0.45V
V
OHmin=1.4V
2.85V：
V
max=1.0V
IL
V
min=1.95V
IH
V
max=0.45V
OL
1.8V/2.85V power
domain.
If unused, keep it
open.
1.8V/2.85V power
domain.
If unused, keep it
open.
1.8V/2.85V power
domain.
External 1.5K resistor
pulled up to
VDD_MDIO is
required.
If unused, keep it
open.
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AG35-Quecopen
Hardware Design
VOHmin=2.55V
V
min=-0.3V
EPHY_INT_N 9 DI
Ethernet PHY
interrupt
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
SGMII Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
SGMII_RX_M 11 AI SGMII receiving (-)
SGMII_RX_P 12 AI SGMII receiving (+)
SGMII_TX_P 14 AO
SGMII_TX_M 15 AO
SGMII transmission
(+)
SGMII transmission
(-)
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
WLAN Interface (SDIO1 and WLAN Control Interfaces)
Pin Name Pin No. I/O Description DC Characteristics Comment
WLAN_SLP_
CLK
169 DO WLAN sleep clock
PM_ENABLE 5 DO
SDC1_CMD 18 IO
External power
enable control
WLAN SDIO
command signal
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
SDC1_CLK 19 DO
SDC1_
DATA0
SDC1_
DATA1
20 IO
21 IO
WLAN SDIO clock
signal
WLAN SDIO data
bus (bit 0)
WLAN SDIO data
bus (bit 1)
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
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AG35-Quecopen
SDC1_
DATA2
SDC1_
DATA3
WLAN_
WAKE
22 IO
23 IO
160 DI
WLAN_EN 149 DO
WLAN SDIO data
bus (bit 2)
WLAN SDIO data
bus (bit 3)
Wake up the module
via WLAN
WLAN function
enable control via
Wi-Fi module
VIHmin=1.2V
VIHmax=2.0V
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
Hardware Design
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
Active low.
If unused, keep it
open.
1.8V power domain.
Active high.
If unused, keep it
open.
LTE/WLAN&BT
COEX_
UART_RX/U
SB_BOOT
146 DI
coexistence signal/
Force the module to
enter into
emergency
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
download mode.
COEX_
UART_TX
145 DO
LTE/WLAN&BT
coexistence signal
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep it
open.
RF Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
ANT_MAIN 107 IO
ANT_GNSS 119 AI
ANT_DIV 127 AI
Main antenna
interface
GNSS antenna
interface
Diversity antenna
interface
50Ω impedance
50Ω impedance.
If unused, keep it
open.
50Ω impedance.
If unused, keep it
open.
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AG35-Quecopen
Hardware Design
GPIO Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
GPIO1 59 IO
GPIO2 61 IO
GPIO3 62 IO
GPIO4 144 IO
GPIO5 147 IO
GPIO6 150 IO
General purpose
input/output
interface
VILmin=-0.3V
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep the
pins open.
GPIO7 159 IO
GPIO8 143 IO
BT Control Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
BT_EN* 3 DO
Bluetooth enable
control
The function is still
under development.
RESERVED Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
36~38, 40,
41, 95,
101, 113,
115,
151, 161,
RESERVED
162, 179,
Reserved
180, 182,
183, 185,
186,
188~190,
192~195
NOTES
1. “*” means under development.
2. Keep all RESERVED pins and unused pins unconnected.
Keep these pins
unconnected.
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AG35-QuecOpen
The following table lists the multiplexing pins and their respective alternate functions of AG35-Quecopen.
Table 5: Alternate Functions of Multiplexing Pins
Hardware Design
Pin Name Pin No.
Mode 1
(Default)
Mode 2 Mode 3 Mode 4 Reset 1)
Status in
Booting
Wake-up
Interrupt
2)
Remark
GPIO1 59 GPIO_38 -- -- -- B-PD,L Low level YES BOOT_CONFIG_12
GPIO2 61 GPIO_75 -- -- -- B-PD,L Low level YES
GPIO3 62 GPIO_74 -- -- -- B-PD,L Low level YES
GPIO4 144 GPIO_25 -- -- -- B-PD,L Low level YES BOOT_CONFIG_2
GPIO5 147 GPIO_24 -- -- -- B-PD,L Low level NO BOOT_CONFIG_1
Recommended to be
GPIO6 150 GPIO_42 -- -- -- B-PD,L Low level YES
“output”. Please refer to
NOTE 2 for details.
BOOT_CONFIG_11.
GPIO7 159 GPIO_58 -- -- -- B-PD,L Low level NO
Recommended to be
“output”. Please refer to
NOTE 2 for details.
Recommended to be
GPIO8 143 GPIO_41 -- -- -- B-PD,L Low level NO
“output”. Please refer to
NOTE 2 for details.
BT_EN* 3 BT_EN*
PMU_
GPIO_02
-- -- B-PD,L Low level NO
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AG35-QuecOpen
Hardware Design
PM_ENABLE 5 PM_ENABLE
PMU_
GPIO_03
SDC1_CMD 18 SDC1_CMD GPIO_17
SDC1_CLK 19 SDC1_CLK GPIO_16
SDC1_DATA0 20 SDC1_DATA0 GPIO_15
SDC1_DATA1 21 SDC1_DATA1 GPIO_14
SDC1_DATA2 22 SDC1_DATA2 GPIO_13
SDC1_DATA3 23 SDC1_DATA3 GPIO_12
USIM_
PRESENCE
25
I2C1_SDA 42
USIM_
PRESENCE
I2C_SDA_
BLSP4
GPIO_34 -- -- B-PD,L Low level YES
GPIO_18 -- -- B-PD,L High level NO
-- -- B-PD,L Low level NO
UART_RXD_
BLSP4
UART_TXD_
BLSP4
UART_CTS_
BLSP1
UART_RTS_
BLSP1
UART_RXD_
BLSP1
UART_TXD_
BLSP1
-- B-PD,L Low level YES
-- B-NP,L Low level YES
SPI_CLK_
BLSP1
SPI_CS_N
_BLSP1
SPI_MISO
_BLSP1
SPI_MOSI
_BLSP1
B-PD,L Low level NO
B-PD,L Low level NO
B-PD,L Low level YES
B-PD,L Low level YES
I2C1_SCL 43
SDC2_INT_
DET
52
UART1_CTS 56
UART1_RTS 57
I2C_SCL_
BLSP4
SDC2_INT_
DET
UART_CTS_
BLSP3
UART_RTS_
BLSP3
GPIO_19 -- -- B-PD,L High level NO
GPIO_26 -- -- B-PD,L Low level YES
GPIO_3
GPIO_2
SPI_CLK_BL
SP3
SPI_CS_N_B
LSP3
-- B-PD,L Low level YES
-- B-PD,L Low level NO
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AG35-QuecOpen
Hardware Design
UART1_RXD 58
UART1_TXD 60
UART_RXD_
BLSP3
UART_TXD_
BLSP3
GPIO_1
GPIO_0
SPI_MISO_B
LSP3
SPI_MOSI_B
LSP3
-- B-PD,L Low level YES
-- B-PD,L Low level NO
PCM_SYNC 65 PCM_SYNC GPIO_79 -- -- B-PD,L Low level YES BOOT_CONFIG_7
PCM_IN 66 PCM_IN GPIO_76 -- -- B-PD,L Low level YES
PCM_CLK 67 PCM_CLK GPIO_78 -- -- B-PD,L Low level NO BOOT_CONFIG_8
PCM_OUT 68 PCM_OUT GPIO_77 -- -- B-PD,L Low level NO
Recommended to be “input”.
Please refer to NOTE 3 for
details.
I2C2_SDA 73
I2C2_SCL 74
SPI_MOSI 77
SPI_MISO 78
I2C_SDA_
BLSP2
I2C_SCL_
BLSP2
SPI_MOSI_
BLSP6
SPI_MISO_
BLSP6
GPIO_6 -- -- B-PD,L High pulse NO
GPIO_7 -- -- B-PD,L Low level NO
GPIO_20
GPIO_21
UART_TXD_
BLSP6
UART_RXD_
BLSP6
PCM_1A_
SYNC
PCM_1A
_IN
B-PD,L Low level YES
B-PD,L Low level YES
SPI_CS_N 79
SPI_CLK 80
SPI_CS_N_
BLSP6
SPI_CLK_
BLSP6
GPIO_22
GPIO_23
UART_RTS_
BLSP6
UART_CTS_
BLSP6
PCM_1A
_OUT
PCM_1A
_CLK
B-PD,L Low level YES
B-PU,H High level NO BOOT_CONFIG_4
WLAN_EN 149 WLAN_EN GPIO_54 -- -- B-PD,L Low level NO BOOT_CONFIG_6
UART2_TXD 163
UART_TXD_B
LSP5
GPIO_8
SPI_MOSI_B
LSP5
-- B-PD,L Low level YES
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AG35-QuecOpen
Hardware Design
UART2_CTS 164
UART2_RXD 165
UART2_RTS 166
WLAN_SLP_
CLK
169
NET_STATUS 170
UART_CTS_B
LSP5
UART_RXD_
BLSP5
UART_RTS_B
LSP5
WLAN_SLP_
CLK
PMU_GPIO_0
1
GPIO_11
GPIO_9
GPIO_10
PMU_
GPIO_06
NET_STA
TUS
SPI_CLK_BL
SP5
SPI_MISO_B
LSP5
SPI_CS_N_B
LSP5
-- B-PU,L High level YES
-- B-PD,L Low level YES
-- B-PD,L Low level NO
-- -- B-PD,L Low level NO
-- -- B-PD,L Low level NO
NOTES
1. The pin functions in Mode 2/3/4 take effect only after software configuration.
2. Pins 150, 159 and 143 are recommended to be “output” when they are used as GPIOs. When they are used as “input”, they should be configured as NP
(no pull-up or pull-down internally) and add pull-up/pull-down circuits externally.
3. The module will generate a high pulse on pin 73 during power-up. Therefore, when pin 73 is used as GPIO, it is recommended to use it as “input”.
1)
4.
Please refer to Table 3 for more details about the symbol description.
2)
5.
If the GPIOs of no interrupt function configured as interrupter function, it will increase consumption of the module. (“YES” means “interrupt function
supported”. “NO” means “interrupt function not supported”.)
6. Pins 59, 65, 67, 144~147, 149 and 159 cannot be pulled up before power-up. Pin 80 cannot be pulled down before power-up.
7. “*” means under development.
The following table lists the pull-up and pull-down resistance values of AG35-Quecopen GPIOs.
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AG35-QuecOpen
Hardware Design
Table 6: Pull-up/Pull-down Resistance of GPIOs
Symbol Description Pin number Min Typ . Max Unit
RPU
RPD
Pull-up
resistance
Pull-down
resistance
18~23, 25, 42, 43, 52, 56~62, 65~68, 73, 74, 77~80, 144, 147, 149, 163~166 55 100 390 kohm
143, 150, 159 5 7 50 kohm
18~23, 25, 42, 43, 52, 56~62, 65~68, 73, 74, 77~80, 144, 147, 149, 163~166 55 100 390 kohm
143, 150, 159 5 7 50 kohm
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AG35-QuecOpen
Hardware Design
3.4. Operating Modes
The table below briefly summarizes the various operating modes referred in the following chapters.
Table 7: Overview of Operating Modes
Mode Details
Normal
Idle
Operation
Talk/Data
Minimum
Functionality
Mode
Airplane Mode
AT+C FUN =0 can set the module into a minimum functionality mode without removing
the power supply. In this case, both RF function and (U)SIM card will be invalid.
AT+C FUN =4 can set the module into airplane mode. In this case, RF function will be
invalid.
In this mode, the current consumption of the module will be reduced to the minimal
Sleep Mode
level. During this mode, the module can still receive paging message, SMS, voice call
and TCP/UDP data from the network normally.
Power down
Mode
In this mode, the power management unit shuts down the power supply. Software is
not active. The serial interfaces are not accessible. Operating voltage (connected to
VBAT_RF and VBAT_BB) remains applied.
3.5. Power Saving
Software is active. The module has registered on the network, and it is
ready to send and receive data.
Network connection is ongoing. In this mode, the power consumption is
decided by network setting and data transfer rate.
3.5.1. Sleep Mode
AG35-Quecopen is able to reduce its current consumption to a minimum value during the sleep mode.
This chapter mainly introduces some ways to enter into or exit from sleep mode. The diagram below
illustrates the current consumption of AG35-Quecopen during sleep mode.
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NOTE
LTE Module Series
AG35-QuecOpen
Hardware Design
Figure 3: Sleep Mode Current Consumption Diagram
DRX cycle index values are broadcasted by the wireless network.
3.5.1.1. USB Application with USB Remote Wakeup Function
If the host supports USB suspend/resume and remote wakeup function, the following three preconditions
must be met to let the module enter into the sleep mode.
Use sleep & wakeup API to enable the sleep mode.
Ensure the level of pins that configured as wake-up interrupt in Table 5 are under non-wakeup
status.
The host’s USB bus, which is connected with the module’s USB interface, enters into suspended
state.
The following figure shows the connection between the module and the host.
Figure 4: Sleep Mode Application with USB Remote Wakeup
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LTE Module Series
AG35-QuecOpen
Hardware Design
Sending data to AG35-Quecopen through USB will wake up the module.
When AG35-Quecopen has URC to report, the module will send remote wake-up signals via USB
bus so as to wake up the host.
3.5.1.2. USB Application without USB Remote Wakeup Function
If the host supports USB suspend/resume, but does not support remote wake-up function, it needs to be
woken up via the module’s GPIO.
There are three preconditions to let the module enter into the sleep mode.
Use sleep & wakeup API to enable the sleep mode.
Ensure the level of pins that configured as wake-up interrupt in Table 5 are under non-wakeup
status.
The host’s USB bus, which is connected with the module’s USB interface, enters into suspended
state.
The following figure shows the connection between the module and the host.
Figure 5: Sleep Mode Application without USB Remote Wakeup
Sending data to AG35-Quecopen through USB will wake up the module.
When AG35-Quecopen has URC to report, the module’s GPIO signal can be used to wake up the
host.
3.5.1.3. USB Application without USB Suspend Function
If the host does not support USB suspend function, USB_VBUS should be connected with an external
control circuit to let the module enter into sleep mode.
Use sleep & wakeup API to enable the sleep mode.
Ensure the level of pins that configured as wake-up interrupt in Table 5 are under non-wakeup
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status.
Disconnect USB_VBUS.
The following figure shows the connection between the module and the host.
Hardware Design
Figure 6: Sleep Mode Application without Suspend Function
Switching on the power switch to supply power to USB_VBUS will wake up the module.
NOTE
Please pay attention to the level match shown in dotted line between the module and the host. Refer to
document [1] for more details about the module’s power management application.
3.5.2. Airplane Mode
When the module enters into airplane mode, the RF function does not work, and all AT commands
correlative with RF function will be inaccessible. The mode can be set via AT+CFUN=<fun> command.
The parameter <fun> indicates the module’s functionality levels, as shown below.
AT+C FUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
AT+C FUN=1: Full functionality mode (by default).
AT+C FUN=4: Airplane mode. RF function is disabled.
NOTE
The execution of AT+C FUN command will not affect GNSS function.
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3.6. Power Supply
3.6.1. Power Supply Pins
AG35-Quecopen provides six VBAT pins for connection with an external power supply. There are two
separate voltage domains for VBAT.
Four VBAT_RF pins for module’s RF part
Two VBAT_BB pins for module’s baseband part
The following table shows the details of VBAT pins and ground pins.
Table 8: VBAT and GND Pins
Pin Name Pin No. Description Min. Typ . Max. Unit
VBAT_RF 85, 86, 87, 88
VBAT_BB 155, 156
10, 13, 16, 17, 30,
31, 35, 39, 44, 45,
54, 55, 63, 64, 69,
70, 75, 76, 81~84,
89~94, 96~100,
GND
102~106, 108~112,
114, 116~118,
120~126, 128~131,
142, 148, 153, 154,
157, 158, 167, 174,
177, 178, 181, 184,
187, 191, 196~299
3.6.2. Decrease Voltage Drop
Power supply for
module’s RF part
Power supply for
module’s baseband part
3.3 3.8 4.3 V
3.3 3.8 4.3 V
Ground 0 V
The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will
never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G
network. The voltage drop will be less in 3G and 4G networks.
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Figure 7: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a
multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is
recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and
place these capacitors close to VBAT pins. The main power supply from an external application has to be
a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB
trace should be no less than 1mm, and the width of VBAT_RF trace should be no less than 2mm. In
principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to get a stable power source, it is suggested to use a power TVS ( e.g. WS4.5DPF-B,
V
=4.5V, Ppp=450W) and a zener diode with dissipation power more than 0.5W, and place them as
RWM
close to the VBAT pins as possible. The following figure shows the star structure of the power supply.
Figure 8: Star Structure of the Power Supply
3.6.3. Reference Design for Power Supply
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply for AG35-Quecopen should be able to provide sufficient current up to 2A
at least. If the voltage drop between the input and output is not too high, it is also to use an LDO to supply
power for the module. If there is a big voltage difference between the input source and the desired output
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(VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +12V/+24V input power source. The designed output
for the power supply is about 3.8V and the maximum rated current is 5A.
Figure 9: Reference Circuit of Power Supply
3.6.4. Monitor the Power Supply
AT+C BC command can be used to monitor the VBAT_BB voltage value. Please refer to document [2] for
more details.
3.7. Turn on and off Scenarios
3.7.1. Turn on Module Using PWRKEY
The following table shows the pin definition of PWRKEY.
Table 9: PWRKEY Pin Description
Pin Name Pin No. Description DC Characteristics Comment
max=2.1V
PWRKEY 2 Turn on/off the module
V
IH
V
min=1.3V
IH
V
max=0.5V
IL
The output voltage is 0.8V
because of the diode drop in
the Qualcomm chipset.
When AG35-Quecopen is in power down mode, it can be turned on by driving the PWRKEY pin to a low
level for at least 500ms. It is recommended to use an open drain/collector driver to control the PWRKEY.
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After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be released. A simple
reference circuit is illustrated in the following figure.
Figure 10: Turn on the Module Using Driving Circuit
Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike
may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
Figure 11: Turn on the Module Using Keystroke
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The turn on scenario is illustrated in the following figure.
Hardware Design
Figure 12: Timing of Turning on Module
NOTES
1. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is
no less than 30ms.
2. It is recommended to use an external OD/OC circuit to control the PWRKEY pin.
3.7.2. Turn off Module
Either of the following methods can be used to turn off the module:
Normal power down procedure: Turn off the module using the PWRKEY pin.
Normal power down procedure: Turn off the module using AT command or API interface.
3.7.2.1. Turn off Module Using the PWRKEY Pin
Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-down
procedure after PWRKEY is released. The power-down scenario is illustrated in the following figure.
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Figure 13: Timing of Turning off Module
3.7.2.2. Turn off Module Using AT Command or API Interface
It is also a safe way to use AT+QPOW D command or API interface to turn off the module, which is similar
to turning off the module via PWRKEY Pin.
Please refer to document [2] and [3] for details about the AT command and API function, respectively.
NOTES
1. In order to avoid damaging the internal flash, please do not switch off the power supply when the
module works normally. Only after the module is shut down by PWRKEY or AT command or API
interface, the power supply can be cut off.
2. When turn off module with AT command or API, please keep PWRKEY at high level after the
execution of power off command. Otherwise the module will be turned on again after successfully
turn-off.
3.7.2.3. Turn off Module Using SHDN_N
The following table shows the pin definition of SHDN_N.
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Table 10: Pin Definition of SHDN_N
Pin Name Pin No. Description DC Characteristics Comment
V
max=2.1V
IH
V
min=1.3V
IH
V
max=0.5V
IL
SHDN_N 176
Emergency shutdown
for the module
Driving the SHDN_N pin to a low level voltage and then releasing it will make the module shut down
unconditionally. The shut-down scenario is illustrated in the following figure.
Figure 14: Shut Down the Module Using Driving Circuit
Figure 15: Timing of Turning off Module via SHDN_N
NOTES
1. Pulling down SHDN_N for module shutdown is an emergency option when there are failures in
turning off the module by PWRKEY or AT command or API interface. And it is recommended to use
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an external OD circuit to control the SHDN_N pin.
2. Never pull up SHDN_N pin.
3.8. Reset the Module
The RESET_N can be used to reset the module. The module can be reset by driving the RESET_N to a
low level voltage for 150~460ms. As the RESET_N pin is sensitive to interference, the routing trace on the
interface board of the module is recommended to be as short as possible and totally ground shielded.
Table 11: RESET_N Pin Description
Pin Name Pin No. Description DC Characteristics Comment
max=2.1V
V
RESET_N 1 Reset the module
IH
V
min=1.3V
IH
V
max=0.5V
IL
Pull-up to 1.8V internally.
Active low.
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
Figure 16: Reference Circuit of RESET_N by Using Driving Circuit
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Figure 17: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated in the following figure.
Hardware Design
Figure 18: Timing of Resetting Module
NOTES
1. Use RESET_N only when turning off the module by AT command, API interface and PWRKEY pin all
failed.
2. Please assure that there is no large capacitance on PWRKEY and RESET_N pins.
3.9. (U)SIM Interface
The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards
are supported.
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Table 12: Pin Definition of (U)SIM Interface
Pin Name Pin No. I/O Description Comment
Hardware Design
USIM_VDD 26 PO Power supply for (U)SIM card
Either 1.8V or 3.0V is supported
by the module automatically.
USIM_DATA 29 IO Data signal of (U)SIM card
USIM_CLK 27 DO Clock signal of (U)SIM card
USIM_RST 28 DO Reset signal of (U)SIM card
USIM_
PRESENCE
25 DI (U)SIM card insertion detection
USIM_GND 24 Specified ground for (U)SIM card
AG35-Quecopen supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports
low level and high level detections, and is disabled by default. Please refer to document [2] about
AT+QSIMDET command.
The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
Figure 19: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector
If (U)SIM card detection function is not needed, then USIM_PRESENCE can be used for other functions.
Please refer to Tabl e 5 for more details. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card
connector is illustrated in the following figure.
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Figure 20: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector
In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please
follow the criteria below in the (U)SIM circuit design:
Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace
length as less than 200mm as possible.
Keep (U)SIM card signals away from RF and VBAT traces.
Assure the trace between the ground of the module and that of the (U)SIM card connector short and
wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same
electric potential.
To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic
capacitance not exceeding 10pF. The 0Ω resistors should be added in series between the module
and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD
protection. The 33pF capacitors are used for filtering interference of EGSM900. Please note that the
(U)SIM peripheral circuit should be close to the (U)SIM card connector.
The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
and sensitive occasions are applied, and should be placed close to the (U)SIM card connector.
NOTE
The load capacitance of (U)SIM interface will affect rise and fall time of the data exchange.
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3.10. USB Interface
AG35-Quecopen contains one integrated Universal Serial Bus (USB) interface which complies with the
USB 2.0 specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB
interface is used for AT command communication, data transmission, GNSS NMEA sentences output,
software debugging, firmware upgrade and voice over USB*. The following table shows the pin definition
of USB interface.
Table 13: Pin Description of USB Interface
Pin Name Pin No. I/O Description Comment
USB_VBUS 32 PI USB connection detection
USB_DM 33 IO USB differential data bus (-)
USB_DP 34 IO USB differential data bus (+)
Typical 5.0V
Maximum current: 1mA
Require differential
impedance of 90Ω
GND 30 Ground
For more details about the USB 2.0 specifications, please visit http://www.usb.org/home.
The USB interface is recommended to be reserved for firmware upgrade in application design. The
following figure shows a reference circuit of USB interface.
Figure 21: Reference Circuit of USB Application
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In order to ensure signal integrity of USB data lines, components R1, R2 and L1 must be placed close to
the module, and also these resistors should be placed close to each other. The extra stubs of trace must
be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 2pF.
Keep the ESD protection components as close to the USB connector as possible.
NOTES
1. The module supports USB host mode, provided that a GPIO signal is available for USB mode control.
USB mode switching is effective after module reboot.
2. “*” means under development.
3.11. UART Interfaces
The module provides six UART interfaces: UART1~UART5 and debug UART. The following are the
features of these UART interfaces.
UART1~UART4 have the same functions. They all support RTS and CTS hardware flow control, and
are used for data transmission with peripherals.
UART1~UART5 support 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,
230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps.
UART3 is multiplexed from SPI. UART4 and UART5 are multiplexed from SDIO1.
UART5 does not support hardware flow control.
The debug UART interface supports 115200bps baud rate, and is used for Linux console and log
output.
The following tables show the pin definition of the UART interfaces.
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Table 14: Pin Definition of UART1 Interface
Pin Name Pin No. I/O Description Comment
UART1_CTS 56 DO DTE clear to send 1.8V power domain
UART1_RTS 57 DI DTE request to send 1.8V power domain
UART1_RXD 58 DI Receive data 1.8V power domain
UART1_TXD 60 DO Transmit data 1.8V power domain
Table 15: Pin Definition of UART2 Interface
Function
Pin Name Pin No. I/O
Alternate
Function 1
(Default)
Alternate
Function 2
Alternate Function 3
UART2_TXD 163 DO UART_TXD_BLSP5 GPIO_8 SPI_MOSI_BLSP5
UART2_CTS 164 DO UART_CTS_BLSP5 GPIO_11 SPI_CLK_BLSP5
UART2_RXD 165 DI UART_RXD_BLSP5 GPIO_9 SPI_MISO_BLSP5
UART2_RTS 166 DI UART_RTS_BLSP5 GPIO_10 SPI_CS_N_BLSP5
Table 16: Pin Definition of UART3 Interface (Multiplexed from SPI)
Function
Pin Name
Pin
No.
SPI_MOSI 77 DO SPI_MOSI_BLSP6 GPIO_20
I/O
Alternate
Function 1
(Default)
Alternate
Function 2
Alternate
Function 3
UART_TXD_BL
SP6
Alternate
Function 4
PCM_1_SYNC
SPI_MISO 78 DI SPI_MISO_BLSP6 GPIO_21
SPI_CS_N 79 DO SPI_CS_N_BLSP6 GPIO_22
SPI_CLK 80 DO SPI_CLK_BLSP6 GPIO_23
UART_RXD_BL
SP6
UART_RTS_BL
SP6
UART_CTS_BL
SP6
PCM_1_DIN
PCM_1_DOUT
PCM_1_CLK
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Table 17: Pin Definition of UART4 Interface (Multiplexed from SDIO1)
Function
Hardware Design
Pin Name Pin No. I/O
Alternate
Function 1
(Default)
Alternate
Function 2
Alternate
Function 3
SDC1_DATA0 20 IO SDC1_DATA0 GPIO_15 UART_CTS_BLSP1
SDC1_DATA1 21 IO SDC1_DATA1 GPIO_14 UART_RTS_BLSP1
SDC1_DATA2 22 IO SDC1_DATA2 GPIO_13 UART_RXD_BLSP1
SDC1_DATA3 23 IO SDC1_DATA3 GPIO_12 UART_TXD_BLSP1
Table 18: Pin Definition of UART5 Interface (Multiplexed from SDIO1)
Function
Pin Name Pin No. I/O
Alternate
Function 1
(Default)
Alternate
Function 2
Alternate
Function 3
SDC1_CMD 18 IO SDC1_CMD GPIO_17 UART_RXD_BLSP4
SDC1_CLK 19 DO SDC1_CLK GPIO_16 UART_TXD_BLSP4
Table 19: Pin Definition of Debug UART Interface
Pin Name Pin No. I/O Description Comment
DBG_TXD 71 DO Transmit data 1.8V power domain
DBG_RXD 72 DI Receive data 1.8V power domain
NOTE
The non-default alternate functions mentioned in the above two tables take effect only after software
configuration. Please refer to corresponding chapters for details.
The logic levels of the UART interfaces are described in the table below.
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Table 20: Logic Levels of Digital I/O
Parameter Min. Max. Unit
VIL -0.3 0.6 V
VIH 1.2 2.0 V
VOL 0 0.45 V
VOH 1.35 1.8 V
The module provides 1.8V UART interfaces. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments
(please visit http://www.ti.com for more information) is recommended. The following figure shows a
reference design.
Figure 22: Reference Circuit with Translator Chip
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.
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Figure 23: Reference Circuit with Transistor Circuit
NOTE
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
3.12. Audio Interface (Optional)
AG35-Quecopen is designed with an optional built-in audio codec to enable analog audio function. The
following table shows the pin definition of analog audio interface.
Table 21: Pin Definition of Analog Audio Interface
Pin Name Pin No. I/O Description Comment
SPK2_P 132 AO Earphone analog output 2 (+)
SPK2_N 133 AO Earphone analog output 2 (-)
SPK1_P 134 AO Earphone analog output 1 (+)
SPK1_N 135 AO Earphone analog output 1 (-)
MICBIAS 136 AO
Bias voltage output for
microphone
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MIC2_N 137 AI Microphone analog input 2 (-)
MIC2_P 138 AI Microphone analog input 2 (+)
MIC1_N 139 AI Microphone analog input 1 (-)
MIC1_P 140 AI Microphone analog input 1 (+)
AGND 141 Analog ground
NOTES
1. The built-in codec uses the same signals as the module’s PCM interface (pins 65~68) for external
digital audio design. Therefore, when the built-in codec is utilized, the PCM interface cannot be used
for other purposes (that is, keep pins 65~68 unconnected).
2. The built-in audio codec (analog audio function) is optional.
3.13. PCM and I2C Interfaces
AG35-Quecopen provides one Pulse Code Modulation (PCM) digital interface for audio design. The
interface supports the following modes:
Primary mode (short frame synchronization, works as both master and slave)
Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC, and also supports 4096kHz
PCM_CLK at 16kHz PCM_SYNC.
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC.
AG35-Quecopen supports 16-bit linear data format. The following figures show the primary mode’s timing
relationship with 8kHz PCM_SYNC and 2048kHz PCM_CLK, as well as the auxiliary mode’s timing
relationship with 8kHz PCM_SYNC and 256kHz PCM_CLK.
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Figure 24: Primary Mode Timing
Figure 25: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
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Table 22: Pin Definition of PCM Interface
Pin Name Pin No. I/O Description Comment
PCM_SYNC 65 IO PCM data frame sync signal 1.8V power domain
PCM_IN 66 DI PCM data input 1.8V power domain
PCM_CLK 67 IO PCM data bit clock 1.8V power domain
PCM_OUT 68 DO PCM data output 1.8V power domain
MCLK 152 DO Output 12.288MHZ
1.8V power domain
Table 23: Pin Definition of I2C Interfaces
Pin Name Pin No. I/O Description Comment
I2C1_SDA 42 IO I2C1 serial data
I2C1_SCL 43 DO I2C1 serial clock
I2C2_SDA 73 IO I2C2 serial data
I2C2_SCL 74 DO I2C2 serial clock
Require external pull-up to
1.8V
Require external pull-up to
1.8V
Require external pull-up to
1.8V
Require external pull-up to
1.8V
NOTES
By default, I2C1 is used for codec configuration while I2C2 is not available with any codec configuration
driver.
1. When the built-in codec is used, its 8-bit address is 0x31 when reading and 0x30 when writing. In
order to avoid conflicts, please avoid using I2C1 peripherals with the same addresses.
2. When the built-in codec is used, pin 152 and pins 65~68 will not be used.
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with an external codec IC.
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Figure 26: Reference Circuit of PCM Application with Audio Codec
Hardware Design
NOTES
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. AG35-Quecopen works as a master device pertaining to I2C interface.
3.14. SDIO Interfaces
AG35-Quecopen provides two SDIO interfaces which support SD 3.0 protocol.
3.14.1. SDIO1 Interface
SDIO1 interface is used for WLAN function. More details are provided in Chapter 3.17.
3.14.2. SDIO2 Interface
SDIO2 interface supports SD card and eMMC (embedded MultiMediaCard).
The following tables show the pin definition of SDIO2 interface.
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Table 24: Pin Definition of SDIO2 Interface
Hardware Design
Pin Name
Pin
No.
I/O Description Comment
VDD_SDIO 46 PO SDIO pull-up power source
SDC2_DATA2 47 IO SDIO data signal (bit 2)
SDC2_DATA3 48 IO SDIO data signal (bit 3)
SDC2_DATA0 49 IO SDIO data signal (bit 0)
SDC2_DATA1 50 IO SDIO data signal (bit 1)
SDC2_CMD 51 IO SDIO commend single
SDC2_CLK 53 DO SDIO bus clock
DI: Insertion detection for SD
SD_INS_DET 52 DI/DO
card.
DO: Reset eMMC
1)
.
1.8V/2.85V configurable output.
SDIO pull up power source for SD
card.
Keep it open for eMMC.
SDIO signal level can be selected
according to the one supported by
SD card.
1.8V power domain for eMMC.
Please refer to SD 3.0 protocol for
more details.
NOTE
1)
SD_INS_DET for eMMC resetting function is currently not supported.
3.14.2.1. Reference Design for SD Card Application
The following figure shows a reference design of SDIO2 interface for SD card application.
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Figure 27: Reference Circuit Design for SD Card Application
Please follow the principles below in the SD card circuit design:
The voltage range of SD card power supply VDD_3V is 2.7~3.6V and a sufficient current up to 0.8A
should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used
for SDIO pull-up resistors, an externally power supply is needed for SD card.
To avoid jitter of bus, it is recommended to reserve resistors R7~R11 for pulling up SDIOs to
VDD_SDIO. The resistors are not mounted by default, and the recommended resistor value is among
10~100kohm.
In order to improve signal quality, it is recommended to add 0Ω resistors R1~R6 in series between
the module and the SD card. The bypass capacitors C1~C6 are reserved and not mounted by default.
All resistors and bypass capacitors should be placed close to the module.
In order to offer good ESD protection, it is recommended to add TVS with capacitance value less
than 2pF on SD card pins.
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50Ω (±10%).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 23mm, so the
exterior total trace length should be less than 27mm.
Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 40pF.
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3.14.2.2. Reference Design for eMMC Application
Hardware Design
Figure 28: Reference Circuit Design for eMMC Application
Please follow the principles below in eMMC circuit design:
To avoid jitter of bus, it is recommended to reserve resistors R7~R11 for pulling up SDIOs to
VDD_1.8V. Resistors R7~R10 are not mounted by default, and the recommended resistor value is
10~100kΩ.
In order to improve signal quality, it is recommended to add 0Ω resistors R1~R6 in series between
the module and eMMC. The bypass capacitors C1~C7 are reserved and not mounted by default. All
resistors and bypass capacitors should be placed close to the module.
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50Ω (±10%).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 23mm, so the
exterior total trace length should be less than 27mm.
Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 40pF.
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3.15. SPI Interfaces
AG35-Quecopen provides three SPI interfaces (two of them multiplexed from UARTs) supporting only
master mode. The maximum clock frequency of SPI1 and SPI3 is up to 50MHz, while that of SPI2 is
38MHz.
The following tables show the pin definition of SPI interfaces.
Table 25: Pin Definition of SPI1 Interface
Pin Name Pin No. I/O Description Comment
SPI_MOSI 77 DO SPI master out slave in 1.8V power domain. If unused, keep it open.
SPI_MISO 78 DI SPI master in slave out 1.8V power domain. If unused, keep it open.
SPI_CS_N 79 DO SPI chip selection 1.8V power domain. If unused, keep it open.
SPI_CLK 80 DO SPI serial clock 1.8V power domain. If unused, keep it open.
Table 26: Pin Definition of SPI2 Interface (Multiplexed from UART1)
Function
Pin Name
Pin
No.
I/O
Alternate
Function 1 (Default)
Alternate
Function 2
Alternate
Function 3
UART1_CTS 56 DO UART_CTS_BLSP3 GPIO_3 SPI_CLK_BLSP3
UART1_RTS 57 DI UART_RTS_BLSP3 GPIO_2 SPI_CS_N_BLSP3
UART1_RXD 58 DI UART_RXD_BLSP3 GPIO_1 SPI_MISO_BLSP3
UART1_TXD 60 DO UART_TXD_BLSP3 GPIO_0 SPI_MOSI_BLSP3
Table 27: Pin Definition of SPI3 Interface (Multiplexed from UART2)
Function
Pin Name
Pin
No.
I/O
Alternate
Function 1 (Default)
Alternate
Function 2
Alternate
Function 3
UART2_TXD 163 DO UART_TXD_BLSP5 GPIO_8 SPI_MOSI_BLSP5
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UART2_CTS 164 DO UART_CTS_BLSP5 GPIO_11 SPI_CLK_BLSP5
UART2_RXD 165 DI UART_RXD_BLSP5 GPIO_9 SPI_MISO_BLSP5
UART2_RTS 166 DI UART_RTS_BLSP5 GPIO_10 SPI_CS_N_BLSP5
NOTE
For more details about non-default alternate functions for the pins mentioned in the above table, please
refer to corresponding chapters.
The following figure shows the timing relationship of SPI interfaces. The related parameters of SPI timing
are shown in the table below.
Figure 29: SPI Timing
Table 28: Parameters of SPI Interface Timing
Parameter Description Min Typical Max Unit
T SPI clock period 20.0 - - ns
t(ch) SPI clock high-level time 9.0 - - ns
t(cl) SPI clock low-level time 9.0 - - ns
t(mov) SPI master data output valid time -5.0 - 5.0 ns
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t(mis) SPI master data input setup time 5.0 - - ns
t(mih) SPI master data input hold time 1.0 - - ns
NOTE
The module provides 1.8V SPI interfaces. A level translator should be used between the module and the
host if customers’ application is equipped with a 3.3V processor or device interface.
3.16. SGMII Interface (Optional)
AG35-Quecopen includes an integrated Ethernet MAC with an SGMII interface and two management
interfaces. Key features of the SGMII interface are shown below:
IEEE802.3 compliant
Half/full duplex for 10/100/1000Mbps
Support VLAN tagging
Support IEEE1588 and Precision Time Protocol (PTP)
Can be used to connect to external Ethernet PHY like DP83TC811S-Q1, or to an external switch
Management interfaces support dual power domains: 1.8V and 2.85V.
The following table shows the pin definition of SGMII interface.
Table 29: Pin Definition of SGMII Interface
Pin Name Pin No. I/O Description Comment
MDIO Interface
EPHY_RST_N 6 DO Ethernet PHY reset 1.8V/2.85V power domain
EPHY_INT_N 9 DI Ethernet PHY interrupt 1.8V power domain
SGMII_MDATA 8 IO
SGMII_MCLK 7 DO
VDD_MDIO 4 PO
SGMII MDIO (Management
Data Input/Output) data
SGMII MDIO (Management
Data Input/Output) clock
SGMII MDIO pull-up power
source
1.8V/2.85V power domain
1.8V/2.85V power domain
1.8V/2.85V power domain.
External pull-up power source
for SGMII MDIO pins.
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SGMII Signal Part
Hardware Design
SGMII_TX_M 15 AO SGMII transmission (-)
SGMII_TX_P 14 AO SGMII transmission (+)
Connect with a 0.1uF capacitor,
close to the PHY side.
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_RX_P 12 AI SGMII receiving (+)
SGMII_RX_M 11 AI SGMII receiving (-)
The following figure shows the simplified block diagram for Ethernet application.
Figure 30: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY application.
Module
R1
R2
EPHY_INT_N
EPHY_RST_N
Cont rol
MDIO_DATA
MDIO_CLK
SGMII_RX_P
SGMII_RX_M
SGMII Data
SGMII_TX_P
SGMII_TX_M
10K
VDD_EXT
VDD_MDIO
C3
C4
INT
RSTN
MDIO
MDC
RX_P
RX_M
TX_P
TX_M
PHY
Close to PHY
Figure 31: Reference Circuit of SGMII Interface with PHY Application
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In order to enhance the reliability and availability of customers’ application, please follow the criteria below
in the Ethernet PHY circuit design:
Keep SGMII data and control signals away from RF and VBAT traces.
Keep the maximum trace length less than 10 inches and keep the intra-pair length matching less
than 20 mils.
The differential impedance of SGMII data trace is 100Ω±10%.
To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
be equal to or larger than 40 mils.
The resistor R2 should be placed near the PHY, and its value varies according to the selection of
PHY.
3.17. Wireless Connectivity Interfaces
AG35-Quecopen provides a low-power SDIO 3.0 interface (SDIO1 interface) for WLAN function and
UART & PCM interfaces for BT function*.
The following table shows the pin definition of wireless connectivity interfaces.
Table 30: Pin Definition of Wireless Connectivity Interfaces
Description
Pin Name
Pin
No.
I/O
Alternate
Function 1
(Default)
Alternate
Function 2
Alternate
Function 3
WLAN Power Supply
PM_ENABLE 5 DO PM_ENABLE PMU_GPIO_3
WLAN Interface
SDC1_CMD 18 IO SDC1_CMD GPIO_17
SDC1_CLK 19 DO SDC1_CLK GPIO_16
SDC1_DATA0 20 IO SDC1_DATA0 GPIO_15
SDC1_DATA1 21 IO SDC1_DATA1 GPIO_14
Alternate
Function 4
SDC1_DATA2 22 IO SDC1_DATA2 GPIO_13
SDC1_DATA3 23 IO SDC1_DATA3 GPIO_12
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WLAN_EN 149 DO WLAN_EN GPIO_54
WLAN_WAKE 1) 160 DI WLAN_WAKE
WLAN_SLP_
CLK
169 DO
WLAN_SLP_
CLK
Coexistence Interface
COEX_UART_
TX
COEX_UART_
RX/
USB_BOOT
145 DO
146 DI
COEX_UART_
TX
COEX_UART_
RX
BT Interface*
BT_EN* 3 DO BT_EN*
UART2_TXD 163 DO
UART2_CTS 164 DO
UART2_RXD 165 DI
UART_TXD_
BLSP5
UART_CTS_
BLSP5
UART_RXD_
BLSP5
GPIO_8
GPIO_11
GPIO_9
SPI_MOSI_
BLSP5
SPI_CLK_
BLSP5
SPI_MISO_
BLSP5
UART2_RTS 166 DI
SPI_MOSI 77 DO
SPI_MISO 78 DI
SPI_CS_N 79 DO
SPI_CLK 80 DO
UART_RTS_
BLSP5
SPI_MOSI_
BLSP6
SPI_MISO_
BLSP6
SPI_CS_N_
BLSP6
SPI_CLK_
BLSP6
GPIO_10
GPIO_20
GPIO_21
GPIO_22
GPIO_23
SPI_CS_N_
BLSP5
UART_TXD_
BLSP6
UART_RXD_
BLSP6
UART_RTS_
BLSP6
UART_CTS_
BLSP6
PCM_1A_
SYNC
PCM_1A _IN
PCM_1A_OUT
PCM_1A _CLK
NOTES
1. For more details about non-default alternate functions for the pins mentioned in the above table,
please refer to corresponding chapters.
2. When WLAN or BT function is used, the coexistence interfacemust be used simultaneously.
1)
3.
The internal pull-up and pull-down resistors of pin 160 (WLAN_WAKE) range between 5kΩ and 50
kΩ, and the typical value is 7kΩ.
4. “*” means under development.
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The following figure shows a reference design for the connection between wireless connectivity interfaces
and Quectel AF20 module.
Figure 32: Reference Circuit for Connection with AF20 Module
NOTES
1. AF20 module can only be used as a slave device.
2. When BT function is enabled on AG35-Quecopen module, PCM_SYNC and PCM_CLK pins are only
used to output signals.
3. For more information about wireless connectivity interfaces application, please refer to document
[7].
4. “*” means under development.
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3.17.1. WLAN Interface
AG35-Quecopen provides SDIO1 interface and a control interface for WLAN design.
The WLAN interface (SDIO1 interface) supports the following modes:
Single data rate (SDR) mode (up to 208MHz)
Double data rate (DDR) mode (up to 50MHz)
As SDIO signals are very high-speed signals, in order to ensure the SDIO1 interface design corresponds
with the SDIO 3.0 specification, please comply with the following principles:
It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50Ω (±10%).
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total length of SDIO signal traces inside
AG35-Quecopen module is 12mm and that inside AF20 is 10mm, so the exterior total trace length
should be less than 28mm.
Keep termination resistors within 15~24Ω on clock lines near the module and keep the route distance
from the module clock pins to termination resistors less than 5mm.
Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less
than 40pF.
3.17.2. BT Interface*
More information about BT interface will be added in the future version of this document.
NOTE
“*” means under development.
3.18. ADC Interfaces
The module provides three analog-to-digital converter (ADC) interfaces. The voltage value on ADC pins
can be read via AT+QADC=<port> command, through setting <port> into 0, 1 or 2. For more details
about the AT command, please refer to document [2].
AT+QADC=0: read the voltage value on ADC0
AT+QADC=1: read the voltage value on ADC1
AT+QADC=2: read the voltage value on ADC2
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In order to improve the accuracy of ADC, the traces of ADC interfaces should be surrounded by ground.
Table 31: Pin Definition of ADC Interfaces
Pin Name Pin No. Description
ADC2 172 General purpose analog to digital converter interface
ADC1 175 General purpose analog to digital converter interface
ADC0 173 General purpose analog to digital converter interface
The following table describes the characteristic of ADC interfaces.
Table 32: Characteristic of ADC Interfaces
Parameter Min. Typ. Max. Unit
ADC2 Voltage Range 0.1 1.7 V
ADC1 Voltage Range 0.3 VBAT_BB V
ADC0 Voltage Range 0.3 VBAT_BB V
ADC Resolution 15 bits
ADC Sample Rate 2.4 MHz
NOTES
1. The input voltage for each ADC interface must not exceed its corresponding voltage range.
2. It is prohibited to supply any voltage to ADC pins when VBAT is removed.
3. It is recommended to use resistor divider circuit for ADC application.
3.19. Network Status Indication
AG35-Quecopen provides one network indication pin: NET_STATUS. The pin is used to drive a network
status indication LED.
The following tables describe the pin definition and logic level changes of NET_STATUS in different
network status.
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Table 33: Pin Definition of the Network Status Indicator (NET_STATUS)
Pin Name Pin No. I/O Description Comment
NET_STATUS 170 DO
Indicate the module’s network activity
status.
1.8V power domain
Table 34: Working State of the Network Status Indicator (NET_STATUS)
Pin Name Indicator Status (Logic Level Changes) Network Status
Flicker slowly (200ms High/1800ms Low) Network searching
Flicker slowly (1800ms High/200ms Low) Idle
NET_STATUS
Flicker quickly (125ms High/125ms Low) Data transfer is ongoing
Always High Voice calling
A reference circuit is shown in the following figure.
Figure 33: Reference Circuit of the Network Status Indicator
3.20. STATUS
The STATUS pin is an open drain output for indicating the module’s operation status. It can be connected
to a GPIO of DTE with a pulled up resistor, or as LED indication circuit as shown below. When the module
is turned on normally, the STATUS will present a low level state. Otherwise, the STATUS will present
high-impedance state.
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Table 35: Pin Definition of STATUS
Pin Name Pin No. I/O Description Comment
STATUS 171 OD Indicate the module’s operation status Require external pull-up
The following figure shows different circuit designs of STATUS, and customers can choose either one
according to specific application demands.
Figure 34: Reference Circuits of STATUS
NOTES
1. In sleep state, STATUS will still output a low voltage to drive the LED, causing an extra current
consumption on VBAT. So it is recommended to replace VBAT with an external controllable power
supply, and use it to switch off the power source during sleep state so as to reduce power
consumption.
2. It is not recommended to use level translator circuit for STATUS.
3.21. USB_BOOT Interface
AG35-Quecopen provides a USB_BOOT pin which is multiplexed with COEX_UART_RX. Developers
can pull up the USB_BOOT to VDD_EXT before powering on the module, thus the module will enter into
emergency download mode when powered on. In this mode, the module supports firmware upgrade over
USB interface.
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Table 36: Pin Definition of USB_BOOT Interface
Pin Name Pin No. I/O Description Comment
Hardware Design
COEX_
UART_RX/
USB_BOOT
146 DI
Force the module to enter into
emergency download mode
The following figure shows a reference circuit of USB_BOOT interface.
1.8V power domain.
Active high.
If unused, keep it open.
Figure 35: Reference Circuit of USB_BOOT Interface
3.22. RTC
AG35-Quecopen has a real time clock within the PMIC, but has no dedicated RTC power supply pin.
The RTC is powered by VBAT_BB. If VBAT_BB is removed, the RTC will not be maintained.
NOTE
If RTC needs to be maintained, then VBAT_BB must be powered all the time.
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4 GNSS Receiver
4.1. General Description
AG35-Quecopen includes a fully integrated global navigation satellite system solution that supports
Gen8C-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS).
AG35-Quecopen supports standard NMEA-0183 protocol, and outputs NMEA sentences at 10Hz data
update rate via USB interface by default.
By default, GNSS engine of the module is switched off. It has to be switched on via AT command. For
more details about GNSS engine technology and configurations, please refer to document [5].
4.2. GNSS Performance
The following table shows GNSS performance of AG35-Quecopen.
Table 37: AG35-CE GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous -146 dBm
Sensitivity
(GNSS)
TTFF
(GNSS)
Reacquisition Autonomous -158 dBm
Tracking Autonomous -162 dBm
Cold start
@open sky
Warm start
@open sky
Autonomous 35 s
XTRA enabled 18 s
Autonomous 26 s
XTRA enabled 2.2 s
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Autonomous 2.5 s
XTRA enabled 1.8 s
Autonomous
@open sky
< 2.5 m
Accuracy
(GNSS)
Hot start
@open sky
CEP-50
Table 38: AG35-E GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous TBD dBm
Sensitivity
(GNSS)
Reacquisition Autonomous TBD dBm
Tracking Autonomous TBD dBm
Cold start
@open sky
Autonomous TBD s
XTRA enabled TBD s
TTFF
(GNSS)
Accuracy
(GNSS)
Warm start
@open sky
Hot start
@open sky
CEP-50
Autonomous TBD s
XTRA enabled TBD s
Autonomous TBD s
XTRA enabled TBD s
Autonomous
@open sky
TBD m
Table 39: AG35-NA GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous -146.5 dBm
Sensitivity
(GNSS)
Reacquisition Autonomous -158 dBm
Tracking Autonomous -163 dBm
Autonomous 35 s
XTRA enabled 18 s
TTFF
(GNSS)
Cold start
@open sky
Warm start Autonomous 26 s
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Accuracy
(GNSS)
@open sky
Hot start
@open sky
CEP-50
XTRA enabled 2.2 s
Autonomous 2.5 s
XTRA enabled 1.8 s
Autonomous
@open sky
< 2.5 m
Table 40: AG35-LA GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous TBD dBm
Sensitivity
(GNSS)
Reacquisition Autonomous TBD dBm
Tracking Autonomous TBD dBm
Cold start
@open sky
Autonomous TBD s
XTRA enabled TBD s
TTFF
(GNSS)
Accuracy
(GNSS)
Warm start
@open sky
Hot start
@open sky
CEP-50
Autonomous TBD s
XTRA enabled TBD s
Autonomous TBD s
XTRA enabled TBD s
Autonomous
@open sky
TBD m
Table 41: AG35-J GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous -146 dBm
Sensitivity
(GNSS)
Reacquisition Autonomous -158 dBm
Tracking Autonomous -162 dBm
TTFF
(GNSS)
Cold start
@open sky
Autonomous 35 s
XTRA enabled 18 s
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Autonomous 26 s
XTRA enabled 2.2 s
Autonomous 2.5 s
XTRA enabled 1.8 s
Autonomous
@open sky
< 2.5 m
Accuracy
(GNSS)
Warm start
@open sky
Hot start
@open sky
CEP-50
NOTES
1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep
on positioning for 3 minutes.
2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can
fix position again within 3 minutes after loss of lock.
3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes
position within 3 minutes after executing cold start command.
4.3. Layout Guidelines
The following layout guidelines should be taken into account in application design.
Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna.
Digital circuits such as (U)SIM card, USB interface, camera module, display connector and eMMC
should be kept away from the antennas.
Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar
isolation and protection.
Control the characteristic impedance for ANT_GNSS trace as 50Ω.
Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information.
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5 Antenna Interfaces
AG35-Quecopen include a main antenna interface, an Rx-diversity antenna interface which is used to
resist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna
interface. The antenna ports have an impedance of 50Ω.
5.1. Main/Rx-diversity Antenna Interface
5.1.1. Pin Definition
The pin definition of main antenna and Rx-diversity antenna interfaces are shown below.
Table 42: Pin Definition of the RF Antenna Interfaces
Pin Name Pin No. I/O Description Comment
ANT_MAIN 107 IO Main antenna interface 50Ω impedance
ANT_DIV 127 AI Receive diversity antenna interface 50Ω impedance
5.1.2. Operating Frequency
Table 43: AG35-CE Operating Frequencies
3GPP Band Transmit Receive Unit
EGSM900 880~915 925~960 MHz
DCS1800 1710~1785 1805~1880 MHz
WCDMA B1 1920~1980 2110~2170 MHz
WCDMA B8 880~915 925~960 MHz
EVDO/CDMA BC0 1) 824~849 869~894 MHz
TD-SCDMA B34 2010~2025 2010~2025 MHz
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TD-SCDMA B39 1880~1920 1880~1920 MHz
LTE-FDD B1 1920~1980 2110~2170 MHz
LTE-FDD B3 1710~1785 1805~1880 MHz
LTE-FDD B5 824~849 869~894 MHz
LTE-FDD B8 880~915 925~960 MHz
LTE-TDD B34 2010~2025 2010~2025 MHz
LTE-TDD B38 2570~2620 2570~2620 MHz
LTE-TDD B39 1880~1920 1880~1920 MHz
LTE-TDD B40 2300~2400 2300~2400 MHz
LTE-TDD B41 2555~2655 2555~2655 MHz
Table 44: AG35-E Operating Frequencies
3GPP Band Transmit Receive Unit
EGSM900 880~915 925~960 MHz
DCS1800 1710~1785 1805~1880 MHz
WCDMA B1 1920~1980 2110~2170 MHz
WCDMA B5 824~849 869~894 MHz
WCDMA B8 880~915 925~960 MHz
LTE-FDD B1 1920~1980 2110~2170 MHz
LTE-FDD B3 1710~1785 1805~1880 MHz
LTE-FDD B5 824~849 869~894 MHz
LTE-FDD B7 2500~2570 2620~2690 MHz
LTE-FDD B8 880~915 925~960 MHz
LTE-FDD B20 832~862 791~821 MHz
LTE FDD B28 703~748 758~803 MHz
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LTE-TDD B38 2570~2620 2570~2620 MHz
LTE-TDD B40 2300~2400 2300~2400 MHz
Table 45: AG35-NA Operating Frequencies
3GPP Band Transmit Receive Unit
GSM850 824~849 869~894 MHz
PCS1900 1850~1910 1930~1990 MHz
WCDMA B2 1850~1910 1930~1990 MHz
WCDMA B4 1710~1755 2110~2155 MHz
WCDMA B5 824~849 869~894 MHz
LTE-FDD B2 1850~1910 1930~1990 MHz
LTE-FDD B4 1710~1755 2110~2155 MHz
LTE-FDD B5 824~849 869~894 MHz
LTE-FDD B7 2500~2570 2620~2690 MHz
LTE-FDD B12 699~716 729~746 MHz
LTE-FDD B13 777~787 746~756 MHz
LTE-FDD B17 704~716 734~746 MHz
Table 46: AG35-LA Operating Frequencies
3GPP Band Transmit Receive Unit
GSM850 824~849 869~894 MHz
EGSM900 880~915 925~960 MHz
DCS1800 1710~1785 1805~1880 MHz
PCS1900 1850~1910 1930~1990 MHz
WCDMA B1 1920~1980 2110~2170 MHz
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WCDMA B2 1850~1910 1930~1990 MHz
WCDMA B3 1710~1785 1805~1880 MHz
WCDMA B4 1710~1755 2110~2155 MHz
WCDMA B5 824~849 869~894 MHz
WCDMA B8 880~915 925~960 MHz
LTE-FDD B1 1920~1980 2110~2170 MHz
LTE-FDD B2 1850~1910 1930~1990 MHz
LTE-FDD B3 1710~1785 1805~1880 MHz
LTE-FDD B4 1710~1755 2110~2155 MHz
LTE-FDD B5 824~849 869~894 MHz
LTE-FDD B7 2500~2570 2620~2690 MHz
LTE-FDD B8 880~915 925~960 MHz
LTE FDD B28 703~748 758~803 MHz
Table 47: AG35-J Operating Frequencies
3GPP Band Transmit Receive Unit
WCDMA B1 1920~1980 2110~2170 MHz
WCDMA B3 1710~1785 1805~1880 MHz
WCDMA B5 824~849 869~894 MHz
WCDMA B6 830~840 875~885 MHz
WCDMA B8 880~915 925~960 MHz
WCDMA B19 830~845 875~890 MHz
LTE-FDD B1 1920~1980 2110~2170 MHz
LTE-FDD B3 1710~1785 1805~1880 MHz
LTE-FDD B5 824~849 869~894 MHz
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LTE-FDD B8 880~915 925~960 MHz
LTE-FDD B9 1749.9~1784.8 1844.9~1879.8 MHz
LTE-FDD B19 830~845 875~890 MHz
LTE-FDD B21 1747.9~1462.8 1495.9~1510.8 MHz
LTE FDD B28 703~748 758~803 MHz
LTE TDD B41 2535~2655 2535~2655 MHz
NOTE
1)
EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional.
5.1.3. Reference Design of RF Antenna Interface
A reference design of main and Rx-diversity antenna interfaces is shown as below. It is recommended to
reserve a π-type matching circuit for better RF performance, and the π-type matching components
(R1/C1/C2 and R2/C3/C4) should be placed as close to the antennas as possible. The capacitors are not
mounted by default.
Figure 36: Reference Circuit of RF Antenna Interfaces
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1. Keep a proper distance between the main antenna and the Rx-diversity antenna to improve receiving
sensitivity.
2. ANT_DIV function is enabled by default. AT+QCFG="diversity",0 command can be used to disable
receive diversity. Please refer to document [2] for details.
5.1.4. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
height from the reference ground to the signal layer (H), and the clearance between RF traces and
grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic
impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB
structures.
Figure 37: Microstrip Design on a 2-layer PCB
Figure 38: Coplanar Waveguide Design on a 2-layer PCB
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Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to
50Ω.
The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
The distance between the RF pins and the RF connector should be as short as possible, and all the
right-angle traces should be changed to curved ones.
There should be clearance under the signal pin of the antenna connector or solder joint.
The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times as wide as RF signal traces (2*W).
For more details about RF layout, please refer to document [6].
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5.2. GNSS Antenna Interface
The following tables show the pin definition and frequency specification of GNSS antenna interface.
Table 48: Pin Definition of GNSS Antenna Interface
Pin Name Pin No. I/O Description Comment
ANT_GNSS 119 AI GNSS antenna interface 50Ω impedance
Table 49: GNSS Frequency
Typ e Frequency Unit
GPS 1575.42±1.023 MHz
GLONASS 1597.5~1605.8 MHz
Galileo 1575.42±2.046 MHz
BeiDou 1561.098±2.046 MHz
QZSS 1575.42 MHz
A reference design of GNSS antenna is shown as below.
Figure 41: Reference Circuit of GNSS Antenna
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NOTES
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1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
5.3. Antenna Installation
5.3.1. Antenna Requirements
The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna.
Table 50: Antenna Requirements
Typ e Requirements
Frequency range: 1559MHz~1609MHz
Polarization: RHCP or linear
VSWR: < 2 (Typ.)
GNSS 1)
Passive antenna gain: > 0dBi
Active antenna noise figure: < 1.5dB
Active antenna gain: > 0dBi
Active antenna embedded LNA gain: < 17dB
VSWR: ≤ 2
Efficiency: > 30%
Max input power: 50W
Input impedance: 50Ω
Cable insertion loss: < 1dB
(GSM850/EGSM900, WCDMA B5/B6/B8/B19,
GSM/EVDO/CDMA/UMTS/
TD-SCDMA/LTE
LTE-FDD B5/B8/B12/B13/B17/B19/B20/B28,
EVDO/CDMA BC0)
Cable insertion loss: < 1.5dB
(DCS1800/PCS900, WCDMA B1/B2/B3/B4,
LTE-FDD B1/B2/B3/B4/B9/B11/B21, LTE-TDD B34/B39,
TD-SCDMA B34/B39)
Cable insertion loss: < 2dB
(LTE-FDD B7, LTE-TDD B38/B40/B41)
NOTE
1)
It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of
active antenna may generate harmonics which will affect the GNSS performance.
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5.3.2. Recommended RF Connector for Antenna Installation
If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector
provided by HIROSE.
Figure 42: Dimensions of the U.FL-R-SMT Connector (Unit: mm)
U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT.
Figure 43: Mechanicals of U.FL-LP Connectors
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The following figure describes the space factor of mated connector.
Hardware Design
Figure 44: Space Factor of Mated Connector (Unit: mm)
For more details, please visit https://www.hirose.com.
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6 Electrical, Reliability and Radio
Characteristics
6.1. Absolute Maximum Ratings
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.
Table 51: Absolute Maximum Ratings
Parameter Min. Max. Unit
VBAT_RF/VBAT_BB -0.3 4.7 V
USB_VBUS -0.3 5.5 V
Peak Current of VBAT_BB 0 0.8 A
Peak Current of VBAT_RF 0 1.8 A
Voltage at Digital Pins -0.3 2.3 V
Voltage at ADC0 0.3 VBAT_BB V
Voltage at ADC1 0.3 VBAT_BB V
Voltage at ADC2 0.1 1.7 V
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6.2. Power Supply Ratings
Table 52: Power Supply Ratings
Parameter Description Conditions Min. Typ. Max. Unit
The actual input voltages
VBAT_BB and
VBAT_RF
VBAT
must stay between the
minimum and maximum
values.
3.3 3.8 4.3 V
I
VBAT
USB_VBUS
Voltage drop during
burst transmission
Peak supply current
(during transmission
slot)
USB connection
detection
Maximum power control
level on EGSM900.
Maximum power control
level on EGSM900.
400 mV
1.8 2.0 A
3.0 5.0 5.25 V
6.3. Operation and Storage Temperatures
Table 53: Operation and Storage Temperatures
Parameter Min. Typ . Max. Unit
Operation Temperature Range 1) -35 +25 +75 ºC
Extended Temperature Range 2) -40 +85 ºC
eCall Temperature Range 3) -40 +90 ºC
Storage Temperature Range -40 +95 ºC
NOTES
1. 1) Within operation temperature range, the module is 3GPP compliant, and emergency call can be
dialed out with a maximum power and data rate.
2. 2) Within extended temperature range, the module remains fully functional and retains the ability to
establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no
unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio
network. Only one or more parameters like P
might reduce in their value and exceed the specified
out
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tolerances. When the temperature returns to normal operation temperature levels, the module will
meet 3GPP specifications again.
3. 3) Within eCall temperature range, the emergency call function must be functional until the module is
broken. When the ambient temperature is between 75°C and 90°C and the module temperature has
reached the threshold value, the module will trigger protective measures (such as reduce power,
decrease throughput, unregister the device, etc.) to ensure the full function of emergency call.
6.4. Current Consumption
Table 54: AG35-CE Current Consumption (25°C, 3.8V Power Supply)
Parameter Description Conditions Typ . Unit
I
VBAT
OFF state
Sleep state
Power down 20 uA
AT+C FUN =0 (USB disconnected)
GSM DRX=2 (USB disconnected) 2.3 mA
GSM DRX=9 (USB disconnected) 1.8 mA
WCDMA PF=128 (USB disconnected) 1.8 mA
WCDMA PF=512 (USB disconnected) 1.5 mA
LTE-FDD PF=128 (USB disconnected) 2.1 mA
LTE-FDD PF=256 (USB disconnected) 1.7 mA
LTE-TDD PF=128 (USB disconnected) 2.2 mA
LTE-TDD PF=256 (USB disconnected) 1.7 mA
GSM DRX=5 (USB connected) 20 mA
1.2 mA
GSM DRX=5 (USB disconnected) 34.0 mA
WCDMA PF=64 (USB connected) 35.0 mA
Idle state
WCDMA PF=64 (USB disconnected) 22.0 mA
LTE-FDD PF=64 (USB connected) 35.0 mA
LTE-FDD PF=64 (USB disconnected) 22.0 mA
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LTE-TDD PF=64 (USB connected) 35.0 mA
LTE-TDD PF=64 (USB disconnected) 23.0 mA
EGSM900 4DL/1UL @32.66dBm 249.2 mA
EGSM900 3DL/2UL @32.51dBm 421.6 mA
EGSM900 2DL/3UL @30.65dBm 495.0 mA
GPRS data transfer
(GNSS OFF)
EDGE data transfer
(GNSS OFF)
EGSM900 1DL/4UL @29.37dBm 568.9 mA
DCS1800 4DL/1UL @29.21dBm 174.1 mA
DCS1800 3DL/2UL @29.03dBm 276.1 mA
DCS1800 2DL/3UL @28.95dBm 374.9 mA
DCS1800 1DL/4UL @28.81dBm 476.8 mA
EGSM900 4DL/1UL @27.02dBm 155.2 mA
EGSM900 3DL/2UL @27.05dBm 256.9 mA
EGSM900 2DL/3UL @26.82dBm 350.0 mA
EGSM900 1DL/4UL @26.69dBm 446.0 mA
DCS1800 4DL/1UL @25.21dBm 146.0 mA
DCS1800 3DL/2UL @25.11dBm 226.7 mA
DCS1800 2DL/3UL @25.01dBm 312.0 mA
DCS1800 1DL/4UL @24.84dBm 401.6 mA
EVDO/CDMA data
transfer (GNSS OFF)
TD-SCDMA data
transfer (GNSS OFF)
1)
BC0
@23.71dBm 609.06 mA
B34 @22.73dBm 131.51 mA
B39 @22.94dBm 132.77 mA
WCDMA B1 HSDPA @21.95dBm 540.18 mA
WCDMA data transfer
(GNSS OFF)
WCDMA B8 HSDPA @22.32dBm 481.27 mA
WCDMA B1 HSUPA @21.52dBm 532.06 mA
WCDMA B8 HSUPA @21.49dBm 466.51 mA
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LTE-FDD B1 @23.01dBm 698.07 mA
LTE-FDD B3 @23.24dBm 708.78 mA
LTE-FDD B5 @23.28dBm 629.16 mA
LTE-FDD B8 @23.27dBm 597.21 mA
LTE data transfer
(GNSS OFF)
GSM voice call
LTE-TDD B34 @22.73dBm 334.99 mA
LTE-TDD B38 @22.85dBm 430.39 mA
LTE-TDD B39 @22.97dBm 330.62 mA
LTE-TDD B40 @22.94dBm 405.78 mA
LTE-TDD B41 @22.91dBm 456.63 mA
EGSM900, PCL=5 @32.3dBm 230.4 mA
EGSM900, PCL=12 @19.3dBm 103.2 mA
EGSM900, PCL=19 @5.3dBm 73.0 mA
DCS1800, PCL=0 @29.26dBm 155.5 mA
DCS1800, PCL=7 @16.52dBm 117.3 mA
DCS1800, PCL=15 @0.3dBm 97 mA
EVDO/CDMA voice
call
BC0
BC0
@23.78dBm 592.7 mA
1)
@-60.55dBm 112.7 mA
1)
WCDMA B1 @23.15dBm 502.2 mA
WCDMA voice call
WCDMA B8 @23.24dBm 525.6 mA
Table 55: AG35-E Current Consumption
Parameter Description Conditions Typ . Unit
I
VBAT
OFF state
Sleep state
Power down 20 uA
AT+C FUN =0 (USB disconnected)
GSM DRX=2 (USB disconnected) 2.3 mA
1.2 mA
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