Table Index ............................................................................................................................................... 5
Figure Index .............................................................................................................................................. 6
RoHS All hardware components are fully compliant with EU RoHS directive
NOTES
1)
1.
Within operation temperature range, the module is 3GPP compliant.
2)
2.
Within extended temperature range, the module remains the ability to establish and maintain an
SMS*, data transmission, etc. There is no unrecoverable malfunction. There are also no effects on
radio spectrum and no harm to radio network. Only one or more parameters like P
might reduce in
out
their value and exceed the specified tolerances. When the temperature returns to normal operation
temperature levels, the module will meet 3GPP specifications again.
3. "*" means under development.
2.3. Functional Diagram
The following figure shows a block diagram of BC66 and illustrates the major functional parts.
Radio frequency
Baseband
Power management
Peripheral interfaces
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Figure 1: Functional Diagram
NOTE
“*” means under development.
2.4. Development Board
Quectel provides a complete set of development tools to facilitate the use and testing of BC66 module.
The development tool kit includes the TE-B board, USB cable, antenna and other peripherals. For more
details, please refer to document [1].
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3Application Interfaces
3.1. General Description
BC66 is equipped with a total of 58 pins, including 44 LCC pins and 14 LGA pins. The subsequent
chapters will provide detailed descriptions of the following functions/pins/interfaces:
PSM
Power Supply
RESET
PWRKEY
UART Interfaces
SPI Interface
USIM Interface
ADC Interface
Network Status Indication*
Antenna Interface
NOTE
“*” means under development.
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3.2. Pin Assignment
Figure 2: Pin Assignment
NOTES
1. Keep all reserved pins unconnected.
2. “*” means under development.
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3.3. Pin Description
Table 3: I/O Parameters Definition
Type Description
IO Bidirectional
DI Digital input
DO Digital output
PI Power input
PO Power output
AI Analog input
AO Analog output
Table 4: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
VBAT_BB 42 PI
VBAT_RF 43 PI
Power supply for
the module’s
baseband part
Power supply for
the module’s RF
part
Vmax=3.63V
Vmin=2.1V
Vnorm=3.3V
Vmax=3.63V
Vmin=2.1V
Vnorm=3.3V
No voltage output in
PSM mode.
It is intended to supply
VDD_
EXT
24 PO
1.8V output
power supply
Vnorm=1.8V
power for the module’s
pull-up circuits, and is
thus not recommended
to be used as the
power supply for
external circuits.
1, 27, 34,
GND
36, 37, 40,
GND
41
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Power Key Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
PWRKEY 7 DI
Pull down
PWRKEY to turn
on the module
V
max=0.3*VBAT
IL
V
min=0.7*VBAT
IH
Reset Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
RESET 15 DI Reset the moduleActive low.
PSM_EINT Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
Dedicated
external interrupt
PSM_EINT 19 DI
pin.
Used to wake up
the module from
PSM.
Network Status Indication
Pin Name Pin No. I/O Description DC Characteristics Comment
NETLIGHT* 16 DO
Network status
indication
ADC Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
General purpose
ADC0* 9 AI
analog to digital
converter
Voltage range:
0V~1.4V
interface
Main UART Port
Pin Name Pin No. I/O Description DC Characteristics Comment
RXD 18 DI Receive data
1.8V power domain.
TXD 17 DO Transmit data
Auxiliary UART Port
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Pin Name Pin No. I/O Description DC Characteristics Comment
RXD_AUX 28 DI Receive data
1.8V power domain.
TXD_AUX 29 DO Transmit data
Debug UART Port
Pin Name Pin No. I/O Description DC Characteristics Comment
RXD_DBG 38 DI Receive data
1.8V power domain.
TXD_DBG 39 DO Transmit data
Ringing Signal
Pin Name Pin No. I/O Description DC Characteristics Comment
RI* 20 DO Ring indicator 1.8V power domain.
USIM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
SIM_VDD 14 DO
SIM_RST 12 DO
SIM_DATA 11 IO
SIM_CLK 13 DO
USIM card
power supply
USIM card reset
signal
USIM card data
signal
USIM card clock
signal
Vnorm=1.8V
V
max=0.15×SIM_VDD
OL
V
min=0.85×SIM_VDD
OH
V
max=0.25×SIM_VDD
IL
VIHmin=0.75×SIM_VDD
max=0.15×SIM_VDD
V
OL
min=0.85×SIM_VDD
V
OH
V
max=0.15×SIM_VDD
OL
V
min=0.85×SIM_VDD
OH
Specified
SIM_GND 10 GND
ground for USIM
card
Antenna Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
RF_ANT 35 IO
RF antenna
interface
50Ω characteristic
impedance
SPI Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
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Master input
SPI_MISO* 3 DI
slave output of
SPI interface
Master output
SPI_MOSI* 4 DO
slave input of SPI
interface
1.8V power domain.
Serial clock
SPI_SCLK* 5 DO
signal of SPI
interface
SPI_CS* 6 DO
Chip select of
SPI interface
Reserved Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
2, 8,
RESERVED
21~23,
25~26,
30~33,
Keep these pins
unconnected.
44~58
NOTES
1. Keep all unused pins unconnected.
2. “*” means under development.
3.4. Operating Modes
The following table briefly describes the three operating modes of the module.
Table 5: Overview of Operating Modes
Mode Function
In active mode, all functions of the module are available and all
Active
Normal Operation
Idle
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processors are active; radio transmission and reception can be
performed. Transitions to idle mode or PSM can be initiated in active
mode.
In idle mode, the module is in light sleep and network connection is
maintained in DRX/eDRX state; paging messages can be received.
Transitions to active mode or PSM can be initiated in idle mode.
NB-IoT Module Series
BC66 Hardware Design
In PSM, only the 32kHz RTC is working, and the network is
PSM
disconnected. The module will exit from PSM and enter into active
mode when the timer T3412 times out, and it can also be woken up
from PSM by PSM_EINT. For more details, please refer to Chapter 3.5.
3.5. Power Saving Mode (PSM)
Based on system performance, the module consumes an ultra-low current (maximally 5μA power
consumption) in PSM. PSM is designed to reduce power consumption of the module and improve battery
life. The following figure shows the power consumption of the module in different modes.
Figure 3: Module Power Consumption in Different Modes
The procedure for entering PSM is as follows: the module requests to enter PSM in “ATTACH REQUEST”
message during attach/TAU (Tracking Area Update) procedure. Then the network accepts the request
and provides an active time value (T3324) to the module and the mobile reachable timer starts. When the
T3324 timer expires, the module enters PSM for duration of T3412 (periodic TAU timer). Please note that
the module cannot request PSM when it is establishing an emergency attachment or initializing the PDN
(Public Data Network) connection.
When the module is in PSM, it cannot be paged and stops access stratum activities such as cell
reselection, but T3412 is still active.
Either of the following methods can make the module exit from PSM:
After the T3412 timer expires, the module will exit PSM automatically.
Pulling down PSM_EINT (falling edge) will wake the module up from PSM. The timing of waking up
the module from PSM is illustrated below.
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Figure 4: Timing of Waking up Module from PSM
NOTE
Among all GPIO interrupts, only the dedicated external interrupt pin PSM_EINT can successfully wake up
the module from PSM. The module cannot be woken up by any other general purpose GPIO interrupts.
3.6. Power Supply
3.6.1. Power Supply Pins
BC66 provides two VBAT pins for connection with an external power supply. The table below describes
the module's VBAT and ground pins.
Table 6: Power Supply Pins
Pin Name Pin No. Description Min. Typ. Max. Unit
Power supply for the
VBAT_BB 42
VBAT_RF 43
GND
1, 27, 34,
36, 37, 40, 41
module’s baseband
part
Power supply for the
module’s RF part
GND
2.1 3.3 3.63 V
2.1 3.3 3.63 V
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3.6.2. Reference Design for Power Supply
Power design for a module is critical to its performance. It is recommended to use a low quiescent current
LDO with output current capacity of 0.5A as the power supply for BC66. A Li-MnO2/2S alkaline battery
can also be used as the power supply. The supply voltage of the module ranges from 2.1V to 3.63V.
When the module is working, please make sure its input voltage will never drop below 2.1V; otherwise the
module will be abnormal.
For better power performance, it is recommended to place a 100uF tantalum capacitor with low ESR
(ESR=0.7Ω) and three ceramic capacitors (100nF, 100pF and 22pF) near the VBAT pins. Also, it is
recommended to add a TVS diode on the VBAT trace (near VBAT pins) to improve surge voltage
withstand capability. In principle, the longer the VBAT trace is, the wider it should be. A reference circuit
for power supply is illustrated in the following figure.
Figure 5: Reference Circuit for Power Supply
3.7. Power up/Power down Scenarios
3.7.1. Turn on
BC66 will be powered up after driving the PWRKEY pin to a low level voltage for at least 500ms.
Table 7: PWRKEY Pin
Pin Name Pin No. Description PWRKEY Pull-down Time
PWRKEY 7
Pull down PWRKEY to power
up the module
≥500ms
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It is recommended use an open drain/collector driver to control the PWRKEY. A simple reference circuit is
illustrated in the following figure.
Figure 6: Turn on the Module Using Driving Circuit
Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike
may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
Figure 7: Turn on the Module Using Keystroke
The power up timing is illustrated in the following figure.
Figure 8: Power up Timing
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NOTE
PWRKEY cannot be pulled down all the time, otherwise the module will not be able to enter into PSM.
3.7.2. Turn off
BC66 can be powered off though any of the following methods:
Power off by AT+QPOWD=0.
In emergent conditions, the module can be powered off through disconnecting VBAT power supply.
The module will be powered off automatically when VBAT drops below 2.1V.
Figure 9: Power down Timing (Power off by AT Command)
Figure 10: Power down Timing (Power off by Disconnecting VBAT)
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3.7.3. Reset the Module
Driving the RESET pin to a low level voltage for at least 50ms will reset the module.
Table 8: Reset Pin
Pin Name Pin No. Description Reset Pull-down Time
RESET 15
Reset the module.
Active low.
≥50ms
The recommended circuits of resetting the module are shown below. An open drain/collector driver or
button can be used to control the RESET pin.
Figure 11: Reference Circuit of RESET by Using Driving Circuit
Figure 12: Reference Circuit of RESET by Using Button
The reset scenario is illustrated in the following figure.
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Figure 13: Reset Timing
3.8. UART Interfaces
The module provides three UART ports: main UART port, debug UART port and auxiliary UART port. The
module is designed as DCE (Data Communication Equipment), following the traditional DCE-DTE (Data
Terminal Equipment) connection.
Table 9: Pin Definition of UART Interfaces
Interface Pin Name Pin No.Description Comment
TXD 17 Send data to RXD of DTE
Main UART Port
RXD 18 Receive data from TXD of DTE
RXD_DBG 38 Send data to RXD of DTE
Debug UART Port
TXD_DBG 39 Receive data from TXD of DTE
RXD_AUX 28 Send data to RXD of DTE
Auxiliary UART Port
TXD_AUX 29 Receive data from TXD of DTE
1.8V power
domain
Ring indicator (when there is a SMS
Ringing Signal RI* 20
or URC output, the module will inform
DTE with the RI* pin)
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NOTE
“*” means under development.
3.8.1. Main UART Port
The main UART port supports AT command communication, data transmission and firmware upgrade.
By default, the module is in auto-baud mode and it supports automatic baud rates not exceeding
115200bps. When powering on the module, the MCU has to send AT command consecutively to
synchronize baud rate with the module. When OK is returned, it indicates the baud rate has been
synchronized successfully. When the module is woken up from PSM or idle mode, the baud rate
synchronized during start-up will be used directly.
When the port is used for firmware upgrade, the baud rate is 921600bps by default.
The figure below shows the connection between DCE and DTE.
Figure 14: Reference Design for Main UART Port
3.8.2. Debug UART Port
Through debug tools, the debug UART port can be used to output logs for firmware debugging. Its baud
rate is 115200bps by default. The following is a reference design of debug UART port.
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Figure 15: Reference Design of Debug UART Port
3.8.3. Auxiliary UART Port
The auxiliary UART port is designed as a general purpose UART for communication with DTE. It also
supports log output for firmware debugging, and hardware flow control*. Its baud rate is 115200bps by
default. The following is a reference design of auxiliary UART port.
Figure 16: Reference Design of Auxiliary UART Port
3.8.4. UART Application
The module provides 1.8V UART interfaces. A level translator should be used if the application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
(please visit http://www.ti.com
reference design.
for more information) is recommended. The following figure shows a
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Figure 17: Reference Circuit with Voltage Level Translator Chip
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.
Figure 18: Reference Circuit with Transistor Circuit
The following circuit shows a reference design for the communication between the module and a PC with
standard RS-232 interface. Please make sure the I/O voltage of level shifter which connects to module is
1.8V.
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Figure 19: Sketch Map for RS-232 Interface Match
Please visit vendors’ websites to select a suitable RS-232 transceiver, such as: http://www.exar.com
http://www.maximintegrated.com
.
and
NOTES
1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
2. “ ” represents the test point of UART interfaces. It is also recommended to reserve the test points of
VBAT and PWRKEY, for convenient firmware upgrade and debugging when necessary.
3. “*” means under development.
3.9. SPI Interface
BC66 provides one SPI master interface. The following table shows the pin definition of SPI interface.
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Table 10: Pin Definition of SPI Interface
Pin Name Pin No. I/O Description Comment
SPI_MISO 3 DI Master input slave output of SPI interface
SPI_MOSI 4 DO Master output slave input of SPI interface
1.8V power domain
SPI_SCLK 5 DO Clock signal of SPI interface
SPI_CS 6 DO Chip select of SPI interface
The module provides a 1.8V SPI interface. A level translator between the module and host should be
used if the application is equipped with a 3.3V processor or device interface. A voltage level translator that
supports SPI data rate is recommended. The following figure shows a reference design.
Figure 20: SPI Interface Reference Circuit with Translator Chip
3.10. USIM Interface
The module provides a USIM interface compliant to ISO/IEC 7816-3, enabling the module to access to an
external 1.8V USIM card.
The external USIM card is powered by an internal regulator in the module and supports 1.8V power
supply.
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Table 11: Pin Definition of USIM Interface
Pin Name Pin No. Description Comment
SIM_VDD 14 Power supply for USIM card
Voltage accuracy: 1.8V±5%.
Maximum supply current: about 60mA.
SIM_CLK 13 Clock signal of USIM card
SIM_DATA 11 Data signal of USIM card
SIM_RST 12 Reset signal of USIM card
SIM_GND 10 Specified ground for USIM card
A reference circuit design for USIM interface with a 6-pin USIM card connector is illustrated below.
Figure 21: Reference Circuit for USIM Interface with a 6-pin USIM Card Connector
For more information of USIM card connector, please visit http://www.amphenol.com
http://www.molex.com
.
or
In order to enhance the reliability and availability of USIM card in application, please follow the criteria
below in USIM circuit design:
Keep the placement of USIM card connector as close as possible to the module. Keep the trace
length as less than 200mm as possible.
Keep USIM card signals away from RF and VBAT traces.
Assure the trace between the ground of module and that of USIM card connector is short and wide.
Keep the trace width of ground no less than 0.5mm to maintain the same electric potential. The
decouple capacitor between SIM_VDD and GND should be not more than 1μF and be placed close
to the USIM card connector.
To avoid cross talk between SIM_DATA and SIM_CLK, keep them away from each other and shield
them separately with surrounded ground.
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In order to offer good ESD protection, it is recommended to add a TVS diode array. For more
information of TVS diode, please visit http://www.onsemi.com
placed as close to USIM card connector as possible, and make sure the USIM card signal lines go
through the ESD protection device first and then to the module. The 22Ω resistors should be
connected in series between the module and the USIM card connector so as to suppress EMI
spurious transmission and enhance ESD protection. Please note that the USIM peripheral circuit
should be close to the USIM card connector.
Place the RF bypass capacitors (33pF) close to the USIM card connector on all signal traces to
improve EMI suppression.
. The ESD protection device should be
3.11. ADC Interface
The module provides a 10-bit ADC input channel to read the voltage value. The interface is available in
both active and idle modes.
Table 12: Pin Definition of ADC Interface
Pin Name Pin No. Description
ADC0 9 Analog to digital converter interface
3.12. RI Behaviors*
When there is a SMS or URC output, the module will inform DTE with the RI pin. More details will be
added in the future version of this document.
NOTE
“*” means under development.
3.13. Network Status Indication*
The NETLIGHT signal can be used to drive a network status indicator LED.
A reference circuit is shown as below.
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Figure 22: Reference Design for NETLIGHT
NOTE
“*” means under development.
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4Antenna Interface
The pin 35 is the RF antenna pad. The antenna port has an impedance of 50Ω.
4.1. Pin Definition
Table 13: Pin Definition of NB-IoT Antenna Interface
Pin Name Pin No. Description
RF_ANT 35 RF antenna interface
GND 34, 36, 37 Ground
4.2. Operating Frequencies
Table 14: Module Operating Frequencies
Frequency Band Receiving Frequency Transmitting Frequency
B1 2110MHz~2170MHz 1920MHz~1980MHz
B2 1930MHz~1990MHz 1850MHz~1910MHz
B3 1805MHz~1880MHz 1710MHz~1785MHz
B4 2110MHz~2155MHz 1710MHz~1755MHz
B5 869MHz~894MHz 824MHz~849MHz
B8 925MHz~960MHz 880MHz~915 MHz
B12 729MHz~746MHz 699MHz~716MHz
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B13 746MHz~756MHz 777MHz~787MHz
B17 734MHz~746MHz 704MHz~716MHz
B18 860MHz~875MHz 815MHz~830MHz
B19 875MHz~890MHz 830MHz~845MHz
B20 791MHz~821MHz 832MHz~862MHz
B25 1930MHz~1995MHz 1850MHz~1915MHz
B26* 859MHz~894MHz 814MHz~849MHz
B28 758MHz~803MHz 703MHz~748MHz
B66 2110MHz~2200MHz 1710MHz~1780MHz
NOTE
“*” means under development.
4.3. RF Antenna Reference Design
BC66 provides an RF antenna pad for external NB-IoT antenna connection.
The RF trace on host PCB connected to the module’s RF antenna pad should be coplanar
waveguide or microstrip, whose characteristic impedance should be close to 50Ω.
BC66 comes with ground pads which are next to the antenna pad in order to give a better grounding.
In order to achieve better RF performance, it is recommended to reserve a π type matching circuit
and place the π-type matching components (R1/C1/C2) as close to the antenna as possible. By
default, the capacitors (C1/C2) are not mounted and a 0Ω resistor is mounted on R1.
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A reference design of the RF interface is shown as below.
Figure 23: Reference Design of NB-IoT Antenna Interface
4.4. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the height between signal layer and reference ground (H), and the clearance between RF trace and
ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic
impedance control. The following are reference designs of microstrip line or coplanar waveguide line with
different PCB structures.
.
Figure 24: Microstrip Line Design on a 2-layer PCB
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Figure 25: Coplanar Waveguide Line Design on a 2-layer PCB
Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
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Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω.
The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
The distance between the RF pins and the RF connector should be as short as possible, and all the
right angle traces should be changed to curved ones.
There should be clearance area under the signal pin of the antenna connector or solder joint.
The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).
For more details, please refer to document [2].
4.5. Antenna Requirements
To minimize the loss on RF trace and RF cable, please pay attention to the antenna design. The following
tables show the requirements on NB-IoT antenna.
Table 15: Antenna Cable Insertion Loss Requirements