Quectel Wireless Solutions 201707BG96 Users Manual

BG96 Hardware Design

LTE Module Series

Rev. BG96_Hardware_Design_V1.5
Date: 2017-05-31

www.quectel.com

LTE Module Series

BG96 Hardware Design

Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd.

Office 501, Building 13, No.99, Tianzhou Road, Shanghai, China, 200233
Tel: [phone]
Email: [e-mail]

Or our local office. For more information, please visit:

http://www.quectel.com/support/salesupport.aspx

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Or email to: [e-mail]

GENERAL NOTES

QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION

PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT

TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
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COPYRIGHT

THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION AND EDITING OF THIS
DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE FORBIDDEN WITHOUT
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ARE RESERVED IN THE EVENT OF A PATENT GRANT OR REGISTRATION OF A UTILITY MODEL
OR DESIGN.

Copyright © Quectel Wireless Solutions Co., Ltd. 2017. All rights reserved.

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BG96 Hardware Design

Revision

Date

Author

Description

1.0

2017-01-05

Lyndon LIU/
Daryl DU/
Allen WANG

Initial

1.1

2017-03-16

Allen WANG

1. Updated operating frequencies of the module in
Table 1.

2. Added GSM features in Table 2.

1.2

2017-03-28

Allen WANG/
Lyndon LIU

1. Updated function diagram in Figure 1.

2. Updated pin assignment (top view) in Figure 2.

3. Added the description of SPI interface in Chapter

3.12.

1.3

2017-04-11

Allen WANG

1. Updated model and frequency band of the module in
Table1.

2. Updated download and upload rates of the module
in Table 2.

3. Added the description of NEMA UART interface in
Table 4 and Table 13.

1.4

2017-04-28

Allen WANG

1. Updated the function diagram in Figure 1.

2. Updated the pin assignment (top view) in Figure 2.

3. Added the reference circuit of I2S application with
audio codec (Figure 20).

4. Added the description of power saving mode (PSM)
and the note in Chapter 3.3.

5. Updated the timing of resetting module in Figure 14.

1.5

2017-05-31

Allen WANG

1. Updated the functional diagram (Figure 1).

2. Added specification requirements for GNSS antenna
in Table 27.

3. Updated the recommended footprint (Figure 35).

4. Added the recommended stencil design (Figure 36).

About the Document

History

LTE Module Series

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BG96 Hardware Design

Contents

About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3

Table Index ................................................................................................................................................... 6

Figure Index ................................................................................................................................................. 7

1 Introduction .......................................................................................................................................... 9

1.1. Safety Information.................................................................................................................... 10

2 Product Concept ................................................................................................................................ 11

2.1. General Description ................................................................................................................. 11

2.2. Directives and Standards ........................................................................................................ 12

2.2.1. FCC Statement .............................................................................................................. 12

2.3. Key Features ........................................................................................................................... 13

2.4. Functional Diagram ................................................................................................................. 15

2.5. Evaluation Board ..................................................................................................................... 16

3 Application Interfaces ....................................................................................................................... 17

3.1. Pin Assignment ........................................................................................................................ 18

3.2. Pin Description ......................................................................................................................... 19

3.3. Operating Modes ..................................................................................................................... 25

3.4. Power Saving ........................................................................................................................... 26

3.4.1. Sleep Mode .................................................................................................................... 26

3.4.1.1. UART Application ................................................................................................. 26

3.4.1.2. USB Application with USB Remote Wakeup Function ........................................ 27

3.4.1.3. USB Application with USB Suspend/Resume and RI Function .......................... 27

3.4.1.4. USB Application without USB Suspend Function ................................................ 28

3.4.2. Airplane Mode ................................................................................................................ 29

3.5. Power Supply ........................................................................................................................... 29

3.5.1. Power Supply Pins ......................................................................................................... 29

3.5.2. Decrease Voltage Drop .................................................................................................. 30

3.5.3. Monitor the Power Supply .............................................................................................. 31

3.6. Turn on and off Scenarios ....................................................................................................... 31

3.6.1. Turn on Module Using the PWRKEY Pin ....................................................................... 31

3.6.2. Turn off Module .............................................................................................................. 33

3.6.2.1. Turn off Module Using the PWRKEY Pin ............................................................. 33

3.6.2.2. Turn off Module Using AT Command ................................................................... 33

3.7. Reset the Module..................................................................................................................... 34

3.8. (U)SIM Card Interface ............................................................................................................. 35

3.9. USB Interface .......................................................................................................................... 37

3.10. UART Interfaces ...................................................................................................................... 39

3.11. I2S* and I2C Interfaces ........................................................................................................... 41

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3.12. SPI* Interface ........................................................................................................................... 42

3.13. Network Status Indication ........................................................................................................ 43

3.14. STATUS ................................................................................................................................... 44

3.15. Behaviors of RI ........................................................................................................................ 45

3.16. USB_BOOT Interface .............................................................................................................. 45

4 GNSS Receiver ................................................................................................................................... 47

4.1. General Description ................................................................................................................. 47

4.2. GNSS Performance ................................................................................................................. 47

4.3. Layout Guidelines .................................................................................................................... 48

5 Antenna Interfaces ............................................................................................................................. 49

5.1. Main Antenna Interface ........................................................................................................... 49

5.1.1. Pin Definition .................................................................................................................. 49

5.1.2. Operating Frequency ..................................................................................................... 49

5.1.3. Reference Design of RF Antenna Interface ................................................................... 50

5.1.4. Reference Design of RF Layout..................................................................................... 50

5.2. GNSS Antenna Interface ......................................................................................................... 52

5.3. Antenna Installation ................................................................................................................. 54

5.3.1. Antenna Requirements .................................................................................................. 54

5.3.2. Recommended RF Connector for Antenna Installation ................................................. 54

5.3.3. RF Reference Schematic Diagram ................................................................................ 56

5.3.4. Coplanar Waveguide Structure Design.......................................................................... 58

5.3.5. Coplanar WG PCB Layout Example and Guidelines..................................................... 60

6 Electrical, Reliability and Radio Characteristics ............................................................................ 62

6.1. Absolute Maximum Ratings ..................................................................................................... 62

6.2. Power Supply Ratings ............................................................................................................. 62

6.3. Operation Temperature ............................................................................................................ 63

6.4. Current Consumption .............................................................................................................. 63

6.5. RF Output Power ..................................................................................................................... 63

6.6. RF Receiving Sensitivity .......................................................................................................... 64

6.7. Electrostatic Discharge ............................................................................................................ 64

7 Mechanical Dimensions .................................................................................................................... 65

7.1. Mechanical Dimensions of the Module.................................................................................... 65

7.2. Recommended Footprint and Stencil Design .......................................................................... 67

7.3. Design Effect Drawings of the Module .................................................................................... 69

8 Storage, Manufacturing and Packaging .......................................................................................... 70

8.1. Storage .................................................................................................................................... 70

8.2. Manufacturing and Soldering .................................................................................................. 70

8.3. Packaging ................................................................................................................................ 71

9 Appendix A References ..................................................................................................................... 72

10 Appendix B GPRS Coding Schemes ............................................................................................... 75

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11 Appendix C GPRS Multi-slot Classes .............................................................................................. 76

12 Appendix D EDGE Modulation and Coding Schemes ................................................................... 77

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Table Index

TABLE 1: FREQUENCY BANDS OF BG96 MODULE ....................................................................................... 11

TABLE 2: KEY FEATURES OF BG96 ............................................................................................................... 13

TABLE 3: DEFINITION OF I/O PARAMETERS ................................................................................................. 19

TABLE 4: PIN DESCRIPTION ........................................................................................................................... 19

TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................. 25

TABLE 6: VBAT AND GND PINS ....................................................................................................................... 30

TABLE 7: PIN DEFINITION OF PWRKEY ........................................................................................................ 31

TABLE 8: RESET_N PIN DESCRIPTION ......................................................................................................... 34

TABLE 9: PIN DEFINITION OF (U)SIM CARD INTERFACE ............................................................................ 35

TABLE 10: PIN DEFINITION OF USB INTERFACE ......................................................................................... 37

TABLE 11: PIN DEFINITION OF UART1 INTERFACE ..................................................................................... 39

TABLE 12: PIN DEFINITION OF UART2 INTERFACE ..................................................................................... 39

TABLE 13: PIN DEFINITION OF UART3 INTERFACE ..................................................................................... 40

TABLE 14: LOGIC LEVELS OF DIGITAL I/O .................................................................................................... 40

TABLE 15: PIN DEFINITION OF I2S* AND I2C INTERFACES ........................................................................ 41

TABLE 16: PIN DEFINITION OF SPI* INTERFACE ......................................................................................... 43

TABLE 17: PIN DEFINITION OF NETWORK STATUS INDICATOR ................................................................ 43

TABLE 18: WORKING STATE OF THE NETWORK STATUS INDICATOR ...................................................... 43

TABLE 19: PIN DEFINITION OF STATUS ........................................................................................................ 44

TABLE 20: DEFAULT BEHAVIORS OF RI ........................................................................................................ 45

TABLE 21: PIN DEFINITION OF USB_BOOT INTERFACE ............................................................................. 45

TABLE 22: GNSS PERFORMANCE ................................................................................................................. 47

TABLE 23: PIN DEFINITION OF MAIN ANTENNA INTERFACE ...................................................................... 49

TABLE 24: MODULE OPERATING FREQUENCIES ........................................................................................ 49

TABLE 25: PIN DEFINITION OF GNSS ANTENNA INTERFACE ..................................................................... 52

TABLE 26: GNSS FREQUENCY ....................................................................................................................... 53

TABLE 27: ANTENNA REQUIREMENTS .......................................................................................................... 54

TABLE 28: ABSOLUTE MAXIMUM RATINGS .................................................................................................. 62

TABLE 29: POWER SUPPLY RATINGS ........................................................................................................... 62

TABLE 30: OPERATION TEMPERATURE ........................................................................................................ 63

TABLE 31: RF OUTPUT POWER ........................................................................................... 错误!未定义书签。

TABLE 32: BG96 CONDUCTED RF RECEIVING SENSITIVITY ..................................................................... 64

TABLE 33: RELATED DOCUMENTS ................................................................................................................ 72

TABLE 34: TERMS AND ABBREVIATIONS ...................................................................................................... 72

TABLE 35: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 75

TABLE 36: GPRS MULTI-SLOT CLASSES ...................................................................................................... 76

TABLE 37: EDGE MODULATION AND CODING SCHEMES ........................................................................... 77

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BG96 Hardware Design

Figure Index

FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16

FIGURE 2: PIN ASSIGNMENT (TOP VIEW)..................................................................................................... 18

FIGURE 3: SLEEP MODE APPLICATION VIA UART ....................................................................................... 26

FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 27

FIGURE 5: SLEEP MODE APPLICATION WITH RI ......................................................................................... 28

FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION ................................................ 28

FIGURE 7: STAR STRUCTURE OF THE POWER SUPPLY............................................................................ 30

FIGURE 8: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 31

FIGURE 9: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 32

FIGURE 10: TIMING OF TURNING ON MODULE ........................................................................................... 32

FIGURE 11: TIMING OF TURNING OFF MODULE .......................................................................................... 33

FIGURE 12: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 34

FIGURE 13: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 34

FIGURE 14: TIMING OF RESETTING MODULE ............................................................................................. 35

FIGURE 15: REFERENCE CIRCUIT OF (U)SIM CARD INTERFACE WITH AN 8-PIN (U)SIM CARD

CONNECTOR .................................................................................................................................................... 36

FIGURE 16: REFERENCE CIRCUIT OF (U)SIM CARD INTERFACE WITH A 6-PIN (U)SIM CARD

CONNECTOR .................................................................................................................................................... 37

FIGURE 17: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 38

FIGURE 18: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 40

FIGURE 19: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 41

FIGURE 20: REFERENCE CIRCUIT OF I2S APPLICATION WITH AUDIO CODEC ....................................... 42

FIGURE 21: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR ........................................... 44

FIGURE 22: REFERENCE CIRCUIT OF STATUS ........................................................................................... 44

FIGURE 23: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 46

FIGURE 24: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................. 50

FIGURE 25: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ...................................................................... 51

FIGURE 26: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB .................................................. 51

FIGURE 27: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE

GROUND) .......................................................................................................................................................... 51

FIGURE 28: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE

GROUND) .......................................................................................................................................................... 52

FIGURE 29: REFERENCE CIRCUIT OF GNSS ANTENNA INTERFACE ........................................................ 53

FIGURE 30: DIMENSIONS OF THE UF.L-R-SMT CONNECTOR (UNIT: MM) ................................................ 55

FIGURE 31: MECHANICALS OF UF.L-LP CONNECTORS ............................................................................. 55

FIGURE 32: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) ........................................................... 56

FIGURE 33: MODULE TOP AND SIDE DIMENSIONS ..................................................................................... 65

FIGURE 34: MODULE BOTTOM DIMENSIONS (BOTTOM VIEW) ................................................................. 66

FIGURE 35: RECOMMENDED FOOTPRINT (TOP VIEW) .............................................................................. 67

FIGURE 36: RECOMMENDED STENCIL DESIGN (TOP VIEW) ..................................................................... 68

FIGURE 37: TOP VIEW OF THE MODULE ...................................................................................................... 69

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FIGURE 38: BOTTOM VIEW OF THE MODULE .............................................................................................. 69

FIGURE 39: REFLOW SOLDERING THERMAL PROFILE .............................................................................. 71

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BG96 Hardware Design

1 Introduction

This document defines BG96 module and describes its air interface and hardware interfaces which are
connected with customers’ applications.

This document can help customers quickly understand the interface specifications, electrical and
mechanical details, as well as other related information of BG96. To facilitate its application in different
fields, reference design is also provided for customers’ reference. Associated with application note and
user guide, customers can use the module to design and set up mobile applications easily.

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LTE Module Series

Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. You must comply with laws and regulations
restricting the use of wireless devices while driving.

Switch off the cellular terminal or mobile before boarding an aircraft. Make sure it is
switched off. The operation of wireless appliances in an aircraft is forbidden, so as
to prevent interference with communication systems. Consult the airline staff about
the use of wireless devices on boarding the aircraft, if your device offers an
Airplane Mode which must be enabled prior to boarding an aircraft.

Switch off your wireless device when in hospitals, clinics or other health care
facilities. These requests are designed to prevent possible interference with
sensitive medical equipment.

Cellular terminals or mobiles operating over radio frequency signal and cellular
network cannot be guaranteed to connect in all conditions, for example no mobile
fee or with an invalid (U)SIM card. While you are in this condition and need
emergent help, please remember using emergency call. In order to make or
receive a call, the cellular terminal or mobile must be switched on and in a service
area with adequate cellular signal strength.

Your cellular terminal or mobile contains a transmitter and receiver. When it is ON,
it receives and transmits radio frequency energy. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.

In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.

BG96 Hardware Design

1.1. Safety Information

The following safety precautions must be observed during all phases of the operation, such as usage,
service or repair of any cellular terminal or mobile incorporating BG96. Manufacturers of the cellular
terminal should send the following safety information to users and operating personnel, and incorporate
these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for the
customers’ failure to comply with these precautions.

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LTE Module Series

1.

1)

GNSS function is optional.

2.

2)

BG96 does not support VoLTE (Voice over LTE) function temporarily.

Module

LTE Bands

GSM

Rx-diversity

GNSS 1)

BG96

Cat.M1:

LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/
B13/ B20/B26/B28
LTE-TDD: B39

GSM850/GSM900/
DCS1800/PCS1900

Not
Supported

GPS,
GLONASS,
BeiDou/Compass,
Galileo, QZSS

NOTES

BG96 Hardware Design

2 Product Concept

2.1. General Description

BG96 is an embedded IoT (LTE Cat.M1) wireless communication module without receive diversity. It
supports LTE-TDD and Half-Duplex LTE-FDD wireless communication, which provides data connectivity
on LTE-TDD/FDD networks. It also provides GNSS1) function and voice2) interface to meet customers’
specific application demands. The following table shows the frequency bands of BG96 module.

Table 1: Frequency Bands of BG96 Module

With a compact profile of 22.5mm × 26.5mm × 2.3mm, BG96 can meet almost all requirements for M2M
applications such as automotive, smart metering, tracking system, security, router, wireless POS, mobile
computing device, PDA phone, tablet PC, etc.

BG96 is an SMD type module which can be embedded into applications through its 102 LGA pads. BG96
supports internet service protocols like TCP, UDP and PPP. Extended AT commands have been
developed for customers to use these internet service protocols easily.

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BG96 Hardware Design

2.2. Directives and Standards

The BG96 module is designed to comply with the FCC statements. FCC ID: XMR201707BG96
The Host system using BG96 should have label “contains FCC ID: XMR201707BG96

2.2.1. FCC Statement

According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a
mobile device.

And the following conditions must be met:

1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.

The antenna installation and operating configurations of this transmitter, including any applicable
source-based time- averaging duty factor, antenna gain and cable loss must satisfy MPE categorical
Exclusion Requirements of 2.1091.

2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the user’s
body and must not transmit simultaneously with any other antenna or transmitter.

3. A label with the following statements must be attached to the host end product: This device contains
FCC ID: XMR201707BG96.

4. To comply with FCC regulations limiting both maximum RF output power and human exposure to RF
radiation, maximum antenna gain (including cable loss) must not exceed:

❒LTE B1/B2/B3/B4/B5/B8/B12/B13/B20/B26/B28 <4dBi
❒GSM 850/900/1800/1900 <4dBi

5. This module must not transmit simultaneously with any other antenna or transmitter

6. The host end product must include a user manual that clearly defines operating requirements and
conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.

For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is
required to satisfy the SAR requirements of FCC Part 2.1093.

If the device is used for other equipment that separate approval is required for all other operating
configurations, including portable configurations with respect to 2.1093 and different antenna
configurations.

For this device, OEM integrators must be provided with labeling instructions of finished products. Please
refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:

A certified modular has the option to use a permanently affixed label, or an electronic label. For a
permanently affixed label, the module must be label led with an FCC ID - Section 2.926 (see 2.2
Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining

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LTE Module Series

Features

Details

BG96 Hardware Design

to the OEM the labeling requirements, options and OEM user manual instructions that are required (see
next paragraph).

For a host using a certified modular with a standard fixed label, if (1) the module’s FCC ID is not visible
when installed in the host, or (2) if the host is marketed so that end users do not have straight forward
commonly used methods for access to remove the module so that the FCC ID of the module is visible;
then an additional permanent label referring to the enclosed module: “Contains Transmitter Module FCC
ID:XMR201707BG96” or “Contains FCC ID: XMR201707BG96” must be used. The host OEM user
manual must also contain clear instructions on how end users can find and/or access the module and the
FCC ID.

The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for
unintentional radiators in order to be properly authorized for operation as a Part 15 digital device.
The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user
that changes or modifications not expressly approved by the party responsible for compliance could void
the user's authority to operate the equipment. In cases where the manual is provided only in a form other
than paper, such as on a computer disk or over the Internet, the information required by this section may
be included in the manual in that alternative form, provided the user can reasonably be expected to have
the capability to access information in that form.

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the manufacturer could void the user’s authority to

operate the equipment.

To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring
compliance with the module(s) installed and fully operational. For example, if a host was previously
authorized as an unintentional radiator under the Declaration of Conformity procedure without a
transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that
the after the module is installed and operational the host continues to be compliant with the Part 15B
unintentional radiator requirements.

2.3. Key Features

The following table describes the detailed features of BG96.

Table 2: Key Features of BG96

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Power Supply

Supply voltage: 3.3V~4.3V
Typical supply voltage: 3.8V

LTE Features

Support up to LTE Cat.M1
Support 1.08MHz RF bandwidth
Support SISO in DL direction
Cat.M1: Max. 375kbps (DL)/375kbps (UL)

GSM Features

GPRS:

Support GPRS multi-slot class 12 (12 by default)
Coding schemes: CS-1, CS-2, CS-3 and CS-4
Maximum of four Rx time slots per frame
GPRS: Max. 85.6kbps (DL)/85.6kbps (UL)

EDGE:

Support EDGE multi-slot class 12 (12 by default)
Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
Downlink coding schemes: CS 1-4 and MCS 1-9
Uplink coding schemes: CS 1-4 and MCS 1-9
EDGE: Max. 236.8kbps (DL)/236.8kbps (UL)

Internet Protocol
Features*

Support TCP/UDP/PPP protocols
Support PAP (Password Authentication Protocol) and CHAP (Challenge
Handshake Authentication Protocol) protocols which are usually used for
PPP connections

SMS*

Text and PDU mode
Point to point MO and MT
SMS cell broadcast
SMS storage: ME by default

(U)SIM Card Interface

Support (U)SIM card: 1.8V, 3.0V

Audio Feature*

Support one digital audio interface: I2S interface

USB Interface

Compliant with USB 2.0 specification (slave only) and the data transfer rate
can reach up to 480Mbps
Used for AT command communication, data transmission, GNSS NEMA
output, software debugging and firmware upgrade
Support USB drivers for Windows XP, Windows Vista, Windows 7,
Windows 8/8.1, Windows 10, Windows CE 5.0/6.0/7.0*, Linux 2.6/3.x/4.1,
Android 4.x/5.x/6.0

UART Interfaces

UART1:

Used for data transmission and AT command communication
Baud rate reach up to 3000000bps; 115200bps by default
Support RTS and CTS hardware flow control

UART2:

Used for module debugging and log output
115200bps baud rate

UART3/SPI*:

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UART3 is the default configuration when the module is used as a modem.
In this case, it is used for outputting GNSS data or NEMA sentences.
When the module is used as the core board, the port can be multiplexed
into SPI* interface for data transferring.

AT Commands

3GPP TS 27.007 and 3GPP TS 27.005 AT commands, as well as
Quectel enhanced AT commands

Network Indication

One NETLIGHT pin for network connectivity status indication

Antenna Interfaces

Including main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS)
interfaces

Physical Characteristics

Size: 22.5mm × 26.5mm × 2.3mm
Weight: approx. 3.1g

Temperature Range

Operation temperature range: -35°C ~ +75°C 1)
Extended temperature range: -40°C ~ +85°C 2)

Firmware Upgrade

USB interface and DFOTA*

RoHS

All hardware components are fully compliant with EU RoHS directive

1. “*” means under development.

2.

1)

Within operation temperature range, the module is 3GPP compliant.

3.

2)

Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like
P

out

might reduce in their value and exceed the specified tolerances. When the temperature returns to

the normal operating temperature levels, the module will meet 3GPP specifications again.

NOTES

BG96 Hardware Design

2.4. Functional Diagram

The following figure shows a block diagram of BG96 and illustrates the major functional parts.

 Power management
 Baseband
 DDR+NAND flash
 Radio frequency
 Peripheral interfaces

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Baseband

PMIC

Transceiver

NAND
DDR2

SDRAM

PA

RF5212A

Filter

ANT_MAIN

ANT_GNSS

VBAT_BB

VBAT_RF

PWRKEY

VDD_EXT

USB

USIM I2S* I2C

RESET_N

19.2M
XO

STATUS

GPIOs

Control

IQ Control

LNA

Tx

PRx

GNSS

UART/SPI*

NETLIGHT

PA

RF3628

“*” means under development.

NOTE

BG96 Hardware Design

Figure 1: Functional Diagram

2.5. Evaluation Board

In order to help customers develop applications conveniently with BG96, Quectel supplies the evaluation
board (EVB), USB data cable, earphone, antenna and other peripherals to control or test the module.

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BG96 Hardware Design

3 Application Interfaces

BG96 is equipped with 62-pin 1.1mm pitch SMT pads and 40-pin ground/reserved pads that can be
connected to customers’ cellular application platforms. The following sub-chapters will provide detailed
description of interfaces listed below:

 Power supply
 (U)SIM card interface
 USB interface
 UART interfaces
 I2S* interface
 UART3/SPI* interface
 Status indication
 USB_BOOT interface

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BG96 Hardware Design

PSM_IND

I2S_WCLK*

I2S_BCLK*

I2S_D0*

I2S_D1*

RESERVED
RESERVED

PWRKEY

1)

RESERVED

RESET_N

W_DISABLE#

1
2
3

4
5
6
7

11
12
13
14
15
16
17

50

51

52

53

54

55

58

59

60

61

62

USB_DM

AP_READY

STATUS

NETLIGHT

DBG_RXD

DBG_TXD

ADC0

RESERVED

GPIO/SPI_CLK*

UART3_TXD/SPI_MOSI*

UART3_RXD/SPI_MISO*

VDD_EXT

DTR

GND

USIM_CLK
USIM_DATA

USIM_RST
USIM_VDD

RI
DCD

CTS
TXD

RXD
VBAT_BB

VBAT_BB

USIM_GND

GND

RESERVED

31

30

29

28

27

26

23

22

21

20

19

10

9

USB_DP

USB_VBUS

ADC1

GND

RESERVED
RESERVED

RTS

I2C_SCL

I2C_SDA

8

49
48
47

46
45
44
43

40

41

42

39
38
37
36
35
34
33
32

24

57

56

GND

GND

ANT_MAIN

GND

GND

VBAT_RF

VBAT_RF

GND

GND

ANT_GNSS

RESERVED

GND

USIM_PRESENCE

63

64

65

66

67

68

83

84

85

86

87

88

98

97

96

95

94

93

78

77

76

75

74

73

91 92

89 90

71

72

69

70

80 79

82 81

100

99

102 101

POWER USB UART

USIM

OTHERS

GND

RESERVED

I2S

ANT

25

I2S_MCLK*

RESERVED

USB_BOOT

18

SPI

GPIO*

3.1. Pin Assignment

The following figure shows the pin assignment of BG96.

LTE Module Series

Figure 2: Pin Assignment (Top View)

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BG96 Hardware Design

1. Keep all RESERVED pins and unused pins unconnected.

2. GND pads should be connected to ground in the design.

3. 1) PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset.

4. “*” means under development.

Type

Description

IO

Bidirectional

DI

Digital input

DO

Digital output

PI

Power input

PO

Power output

AI

Analog input

AO

Analog output

OD

Open drain

Power Supply

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

VBAT_BB

32, 33

PI

Power supply
for module
baseband part

Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V

VBAT_RF

52, 53

PI

Power supply
for module RF

Vmax=4.3V
Vmin=3.3V

NOTES

3.2. Pin Description

The following tables show the pin definition and description of BG96.

Table 3: Definition of I/O Parameters

LTE Module Series

Table 4: Pin Description

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LTE Module Series

part

Vnorm=3.8V

VDD_EXT

29

PO

Provide 1.8V for
external circuit

Vnorm=1.8V
IOmax=50mA

Power supply for external
GPIO’s pull up circuits.

GND

3, 31, 48,
50, 54, 55,
58, 59, 61,
62, 67~74,
79~82,
89~91,
100~102

Ground

Turn on/off

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

PWRKEY

15

DI

Turn on/off the
module

VIHmax=2.1V
VIHmin=1.3V
VILmax=0.5V

The output voltage is

0.8V because of the
diode drop in the
Qualcomm chipset.

RESET_N

17

DI

Reset signal of
the module

VIHmax=2.1V
VIHmin=1.3V
VILmax=0.5V

If unused, keep this pin
open.

Status Indication

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

STATUS

20

OD

Indicate the
module’s
operation status

VOHmin=1.35V
VOLmax=0.45V

1.8V power domain.
If unused, keep this pin
open.

NETLIGHT

21

DO

Indicate the
module’s
network activity
status

VOHmin=1.35V
VOLmax=0.45V

1.8V power domain.
If unused, keep it open.

USB Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

USB_VBUS

8

PI

USB detection

Vmax=5.25V
Vmin=3.0V
Vnorm=5.0V

USB_DP

9

IO

USB differential
data bus (+)

Compliant with
USB 2.0 standard
specification.

Require differential
impedance of 90Ω.

BG96 Hardware Design

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LTE Module Series

USB_DM

10

IO

USB differential
data bus (-)

Compliant with
USB 2.0 standard
specification.

Require differential
impedance of 90Ω.

(U)SIM Card Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

USIM_GND

47

Specified
ground for
(U)SIM card

USIM_VDD

43

PO

Power supply
for (U)SIM card

For 1.8V (U)SIM:

Vmax=1.9V
Vmin=1.7V

For 3.0V (U)SIM:

Vmax=3.05V
Vmin=2.7V

IOmax=50mA

Either 1.8V or 3V is
supported by the module
automatically.

USIM_DATA

45

IO

Data signal of
(U)SIM card

For 1.8V (U)SIM:

VILmax=0.6V
VIHmin=1.2V
VOLmax=0.45V
VOHmin=1.35V

For 3.0V (U)SIM:

VILmax=1.0V
VIHmin=1.95V
VOLmax=0.45V
VOHmin=2.55V

USIM_CLK

46

DO

Clock signal of
(U)SIM card

For 1.8V (U)SIM:

VOLmax=0.45V
VOHmin=1.35V

For 3.0V (U)SIM:

VOLmax=0.45V
VOHmin=2.55V

USIM_RST

44

DO

Reset signal of
(U)SIM card

For 1.8V (U)SIM:

VOLmax=0.45V
VOHmin=1.35V

For 3.0V (U)SIM:

VOLmax=0.45V
VOHmin=2.55V

BG96 Hardware Design

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LTE Module Series

USIM_
PRESENCE

42

DI

(U)SIM card
insertion
detection

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

UART1 Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

RI

39

DO

Ring indicator

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

DCD

38

DO

Data carrier
detection

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

RTS

37

DI

Request to
send

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

CTS

36

DO

Clear to send

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

TXD

35

DO

Transmit data

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

RXD

34

DI

Receive data

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

DTR

30

DI

Data terminal
ready. Sleep
mode control.

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
Pull-up by default. Low
level wakes up the
module.
If unused, keep it open.

UART2 Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

DBG_TXD

23

DO

Transmit data

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

DBG_RXD

22

DI

Receive data

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

UART3/SPI* Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

BG96 Hardware Design

BG96_Hardware_Design Confidential / Released 22 / 71

LTE Module Series

GPIO/
SPI_CLK*

26

DO

GPIO/SPI
master clock

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

UART3_TXD/
SPI_MOSI*

27

DO

Transmit data/
Master Out

Salve In of SPI
interface

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

UART3_RXD/
SPI_MISO*

28

DI

Receive data/
Master In Slave
Out of SPI
interface

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

I2S* Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

I2S_MCLK*

63

DO

I2S master
clock

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

I2S_BCLK*

4

DO

I2S bit clock

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

I2S_WCLK*

5

DO

I2S data frame
clock

VOLmax=0.45V
VOHmin=1.35V

1.8V power domain.
If unused, keep it open.

I2S_D0*

6

IO

I2S data 0

VILmax=0.6V
VIHmin=1.2V
VOLmax=0.45V
VIHmin=1.35V

1.8V power domain.
If unused, keep it open.

I2S_D1*

7

IO

I2S data 1

VILmax=0.6V
VIHmin=1.2V
VOLmax=0.45V
VIHmin=1.35V

1.8V power domain.
If unused, keep it open.

I2C Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

I2C_SCL

40

OD

I2C serial clock.
Used for
external codec.

External pull-up resistor is
required.

1.8V only. If unused, keep
it open.

I2C_SDA

41

OD

I2C serial data.
Used for
external codec.

External pull-up resistor is
required.

1.8V only. If unused, keep
it open.

Antenna Interfaces

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

BG96 Hardware Design

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LTE Module Series

ANT_MAIN

60

IO

Main antenna
interface

50Ω impedance

ANT_GNSS

49

AI

GNSS antenna
interface

50Ω impedance

If unused, keep it open.

Other Pins

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

PSM_IND*

1

DO

Power saving
mode indicator

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

W_DISABLE#

18

DI

Airplane mode
control

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
Pull-up by default.
In low voltage level, the
module can enter into
airplane mode.
If unused, keep it open.

AP_READY*

19

DI

Application
processor sleep
state detection

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

USB_BOOT

75

DI

Force the
module to boot
from USB port

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

GPIO*

64

IO

General­purpose input/
output interface

VILmin=-0.3V
VILmax=0.6V
VIHmin=1.2V
VIHmax=2.0V

1.8V power domain.
If unused, keep it open.

ADC Interface

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

ADC1

2

AI

General
purpose analog
to digital
converter
interface

Voltage range:

0.3V to VBAT_BB

If unused, keep it open.

ADC0

24

AI

General
purpose analog
to digital
converter
interface

Voltage range:

0.3V to VBAT_BB

If unused, keep it open.

BG96 Hardware Design

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LTE Module Series

RESERVED Pins

Pin Name

Pin No.

I/O

Description

DC
Characteristics

Comment

RESERVED

11~14, 16,
25, 51, 56,
57, 65,66,
76~78,
83~88,
92~99

Reserved

Keep these pins
unconnected.

1. Keep all RESERVED pins and unused pins unconnected.

2. “*” means under development.

Mode

Details

Normal
Operation

Idle

Software is active. The module has registered on network, and it is
ready to send and receive data.

Talk/Data

Network connection is ongoing. In this mode, the power consumption is
decided by network setting and data transfer rate.

Minimum
Functionality
Mode

AT+CFUN command can set the module to a minimum functionality mode without
removing the power supply. In this case, both RF function and (U)SIM card will be invalid.

Airplane
Mode

AT+CFUN command or W_DISABLE# pin can set the module to airplane mode. In this
case, RF function will be invalid.

Sleep Mode

In this mode, the current consumption of the module will be reduced to the minimal level.
During this mode, the module can still receive paging message, SMS, voice call and
TCP/UDP data from the network normally.

PSM*

A UE may adopt the PSM (Power Saving Mode) for reducing its power consumption.
PSM is similar to power-off, but the UE remains registered on the network and there is no
need to re-attach or re-establish PDN connections. When the module is successfully
entered into the PSM, PSM_IND* outputs a low level.

NOTES

BG96 Hardware Design

3.3. Operating Modes

The table below briefly summarizes the various operating modes referred in the following chapters.

Table 5: Overview of Operating Modes

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BG96 Hardware Design

Power Down
Mode

In this mode, the power management unit shuts down the power supply. Software is not
active. The serial interface is not accessible. Operating voltage (connected to VBAT_RF
and VBAT_BB) remains applied.

1. In PSM or sleep mode, it is recommended to use UART interface for module connection. USB
connection is NOT recommended as it will cause increase in power consumption.

2. “*” means under development.

RXD

TXD

RI

DTR

AP_READY*

TXD

RXD

EINT

GPIO

GPIO

Module

Host

GND

GND

NOTES

3.4. Power Saving

3.4.1. Sleep Mode

LTE Module Series

BG96 is able to reduce its current consumption to a minimum value during sleep mode. The following
describes the power saving procedure of BG96 module.

3.4.1.1. UART Application

If the host communicates with module via UART interface, the following preconditions can let the module
enter into sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.
 Drive DTR to high level.

The following figure shows the connection between the module and the host.

BG96_Hardware_Design Confidential / Released 26 / 71

Figure 3: Sleep Mode Application via UART

LTE Module Series

USB_VBUS

USB_DP

USB_DM

AP_READY*

VDD

USB_DP

USB_DM

GPIO

Module

Host

GND

GND

BG96 Hardware Design

 Driving the host DTR to low level will wake up the module.
 When BG96 has URC to report, RI signal will wake up the host. Refer to Chapter 3.15 for details

about RI behaviors.

 AP_READY* will detect the sleep state of the host (can be configured to high level or low level

detection). Please refer to AT+QCFG=“apready” command for details.

3.4.1.2. USB Application with USB Remote Wakeup Function

If the host supports USB suspend/resume and remote wakeup functions, the following three preconditions
must be met to let the module enter into sleep mode.

 Execute AT+QSCLK=1 command to enable the sleep mode.
 Ensure the DTR is held in high level or keep it open.
 The host’s USB bus, which is connected with the module’s USB interface, enters into suspended

state.

The following figure shows the connection between the module and the host.

Figure 4: Sleep Mode Application with USB Remote Wakeup

 Sending data to BG96 through USB will wake up the module.
 When BG96 has URC to report, the module will send remote wake-up signals via USB bus so as to

wake up the host.

3.4.1.3. USB Application with USB Suspend/Resume and RI Function

If the host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is
needed to wake up the host. There are three preconditions to let the module enter into sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.
 Ensure the DTR is held in high level or keep it open.
 The host’s USB bus, which is connected with the module’s USB interface, enters into suspended

state.

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BG96 Hardware Design

USB_VBUS

USB_DP

USB_DM

AP_READY*

VDD

USB_DP

USB_DM

GPIO

Module Host

GND

GND

RI

EINT

USB_VBUS

USB_DP

USB_DM

AP_READY

VDD

USB_DP

USB_DM

GPIO

Module Host

RI

EINT

Power
Switch

GPIO

GND

GND

The following figure shows the connection between the module and the host.

Figure 5: Sleep Mode Application with RI

 Sending data to BG96 through USB will wake up the module.
 When BG96 has a URC to report, RI signal will wake up the host.

LTE Module Series

3.4.1.4. USB Application without USB Suspend Function

If the host does not support USB suspend function, USB_VBUS should be disconnected via an additional
control circuit to let the module enter into sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.
 Ensure the DTR is held in high level or keep it open.
 Disconnect USB_VBUS.

The following figure shows the connection between the module and the host.

Figure 6: Sleep Mode Application without Suspend Function

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LTE Module Series

1. Please pay attention to the level match shown in dotted line between the module and the host. Refer
to document [1] for more details about BG96 power management application.

2. “*” means under development.

1. Airplane mode control via W_DISABLE# is disabled in firmware by default. It can be enabled by
AT+QCFG=“airplanecontrol” command. The command is still under development.

2. The execution of AT+CFUN command will not affect GNSS function.

NOTES

NOTES

BG96 Hardware Design

Switching on the power switch to supply power to USB_VBUS will wake up the module.

3.4.2. Airplane Mode

When the module enters into airplane mode, the RF function does not work, and all AT commands
correlative with RF function will be inaccessible. This mode can be set via the following ways.

Hardware:
W_DISABLE# is pulled up by default. Driving it to low level will let the module enter into airplane mode.

Software:
AT+CFUN=<fun> command provides choice of the functionality level, through setting <fun> into 0, 1 or 4.

 AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
 AT+CFUN=1: Full functionality mode (by default).
 AT+CFUN=4: Airplane mode. RF function is disabled.

3.5. Power Supply

3.5.1. Power Supply Pins

BG96 provides four VBAT pins for connection with an external power supply. There are two separate
voltage domains for VBAT.

 Two VBAT_RF pins for module’s RF part.
 Two VBAT_BB pins for module’s baseband part.

The following table shows the details of VBAT pins and ground pins.

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BG96 Hardware Design

Pin Name

Pin No.

Description

Min.

Typ.

Max.

Unit

VBAT_RF

52, 53

Power supply for module’s RF
part

3.3

3.8

4.3 V VBAT_BB

32, 33

Power supply for module’s
baseband part

3.3

3.8

4.3

V

GND

3, 31, 48, 50,
54, 55, 58, 59,
61, 62, 67~74,
79~82, 89~91,
100~102

Ground

- - -

-

Module

VBAT_RF

VBAT_BB

VBAT

C1

100uF

C6

100nFC733pFC810pF

+

+

C2

100nF

C5

100uF

C3

33pF

C4

10pF

D1

5.1V

Table 6: VBAT and GND Pins

3.5.2. Decrease Voltage Drop

LTE Module Series

The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will
never drop below 3.3V.

To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a
multi-layer ceramic chip capacitor (MLCC) array should also be used to provide the low ESR. The main
power supply from an external application has to be a single voltage source and can be expanded to two
sub paths with star structure. The width of VBAT_BB trace should be no less than 1mm, and the width of
VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.

Three ceramic capacitors (100nF, 33pF, 10pF) are recommended to be applied to the VBAT pins. These
capacitors should be placed close to the VBAT pins. In addition, in order to get a stable power source, it is
suggested that you should use a zener diode of which reverse zener voltage is 5.1V and dissipation
power is more than 0.5W. The following figure shows the star structure of the power supply.

BG96_Hardware_Design Confidential / Released 30 / 71

Figure 7: Star Structure of the Power Supply

LTE Module Series

Pin Name

Pin No.

Description

DC Characteristics

Comment

PWRKEY

15

Turn on/off the module

VIHmax=2.1V
VIHmin=1.3V
VILmax=0.5V

The output voltage is

0.8V because of the

diode drop in the
Qualcomm chipset.

Turn on pulse

PWRKEY

4.7K

47K

≥100ms

BG96 Hardware Design

3.5.3. Monitor the Power Supply

AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to

document [2].

3.6. Turn on and off Scenarios

3.6.1. Turn on Module Using the PWRKEY Pin

The following table shows the pin definition of PWRKEY.

Table 7: Pin Definition of PWRKEY

When BG96 is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin to a
low level for at least 100ms. It is recommended to use an open drain/collector driver to control the
PWRKEY. After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be
released. A simple reference circuit is illustrated in the following figure.

Figure 8: Turn on the Module Using Driving Circuit

The other way to control the PWRKEY is using a button directly. When pressing the key, electrostatic
strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.

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BG96 Hardware Design

PWRKEY

S1

Close to S1

TVS

VIL≤0.5V

VIH≥1.3V

VBAT

PWRKEY

≥100ms

RESET_N

STATUS
(OD)

Inactive

Active

UART

NOTE

Inactive

Active

USB

TBD

TBD

TBD

Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than
30ms.

NOTE

Figure 9: Turn on the Module Using Keystroke

The turn on scenario is illustrated in the following figure.

LTE Module Series

Figure 10: Timing of Turning on Module

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LTE Module Series

VBAT

PWRKEY

TBDTBD

RUNNING

Power-down procedure

OFF

Module
Status

STATUS

BG96 Hardware Design

3.6.2. Turn off Module

The following procedures can be used to turn off the module:

 Normal power down procedure: Turn off the module using the PWRKEY pin.
 Normal power down procedure: Turn off the module using AT+QPOWD command.

3.6.2.1. Turn off Module Using the PWRKEY Pin

Driving the PWRKEY pin to a low level voltage (the specific time is TBD), the module will execute
power-down procedure after the PWRKEY is released. The power-down scenario is illustrated in the
following figure.

Figure 11: Timing of Turning off Module

3.6.2.2. Turn off Module Using AT Command

It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the
module via PWRKEY pin.

Please refer to document [2] for details about AT+QPOWD command.

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LTE Module Series

Pin Name

Pin No.

Description

DC Characteristics

Comment

RESET_N

17

Reset signal of the
module

VIHmax=2.1V
VIHmin=1.3V
VILmax=0.5V

Reset pulse

RESET_N

4.7K

47K

150~460ms

RESET_N

S2

Close to S2

TVS

BG96 Hardware Design

3.7. Reset the Module

The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a
low level voltage for time between 150ms and 460ms.

Table 8: RESET_N Pin Description

The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.

Figure 12: Reference Circuit of RESET_N by Using Driving Circuit

Figure 13: Reference Circuit of RESET_N by Using Button

The reset scenario is illustrated in the following figure.

BG96_Hardware_Design Confidential / Released 34 / 71

LTE Module Series

VBAT

≥150ms

Resetting

Module
Status

Running

RESET_N

Restart

≤460ms

VIL≤0.5V

VIH≥1.3V

1. Use RESET_N only when turning off the module by AT+QPOWD command and PWRKEY pin both
failed.

2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.

Pin Name

Pin No.

I/O

Description

Comment

USIM_VDD

43

PO

Power supply for (U)SIM card

Either 1.8V or 3.0V is supported
by the module automatically.

USIM_DATA

45

IO

Data signal of (U)SIM card

USIM_CLK

46

DO

Clock signal of (U)SIM card

USIM_RST

44

DO

Reset signal of (U)SIM card

USIM_
PRESENCE

42

DI

(U)SIM card insertion detection

USIM_GND

47

Specified ground for (U)SIM
card

NOTES

BG96 Hardware Design

Figure 14: Timing of Resetting Module

3.8. (U)SIM Card Interface

The (U)SIM card interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM
cards are supported.

Table 9: Pin Definition of (U)SIM Card Interface

BG96_Hardware_Design Confidential / Released 35 / 71

LTE Module Series

Module

USIM_VDD

USIM_GND

USIM_RST

USIM_CLK

USIM_DATA

USIM_PRESENCE

22R

22R

22R

VDD_EXT

51K

100nF (U)SIM Card Connector

GND

GND

33pF

33pF 33pF

VCC
RST

CLK

IO

VPP

GND

GND

USIM_VDD

15K

Module

USIM_VDD

USIM_GND

USIM_RST
USIM_CLK

USIM_DATA

22R

22R

22R

100nF

(U)SIM Card Connector

GND

33pF 33pF 33pF

VCC
RST
CLK IO

VPP

GND

GND

15K

USIM_VDD

BG96 Hardware Design

BG96 supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and
high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET
command for details.

The following figure shows a reference design of (U)SIM card interface with an 8-pin (U)SIM card
connector.

Figure 15: Reference Circuit of (U)SIM Card Interface with an 8-Pin (U)SIM Card Connector

If (U)SIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A
reference circuit for (U)SIM card interface with a 6-pin (U)SIM card connector is illustrated in the following
figure.

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LTE Module Series

Pin Name

Pin No.

I/O

Description

Comment

USB_VBUS

8

PI

USB connection detection

Typically 5.0V

USB_DP

9

IO

USB differential data bus (+)

Require differential
impedance of 90Ω

USB_DM

10

IO

USB differential data bus (-)

Require differential
impedance of 90Ω

GND

3 Ground

BG96 Hardware Design

Figure 16: Reference Circuit of (U)SIM Card Interface with a 6-Pin (U)SIM Card Connector

In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the
criteria below in (U)SIM circuit design:

 Keep layout of (U)SIM card as close to the module as possible. Keep the trace length as less than

200mm as possible.

 Keep (U)SIM card signals away from RF and VBAT traces.
 Assure the ground between the module and the (U)SIM card connector short and wide. Keep the

trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.

 To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and

shield them with surrounded ground.

 In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic

capacitance not exceeding 50pF. The 22Ω resistors should be added in series between the module
and the (U)SIM card so as to suppress EMI spurious transmission and enhance ESD protection. The
33pF capacitors are used for filtering interference of GSM900. Please note that the (U)SIM peripheral
circuit should be close to the (U)SIM card connector.

 The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace

and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.

3.9. USB Interface

BG96 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0
specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is
used for AT command communication, data transmission, software debugging and firmware upgrade. The
following table shows the pin definition of USB interface.

Table 10: Pin Definition of USB Interface

For more details about USB 2.0 specification, please visit http://www.usb.org/home.

BG96_Hardware_Design Confidential / Released 37 / 71

LTE Module Series

USB_DP

USB_DM

GND

USB_DP

USB_DM

GND

R1
R2

Close to Module

R3
R4

Test Points

ESD Array

NM_0R
NM_0R

0R
0R

Minimize these stubs

Module

MCU

USB_VBUS

VDD

BG96 module can only be used as a slave device.

NOTE

BG96 Hardware Design

The USB interface is recommended to be reserved for firmware upgrade in your design. The following
figure shows a reference circuit of USB interface.

Figure 17: Reference Circuit of USB Application

In order to ensure signal integrity of USB data lines, components R1, R2, R3 and R4 must be placed
close to the module, and also these resistors should be placed close to each other. The extra stubs of
trace must be as short as possible.

The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.

 It is important to route the USB signal traces as differential pairs with total grounding. The impedance

of USB differential trace is 90Ω.

 Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is

important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.

 Pay attention to the influence of junction capacitance of ESD protection components on USB data

lines. Typically, the capacitance value should be less than 2pF.

 Keep the ESD protection components to the USB connector as close as possible.

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LTE Module Series

Pin Name

Pin No.

I/O

Description

Comment

DTR

30

DI

Sleep mode control

1.8V power domain

RXD

34

DI

Receive data

1.8V power domain

TXD

35

DO

Transmit data

1.8V power domain

CTS

36

DO

Clear to send

1.8V power domain

RTS

37

DI

Request to send

1.8V power domain

DCD

38

DO

Data carrier detection

1.8V power domain

RI

39

DO

Ring indicator

1.8V power domain

Pin Name

Pin No.

I/O

Description

Comment

DBG_TXD

23

DO

Transmit data

1.8V power domain

DBG_RXD

22

DI

Receive data

1.8V power domain

BG96 Hardware Design

3.10. UART Interfaces

The module provides three UART interfaces: UART1, UART2 and UART3 interfaces. The following are
their features.

 UART1 interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 and

3000000bps baud rates, and the default is 115200bps. This interface is used for data transmission
and AT command communication.

 UART2 interface supports 115200bps baud rate. It is used for module debugging and log output.
 UART3 interface is used for outputting GNSS data or NEMA sentences. It can be multiplexed into

SPI* interface.

The following tables show the pin definition of the three UART interfaces.

Table 11: Pin Definition of UART1 Interface

Table 12: Pin Definition of UART2 Interface

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BG96 Hardware Design

Pin Name

Pin No.

I/O

Description

Comment

UART3_TXD

27

DO

Transmit data

1.8V power domain

UART3_RXD

28

DI

Receive data

1.8V power domain

Parameter

Min.

Max.

Unit

VIL

-0.3

0.6 V VIH

1.2

2.0 V VOL 0 0.45

V

VOH

1.35

1.8

V

VCCA VCCB

OE
A1

A2
A3

A4
A5
A6
A7
A8

GND

B1
B2
B3
B4
B5
B6
B7
B8

VDD_EXT

RI

DCD

RTS

RXD

DTR

CTS

TXD

51K

51K

0.1uF

0.1uF

RI_MCU

DCD_MCU

RTS_MCU

RXD_MCU

DTR_MCU

CTS_MCU

TXD_MCU

VDD_MCU

Translator

Table 13: Pin Definition of UART3 Interface

The logic levels are described in the following table.

Table 14: Logic Levels of Digital I/O

LTE Module Series

The module provides 1.8V UART interface. A level translator should be used if your application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instrument is
recommended. The following figure shows a reference design.

Please visit http://www.ti.com for more information.

BG96_Hardware_Design Confidential / Released 40 / 71

Figure 18: Reference Circuit with Translator Chip

LTE Module Series

MCU/ARM

TXD

RXD

VDD_EXT

10K

VCC_MCU

4.7K

10K

VDD_EXT

TXD

RXD

RTS
CTS
DTR
RI

RTS
CTS

GND

GPIO DCD

Module

GPIO

EINT

VDD_EXT

4.7K

GND

1nF

1nF

Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.

Pin Name

Pin No.

I/O

Description

Comment

I2S_MCLK*

63

DO

I2S master clock

1.8V power domain.

I2S_BCLK*

4

DO

I2S bit clock

1.8V power domain

I2S_WCLK*

5

DO

I2S data frame clock

1.8V power domain

NOTE

BG96 Hardware Design

Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the circuit design of solid line section, in terms of both module input and output circuit
designs, but please pay attention to the direction of connection.

Figure 19: Reference Circuit with Transistor Circuit

3.11. I2S* and I2C Interfaces

BG96 provides one Inter-IC Sound (I2S) digital interface* and one I2C interface.

The following table shows the pin definition of I2S* and I2C interfaces which can be applied on audio
codec design.

Table 15: Pin Definition of I2S* and I2C Interfaces

BG96_Hardware_Design Confidential / Released 41 / 71

LTE Module Series

I2S_D0*

6

IO

I2S data 0

1.8V power domain

I2S_D1*

7

IO

I2S data 1

1.8V power domain

I2C_SCL

40

OD

I2C serial clock

Require external pull-up to 1.8V

I2C_SDA

41

OD

I2C serial data

Require external pull-up to 1.8V

I2S_D0

I2S_WCLK

I2S_BCLK

I2S_MCLK

I2C_SCL
I2C_SDA

Module

1.8V

4.7K

4.7K

MCLK

BCLK

WCLK

ADC

SCL

SDA

BIAS

MICBIAS

INP
INN

LOUTP

LOUTN

Codec

I2S_D1

DAC

“*” means under development.

NOTE

BG96 Hardware Design

The following figure shows a reference design of I2S* and I2C interfaces with an external codec IC.

Figure 20: Reference Circuit of I2S Application with Audio Codec

3.12. SPI* Interface

BG96 provides one Serial Peripheral Interface (SPI) digital interface* which is multiplexed from UART3
(default configuration).

The following table shows the pin definition of SPI* interface which can be used to transfer data.

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BG96 Hardware Design

Pin Name

Pin No.

I/O

Description

Comment

SPI_CLK*

26

DO

SPI master clock

1.8V power domain.

SPI_MOSI*

27

DO

Master Out Slave in of SPI
interface

1.8V power domain

SPI_MISO*

28

DI

Master In Slave Out of SPI
interface

1.8V power domain

“*” means under development.

Pin Name

Pin No.

I/O

Description

Comment

NETLIGHT

21

DO

Indicate the module’s network activity
status

1.8V power domain

Pin Name

Logic Level Changes

Network Status

NETLIGHT

Flicker slowly (200ms High/1800ms Low)

Network searching

Flicker slowly (1800ms High/200ms Low)

Idle

Flicker quickly (125ms High/125ms Low)

Data transfer is ongoing

Always high

Voice calling

NOTE

Table 16: Pin Definition of SPI* Interface

LTE Module Series

3.13. Network Status Indication

BG96 provides one network indication pin: NETLIGHT. The pin is used to drive a network status indication
LED. The following tables describe the pin definition and logic level changes of NETLIGHT in different
network activity status.

Table 17: Pin Definition of Network Status Indicator

Table 18: Working State of the Network Status Indicator

A reference circuit is shown in the following figure.

BG96_Hardware_Design Confidential / Released 43 / 71

4.7K

47K

VBAT

2.2K

Module

NETLIGHT

Pin Name

Pin No.

I/O

Description

Comment

STATUS

20

OD

Indicate the module’s operation status

Require external pull-up

VDD_MCU

10K

Module

STATUS MCU_GPIO

Module

STATUS

VBAT

2.2K

3.14. STATUS

LTE Module Series

BG96 Hardware Design

Figure 21: Reference Circuit of the Network Status Indicator

The STATUS pin is an open drain output for indicating the module’s operation status. It can be connected
to a GPIO of DTE with a pulled up resistor, or as LED indication circuit as below. When the module is
turned on normally, the STATUS will present a low state. Otherwise, the STATUS will present
high-impedance state.

Table 19: Pin Definition of STATUS

The following figure shows different circuit designs of STATUS, and you can choose either one according
to your application demands.

BG96_Hardware_Design Confidential / Released 44 / 71

Figure 22: Reference Circuit of STATUS

LTE Module Series

URC can be outputted from UART port, USB AT port and USB modem port, through configuration via

AT+QURCCFG command. The default port is USB AT port.

State

Response

Idle

RI keeps in high level.

URC

RI outputs 120ms low pulse when new URC returns.

Pin Name

Pin No.

I/O

Description

Comment

USB_BOOT

75

DI

Force the module to boot from USB
port

1.8V power domain.
Active high.
If unused, keep it open.

NOTE

BG96 Hardware Design

3.15. Behaviors of RI

AT+QCFG=“risignaltype”,“physical” command can be used to configure RI behavior.

No matter on which port URC is presented, URC will trigger the behavior of RI pin.

The default behaviors of RI are shown as below.

Table 20: Default Behaviors of RI

The default RI behaviors can be configured flexibly by AT+QCFG=“urc/ri/ring” command. AT+QCFG
command is still under development. For more details, please refer to document [2].

3.16. USB_BOOT Interface

BG96 provides a USB_BOOT pin. During development or factory production, USB_BOOT pin can force
the module to boot from USB port for firmware upgrade.

Table 21: Pin Definition of USB_BOOT Interface

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BG96 Hardware Design

Module

USB_BOOT

VDD_EXT

10K

Test point

TVS

Close to test point

The following figure shows a reference circuit of USB_BOOT interface.

LTE Module Series

Figure 23: Reference Circuit of USB_BOOT Interface

BG96_Hardware_Design Confidential / Released 46 / 71

LTE Module Series

Parameter

Description

Conditions

Typ.

Unit

Sensitivity
(GNSS)

Cold start

Autonomous

TBD

dBm

Reacquisition

Autonomous

TBD

dBm

Tracking

Autonomous

TBD

dBm

TTFF
(GNSS)

Cold start
@open sky

Autonomous

TBD

s

XTRA* enabled

TBD

s

Warm start
@open sky

Autonomous

TBD

s

XTRA* enabled

TBD

s

Hot start

Autonomous

TBD

s

BG96 Hardware Design

4 GNSS Receiver

4.1. General Description

BG96 includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of
Qualcomm (GPS, GLONASS, BeiDou/Compass, Galileo and QZSS).

BG96 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via
USB interface by default.

By default, BG96 GNSS engine is switched off. It has to be switched on via AT command. For more
details about GNSS engine technology and configurations, please refer to document [3].

4.2. GNSS Performance

The following table shows the GNSS performance of BG96.

Table 22: GNSS Performance

BG96_Hardware_Design Confidential / Released 47 / 71

LTE Module Series

@open sky

XTRA* enabled

TBD

s

Accuracy
(GNSS)

CEP-50

Autonomous
@open sky

TBD

m

1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep
on positioning for 3 minutes.

2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can
fix position again within 3 minutes after loss of lock.

3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes
position within 3 minutes after executing cold start command.

4. “*” means under development.

NOTES

BG96 Hardware Design

4.3. Layout Guidelines

The following layout guidelines should be taken into account in your design.

 Maximize the distance between GNSS antenna and main antenna.
 Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card

should be kept away from the antennas.

 Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar

isolation and protection.

 Keep 50Ω characteristic impedance for the ANT_GNSS trace.

Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information.

BG96_Hardware_Design Confidential / Released 48 / 71

LTE Module Series

Pin Name

Pin No.

I/O

Description

Comment

ANT_MAIN

60

IO

Main antenna interface

50Ω impedance

3GPP Band

Transmit

Receive

Unit

B1

1920~1980

2110~2170

MHz

B2 (PCS1900)

1850~1910

1930~1990

MHz

B3 (DCS1800)

1710~1785

1805~1880

MHz

B4

1710~1755

2110~2155

MHz

B5 (GSM850)

824~849

869~894

MHz

B8 (GSM900)

880~915

925~960

MHz

B12

699~716

728~746

MHz

BG96 Hardware Design

5 Antenna Interfaces

BG96 includes a main antenna interface and a GNSS antenna interface. The antenna interfaces have an
impedance of 50Ω.

5.1. Main Antenna Interface

5.1.1. Pin Definition

The pin definition of main antenna interface is shown below.

Table 23: Pin Definition of Main Antenna Interface

5.1.2. Operating Frequency

Table 24: Module Operating Frequencies

BG96_Hardware_Design Confidential / Released 49 / 71

LTE Module Series

B13

777~787

746~757

MHz

B20

832~862

791~821

MHz

B26

814~848.9

859~893.9

MHz

B28

703~748

758~803

MHz

B39

1880~1920

1880~1920

MHz

ANT_MAIN

R1 0R

C1

Module

Main
antenna

NM

C2

NM

BG96 Hardware Design

5.1.3. Reference Design of RF Antenna Interface

A reference design of ANT_MAIN antenna pad is shown as below. A π-type matching circuit should be
reserved for better RF performance, and the π-type matching components (R1/C1/C2) should be placed

as close the antenna as possible. The capacitors are not mounted by default.

Figure 24: Reference Circuit of RF Antenna Interface

5.1.4. Reference Design of RF Layout

For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the distance between signal layer and reference ground (H), and the clearance between RF trace and
ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic
impedance control. The following are reference designs of microstrip line or coplanar waveguide line with
different PCB structures.

BG96_Hardware_Design Confidential / Released 50 / 71

LTE Module Series

BG96 Hardware Design

Figure 25: Microstrip Line Design on a 2-layer PCB

Figure 26: Coplanar Waveguide Line Design on a 2-layer PCB

Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)

BG96_Hardware_Design Confidential / Released 51 / 71

LTE Module Series

Pin Name

Pin No.

I/O

Description

Comment

ANT_GNSS

49

AI

GNSS antenna interface

50Ω impedance

BG96 Hardware Design

Figure 28: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)

In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:

 Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω.
 The GND pins adjacent to RF pins should not be hot welded, and should be fully connected to

ground.

 The distance between the RF pins and the RF connector should be as short as possible, and all the

right angle traces should be changed to curved ones.

 There should be clearance area under the signal pin of the antenna connector or solder joint.
 The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around

RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).

For more details about RF layout, please refer to document [4].

5.2. GNSS Antenna Interface

The following tables show the pin definition and frequency specification of GNSS antenna interface.

Table 25: Pin Definition of GNSS Antenna Interface

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BG96 Hardware Design

Type

Frequency

Unit

GPS/Galileo/QZSS

1575.42±1.023

MHz

GLONASS

1597.5~1605.8

MHz

BeiDou

1561.098±2.046

MHz

GNSS
Antenna

VDD

Module

ANT_GNSS

47nH

10R

0.1uF

100pF

NMNM

1. An external LDO can be selected to supply power according to the active antenna requirement.

2. If the module is designed with a passive antenna, then the VDD circuit is not needed.

NOTES

Table 26: GNSS Frequency

A reference design of GNSS antenna is shown as below.

LTE Module Series

Figure 29: Reference Circuit of GNSS Antenna Interface

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BG96 Hardware Design

Antenna Type

Requirements

LTE/GSM

VSWR: ≤ 2
Gain (dBi): 1
Max Input Power (W): 50
Input Impedance (Ω): 50
Polarization Type: Vertical
Cable Insertion Loss: < 1dB
(LTE B5/B8/B12/B13/B20/B26/B28
GSM850/GSM900)
Cable Insertion Loss: < 1.5dB
(LTE B1/B2/B3/B4/B39, DCS1800/PCS1900)

GNSS

Frequency range: 1561~1615MHz
Polarization: RHCP or linear
VSWR: <2 (Typ.)
Passive antenna gain: >0dBi
Active antenna noise figure: <1.5dB
Active antenna gain: >-2dBi
Active antenna embedded LNA gain: 20dB (Typ.)
Active antenna total gain: >18dBi (Typ.)

5.3. Antenna Installation

5.3.1. Antenna Requirements

The following table shows the requirements on main antenna and GNSS antenna.

Table 27: Antenna Requirements

LTE Module Series

5.3.2. Recommended RF Connector for Antenna Installation

If RF connector is used for antenna connection, it is recommended to use the UF.L-R-SMT connector
provided by HIROSE.

BG96_Hardware_Design Confidential / Released 54 / 71

LTE Module Series

BG96 Hardware Design

Figure 30: Dimensions of the UF.L-R-SMT Connector (Unit: mm)

U.FL-LP serial connectors listed in the following figure can be used to match the UF.L-R-SMT.

Figure 31: Mechanicals of UF.L-LP Connectors

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BG96 Hardware Design

The following figure describes the space factor of mated connector.

LTE Module Series

Figure 32: Space Factor of Mated Connector (Unit: mm)

For more details, please visit http://www.hirose.com.

5.3.3. RF Reference Schematic Diagram

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LTE Module Series

BG96 Hardware Design

Figure 33: RF Reference Schematic Diagram

C1, R1 and C2 form a “PI” type matching circuit which is reserved for antenna optimization. By default, R1

is 0ohm while C1 and C2 are both Not Mounted (NM).

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BG96 Hardware Design

Dielectric Height (H)

RF Trace Width (W)

Space between RF Trace and the
Ground (S)

0.076mm

0.1188mm

0.15mm

0.1mm

0.1623mm

0.2mm

0.15mm

0.24mm

0.2mm

0.8mm

0.8mm

0.18mm

1.0mm

0.8mm

0.17mm

5.3.4. Coplanar Waveguide Structure Design

The recommended coplanar waveguide structure is shown as Figure 2.

LTE Module Series

Figure 34: Structure of Coplanar WG

The factors which influence impedance include dielectric constant (usually 4.2~4.6, here is 4.4), dielectric
height (H), RF trace width (W), the space between RF trace, the ground (S) and copper thickness (T).
When T=0.035mm, the recommended value of W and S for 50 ohm coplanar WG under different PCB
structure is listed in Table 1.

Table 28: Recommended Value of W and S for 50 ohm Coplanar WG under Different PCB Structure

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LTE Module Series

1.2mm

0.8mm

0.16mm

1.6mm

0.8mm

0.15mm

2mm

0.8mm

0.14mm

BG96 Hardware Design

If there are two layers, the TOP layer is the signal layer, and the BOTTOM layer is the reference ground,
as shown in Figure 3. If there are 4 layers, the reference ground could be the second layer, the third layer
or the fourth layer. If third layer is chosen, the second layer should be kept out and the width of keepout
area should be at least five times of the trace width, as shown in Figure 4. If the fourth layer is chosen,
both the second and third layer should be kept out and the width of keepout area should be at least five
times of the trace width, as shown in Figure 5. Same as 6 or more layers.

Figure 35: Two Layers PCB Layout

Figure 36: Four Layers PCB Layout (Third Layer as Reference Ground)

Figure 37: Four Layers PCB Layout (Fourth Layer as Reference Ground)

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BG96 Hardware Design

5.3.5. Coplanar WG PCB Layout Example and Guidelines

LTE Module Series

Figure 38: An example of PCB layout

There are 6 guidelines should be taken into account, as marked in the above figure:

1. Control corresponding W and S of 50 ohm coplanar waveguide. Use the common PCB as FR4
medium (dielectric constant is 4.2) and take copper clad of 35 um thickness as an example. Values of
W and S for 50 ohm coplanar WG under different PCB structure is shown as Table 1. Keep in mind to
remind PCB manufacturers to keep the accuracy of W and S.

2. Do not hot sealing the PIN in this position and make it contacted with the ground closely enough.

3. Keep out pouring copper in the surface layer and reduce parasitic effect. The RF trace line should be
as short as possible. It will be better for RF trace line to avoid vertical angle layout. The RF trace
line should be kept 135 degree angle around the corner.

4. Keep a certain distance between signal pad and ground when packaging the device. Refer to Figure

6. If the signal pad is in SMD type, pouring copper on the corresponding signal pad.

5. Ensure the corresponding reference ground of RF trace line is integrated and do not forget to add
more ground via to help RF reflow. The ground and RF trace should be kept at least two times of the
trace width. Guarantee the contact area which is in the same layer with RF trace is as large as

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LTE Module Series

BG96 Hardware Design

possible and its corresponding reference ground in the opposite layer is as integrated as possible,
meanwhile ensure the two layer ground is connected by amount of ground hole.

6. Three components consist of PI type matching circuit shown as Figure 6. Place the pad to antenna
as close as possible, as shown in Figure 6. If the distance between SMA and RF PIN is too short to
place the three pin of PI type matching circuit, PI type matching circuit can be changed into L
matching circuit.

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LTE Module Series

Parameter

Min.

Max.

Unit

VBAT_RF/VBAT_BB

-0.3

4.7 V USB_VBUS

-0.3

5.5 V Peak Current of VBAT_BB

0

TBD

A

Peak Current of VBAT_RF

0

TBD

A

Voltage at Digital Pins

-0.3

2.3

V

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

VBAT

VBAT_BB and
VBAT_RF

Voltage must stay within the
min/max values, including
voltage drop, ripple and
spikes.

3.3

3.8

4.3

V
I

VBAT

Peak supply current
(during transmission
slot)

TBD

TBD

A

BG96 Hardware Design

6 Electrical, Reliability and Radio Characteristics

6.1. Absolute Maximum Ratings

Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.

Table 29: Absolute Maximum Ratings

6.2. Power Supply Ratings

Table 30: Power Supply Ratings

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BG96 Hardware Design

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

USB_VBUS

USB detection

3.0

5.0

5.25

V

Parameter

Min.

Typ.

Max.

Unit

Operation Temperature Range 1)

-35

+25

+75

ºC

Extended Temperature Range 2)

-40 +85

ºC

1.

1)

Within operation temperature range, the module is 3GPP compliant.

2.

2)

Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters
like P

out

might reduce in their value and exceed the specified tolerances. When the temperature

returns to the normal operating temperature levels, the module will meet 3GPP specifications again.

NOTES

6.3. Operation Temperature

The operation temperature is listed in the following table.

Table 31: Operation Temperature

LTE Module Series

6.4. Current Consumption

The information will be added in the future version of this document.

6.5. RF Output Power

The following table shows the RF output power of BG96 module.

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BG96 Hardware Design

Frequency

Primary

Diversity

SISO

3GPP

LTE-FDD B1

TBD

Not Supported

TBD

-102.7dBm

LTE-FDD B2

TBD

Not Supported

TBD

-100.3dBm

LTE-FDD B3

TBD

Not Supported

TBD

-99.3dBm

LTE-FDD B4

TBD

Not Supported

TBD

-102.3dBm

LTE-FDD B5

TBD

Not Supported

TBD

-100.8dBm

LTE-FDD B8

TBD

Not Supported

TBD

-99.8dBm

LTE-FDD B12

TBD

Not Supported

TBD

-99.3dBm

LTE-FDD B13

TBD

Not Supported

TBD

-99.3dBm

LTE-FDD B20

TBD

Not Supported

TBD

-99.8dBm

LTE-FDD B26

TBD

Not Supported

TBD

-100.3dBm

LTE-FDD B28

TBD

Not Supported

TBD

-100.8dBm

LTE-TDD B39

TBD

Not Supported

TBD

-103dBm

GSM850/GSM900

TBD

Not Supported

TBD

-102.4dBm

DCS1800/PCS1900

TBD

Not Supported

TBD

-102.4dBm

6.6. RF Receiving Sensitivity

The following table shows the conducted RF receiving sensitivity of BG96 module.

Table 32: BG96 Conducted RF Receiving Sensitivity

LTE Module Series

6.7. Electrostatic Discharge

The information will be added in the future version of this document.

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LTE Module Series

22.50±0.1

26.50±0.1

2.3±0.2

BG96 Hardware Design

7 Mechanical Dimensions

This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm.

7.1. Mechanical Dimensions of the Module

Figure 39: Module Top and Side Dimensions

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LTE Module Series

22.50

26.50

0.92

0.92

1.50

1.10

7.45

7.15

1.95

0.55

1.10

1.66

5.10

1.00

8.50

0.85

1.70

0.85

1.00

1.00

1.70

1.70

0.55

1.50

1.15

1.90

1.10

0.50

0.70

40x1.0

40x1.0

62x0.7

62x1.15

BG96 Hardware Design

Figure 40: Module Bottom Dimensions (Bottom View)

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BG96 Hardware Design

1.00

1.70

0.70

0.55

0.85

1.00

1.70

1.70

62x0.7

40x1.00

40x1.00

22.50

26.50

1.65

1.50

1.50

1.65

1.15

1.15

7.45

7.15

0.85

5.10

0.20

1.10

1.90

1.10

1.95

1.00

1.10

1.10

62x1.15

8.50

7.2. Recommended Footprint and Stencil Design

LTE Module Series

Figure 41: Recommended Footprint (Top View)

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LTE Module Series

1.00

1.70

0.70

0.55

0.85

1.00

1.70

1.70

62x0.7

40x1.00

40x1.00

22.50

26.50

1.65

1.50

1.50

1.65

1.15

1.15

7.45

7.15

0.85

5.10

0.20

1.10

1.90

1.10

1.95

1.00

1.10

1.10

62x1.15

8.50

1. For easy maintenance of the module, please keep about 3mm between the module and other

components in the host PCB.

2. All Reserved pins MUST be kept open.

NOTES

BG96 Hardware Design

Figure 42: Recommended Stencil Design (Top View)

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BG96 Hardware Design

These are design effect drawings of BG96 module. For more accurate pictures, please refer to the
module that you get from Quectel.

NOTE

7.3. Design Effect Drawings of the Module

LTE Module Series

Figure 43: Top View of the Module

Figure 44: Bottom View of the Module

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LTE Module Series

As the plastic package cannot be subjected to high temperature, it should be removed from devices
before high temperature (125ºC ) baking. If shorter baking time is desired, please refer to
IPC/JEDECJ-STD-033 for baking procedure.

NOTE

BG96 Hardware Design

8 Storage, Manufacturing and Packaging

8.1. Storage

BG96 is stored in a vacuum-sealed bag. The storage restrictions are shown as below.

1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH.

2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other
high temperature processes must be:

 Mounted within 168 hours at the factory environment of ≤30ºC/60%RH.
 Stored at <10%RH.

3. Devices require baking before mounting, if any circumstance below occurs.

 When the ambient temperature is 23ºC±5ºC and the humidity indication card shows the humidity

is >10% before opening the vacuum-sealed bag.

 Device mounting cannot be finished within 168 hours at factory conditions of ≤30ºC/60%

4. If baking is required, devices may be baked for 48 hours at 125ºC±5ºC.

8.2. Manufacturing and Soldering

Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the
thickness of stencil for the module is recommended to be 0.18mm. For more details, please refer to
document [5].

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LTE Module Series

Time

50

100

150 200

250 300

50

100

150

200

250

160ºC

200ºC

217

0

70s~120s

40s~60s

Between 1~3ºC/s

Preheat Heating Cooling

ºC

s

Liquids Temperature

Temperature

During manufacturing and soldering, or any other processes that may contact the module directly, NEVER
wipe the module label with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol,
trichloroethylene, etc.

NOTE

BG96 Hardware Design

It is suggested that the peak reflow temperature is 235~245ºC (for SnAg3.0Cu0.5 alloy). The absolute
max reflow temperature is 260ºC. To avoid damage to the module caused by repeated heating, it is
suggested that the module should be mounted after reflow soldering for the other side of PCB has been
completed. Recommended reflow soldering thermal profile is shown below.

Figure 45: Reflow Soldering Thermal Profile

8.3. Packaging

The information will be added in the future version of this document.

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BG96 Hardware Design

SN

Document Name

Remark

[1]

Quectel_BG96_Power_Management_Application_Note

BG96 Power Management Application
Note

[2]

Quectel_BG96_AT_Commands_Manual

BG96 AT Commands Manual

[3]

Quectel_BG96_GNSS_AT_Commands_Manual

BG96 GNSS AT Commands Manual

[4]

Quectel_RF_Layout_Application_Note

RF Layout Application Note

[5]

Quectel_Module_Secondary_SMT_User_Guide

Module Secondary SMT User Guide

Abbreviation

Description

AMR

Adaptive Multi-rate

bps

Bits Per Second

CHAP

Challenge Handshake Authentication Protocol

CS

Coding Scheme

CTS

Clear To Send

DC-HSPA+

Dual-carrier High Speed Packet Access

DFOTA

Delta Firmware Upgrade Over The Air

DL

Downlink

DTR

Data Terminal Ready

DTX

Discontinuous Transmission

EFR

Enhanced Full Rate

9 Appendix A References

Table 33: Related Documents

LTE Module Series

Table 34: Terms and Abbreviations

BG96_Hardware_Design Confidential / Released 72 / 71

LTE Module Series

ESD

Electrostatic Discharge

FDD

Frequency Division Duplex

FR

Full Rate

GMSK

Gaussian Minimum Shift Keying

GSM

Global System for Mobile Communications

HR

Half Rate

HSPA

High Speed Packet Access

HSDPA

High Speed Downlink Packet Access

HSUPA

High Speed Uplink Packet Access

I/O

Input/Output

Inorm

Normal Current

LED

Light Emitting Diode

LNA

Low Noise Amplifier

LTE

Long Term Evolution

MIMO

Multiple Input Multiple Output

MO

Mobile Originated

MS

Mobile Station (GSM engine)

MT

Mobile Terminated

PAP

Password Authentication Protocol

PCB

Printed Circuit Board

PDU

Protocol Data Unit

PPP

Point-to-Point Protocol

QAM

Quadrature Amplitude Modulation

QPSK

Quadrature Phase Shift Keying

RF

Radio Frequency

RHCP

Right Hand Circularly Polarized

Rx

Receive

BG96 Hardware Design

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LTE Module Series

SISO

Single Input Single Output

SMS

Short Message Service

TDD

Time Division Duplexing

TX

Transmitting Direction

UL

Uplink

UMTS

Universal Mobile Telecommunications System

URC

Unsolicited Result Code

(U)SIM

(Universal) Subscriber Identity Module

Vmax

Maximum Voltage Value

Vnorm

Normal Voltage Value

Vmin

Minimum Voltage Value

VIHmax

Maximum Input High Level Voltage Value

VIHmin

Minimum Input High Level Voltage Value

VILmax

Maximum Input Low Level Voltage Value

VILmin

Minimum Input Low Level Voltage Value

VImax

Absolute Maximum Input Voltage Value

VImin

Absolute Minimum Input Voltage Value

VOHmax

Maximum Output High Level Voltage Value

VOHmin

Minimum Output High Level Voltage Value

VOLmax

Maximum Output Low Level Voltage Value

VOLmin

Minimum Output Low Level Voltage Value

VSWR

Voltage Standing Wave Ratio

WCDMA

Wideband Code Division Multiple Access

BG96 Hardware Design

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BG96 Hardware Design

Scheme

CS-1

CS-2

CS-3

CS-4

Code Rate

1/2

2/3

3/4

1

USF

3 3 3

3

Pre-coded USF

3 6 6

12

Radio Block excl.USF and BCS

181

268

312

428

BCS

40

16

16

16

Tail

4 4 4

-

Coded Bits

456

588

676

456

Punctured Bits

0

132

220

-

Data Rate Kb/s

9.05

13.4

15.6

21.4

10 Appendix B GPRS Coding Schemes

Table 35: Description of Different Coding Schemes

LTE Module Series

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LTE Module Series

Multislot Class

Downlink Slots

Uplink Slots

Active Slots

1 1 1 2 2 2 1 3 3 2 2

3

4 3 1 4 5 2 2

4

6 3 2 4 7 3 3 4 8 4 1 5 9 3 2

5

10 4 2

5

11 4 3

5

12 4 4

5

BG96 Hardware Design

11 Appendix C GPRS Multi-slot Classes

Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot
classes are product dependent, and determine the maximum achievable data rates in both the uplink and
downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots,
while the second number indicates the amount of uplink timeslots. The active slots determine the total
number of slots the GPRS device can use simultaneously for both uplink and downlink communications.

The description of different multi-slot classes is shown in the following table.

Table 36: GPRS Multi-slot Classes

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BG96 Hardware Design

Coding
Schemes

Modulation

Coding Family

1 Timeslot

2 Timeslot

4 Timeslot

CS-1:

GMSK

/

9.05kbps

18.1kbps

36.2kbps

CS-2:

GMSK

/

13.4kbps

26.8kbps

53.6kbps

CS-3:

GMSK

/

15.6kbps

31.2kbps

62.4kbps

CS-4:

GMSK

/

21.4kbps

42.8kbps

85.6kbps

MCS-1

GMSK

C

8.80kbps

17.60kbps

35.20kbps

MCS-2

GMSK

B

11.2kbps

22.4kbps

44.8kbps

MCS-3

GMSK

A

14.8kbps

29.6kbps

59.2kbps

MCS-4

GMSK

C

17.6kbps

35.2kbps

70.4kbps

MCS-5

8-PSK

B

22.4kbps

44.8kbps

89.6kbps

MCS-6

8-PSK

A

29.6kbps

59.2kbps

118.4kbps

MCS-7

8-PSK

B

44.8kbps

89.6kbps

179.2kbps

MCS-8

8-PSK

A

54.4kbps

108.8kbps

217.6kbps

MCS-9

8-PSK

A

59.2kbps

118.4kbps

236.8kbps

12 Appendix D EDGE Modulation and Coding Schemes

Table 37: EDGE Modulation and Coding Schemes

LTE Module Series

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