Philips NE568AN, NE568AD, SA568AN, SA568AD Datasheet

Philips Semiconductors Product specification

NE/SA568A150MHz phase-locked loop

1

1996 Feb 1 853-1558 16328

DESCRIPTION

The NE568A is a monolithic phase-locked loop (PLL) which
operates from 1Hz to frequencies in excess of 150MHz and features
an extended supply voltage range and a lower temperature
coefficient of the V

CO

center frequency in comparison with its
predecessor, the NE 568. The NE568A is function and
pin-compatible with the NE568, requiring only minor changes in
peripheral circuitry (see Figure 3). Temperature compensation
network is different, no resistor on Pin 12, needs to be grounded and
Pin 13 has a 3.9kΩ resistor to ground. Timing cap, C

2

, is different
and for 70MHz operation with temperature compensation network
should be 16pF, not 34pF as was used in the NE568. The NE568A
has the following improvements: ESD protected; extended V

CC

range from 4.5V to 5.5V; operating temperature range -55 to 125°C
(see Signetics Military 568A data sheet); less layout sensitivity; and
lower T

C

of VCO (center frequency). The integrated circuit consists
of a limiting amplifier, a current-controlled oscillator (ICO), a phase
detector, a level shift circuit, V/I and I/V converters, an output buf fer,
and bias circuitry with temperature and frequency compensating
characteristics. The design of the NE568A is particularly well-suited
for demodulation of FM signals with extremely large deviation in
systems which require a highly linear output. In satellite receiver
applications with a 70MHz IF, the NE568A will demodulate ±20%
deviations with less than 1.0% typical non-linearity. In addition to
high linearity, the circuit has a loop filter which can be configured
with series or shunt elements to optimize loop dynamic
performance. The NE568A is available in 20-pin dual in-line and
20-pin SO (surface mounted) plastic packages.

FEATURES

•Operation to 150MHz

•High linearity buffered output

PIN CONFIGURATION

V

CC2

GND1

D, N Packages

LF1

V

CC1

REFBYP
PNPBYP

INPBYP

LF3

LF2

LF4
FREQ ADJ

1
2
3
4
5
6
7
8
9

10

11

12

13

14

20
19
18
17
16
15

OUT

FILT

V

OUT

TC

ADJ2

V

IN

TC

ADJ1

GND

2

GND

1

TCAP1
TCAP2

TOP VIEW

SR01037

Figure 1. Pin Configuration

•Series or shunt loop filter component capability

•External loop gain control

•Temperature compensated

•ESD protected

1

APPLICATIONS

•Satellite receivers

•Fiber optic video links

•VHF FSK demodulators

•Clock Recovery

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

20-Pin Plastic Small Outline Large (SOL) Package 0 to +70°C NE568AD SOT163-1
20-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE568AN SOT146-1
20-Pin Plastic Small Outline Large (SOL) Package -40 to +85°C SA568AD SOT163-1
20-Pin Plastic Dual In-Line Package (DIP) -40 to +85°C SA568AN SOT146-1

BLOCK DIAGRAM

PHASE

DETECTOR

1 2 3 4 5 6 7 8 9 10

111213141516

17181920

LEVEL SHIFT

V/I

CONVERTER

AMP

I/V

CONVERTER

OUT
BUF

LEVEL SHIFT

TCADJ BIAS

ICO

V

CC2

GND1

LF1

V

CC1

REFBYP PNPBYP INPBYP

LF3LF2 LF4 FREQ ADJ

OUT

FILTVOUT

TC

ADJ2

V

IN

TC

ADJ1

GND

2

GND

1

TCAP1 TCAP2

NOTE:

Pins 4 and 5 can tolerate
1000V only, and all other
pins, greater than 2000V
for ESD (human body
model).

SR01038

Figure 2. Block Diagram

Philips Semiconductors Product specification

NE/SA568A150MHz phase-locked loop

1996 Feb 1

2

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS

V

CC

Supply voltage 6 V

T

J

Junction temperature +150 °C

T

STG

Storage temperature range -65 to +150 °C

P

DMAX

Maximum power dissipation 400 mW

θ

JA

Thermal resistance 80 °C/W

ELECTRICAL CHARACTERISTICS

The elctrical characteristics listed below are actual tests (unless
otherwise stated) performed on each device with an automatic IC
tester prior to shipment. Performance of the device in automated
test set-up is not necessarily optimum. The NE568A is

layout-sensitive. Evaluation of performance for correlation to the
data sheet should be done with the circuit and layout of Figures 3, 4,
and 5 with the evaluation unit soldered in place. (Do not use a
socket!)

DC ELECTRICAL CHARACTERISTICS

VCC = 5V; TA = 25°C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9kΩ, unless otherwise specified.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA568A

UNITS

MIN TYP MAX

V

CC

Supply voltage 4.5 5 5.5 V

I

CC

Supply current 54 70 mA

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

NE/SA568A

UNITS

MIN TYP MAX

f

OSC

Maximum oscillator operating frequency

3

150 MHz

Input signal level

50

–20

1

2000

+10

mV

P-P

dBm

BW Demodulated bandwidth fO/7 MHz

Non-linearity

5

Dev = ±20%, Input = -20dBm 1.0 4.0 %

Lock range

2

Input = -20dBm ±25 ±35 % of f

O

Capture range

2

Input = -20dBm ±20 ±30 % of f

O

TC of f

O

Figure 3 100 ppm/°C

R

IN

Input resistance

4

1 kΩ

Output impedance 6 Ω
Demodulated V

OUT

Dev = ±20% of fO measured at

Pin 14

0.40 0.52 V

P-P

AM rejection

VIN = -20dBm (30% AM)

referred to ±20% deviation

50 dB

f

O

Distribution

6

Centered at 70MHz, R2 =

1.2kΩ, C

2

= 16pF, R4 = 3.9kΩ

(C

2

+ C

STRAY

= 20pF)

-15 0 +15 %

f

O

Drift with supply 4.5V to 5.5V 2 %/V

NOTE:

1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.

2. Limits are set symmetrical to f

O

. Actual characteristics may have asymmetry beyond the specified limits.

3. Not 100% tested, but guaranteed by design.

4. Input impedance depends on package and layout capacitances. See Figures 6 and 5.

5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (V

OUT

). Non-linearity is

then calculated from a straight line over the deviation range specified.

6. Free-running frequency is measured as feedthrough to Pin 14 (V

OUT

) with no input signal applied.

Philips Semiconductors Product specification

NE/SA568A150MHz phase-locked loop

1996 Feb 1

3

C1

R

FC1

C2

C8

C3

C4

C5 C6

C7

C13

C12

C11

C9

R

FC2

V

CC

V

OUT

V

IN

C10

R1

R2

R3

R4

R5

V

CC2

GND1

GND2

GND1

TCAP1

TCAP2

V

CC1

REFBYP

PNPBYP

INPBYP

LF1

OUTFILT

LF2

LF3

LF4

FREQADJ

V

OUT

TCADJ2

TCADJ1

V

IN

SR01039

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Figure 3. Test Circuit for AC Parameters

FUNCTIONAL DESCRIPTION

The NE568A is a high-performance phase-locked loop (PLL). The
circuit consists of conventional PLL elements, with special circuitry
for linearized demodulated output, and high-frequency performance.
The process used has NPN transistors with f

T

> 6GHz. The high
gain and bandwidth of these transistors make careful attention to
layout and bypass critical for optimum performance. The
performance of the PLL cannot be evaluated independent of the
layout. The use of the application layout in this data sheet and
surface-mount capacitors are highly recommended as a starting
point.

The input to the PLL is through a limiting amplifier with a gain of 200.
The input of this amplifier is differential (Pins 10 and 11). For
single-ended applications, the input must be coupled through a
DC-blocking capacitor with low impedance at the frequency of
interest. The single-ended input is normally applied to Pin 11 with
Pin 10 AC-bypassed with a low-impedance capacitor. The input
impedance is characteristically slightly above 500Ω. Impedance
match is not necessary, but loading the signal source should be
avoided. When the source is 50 or 75Ω, a DC-blocking capacitor is
usually all that is needed.

Input amplification is low enough to assure reasonable response
time in the case of large signals, but high enough for good AM
rejection. After amplification, the input signal drives one port of a
multiplier-cell phase detector. The other port is driven by the
current-controlled oscillator (ICO). The output of the phase
comparator is a voltage proportional to the phase difference of the
input and ICO signals. The error signal is filtered with a low-pass
filter to provide a DC-correction voltage, and this voltage is
converted to a current which is applied to the ICO, shifting the
frequency in the direction which causes the input and ICO to have a
90° phase relationship.

The oscillator is a current-controlled multivibrator. The current
control affects the charge/discharge rate of the timing capacitor . It is
common for this type of oscillator to be referred to as a

voltage-controlled oscillator (VCO), because the output of the phase
comparator and the loop filter is a voltage. To control the frequency
of an integrated ICO multivibrator, the control signal must be
conditioned by a voltage-to-current converter. In the NE568A,
special circuitry predistorts the control signal to make the change in
frequency a linear function over a large control-current range.

The free-running frequency of the oscillator depends on the value of
the timing capacitor connected between Pins 4 and 5. The value of
the timing capacitor depends on internal resistive components and
current sources. When R

2

= 1.2kΩ and R4 = 0Ω, a very close

approximation of the correct capacitor value is:



O

F

STRAY

(ICO Constant) at 70MHz

The loop filter determines the general characteristics of the loop.
Capacitors C

9

, C10, and resistor R1, control the transient output of

the phase detector. Capacitor C

9

suppresses 70MHz feedthrough
by interaction with 100Ω load resistors internal to the phase
detector.

0.0014

C *

f

where

C *  C

2

 C

The temperature-compensation resistor, R4, affects the actual value
of capacitance. This equation is normalized to 70MHz. See 10 for
correction factors.

The loop filter determines the dynamic characteristics of the loop. In
most PLLs, the phase detector outputs are internally connected to
the ICO inputs. The NE568A was designed with filter output to input
connections from Pins 20 (φ DET) to 17 (ICO), and Pins 19 (φ DET)
to 18 (ICO) external. This allows the use of both series and shunt
loop-filter elements. The loop constratints are:

K

 0.12VRadian (Phase Detector Constant)

O

Radians

KO 4.2  10

9

V

–sec