NSC 5962R8973501VSA, 5962R8973501VRA, 5962R8973501V2A, 5962R8973501SA, 5962R8973501RA Datasheet
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54ACTQ273
Quiet Series Octal D Flip-Flop
General Description
TheACTQ273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all
storage elements.
The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO™output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n ICCreduced by 50
%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Buffered common clock and asynchronous master reset
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT273
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD)
5962-89735
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
MR
Master Reset
CP Clock Pulse Input
Q
0–Q7
Data Outputs
GTO™is a trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
DS100240-1
IEEE/IEC
DS100240-2
August 1998
54ACTQ273 Quiet Series Octal D Flip-Flop
© 1998 National Semiconductor Corporation DS100240 www.national.com
Connection Diagrams
Mode Select-Function Table
Operating Mode Inputs Outputs
MR
CP D
n
Q
n
Reset (Clear) L X X L
Load “1” H
N
HH
Load “0” H
N
LL
Note 1: H=HIGH Voltage Level
Note 2: L=LOW Voltage Level
Note 3: X=Immaterial
Note 4:
N
=
LOW-to-HIGH Transition
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100240-3
Pin Assignment
for LCC
DS100240-4
DS100240-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latch-up Source or
Sink Current
±
300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 5: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
Note 6: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
Symbol Parameter V
CC
T
A
=
−55˚C Units Conditions
(V) to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 4.5 2.0 V V
OUT
=
0.1V
Input Voltage 5.5 2.0 or V
CC
− 0.1V
V
IL
Maximum Low Level 4.5 0.8 V V
OUT
=
0.1V
Input Voltage 5.5 0.8 or V
CC
− 0.1V
V
OH
Minimum High Level 4.5 4.4 V I
OUT
=
−50 µA
Output Voltage 5.5 5.4
(Note 7)
V
IN
=
V
IL
or V
IH
4.5 3.7 V I
OH
=
−24 mA
5.5 4.7 I
OH
=
−24 mA
V
OL
Maximum Low Level 4.5 0.1 V I
OUT
=
50 µA
Output Voltage 5.5 0.1
(Note 7)
V
IN
=
V
IL
or V
IH
4.5 0.50 V I
OL
=
24 mA
5.5 0.50 I
OL
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
CCT
Maximum 5.5 1.6 mA V
I
=
V
CC
− 2.1V
I
CC
/Input
I
OLD
Minimum Dynamic
Output Current (Note 8)
5.5 50 mA V
OLD
=
1.65V Max
I
OHD
5.5 −50 mA V
OHD
=
3.85V Min
I
CC
Maximum Quiescent 5.5 80.0 µA V
IN
=
V
CC
Supply Current or GND (Note 9)
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