Nokia 2010 System Module

SYSTEM MODULE GS8

NHE–3

1298 OJ Technical Documentation

Contents of System Module GS8, GS8M

System Module GS8, GS8M 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documentation 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Technical Section 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External and Internal Connectors 8–3. . . . . . . . . . . . . . . . . . . . .

Bottom Connector X100 8–4. . . . . . . . . . . . . . . . . . . . . . . . . .

UIF Module Connector X584 8–5. . . . . . . . . . . . . . . . . . . . . .

SIM Card Connector 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Signals Between RF and ASIC 8–6. . . . . . . . . . . . . . .

Internal Signals Between RF and RFI 8–7. . . . . . . . . . . . . . . . .

Functional Description of Baseband Block 8–8. . . . . . . . . . . . . . .

Technical Specifications 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clocking Sceme 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reset and Power Control 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watchdog System 8–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Names of Functional Blocks 8–12. . . . . . . . . . . . . . . . . . . . . . . . .

CTRLU 8–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of CTRLU 8–12. . . . . . . . . . . . . . . . . . . . . .

Input Signals of CTRLU 8–13. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of CTRLU 8–14. . . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional Signals of CTRLU 8–14. . . . . . . . . . . . . . . . . . . .

Block Description of CTRLU 8–15. . . . . . . . . . . . . . . . . . . . . . .

PWRU 8–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of PWRU 8–18. . . . . . . . . . . . . . . . . . . . . .

Input Signals of PWRU 8–18. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of PWRU 8–18. . . . . . . . . . . . . . . . . . . . . . . . . .

Block Description of PWRU 8–19. . . . . . . . . . . . . . . . . . . . . . .

DSPU 8–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of DSPU 8–21. . . . . . . . . . . . . . . . . . . . . . .

Input Signals of DSPU 8–21. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . . . . .

Bidirectional Signals of DSPU 8–22. . . . . . . . . . . . . . . . . . . . .

Block Description of DSPU 8–22. . . . . . . . . . . . . . . . . . . . . . . .

AUDIO 8–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of AUDIO 8–23. . . . . . . . . . . . . . . . . . . . . .

Input Signals of AUDIO 8–23. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of AUDIO 8–23. . . . . . . . . . . . . . . . . . . . . . . . .

Block Description of AUDIO 8–24. . . . . . . . . . . . . . . . . . . . . . .

ASIC 8–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of ASIC 8–25. . . . . . . . . . . . . . . . . . . . . . . .

Input Signals of ASIC 8–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of ASIC 8–26. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1

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Bidirectional Signals of ASIC 8–27. . . . . . . . . . . . . . . . . . . . . .

Block Description of ASIC 8–27. . . . . . . . . . . . . . . . . . . . . . . . .

RFI 8–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Components of RFI 8–29. . . . . . . . . . . . . . . . . . . . . . . . .

Input Signals of RFI 8–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Signals of RFI 8–29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bidiractional Signals of RFI 8–30. . . . . . . . . . . . . . . . . . . . . . . .

Block Description of RFI 8–30. . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description of RF block 8–31. . . . . . . . . . . . . . . . . . . . . .

Regulators 8–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Distribution 8–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current Consumption 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter 8–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synthesizer 8–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram of Baseband 8–34. . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram of RF 8–35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Distribution Diagram 8–36. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connections between System and RF Blocks 8–37. . . . . . . . . . . .

Parts List of GS8 (for 8 Mb Flash) 8–38. . . . . . . . . . . . . . . . . . . . . .

Parts List of GS8M (for 4 Mb Flash) 8–50. . . . . . . . . . . . . . . . . . . .

8–2

SYSTEM MODULE GS8

NHE–3

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System Module GS8, GS8M

Introduction

GS8 is the baseband/RF module NHE–3 cellular tranceiver. The GS8 module

carries out all the system and RF functions of the tranceiver. System module

GS8 is designed for a handportable phone, that operate in GSM system.

Technical Section

8–3

All functional blocks of the system module are mounted on a single multi layer

printed circuit board. The chassis of the radio unit contains separating walls for

baseband and RF. All components of the baseband are surface mountable. The

connections to accessories are taken through the bottom connector of the radio

unit. The connections to the user interface module (UIF) are fed through a

board to board connector. There is no physical connector between RF and

baseband sections.

External and Internal Connectors

The system module has two connector, external bottom connector and internal

UIF module connector.

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Bottom Connector X100

Battery connector

Antenna connector

System connector

Charging connectors

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X100

9 18

SIM card connector

X584

UIF module connector

8–4

S0001049

System Connector

Pin: Name: Description:

1, 9 GND Digital ground

2 MIC_JCONN External audio input from accessories or

3 AGND Analog ground for accessories.

4 TDA Transmitted DBUS data to the accessories.

5 M2BUS Serial bidirectional data and control between

6 HOOK/RXD2 HOOK indication. The phone has a 100 kΩ

7 PHFS/TXD2 Handsfree device power on/off, data to flash

8, 16 VCHAR Battery charging voltage.

10 EAR_HFPWR External audio output to accessories or

handsfree microphone. Multiplexed with junction box connection control signal.

the handportable and accessories.

pull–up resistor.

programming device.

handsfree speaker. 11 DSYNC DBUS data bit sync clock 12 RDA DBUS received data from the accessories 13 BENA Power supply to headset adapter. 14 VF Programming voltage for FLASH. 15 DCLK DBUS data clock

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Battery Connector

Pin: Name: Description: 1 GND Ground

2 TBAT Battery temperature 3 BTYPE Battery type 4 VBATT Battery voltage

Charging Connector

Pin: Name: Description: 1 VCHAR Battery charging voltage

2 GND Ground 3 VCHAR Battery charging voltage 4 GND Ground

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Antenna Connector

Pin: Name: Description: 1 RF EXT External antenna signal

2 GND Ground

UIF Module Connector X584

Pin: Name: Description: 1 VL1 Logic supply voltage 4.65 V

2, 25 GND Ground 3, 30 VBATT Battery voltage 4 BACKLIGHT Backlights on/off 5 – 8 UIF(0;3) Lines for keyboard read and LCD controller 9 UIF4 Line for keyboard read and LCD drive

10 UIF5 Line for keyboard read and LCD driver

read/write strobe

data/command mode selection 11 UIF6 LCD driver chip select 12 UIF7 Busy signal from LCD driver to MCU 13 – 16 COL(0;3) Lines for keyboard read 17 UIF8 LCD driver reset 18 MICP Microphone (positive node)

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19 MICN Microphone (negative node) 20 EARP Earpiece (negative node) 21 EARN Earpiece (positive node) 22 BUZZER PWM signal buzzer control 23 XPWRON Power key (active low) 24 VA1 Analog supply voltage 4.65 V 26 MICENA Microphone bias enable 27 VIBRA Vibrating alert control 28, 29 AGND Analog ground

SIM Card Connector

Pin: Name: Description: 1 SIMCLK Clock for SIM data

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2 SIMRES Reset for SIM 3, 5 VSIM SIM voltage supply 4 GND Ground for SIM 6 SIMDATA Serial data for SIM

Internal Signals Between RF and ASIC

Symbol: Description: Values: SCLK Synthesizer clock

• load impedance:

• frequency:

SDATA Synthesizer data

• load impedance:

• data rate frequency:

SENAR RX synthesizer enable

• VHF PLL contr. disabled:

• VHF PLL activated:

• current:

10 k

Ω

3.25 MHz

10 k

Ω

3.25 MHz

4.5...4.65...4.8 V

0...0.2...0.7 V 50 µA

SENAT TX synthesizer enable

• UHF PLL contr. disabled:

• UHF PLL activated:

• current:

4.5...4.65...4.8 V

0...0.2...0.7 V 50 µA

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RXPWR RX supply voltage on/off

• RX supply voltage on:

• RX supply voltage off:

• current:

SYNTHPWR Supply voltage on/off

• RF regulators on:

• RF regulators off:

• current:

TXPWR TX supply voltage on/off

• TX supply voltage on:

• TX supply volatge off:

• current:

TXP TX enable

• transmitter power enable:

• transmitter power disable:

CLKIN 26 MHz clock to ASIC

8–7

4.5...4.65...4.8 V

0...0.2...0.7 V

0.5 mA

4.5...4.65...4.8 V

0...0.2...0.7 V

1.0 mA

4.5...4.65...4.8 V

0...0.2...0.7 V

0.5 mA

4.5...4.65...4.8 V

0...0.2...0.7 V

Internal Signals Between RF and RFI

Symbol: Description: Values: AFC Automatic frequency control voltage

• voltage min/max:

• resolution:

• load impedance (dynamic):

TXC TX transmit power control voltage

• voltage range min/max:

• impedance:

TXQP,TXQN Differential TX quadrature signal

• differential voltage swing:

• d.c. level:

• load impedance:

TXIP,TXIN Differential TX inphase signal

• differential voltage swing:

• d.c. level:

• load impedance:

PDATA0 Parallel AGC data

• reduced front end gain:

• normal front end gain:

• current:

0.35...4.35 V 11 bits 10 k

Ω

0.3...4.2 V 10 k

Ω

1.15...1.2...1.25 V

2.30...2.35...2.40 V 30 k

Ω

1.15...1.2...1.25 V

2.30...2.35...2.40 V 30 k

Ω

4.5...4.65...4.8 V

0...0.2...0.7 V

0.1 mA

PDATA1 Parallel AGC data

• AGC 3 dB reduction:

• normal front end gain:

• current:

4.5...4.65...4.8 V

0...0.2...0.7 V 10 µA

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PDATA2 Parallel AGC data

• AGC 6 dB reduction:

• normal front end gain:

• current:

PDATA3 Parallel AGC data

• AGC 12 dB reduction:

• normal front end gain:

• current:

PDATA4 Parallel AGC data

• AGC 24 dB reduction:

• normal front end gain:

• current:

PDATA5 Parallel AGC data

• AGC 12 dB reduction:

• normal front end gain:

• current:

RXQ RX quadrature signal

• output level:

• source impedance:

8–8

4.5...4.65...4.8 V

0...0.2...0.7 V 10 µA

4.5...4.65...4.8 V

0...0.2...0.7 V 10 µA

4.5...4.65...4.8 V

0...0.2...0.7 V 10 µA

4.5...4.65...4.8 V

0...0.2...0.7 V 10 µA

25 mV 470

Ω

RXI RX inphase signal

• output level:

• source impedance: 470 Ω

Functional Description of Baseband Block

The purpose of the baseband module is to control the phone and process audio signals to and from RF. The module also controls the user interface.

Technical Specifications

There are three different operation modes: – Active mode – Idle mode – Power off mode In the active state all the circuits are supplied with power and part of the mod-

ule might be in idle state. The module is usually in the idle mode when there is no call. In the idle mode

circuits are reset, powered down and clocks are stopped or the frequency reduced.

25 mV

In power off mode only the circuits needed for power up are supplied with power.

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Clocking Sceme

DSP Clock

60.2 MHz differential sine wave

ear

mouth

AUDIO CODEC

oscillator

DSP

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RFI Clock 13 MHz

Sleep Mode:

135.4kHz

enable

RFI

ASIC

8–9

RF System Clock

26 MHz

VCTCXO

SIMCLKSIMCLK

3.25 / 1.625 MHz

Codec Sync Clock

8 kHz

DBUSCLK 512kHz

DBUSSYNC 8kHz

Most of the clocks are generated from the 26 MHz VCTCXO frequency by the ASIC:

– 26 MHz clock for the MCU. MCU‘s internal clock frequency is half of that. – 13 MHz for the RFI. The ASIC also generates 135.4 kHz sleep mode clock

for the RFI

– 3.25 MHz clock for SIM. When there is no data transfer between the SIM

card and the HP the clock can be reduced to 1.625 MHz. Some SIM cards also allows the clock to be stopped in that mode

– 512 kHz main clock for the codec and for the data transfer between the

DSP and the codec

– 8 kHz syncronisation clock for data transfer between the DSP and the codec

Codec Main Clock and data Transfer clock

512kHz

MCU Clock

26 MHz

MCU

– 512 kHz clock and 8 kHz sync. clock for the DBUS data transfer. The DSP has its own crystal oscillator which can be turned off and on by the

ASIC. The DSP uses differential sinusoidal clock. The frequency is 60.2 MHz The MCU generates 8 kHz clock to the codec for the control data transfer. In

the idle mode all the clocks can be stopped except 26 MHz main clock coming from the VCTCXO.

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Reset and Power Control

reset in

DSP

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RFI

Reset Out Reset Out

ASIC

Vcc Reset in

resetreg

8–10

SIMReset

PSL+

VL1

XRES reset in

XPWRON

XPwrOff

approx 2Hz

There are three different ways to switch power on:

• Power key pressing grounds the XPWRON line. The PSL+ detects that and switches the power on.

• Charger detection on PSL+ detects that charger is connected and switches power on

• PSL+ will switch power on when the battery is connected. After that the MCU will detect if power key is pressed or charger connected. If not the power will be switched off

All devices are powered up at the same time by the PSL+. It supplies the reset to the ASIC at power up. The ASIC starts the clocks to the DSP and the MCU. After about 20 µs the ASIC releases the resets to MCU, RFI and DSP. MCU and RFI reset is released after 256 13 MHz clock cycles. DSP reset release time from DSP clock activation can be selected from 0 to 255 13MHz clock cycles. In our case it is 255. SIM reset release time is according to GSM SIM specifications.

XPWRON

MCU

To turn off power for the phone, the user presses the PWR key. The MCU detects this. The MCU cuts off any ongoing call, exits all tasks, acts inoperative to the user and leaves the PSL+ watchdog without resets. After power–down

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delay, the PSL+ cuts off the supply from all circuitry. If charging is on the phone stays on but it looks to the user like it is powered off (lights are off and the display is blank) except the charging indicator stays on.

Watchdog System

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reset

DSP

8–11

ASIC

POWER

PSL

XPWROFF

reset

MCU

Normal operation:

1. MCU tests DSP

2. MCU updates ASIC watchdog timer (> 2Hz)

3. MCU pulses the XPWROFF input on the PSL+ (about 2Hz) Failed operation:

4. ASIC resets MCU and DSP after about 0.5 s failure

5. PSL+ switches power off about1.5 s after the previous XPWROFF pulse

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Names of Functional Blocks

Name: Function: CTRLU Control unit for the phone

PWRU Power supply DSPU Digital signal processing block AUDIO Audio coding ASIC EDSA –asic RFI RF –baseband interface

CTRLU

The Control block contains a microcomputer unit (MCU) and three memory circuits (FLASH, SRAM, EEPROM), a 20 bit address bus and an 8 bit data bus.

Main Features of the CTRLU block:

8–12

MCU functions: – system control – communication control – user interface functions – authentication – RF monitoring – power up/down control – accessory monitoring – batttery monitoring and charging control – self–test and production testing – flash loading

Main Components of CTRLU

– Hitachi H8/536

H8/536 is a CMOS microcomputer unit (MCU) comprising a CPU core and on–chip supporting modules with 16 bit architecture. The data bus to outside world has 8 bits.

– 1024 k x 8 bit FLASH memory

– 100 ns maximum read access time. – contains the main program code for the MCU; part of the DSP

program code locates also in FLASH.

– ASIC can address two 4 Mbit memories or one 8 Mbit memory.

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– 32 k x 8 bit SRAM memory

– 100 ns maximum read access time.

– 8 k x 8 bit EEPROM memory

– 150 ns maximum read access time. – contains user defined information. – there is a register bit on the ASIC which must be set before the

Input Signals of CTRLU

Name(from): Description: VL1(PWRU) Power supply voltage for CTRLU block

VREF(PWRU) Reference voltage for MCU A/D converter VBATDET(PWRU) Battery voltage detection

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write operation to the EEPROM.

8–13

VC(PWRU) Charger voltage monitoring EROMSELX(ASIC) Chip select for the EEPROM memory ROMSELX(ASIC) Chip select for the FLASH memory ROM2SELX(ASIC) Chip select for the 2nd FLASH memory RAMSELX(ASIC) Chip select for the SRAM memory RESETX(ASIC) Reset signal for MCU NMI(ASIC) Non–maskable interrupt request MCUCLK(ASIC) Main clock for MCU IRQX(ASIC) Interrup request PCMCDO(AUDIO) Audio codec control data receiving TRF(RF) RF module temperature detection VF(system conn.) Programming voltage for FLASH memory RXD2_HOOK The use of handsfree monitoring

(system conn.) FLASH programming data input on the production line TBAT(batt.conn.) Battery temperature detection BTYPE(batt.conn.) Battery size identification JCON(syst.conn.) Junction box connection identification

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Output Signals of CTRLU

Name(to): Description: XPWROFF(PWRU) Power off control, PSL+ watchdog reset

PWM(PWRU) Charger on/off control WSTROBEX(ASIC) MCU write strobe RSTROBEX(ASIC) MCU read strobe MCUAD(19:0)(ASIC)20 bit MCU address bus MBUSDET(ASIC) MBUS activity detection PCMCLK(AUDIO) Clock for audio cedec control data transfer PCMCDI(AUDIO) Audio codec control data transmitting XSELPCMC(AUDIO)Chip select for audio codec TXD2_PHFS Power on/off control for HF device, verification output

(syst.connector) of the programmed data of FLASH during programming

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8–14

UIF8(UIF) reset for display driver BACKLIGHT(UIF) LCD and display backlight on/off control BUZZER(UIF) Buzzer signal VIBRA(UIF) Vibrating alert control

Bidirectional Signals of CTRLU

Name(to/from): Description: MCUDA(7;0)(ASIC) MCU’s 8 bit data bus

M2BUS Asyncronous serial data bus

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Block Description of CTRLU

– MCU – memories

MCU has a 20 bits wide address bus A(19:0) and an 8 bit data bus with memories. The address bits A(19:16) are used for chip select decoding. The decoding is done in ESA asic.The ASIC can address two 4 Mbit (or smaller) or one 8 Mbit flash memories. Hitachi HD647536 processor has internal ROM and RAM memories.

On the Hitachi HD647536 internal memory map there is the following:

• 00000 – 001FF vector tables

• 00000 – 0F67F 62 kbytes internal ROM

• 0F680 – 0FE7F 2 kbytes internal RAM

• 0FE80 – 0FFFF 384 bytes registers

External memory map is the following:

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8–15

• 10000 – 1FFFF 32 k * 8 bytes RAM

• 20000 – 21FFF 8 k * 8 bytes EEROM

• 30000 – 3FFFF 26 * 8 bytes ASIC

• 40000 – 7FFFF 2 Mbit bytes FlashROM

• 80000 – BFFFF 4 Mbit bytes FlashROM

Chip select generation: Chip: Page: A19: A18: A17: A16:

RAM X 0 0 0 1 EEPROM X 0 0 1 0 ASIC X 0 0 1 1 FLASH1 0 0 1 X X FLASH1 1 0 1 X X FLASH2 or X 1 X X X FLASH1 if 8 Mbit flash used

– Flash programming

In flash programming a special flash programming box and a PC is needed. Loading is done through the bottom connector of HP; multiplexed with HOOK and PHFS line. First MCU goes to minimum mode (MBUS command from PC or if MBUS is connected to MIC_JCONN line in power up). Then the flash software is loaded from PC to flash loading box. When the loading is complete flash loading to HP can be started by MBUS command from PC to the MCU. After that the MCU asks the test box to start flash loading to HP.

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The box supplies 12 V programming voltage for flash and starts to send 250 bytes data blocks to the MCU via HOOK line. The baud rate is 406 kbit/s. The MCU calculates the check sum, sends acknowledge via PHFS line and sends the data to flash. When all the data is loaded the HP makes reset and tells the flash loading box if the loading was succeeded or not. Only PSL+, ASIC and MCU must be active during the loading.

– CTRLU – PWRU

MCU controls the watchdog timer in PSL+. It sends a positive pulse at approximately 2 Hz to XPWROFF pin of the PSL+ to keep the power on. If MCU fails to deliver this pulse, the PSL+ will remove power from the system. MCU controls also the charger on/off switching in the PWRU block. When power off is requested MCU leaves PSL+ watchdog without reset. After the watchdog has elapsed PSL+ cuts off the supply voltages from the phone.

– CTRLU – ASIC

MCU and ASIC have a common 8 bit data bus and a 9 bit address bus. A(4:0) are used for normal addressing whereas bits A(19:16) are decoded in ASIC to chip select inputs for CTRLU memories. ASIC controls the main clock, main reset and interrupts to MCU. The internal clock of MCU is half the MCUCLK clock speed. RESETX resets everything in MCU except the contents of the RAM. IRQX is general purpose interrupt request line from ASIC. After IRQX request the interrupt register of asic is read to find out the reason for interrupt. NMI interrupt is used only to wake up MCU from software standby mode.

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– CTRLU – DSPU

MCU and DSP communicate through ASIC. ASIC has MCU mailbox and DSP mailbox. MCU writes data to DSP mailbox where DSP can only read the incoming data. In MCU mailbox data transfer direction is opposite. When power is switched on the MCU loads data from the flash memory to DSP‘s external memory through this mailbox.

– CTRLU – AUDIO

When the the chip select signal XSELPCMC goes low, MCU writes or reads control data to or from the speech codec registers at the rate defined by PCMCLK. PCMCDI is an output data line from MCU to codec and PCMCDO is an input data line from codec to MCU.

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– CTRLU – RF/BATTERY monitoring

MCU has internal 8 channel 10 bit AD converter. Following signals are used to monitor battery, charging and RF:

• BTYPE; battery size

• TBAT; battery temperature

• VBATDET; battery voltage

• VC; charging voltage

• TRF; RF temperature

– CTRLU – keyboard and LCD driver interface

MCU and user interface communication is controlled through ASIC.

– CTRLU – ACCESSORIES

M2BUS is used to control external accessories. This interface can be used also to factory testing and service and maintenance purposes.

There are also some control and indication signals for the accessories:

8–17

• PHFS is used to turn power on to HF accessories

• JCONN is used to indicate that junction box is connected. Phone

can also enter minimum mode when M2BUS is connected to MIC_JCONN line.

• HOOK is used to indicate accessories hook state

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NHE–3

PWRU

The power block creates the supply voltages for the baseband block and contains the charging electronics.

Main Components of PWRU

– PSL + ASIC

Generates the voltages, has power switch, charger and battery detection and watchdog.

– Transistor BCP69–25 and schottky STPS340U

The charging current is passed through these components.

– Transistor BCX51 and BCP69–25

VL regulators of PSL+ external output transistors.

Input Signals of PWRU

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Name(from): Description: XPWRON(UIF) PWR on swith

XPWROFF(CTRLU) Power off control VBATT(batt.conn.) Battery voltage PWM(CTRLU) Charger on/off control VCHAR(syst.conn.) Charging voltage

Output Signals of PWRU

Name(from): Description: XRES(ASIC) Master reset

VL1(CTRLU,ASIC, Logic supply voltage, max 150 mA RFI,UIF)

VL2(DSPU) Logic supply voltage, max 150 mA VA1(AUDIO,UIF) Analog supply voltage, max 40 mA VA2(RFI) Analog supply voltage, max 80 mA VREF(CTRLU,RF) Reference voltage 4.65 V ±2 %, max 5 mA VBATDEF(CTRLU) Switched VBATT divided by 2 VC(CTRLU) Attenuator VCHAR

SYSTEM MODULE GS8

NHE–3

Block Description of PWRU

The PSL+ IC produces the supply voltages: Name: Description:

2 * VL 150 mA for logic VA1 40 mA for audios VA2 80 mA for RFI VREF 5 mA reference In addition, It has internal watchdog, voltage detection and charger detection

functions. The watchdog will cut off output voltages if it is not reset once in every 1.5 〈±0.75) second. The voltage detector resets the phone if the battery voltage falls below 4.8 V (±0.2 V). The charger detection starts the phone if it is in power–off state when the charging voltage is applied.

The charging electronics is controlled by the MCU. When the charging voltage is applied to the phone and the phone is powered up, the MCU detects it and starts controlling the charging. If MCU detects too high charging voltage (over 14 volts) or current (over 78 A/D bit difference between VC and VBATDET) it will cut off the charging. The phone will accept charging voltages from 5 to 14 volts.

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If the phone is in power–off state, the PSL+ will detect the charging voltage and start the phone. If the battery voltage is high enough the reset will be released and the MCU will start controlling charging.

If the battery voltage is too low the phone stays in reset state and charging control circuitry will pass small charging current to the battery. When the battery voltage has reached 5.25 V (±0.2 V) the reset will be removed and the MCU starts controlling the charging.

MCU controls the charging with pulse width modulation output. Charging voltage is limited by hardware in normal operation to 8.9 V and during a call to 7.6 V.

Battery and charging voltages are calibrated in production; 6 V is fed to the battery and charger pin and the MCU‘s A/D converter values are stored to EEPROM

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