NEC Electronics Inc UPA1727 Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

μPA1727

SWITCHING

N-CHANNEL POWER MOS FET

INDUSTRIAL USE

DESCRIPTION

The μPA1727 is N-Channel MOS Field Effect Transistor designed for high current switching applications.

FEATURES

∙Single chip type

∙Low On-state Resistance

RDS(on)1 = 14 mΩ (TYP.) (VGS = 10 V, ID = 5.0 A)

RDS(on)2 = 17 mΩ (TYP.) (VGS = 4.5 V, ID = 5.0 A)

RDS(on)3 = 19 mΩ (TYP.) (VGS = 4.0 V, ID = 5.0 A)

∙ Low Ciss : Ciss = 2400 pF (TYP.)

∙Built-in G-S protection diode

∙Small and surface mount package (Power SOP8)

PACKAGE DRAWING (Unit : mm)

8 5

1, 2, 3	;	Source
4	;	Gate
5, 6, 7, 8 ;		Drain

		1		4		6.0 ±0.3
						4.4
	Max.1.8	1.44	5.37 Max.	0.15			0.8
				+0.10	–0.05
		Min.				0.5 ±0.2
			1.27	0.78 Max.			0.10
		0.05	0.40 –0.05+0.10		0.12 M

ORDERING INFORMATION

PART NUMBER	PACKAGE
μPA1727	Power SOP8

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, All terminals are connected.)

Drain to Source Voltage (VGS = 0 V)

VDSS

60

V

EQUIVALENT CIRCUIT

Gate to Source Voltage (VDS = 0 V)

VGSS

±20

V

Drain Current (DC)

ID(DC)

±10

A

Drain

Drain Current (Pulse) Note1

ID(pulse)

±40

A

Body

Total Power Dissipation (TA = 25 °C) Note2

PT

2.0

W

Gate

Diode

Channel Temperature

Tch

150

°C

Storage Temperature

Tstg

–55 to + 150

°C

Gate

Single Avalanche Current Note3

IAS

10

A

Protection

Source

Diode

Single Avalanche Energy Note3

EAS

200

mJ

Notes 1. PW ≤ 10 μs, Duty cycle ≤ 1 %

2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm 3. Starting Tch = 25 °C, R G = 25 Ω, VGS = 20 V → 0 V

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage Exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G14330EJ1V0DS00 (1st edition) Date Published January 2000 NS CP(K) Printed in Japan

The mark shows major revised points.	©	1999,2000

μPA1727

ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)

CHARACTERISTICS	SYMBOL	TEST CONDITIONS	MIN.	TYP.	MAX.	UNIT
Drain to Source On-state Resistance	RDS(on)1	VGS = 10 V, ID = 5.0 A		14	19	mΩ
	RDS(on)2	VGS = 4.5 V, ID = 5.0 A		17	22	mΩ
	RDS(on)3	VGS = 4.0 V, ID = 5.0 A		19	25	mΩ
Gate to Source Cut-off Voltage	VGS(off)	VDS = 10 V, ID = 1 mA	1.5	2.0	2.5	V
Forward Transfer Admittance	| yfs |	VDS = 10 V, ID = 5.0 A	8.0	14		S
Drain Leakage Current	IDSS	VDS = 60 V, VGS = 0 V			10	μA
Gate to Source Leakage Current	IGSS	VGS = ±20 V, VDS = 0 V			±10	μA
Input Capacitance	Ciss	VDS = 10 V		2400		pF
Output Capacitance	Coss	VGS = 0 V		400		pF
Reverse Transfer Capacitance	Crss	f = 1 MHz		200		pF
Turn-on Delay Time	td(on)	ID = 5.0 A		24		ns
Rise Time	tr	VGS(on) = 10 V		120		ns
Turn-off Delay Time	td(off)	VDD = 30 V		120		ns
		RG = 10 Ω
Fall Time	tf			71		ns
Total Gate Charge	QG	ID = 10 A		45		nC
Gate to Source Charge	QGS	VDD = 48 V		5.9		nC
Gate to Drain Charge	QGD	VGS = 10 V		13		nC
Body Diode Forward Voltage	VF(S-D)	IF = 10 A, VGS = 0 V		0.8		V
Reverse Recovery Time	trr	IF = 10 A, VGS = 0 V		45		ns
		di/dt = 100A/μs
Reverse Recovery Charge	Qrr			84		nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY		TEST CIRCUIT 2 SWITCHING TIME

D.U.T.
RG = 25 Ω	L		D.U.T.
					VGS
PG.				RL				90 %
				VGS			VGS(on)
50 Ω	VDD				10 %
			RG	Wave Form
VGS = 20 → 0 V				VDD	0
			PG.
					ID	90 %		90 %
	BVDSS						ID
IAS		VGS		ID	0 10 %			10 %
	VDS
		0
ID				Wave Form
					td(on)	tr	td(off)	tf
VDD			τ
			τ = 1 μs			ton		toff
	Starting Tch		Duty Cycle ≤ 1 %

TEST CIRCUIT 3 GATE CHARGE

	D.U.T.
	IG = 2 mA	RL
PG.	50 Ω	VDD

2	Data Sheet G14330EJ1V0DS00