DATA SHEET
Compound Field Effect Power Transistor
μPA1572B
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DESCRIPTION |
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PACKAGE DIMENSIONS |
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The μPA1572B is N-channel Power MOS FET Array |
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in millimeters |
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that built in 4 circuits designed for solenoid, motor and |
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lamp driver. |
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26.8 MAX. |
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4.0 |
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FEATURES |
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10 |
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∙ Full Mold Package with 4 Circuits |
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10 MIN. |
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∙ 4 V driving is possible |
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2.5 |
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∙ Low On-state Resistance |
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RDS(on) = 0.6 Ω MAX. (VGS = 10 V, ID = 1 A) |
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2.54 |
1.4 |
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RDS(on) = 0.8 Ω MAX. (VGS = 4 V, ID = 1 A) |
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0.5±0.1 |
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1.4 |
0.6±0.1 |
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∙ Low Input Capacitance Ciss = 110 pF TYP. |
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ORDERING INFORMATION |
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1 2 3 4 5 6 7 8 910 |
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Type Number |
Package |
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CONNECTION DIAGRAM |
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μPA1572BH |
10Pin SIP |
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3 |
5 |
7 |
9 |
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2 |
4 |
6 |
8 |
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1 |
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10 |
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ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) |
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ELECTRODE CONNECTION |
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Drain to Source Voltage (VGS = 0) |
VDSS |
60 |
V |
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2, 4, 6, 8 : Gate |
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Gate to Source Voltage (VDS = 0) |
VGSS (AC) |
±20 |
V |
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3, 5, 7, 9 : Drain |
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Drain Current (DC) |
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ID (DS) |
±2.0 |
A/unit |
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1, 10 |
: Source |
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Drain Current (pulse) |
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ID (pulse) *1 |
±6.0 |
A/unit |
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Total Power Dissipation |
PT1 *2 |
20 |
W |
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Total Power Dissipation |
PT2 *3 |
3.0 |
W |
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Channel Temperature |
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TCH |
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150 |
°C |
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Storage Tempreature |
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Tstg |
−55 to +150°C |
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Single Avalanche Current |
IAS *4 |
5.0 |
A |
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Single Avalanche Energy |
EAS *4 |
0.1 |
mJ |
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*1 |
PW ≤ 10 μs, Duty Cycle ≤ 1 % |
*2 |
4 Circuits TC = 25 °C |
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*3 |
4 Circuits TA = 25 °C |
*4 |
Starting TCH = 25 °C, VDD = 30 V, VGS = 20 V → 0, RG = 25 Ω, L = 100 μH |
Build-in Gate Diodes are for protection from static electricity in handing.
In case high voltage over VGSs is applied, please append gate protection circuits.
The information in this document is subject to change without notice.
Document No. G11177EJ1V0DS00 (1st edition)
Date Published May 1996 P
Printed in Japan
© 1996
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μPA1572B |
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ELECTRICAL CHARACTERISTICS (TA = 25 °C) |
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CHARACTERISTIC |
SYMBOL |
MIN. |
TYP. |
MAX. |
UNIT |
TEST CONDITION |
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Drain Leakage Current |
IDSS |
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10 |
μA |
VDS = 60 V, VGS = 0 |
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Gate Leakage Current |
IGSS |
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±10 |
μA |
VGS = ±20 V, VDS = 0 |
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Gate Cutoff Voltage |
VGS (off) |
1.0 |
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2.0 |
V |
VDS = 10 V, ID = 1.0 mA |
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Forward Transfer Admittance |
ïYfsï |
0.5 |
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S |
VDS = 10 V, ID = 1.0 A |
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Drain to Source ON-Resistance |
RDS (on)1 |
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0.3 |
0.6 |
W |
VGS = 10 V, ID = 1.0 A |
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Drain to Sourse ON-Resistance |
RDS (on)2 |
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0.4 |
0.8 |
W |
VGS = 4.0 V, ID = 1.0 A |
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Input Capacitance |
Ciss |
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110 |
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pF |
VDS = 10 V, VGS = 0, f = 1.0 MHz |
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Output Capacitance |
Coss |
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70 |
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pF |
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Reverse Transfer Capacitance |
Crss |
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25 |
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pF |
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Turn-on Delay Time |
td (on) |
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30 |
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ns |
ID = 1.0 A, VGS (on) = 10 V, VDD = 30 V, RL = 30 W |
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Rise Time |
tr |
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200 |
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ns |
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Turn-off Delay Time |
td (off) |
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100 |
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ns |
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Fall Time |
tf |
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160 |
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ns |
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Total Gate Charge |
QG |
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5.4 |
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nC |
VGS = 10 V, ID = 2.0 A, VDD = 48 V |
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Gate to Source Charge |
QGS |
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0.7 |
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nC |
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Gate to Drain Charge |
QGD |
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2.0 |
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nC |
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Body Diode Forward Voltage |
VF (S-D) |
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1.0 |
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V |
IF = 2.0 A, VGS = 0 |
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Reverse Recovery Time |
trr |
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130 |
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IF = 2.0 A, VGS = 0, di/dt = 50 A/μs |
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Reverse Recovery Charge |
Qrr |
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110 |
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nC |
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2
μPA1572B
Test Circuit 1 Avalanche Capability
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D.U.T. |
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RG = 25 Ω |
L |
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PG. |
50 |
Ω |
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VGS = 20 V → 0 |
VDD |
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BVDSS |
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IAS |
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ID |
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VDS |
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VDD |
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Starting TCH
Test Circuit 2 Switching Time
D.U.T.
RG
PG.
RG = 10 Ω
VGS
0
t
t = 1 μ s
Duty Cycle ≤ 1 %
RL |
VGS |
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90 % |
VGS |
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10 % |
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VGS (on) |
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0 |
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Wave From |
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VDD |
ID |
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90 % |
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90 % |
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ID |
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ID |
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10 % |
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10 % |
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0 |
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Wave From |
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td (on) |
tr |
td (off) |
tr |
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ton |
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toff |
Test Circuit 3 Gate Charge
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D.U.T. |
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IG = 2 mA |
RL |
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PG. |
50 |
Ω |
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VDD |
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3