NEC Electronics Inc UPA1572BH Datasheet

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NEC Electronics Inc UPA1572BH Datasheet

DATA SHEET

Compound Field Effect Power Transistor

μPA1572B

N-CHANNEL POWER MOS FET ARRAY

SWITCHING

INDUSTRIAL USE

DESCRIPTION

 

 

 

 

PACKAGE DIMENSIONS

The μPA1572B is N-channel Power MOS FET Array

 

in millimeters

 

that built in 4 circuits designed for solenoid, motor and

 

 

 

 

 

 

lamp driver.

 

 

 

 

 

26.8 MAX.

 

4.0

 

 

 

 

 

 

 

 

FEATURES

 

 

 

 

10

 

 

 

Full Mold Package with 4 Circuits

 

 

 

 

 

 

 

 

 

 

 

 

10 MIN.

4 V driving is possible

 

 

 

 

2.5

 

 

Low On-state Resistance

 

 

 

 

 

RDS(on) = 0.6 Ω MAX. (VGS = 10 V, ID = 1 A)

 

 

 

2.54

1.4

RDS(on) = 0.8 Ω MAX. (VGS = 4 V, ID = 1 A)

 

 

 

0.5±0.1

 

1.4

0.6±0.1

 

Low Input Capacitance Ciss = 110 pF TYP.

 

 

 

 

 

ORDERING INFORMATION

 

 

 

1 2 3 4 5 6 7 8 910

 

 

 

 

 

 

 

 

 

Type Number

Package

 

 

 

CONNECTION DIAGRAM

 

μPA1572BH

10Pin SIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

5

7

9

 

 

 

 

 

 

2

4

6

8

 

 

 

 

 

 

1

 

 

10

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

 

 

ELECTRODE CONNECTION

Drain to Source Voltage (VGS = 0)

VDSS

60

V

 

2, 4, 6, 8 : Gate

Gate to Source Voltage (VDS = 0)

VGSS (AC)

±20

V

 

3, 5, 7, 9 : Drain

Drain Current (DC)

 

ID (DS)

±2.0

A/unit

 

1, 10

: Source

 

 

 

 

Drain Current (pulse)

 

ID (pulse) *1

±6.0

A/unit

 

 

 

Total Power Dissipation

PT1 *2

20

W

 

 

 

Total Power Dissipation

PT2 *3

3.0

W

 

 

 

Channel Temperature

 

TCH

 

150

°C

 

 

 

Storage Tempreature

 

Tstg

55 to +150°C

 

 

 

Single Avalanche Current

IAS *4

5.0

A

 

 

 

Single Avalanche Energy

EAS *4

0.1

mJ

 

 

 

*1

PW 10 μs, Duty Cycle 1 %

*2

4 Circuits TC = 25 °C

 

 

 

*3

4 Circuits TA = 25 °C

*4

Starting TCH = 25 °C, VDD = 30 V, VGS = 20 V 0, RG = 25 Ω, L = 100 μH

Build-in Gate Diodes are for protection from static electricity in handing.

In case high voltage over VGSs is applied, please append gate protection circuits.

The information in this document is subject to change without notice.

Document No. G11177EJ1V0DS00 (1st edition)

Date Published May 1996 P

Printed in Japan

© 1996

 

 

 

 

 

 

 

μPA1572B

 

 

 

 

 

 

 

 

 

 

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHARACTERISTIC

SYMBOL

MIN.

TYP.

MAX.

UNIT

TEST CONDITION

 

 

Drain Leakage Current

IDSS

 

 

10

μA

VDS = 60 V, VGS = 0

 

 

 

 

 

 

 

 

 

 

 

Gate Leakage Current

IGSS

 

 

±10

μA

VGS = ±20 V, VDS = 0

 

 

Gate Cutoff Voltage

VGS (off)

1.0

 

2.0

V

VDS = 10 V, ID = 1.0 mA

 

 

 

 

 

 

 

 

 

 

 

Forward Transfer Admittance

ïYfsï

0.5

 

 

S

VDS = 10 V, ID = 1.0 A

 

 

 

 

 

 

 

 

 

 

 

Drain to Source ON-Resistance

RDS (on)1

 

0.3

0.6

W

VGS = 10 V, ID = 1.0 A

 

 

 

 

 

 

 

 

 

 

 

Drain to Sourse ON-Resistance

RDS (on)2

 

0.4

0.8

W

VGS = 4.0 V, ID = 1.0 A

 

 

 

 

 

 

 

 

 

 

 

Input Capacitance

Ciss

 

110

 

pF

VDS = 10 V, VGS = 0, f = 1.0 MHz

 

 

 

 

 

 

 

 

 

 

 

Output Capacitance

Coss

 

70

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

Reverse Transfer Capacitance

Crss

 

25

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

Turn-on Delay Time

td (on)

 

30

 

ns

ID = 1.0 A, VGS (on) = 10 V, VDD = 30 V, RL = 30 W

 

 

 

 

 

 

 

 

 

 

 

Rise Time

tr

 

200

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Turn-off Delay Time

td (off)

 

100

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Fall Time

tf

 

160

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

Total Gate Charge

QG

 

5.4

 

nC

VGS = 10 V, ID = 2.0 A, VDD = 48 V

 

 

 

 

 

 

 

 

 

 

 

Gate to Source Charge

QGS

 

0.7

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

Gate to Drain Charge

QGD

 

2.0

 

nC

 

 

 

 

 

 

 

 

 

 

 

 

Body Diode Forward Voltage

VF (S-D)

 

1.0

 

V

IF = 2.0 A, VGS = 0

 

 

 

 

 

 

 

 

 

 

 

Reverse Recovery Time

trr

 

130

 

ns

IF = 2.0 A, VGS = 0, di/dt = 50 A/μs

 

 

 

 

 

 

 

 

 

 

 

Reverse Recovery Charge

Qrr

 

110

 

nC

 

 

2

μPA1572B

Test Circuit 1 Avalanche Capability

 

 

D.U.T.

 

 

RG = 25 Ω

L

PG.

50

Ω

 

VGS = 20 V 0

VDD

 

 

 

 

 

BVDSS

 

 

IAS

 

 

ID

 

VDS

 

VDD

 

 

Starting TCH

Test Circuit 2 Switching Time

D.U.T.

RG

PG.

RG = 10 Ω

VGS

0

t

t = 1 μ s

Duty Cycle 1 %

RL

VGS

 

 

 

90 %

VGS

 

10 %

 

VGS (on)

0

 

 

Wave From

 

 

 

 

 

 

 

 

 

VDD

ID

 

90 %

 

90 %

 

 

 

 

 

 

 

 

ID

ID

 

10 %

 

10 %

0

 

 

Wave From

 

 

 

 

 

 

 

 

 

 

 

td (on)

tr

td (off)

tr

 

 

 

ton

 

toff

Test Circuit 3 Gate Charge

 

 

D.U.T.

 

 

IG = 2 mA

RL

PG.

50

Ω

 

 

VDD

 

 

 

3

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