NEC Electronics Inc UPA1523BH Datasheet
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DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
μPA1523B
P-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DESCRIPTION
The μPA1523B is P-channel Power MOS FET Array that built in 4 circuits designed for solenoid, motor and lamp driver.
FEATURES
•Full Mold Package with 4 Circuits
•–4 V driving is possible
•Low On-state Resistance
RDS(on)1 = 0.8 Ω MAX. (@VGS = –10 V, ID = –1 A) RDS(on)2 = 1.3 Ω MAX. (@VGS = –4 V, ID = –1 A)
•Low Input Capacitance Ciss = 190 pF TYP.
ORDERING INFORMATION
Type Number |
Package |
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μPA1523BH |
10 Pin SIP |
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ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Drain to Source Voltage (VGS = 0) |
VDSS |
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–60 |
V |
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Gate to Source Voltage (VDS = 0) |
VGSS(AC) |
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± |
20 |
V |
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Drain Current (DC) |
ID(DC) |
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± |
2.0 |
A/unit |
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Drain Current (pulse) |
ID(pulse) |
*1 |
± |
8.0 |
A/unit |
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Total Power Dissipation |
PT1 |
*2 |
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28 |
W |
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Total Power Dissipation |
PT2 |
*3 |
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3.5 |
W |
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Channel Temperature |
TCH |
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150 |
˚C |
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Storage Temperature |
Tstg |
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–55 to + 150 |
˚C |
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Single Avalanche Current |
IAS |
*4 |
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–2.0 |
A |
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Single Avalanche Energy |
EAS |
*4 |
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0.4 |
mJ |
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PACKAGE DIMENSIONS |
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in millimeters |
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26.8 MAX. |
4.0 |
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10 |
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2.5 |
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10 MIN. |
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2.54 |
1.4 |
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1.4 0.6 ± 0.1 |
0.5 ± 0.1 |
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1 2 3 4 5 6 7 8 910 |
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CONNECTION DIAGRAM |
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3 |
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5 |
7 |
9 |
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2 |
4 |
6 |
8 |
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1 |
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10 |
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ELECTRODE CONNECTION |
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2, 4, 6, 8 : Gate |
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3, 5, 7, 9 : Drain |
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1, 10 |
: Source |
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*1 |
PW ≤ 10 μs, Duty Cycle ≤ 1% |
*2 |
4 Circuits, TC = 25 ˚C |
*3 |
4 Circuits, TA = 25 ˚C |
*4 |
Starting TCH = 25 ˚C, VDD = –30 V, VGS = –20 V → 0, RG = 25 Ω, |
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L = 100 μH |
Build-in Gate Diodes are for protection from static electricity in handing.
In case high voltage over VGSS is applied, please append gate protection circuits.
The information in this document is subject to change without notice.
Document No. |
G11331EJ1V0DS00 |
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Date Published |
May 1996 P |
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Printed in Japan |
© |
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1996 |
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μPA1523B
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
CHARACTERISTIC |
SYMBOL |
TEST CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Drain Leakage Current |
IDSS |
VDS = –60 V, VGS = 0 |
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–10 |
μA |
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Gate Leakage Current |
IGSS |
VGS = 20 V, VDS = 0 |
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10 |
μA |
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± |
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± |
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Gate Cutoff Voltage |
VGS(off) |
VDS = –10 V, ID = –1.0 mA |
–1.0 |
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–2.0 |
V |
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Forward Transfer Admittance |
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VDS = –10 V, ID = –1.0 A |
0.8 |
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S |
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Drain to Source ON-Resistance |
RDS(on)1 |
VGS = –10 V, ID = –1.0 A |
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0.5 |
0.8 |
Ω |
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Drain to Source ON-Resistance |
RDS(on)2 |
VGS = –4.0 V, ID = –1.0 A |
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0.8 |
1.3 |
Ω |
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Input Capacitance |
Ciss |
VDS = –10 V, VGS = 0, f = 1.0 MHz |
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190 |
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pF |
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Output Capacitance |
Coss |
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115 |
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pF |
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Reverse Transfer Capacitance |
Crss |
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43 |
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pF |
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Turn-on Delay Time |
td(on) |
ID = –1.0 A, VGS(on) = –10 V, |
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8 |
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ns |
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. |
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Rise Time |
tr |
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53 |
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ns |
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VDD =. –30 V, RL = 30 Ω |
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Turn-off Delay Time |
td(off) |
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400 |
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ns |
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Fall Time |
tf |
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230 |
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ns |
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Total Gate Charge |
QG |
VGS = –10 V, ID = –2.0 A, VDD = –48 V |
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10 |
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nC |
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Gate to Source Charge |
QGS |
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1.1 |
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nC |
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Gate to Drain Charge |
QGD |
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3.5 |
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nC |
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Body Diode Forward Voltage |
VF(S-D) |
IF = 2.0 A, VGS = 0 |
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1.0 |
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V |
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Reverse Recovery Time |
trr |
IF = 2.0 A, VGS = 0, di/dt = 50 A/μs |
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180 |
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ns |
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Reverse Recovery Charge |
Qrr |
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250 |
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nC |
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2
μPA1523B
Test Circuit 1 Avalanche Capability
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D.U.T. |
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RG = 25 Ω |
L |
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PG. |
50 |
Ω |
VDD |
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VGS = –20 V → 0 |
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BVDSS
IAS
VDS
ID
VDD
Starting TCH
Test Circuit 2 Switching Time
D.U.T. 
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RL |
VGS |
VGS |
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90 % |
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RG |
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Wave |
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0 10 % |
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VGS(on) |
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Form |
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PG. |
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RG = 10 Ω |
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VDD |
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ID (—) |
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90 % |
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90 % |
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ID |
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ID |
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10 % |
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10 % |
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0 |
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VGS |
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Wave |
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td(on) |
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tr |
td(off) |
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tf |
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t |
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ton |
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toff |
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t = 1 μ s |
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Duty cycle ≤ 1 % |
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Test Circuit 3 Gate Charge
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D.U.T. |
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IG = 2 mA |
RL |
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PG. |
Ω |
VDD |
50 |
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3