NEC UPA1790G Datasheet

DATA SHEET

MOS FIELD EFFECT TRANSISTOR

SWITCHING

N-AND P-CHANNEL POWER MOS FET

INDUSTRIAL USE

PA1790

µµµµ

DESCRIPTION

This product is N-and P-Channel MOS Field Effect Transistor designed for motor driver applications.

FEATURES

Dual chip type

•

Low on-resistance

•

N-Channel R

P-Channel R

Low input capacitance

•

N-Channel C P-Channel C Built-in G-S protection diode

•

Small and surface mount package (Power SOP8)

•

DS(on)1

= 0.12 Ω TYP. (VGS = 10 V, ID = 0.5 A)

DS(on)2

R

= 0.19 Ω TYP. (VGS = 4 V, ID = 0.5 A)

DS(on)1

= 0.45 Ω TYP. (VGS = –10 V, ID = –0.35 A)

DS(on)2

R

= 0.74 Ω TYP. (VGS = –4 V, ID = –0.35 A)

iss

= 180 pF TYP.

iss

= 230 pF TYP.

ORDERING INFORMATION

PART NUMBER PACKAGE

PA1790G Power SOP8

µ

Gate

1.44

1.8 MAX.

PACKAGE DRAWING (Unit : mm)

85

14

5.37 MAX.

1.27

0.78 MAX.

+0.10

0.40

0.05 MIN.

–0.05

N-Channel 1 ; Source 1

P-Channel 3 ; Source 2

6.0 ±0.3

+0.10

–0.05

0.15

0.12 M

0.5 ±0.2

2 ; Gate 1 7,8 ; Drain 1

4 ; Gate 2 5,6 ; Drain 2

4.4

EQUIVARENT CIRCUIT

Drain

Body Diode

Gate

0.8

0.10

Drain

Body Diode

Remark

The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. G14320EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K) Printed in Japan

Gate Protection Diode

Source

Gate Protection Diode

Source

P-ChannelN-Channel

©

1999

ABSOL UTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)

PARAMETER SYMBOL N-CHANNEL P-CHANNEL UNIT Drain to Source Voltage (VGS = 0 V) V Gate to Source Voltage (VDS = 0 V) V Drain Current (DC) I

Drain Current (pulse) Total Power Dissipation (1 unit) Total Power Dissipation (2 unit)

Note1

Note2

Channel Temperature T Storage Temperature T

DSS

GSS

D(DC)

D(pulse)

I

P P

ch

stg

60 –60 V

±20 ±1.0 ±4.0

T

#

1.7 W

2.0 W

150 °C

–55 to +150 °C

20

0.7

2.8

µµµµ

PA1790

V A A

Notes 1.

PW ≤ 10

2.

Mounted on ceramic substrate of 2000 mm2 x 2.25 mm

s, Duty Cycle ≤ 1 %

µ

2

Data Sheet G14320EJ1V0DS00

ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)

N-CHANNEL

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TY P. MAX. UNIT

µµµµ

PA1790

Drain to Source On-state Resi stance R

Gate to Source Cut-off Voltage V

DS(on)1VGS

DS(on)2VGS

R

GS(off)VDS

= 10 V, ID = 0.5 A 0.12 0.26 = 4 V, ID = 0.5 A 0.19 0.34

= 10 V, ID = 1 mA 1.0 1.7 2.5 V Forward Transfer Admittance | yfs |VDS = 10 V, ID = 0.5 A 1.0 1.7 S Drain Leakage Current I Gate to Source Leakage Current I Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Turn-on Delay Time t Rise Time t Turn-off Delay Time t Fall Time t Total Gate Charge Q Gate to Source Charge Q Gate to Drain Charge Q Body Diode Forward Voltage V

Reverse Recovery Time t Reverse Recovery Charge Q

DSS

VDS = 60 V, VGS = 0 V 10

GSS

VGS = ±16 V, VDS = 0 V ±10

iss

VDS = 10 V 180 pF

oss

VGS = 0 V 100 pF

rss

f = 1 MHz 35 pF

d(on)ID

d(off)

GS

GD

F(S-D)IF

rr

= 0.5 A 1 ns

r

GS(on)

V

= 10 V 1.4 ns

VDD = 30 V 23 ns

f

RG = 10

G

ID = 1.0 A 8 nC

Ω

VDD = 48 V 1 nC VGS = 10 V 3.5 nC

= 1.0 A, VGS = 0 V 0.75 V

IF = 1.0 A, VGS = 0 V 30 ns

rr

di/dt = 100 A /

s33nC

µ

17 ns

Ω Ω

A

µ

A

µ

TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE

IG = 2 mA

50 Ω

D.U.T.

R

L

V

DD

PG.

V

GS

RG = 10 Ω

0

τ

τ = 1 s

µ

Duty Cycle ≤ 1 %

R

G

D.U.T.

V

L

R

V

Wave Form

V

DD

I

D

Wave Form

GS

0

10 %

V

GS(on)

90 %

PG.

90 %

D

I

10 %

0

t

r

t

d(on)

t

on

Data Sheet G14320EJ1V0DS00

90 %

I

D

t

d(off)

10 %

t

f

t

off

3