NEC UPA1759G Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
PA1759
µµµµ
DESCRIPTION
PACKAGE DRAWING (Unit : mm)
This product is Dual N-channel MOS Field Effect
Transistor designed for DC/DC converters.
85
FEATURES
Dual chip type
•
Low on-resistance
•
DS(on)1
R
= 110 mΩ TYP. (VGS = 10 V, ID = 2.5 A)
DS(on)2
R
= 170 mΩ TYP. (VGS = 4 V, ID = 2.5 A)
Low input capacitance C
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
•
iss
= 190 pF TYP.
ORDERING INFORMATION
1.8 Max.
14
5.37 Max.
1.44
1.27
0.78 Max.
+0.10
0.40
0.05 Min.
–0.05
+0.10
PART NUMBER PACKAGE
PA1759G Power SOP8
µ
AB SOLUT E MAXIMUM R ATINGS (TA = 25 °C, All terminals are connected.)
Drain to Source Voltage (VGS = 0) V
DS
Gate to Source Voltage (V
= 0) V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Note1
Note2
Note2
Channel Temperature T
Storage Temperature T
Single Avalanche Current
Single Avalanche Energy
Notes 1.
PW ≤ 10 µs, Duty cycle ≤ 1 %
2.
Mounted on ceramic substrate of 1200 mm2 x 1.7 mm
3.
Starting Tch = 25 °C, RG = 25
Note3
Note3
Ω
DSS
GSS
D(DC)
D(pulse)
I
T
P
T
P
ch
stg
AS
I
AS
E
GS
, V
= 20 V → 0 V
60 V
20
±
5.0
±
20
±
V
A
A
1.7 W
2.0 W
150 °C
–55 to + 150 °C
2.5 A
0.625 mJ
1
; Source 1
2
; Gate 1
7, 8
; Drain 1
3
; Source 2
4
; Gate 2
5, 6
; Drain 2
6.0 ±0.3
4.4
–0.05
0.15
0.12 M
0.5 ±0.2
EQUIVALENT CIRCUIT
(1/2 Circuit)
Drain
Gate
Gate
Protection
Diode
Source
0.8
0.10
Body
Diode
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G13622EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
©
1999
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
µµµµ
PA1759
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 2.5 A 110 150 m
= 4 V, ID = 2.5 A 170 240 m
= 10 V, ID = 1 mA 1.0 1.7 2.5 V
Ω
Ω
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 2.5 A2.03.9S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V 10
GSS
VGS = ±20 V, VDS = 0 V
iss
VDS = 10 V 190 pF
oss
VGS = 0 V 100 pF
rss
f = 1 MHz 36 pF
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= 2.5 A6ns
r
GS(on)
V
= 10 V50ns
VDD = 15 V80ns
f
G
RG = 10
Ω
50 ns
ID = 5.0 A8nC
VDD = 24 V1nC
VGS = 10 V2.4nC
= 5.0 A, VGS = 0 V 0.9 V
IF = 5.0 A, VGS = 0 V 40 ns
rr
di/dt = 100 A/µs50nC
10
±
A
µ
A
µ
TEST CIRCUIT 1 AVALANCHE CAPABILITY
PG.
VGS = 20 → 0 V
V
G
R
DD
= 25 Ω
50 Ω
I
D
D.U.T.
I
AS
BV
DSS
V
DS
Starting T
L
DD
V
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
PG.
= 2 mA
50 Ω
R
L
V
DD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
R
PG.
V
GS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
G
R
G
= 10 Ω
V
V
GS
Wave Form
I
D
Wave Form
GS
10 %
0
I
D
10 %10
0
t
d(on)
V
90
%
I
trt
t
on
GS(on)
D
d(off)tf
t
%
90
90
%
%
off
L
R
V
DD
2
Data Sheet G13622EJ1V0DS00
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