NEC PD4481161, PD4481181, PD4481321, PD4481361 DATA SHEET

查询UPD4481161GF-A65供应商查询UPD4481161GF-A65供应商

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD4481161, 4481181, 4481321, 4481361

8M-BIT ZEROSBTM SRAM

FLOW THROUGH OPERATION

Description

The µPD4481161 is a 524,288-word by 16-bit, the µPD4481181 is a 524,288-word by 18-bit, the µPD4481321 is a

262,144-word by 32-bit and the µPD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cycles for read to

The

µ

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are suitable for applications which require

The

µ

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are packaged in 100-pin PLASTIC LQFP with a

µ

The

1.4 mm package thickness for high density and low capacitive loading.

Features

• Low voltage core supply : V

• Synchronous operation

• Operating temperature : T

• 100 percent bus utilization

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for flow through operation

• All registers triggered off positive clock edge

• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4 (

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.

= 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y)

DD

V

= 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y)

DD

= 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)

A

TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)

PD4481321 and µPD4481361)

µ

/BW1 and /BW2 (µPD4481161 and µPD4481181)

Document No. M15561EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan

The mark

shows major revised points.







2001

µ

PD4481161, 4481181, 4481321, 4481361

Ordering Information

Part number Access Clock Core Supply I/O Interface Operating Package

Time Frequency Voltage Temperature

ns MHz V °C

PD4481161GF-A65 6.5 133 3.3 ± 0.165 3.3 V LVTTL

µ

PD4481161GF-A75 7.5 117 3.3 V or 2.5 V LVTTL LQFP (14 x 20)

µ

PD4481161GF-A85 8.5 100

µ

PD4481181GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481181GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481181GF-A85 8.5 100

µ

PD4481321GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481321GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481321GF-A85 8.5 100

µ

PD4481361GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481361GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481361GF-A85 8.5 100

µ

PD4481161GF-C75 7.5 117 2.5 ± 0.125 2.5 V LVTTL

µ

PD4481161GF-C85 8.5 100

µ

PD4481181GF-C75 7.5 117

µ

PD4481181GF-C85 8.5 100

µ

PD4481321GF-C75 7.5 117

µ

PD4481321GF-C85 8.5 100

µ

PD4481361GF-C75 7.5 117

µ

PD4481361GF-C85 8.5 100

µ

Note

Note

Note

Note

0 to 70 100-pin PLASTIC

(1/2)

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).

Note

2

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

Part number Access Clock Core Supply I/O Interface Operating Package

Time Frequency Voltage Temperature

ns MHz V °C

PD4481161GF-A65Y 6.5 133 3.3 ± 0.165 3.3 V LVTTL

µ

PD4481161GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL LQFP (14 x 20)

µ

PD4481161GF-A85Y 8.5 100

µ

PD4481181GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481181GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481181GF-A85Y 8.5 100

µ

PD4481321GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481321GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481321GF-A85Y 8.5 100

µ

PD4481361GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481361GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481361GF-A85Y 8.5 100

µ

PD4481161GF-C75Y 7.5 117 2.5 ± 0.125 2.5 V LVTTL

µ

PD4481161GF-C85Y 8.5 100

µ

PD4481181GF-C75Y 7.5 117

µ

PD4481181GF-C85Y 8.5 100

µ

PD4481321GF-C75Y 7.5 117

µ

PD4481321GF-C85Y 8.5 100

µ

PD4481361GF-C75Y 7.5 117

µ

PD4481361GF-C85Y 8.5 100

µ

Note

Note

Note

Note

−40 to +85 100-pin PLASTIC

(2/2)

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).

Note

Data Sheet M15561EJ3V0DS

3

Pin Configurations

/××× indicates active low signal.

µ

PD4481161, 4481181, 4481321, 4481361

100-pin PLASTIC LQFP (14 ×××× 20)

[

µµµµ

PD4481161GF,

µµµµ

PD4481181GF]

Marking Side

NC

NC

NC

V

DD

V

SS

NC

NC

I/O9

I/O10

V

SS

V

DD

I/O11

I/O12

V

V

V

V

I/O13

I/O14

V

DD

V

SS

I/O15

I/O16

I/OP2, NC

NC

V

SS

V

DD

NC

NC

NC

A6A7/CE

CE2NCNC

/BW2

/BW1

/CE2

VDDVSSCLK

/WE

/CKE/GADVNCA17A8A9

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

2

3

Q

Q

4

5

6

7

8

9

Q

Q

10

11

12

13

SS

DD

DD

SS

14

15

16

17

18

19

Q

Q

20

21

22

23

24

25

Q

Q

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A18

NC

NC

DD

Q

V

V

SS

Q

NC

I/OP1, NC

I/O8

I/O7

V

SS

Q

V

DD

Q

I/O6

I/O5

V

SS

V

SS

V

DD

ZZ

I/O4

I/O3

V

DD

Q

V

SS

Q

I/O2

I/O1

NC

NC

V

SS

Q

V

DD

Q

NC

NC

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A5A4A3A2A1

A0

NC

NC

SS

V

MODE

Remark Refer to Package Drawing for the 1-pin index mark.

4

Data Sheet M15561EJ3V0DS

DD

NC

NC

V

A10

A11

A12

A13

A14

A15

A16

Pin Identifications

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

PD4481161GF,

[

Symbol Pin No. Description

A0 to A18 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, Synchronous Address Input

I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,

I/OP1, NC

I/OP2, NC

ADV 85 Synchronous Address Load / Advance Input

/CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input

/WE 88 Synchronous Write Enable Input

/BW1, /BW2 93, 94 Synchronous Byte Write Enable Input

/G 86 Asynchronous Output Enable Input

CLK 89 Clock Input

/CKE 87 Synchronous Clock Enable Input

MODE 31 Asynchronous Burst Sequence Select Input

ZZ 64 Asynchronous Power Down State Input

DD

V

SS

V

VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply

VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground

NC 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection

Note

Note

µµµµ

PD4481181GF]

44, 45, 46, 47, 48, 49, 50, 83, 80

18, 19, 22, 23 Synchronous / Asynchronous Data Out

74 Synchronous Data In (Parity),

24 Synchronous / Asynchronous Data Out (Parity)

Have to tied to VDD or VSS during normal operation

15, 16, 41, 65, 91 Power Supply

14, 17, 40, 66, 67, 90 Ground

51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96

NC (No Connection) is used in the µPD4481161GF.

Note

I/OP1 and I/OP2 are used in the µPD4481181GF.

Data Sheet M15561EJ3V0DS

5

µ

PD4481161, 4481181, 4481321, 4481361

100-pin PLASTIC LQFP (14 ×××× 20)

I/OP3, NC

I/O17

I/O18

V

DD

V

SS

I/O19

I/O20

I/O21

I/O22

V

SS

V

DD

I/O23

I/O24

V

V

V

V

I/O25

I/O26

V

DD

V

SS

I/O27

I/O28

I/O29

I/O30

V

SS

V

DD

I/O31

I/O32

I/OP4, NC

µµµµ

[

PD4481321GF,

µµµµ

PD4481361GF]

Marking Side

A6A7/CE

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

2

3

Q

Q

4

5

6

7

8

9

Q

Q

10

11

12

13

SS

DD

DD

SS

14

15

16

17

18

19

Q

Q

20

21

22

23

24

25

Q

Q

26

27

28

29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

CE2

/BW4

/BW3

/BW2

/BW1

/CE2

VDDVSSCLK

/WE

/CKE/GADVNCA17A8A9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/OP2, NC

I/O16

I/O15

DD

Q

V

V

SS

Q

I/O14

I/O13

I/O12

I/O11

V

SS

Q

V

DD

Q

I/O10

I/O9

V

SS

V

SS

V

DD

ZZ

I/O8

I/O7

V

DD

Q

V

SS

Q

I/O6

I/O5

I/O4

I/O3

V

SS

Q

DD

Q

V

I/O2

I/O1

I/OP1, NC

A5A4A3A2A1

A0

NC

NC

MODE

Remark Refer to Package Drawing for the1-pin index mark.

6

Data Sheet M15561EJ3V0DS

SS

DD

NC

V

NC

V

A10

A11

A12

A13

A14

A15

A16

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

PD4481321GF,

[

Symbol Pin No. Description

A0 to A17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,

I/OP1, NC

I/OP2, NC

I/OP3, NC

I/OP4, NC

ADV 85 Synchronous Address Load / Advance Input

/CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input

/WE 88 Synchronous Write Enable Input

/BW1 to /BW4 93, 94, 95, 96 Synchronous Byte Write Enable Input

/G 86 Asynchronous Output Enable Input

CLK 89 Clock Input

/CKE 87 Synchronous Clock Enable Input

MODE 31 Asynchronous Burst Sequence Select Input

ZZ 64 Asynchronous Power Down State Input

DD

V

SS

V

VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply

VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground

NC 38, 39, 42, 43, 84 No Connection

Note

Note

Note

Note

µµµµ

PD4481361GF]

45, 46, 47, 48, 49, 50, 83

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

51 Synchronous Data In (Parity),

80 Synchronous / Asynchronous Data Out (Parity)

1

30

Have to tied to VDD or VSS during normal operation

15, 16, 41, 65, 91 Power Supply

14, 17, 40, 66, 67, 90 Ground

Note NC (No Connection) is used in the

I/OP1 to I/OP4 are used in the µPD4481361GF.

PD4481321GF.

µ

Data Sheet M15561EJ3V0DS

7

Block Diagrams

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

[

PD4481161,

A0 to A18

MODE

CLK

/CKE

ADV
/BW1
/BW2

/WE

/G

/CE

CE2

/CE2

ZZ Power down control

µ

µ

PD4481181]

µ µ

K

Address
register 0

Read

19 17

A1
A0

ADV

K

Write address
register

Write registry and

data coherency

control logic

logic

Burst

logic

A1’
A0’

19

Write

drivers

19

19

Memory Cell Array

512 x 16 columns

(8,388,608 bits)

512 x 18 columns

(9,437,184 bits)

1,024 rows

Sense amplifiers

16/18

16/18

Data steering

Input
register

16/18

E

Output buffers

I/O1 to I/O16
I/OP1, I/OP2

E

16/18

Burst Sequence

µµµµ

[

PD4481161,

Interleaved Burst Sequence Table (MODE = V

External Address A18 to A2, A1, A0

1st Burst Address A18 to A2, A1, /A0

2nd Burst Address A18 to A2, /A1, A0

3rd Burst Address A18 to A2, /A1, /A0

µ

µ

PD4481181]

µ µ

DD

)

Linear Burst Sequence Table (MODE = VSS)

External Address A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1

1st Burst Address A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0

2nd Burst Address A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1

3rd Burst Address A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0

8

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

[

PD4481321,

A0 to A17

MODE

CLK

/CKE

ADV
/BW1
/BW2
/BW3
/BW4

/WE

/G

/CE

CE2

/CE2

ZZ Power down control

µ

µ

PD4481361]

µ µ

K

Address
register 0

18 16

A1
A0

ADV

K

Write address
register

Write registry and

data coherency

control logic

Read

logic

Burst
logic

A1’
A0’

18

Write

drivers

18

18

Memory Cell Array

1,024 rows

256 x 32 columns

(8,388,608 bits)

256 x 36 columns

(9,437,184 bits)

Sense amplifiers

32/36

32/36

Data steering

Input
register

32/36

E

Output buffers

I/O1 to I/O32
I/OP1 to I/OP4

E

32/36

µµµµ

[

PD4481321,

Interleaved Burst Sequence Table (MODE = V

µ

µ

PD4481361]

µ µ

DD

)

External Address A17 to A2, A1, A0

1st Burst Address A17 to A2, A1, /A0

2nd Burst Address A17 to A2, /A1, A0

3rd Burst Address A17 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = VSS)

External Address A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1

1st Burst Address A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0

2nd Burst Address A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1

3rd Burst Address A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0

Data Sheet M15561EJ3V0DS

9

State Diagram

µ

PD4481161, 4481181, 4481321, 4481361

DS BURST

DS DS

DESELECT

READ

DS DS

WRITE

READ

BURST

Command Operation

DS Deselect

Read New Read

Write New Write

Burst Burst Read, Burst Write or Continue Deselect

BEGIN

READ

READ BURST BURST WRITE

BURST

READ

READ

WRITE

BEGIN
WRITE

READWRITE

BURST

WRITE

WRITE

BURST

Remarks 1. States change on the rising edge of the clock.

2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only

blocks the clock (CLK) input and does not change the state of the device.

10

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

Asynchronous Truth Table

Operation /G I/O

Read Cycle L Dout

Read Cycle H High-Z

Write Cycle × High-Z, Din

Deselected × High-Z

Remark × : don’t care

Synchronous Truth Table

Operation /CE CE2 /CE2 ADV /WE /BWs /CKE CLK I/O Address Note

Deselected H ××L ××LL → H High-Z None 1

Deselected × L × L ××LL → H High-Z None 1

Deselected ××HL××LL → H High-Z None 1

Continue Deselected ×××H ××LL → H High-Z None 1

Read Cycle / Begin Burst L H L L H × LL → H Dout External

Read Cycle / Continue Burst ×××H ×× LL → H Dout Next

Write Cycle / Begin Burst LHLLLLLL → H Din External

Write Cycle / Continue Burst ×××H × LLL → HDin Next

Write Cycle / Write Abort L H L L L H L L → H High-Z External

Write Cycle / Write Abort ×××H × HLL → H High-Z Next

Stall / Ignore Clock Edge ЧЧЧЧЧЧHL → H − Current 2

Notes 1. Deselect status is held until new “Begin Burst” entry.

2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low

impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will

be performed during the Ignore Clock Edge cycle.

Remarks 1. × : don’t care

2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.

/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.

Data Sheet M15561EJ3V0DS

11

Partial Truth Table for Write Enables

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

PD4481161,

[

Read Cycle H ××

Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H

Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L

Write Cycle / All Bytes L L L

Write Abort / NOP L H H

µ

µ

PD4481181]

µ µ

Operation /WE /BW1 /BW2

Remark × : don’t care

µµµµ

[

PD4481321,

Read Cycle H ××××

Write Cycle / Byte 1 (I/O [1:8], I/OP1) L L H H H

Write Cycle / Byte 2 (I/O [9:16], I/OP2) L H L H H

Write Cycle / Byte 3 (I/O [17:24], I/OP3) L H H L H

Write Cycle / Byte 4 (I/O [25:32], I/OP4) L H H H L

Write Cycle / All Bytes L L L L L

Write Abort / NOP L H H H H

µ

µ

PD4481361]

µ µ

Operation /WE /BW1 /BW2 /BW3 /BW4

Remark × : don’t care

ZZ (Sleep) Truth Table

ZZ Chip Status

0.2 V Active

≤

Open Active

VDD − 0.2 V Sleep

≥

12

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply voltage V

Output supply voltage VDDQ –0.5 V

Input voltage V

Input / Output voltage V

Operating ambient T

temperature -A65Y, -A75Y, -A85Y, -C75Y, -C85Y –40 +85

Storage temperature T

–2.0 V (MIN.) (Pulse width : 2 ns)

Note

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

DD

-A65, -A75, -A85 –0.5 +4.0 V

-A65Y, -A75Y, -A85Y

-C75, -C85 –0.5 +3.0

-C75Y, -C85Y

DD

Note

IN

I/O

A

stg

-A65, -A75, -A85, -C75, -C85 0 70 °C

–0.5

–0.5

Note

DD

V

+ 0.5 V

VDDQ + 0.5 V

–55 +125 °C

V

Recommended DC Operating Conditions (1/2)

Parameter Symbol Conditions -A65, -A75, -A85 Unit

-A65Y, -A75Y, -A85Y

MIN. TYP. MAX.

Supply voltage V

DD

3.135 3.3 3.465 V

2.5 V LVTTL Interface

Output supply voltage VDDQ 2.375 2.5 2.9 V

High level input voltage V

Low level input voltage V

IH

IL

1.7 VDDQ + 0.3 V

Note

–0.3

+0.7 V

3.3 V LVTTL Interface

Output supply voltage VDDQ 3.135 3.3 3.465 V

High level input voltage V

Low level input voltage V

–0.8 V (MIN.) (Pulse width : 2 ns)

Note

IH

IL

2.0 VDDQ + 0.3 V

Note

–0.3

+0.8 V

Recommended DC Operating Conditions (2/2)

Parameter Symbol Conditions -C75, -C85 Unit

-C75Y, -C85Y

MIN. TYP. MAX.

Supply voltage V

Output supply voltage VDDQ 2.375 2.5 2.625 V

High level input voltage V

Low level input voltage V

DD

IH

IL

2.375 2.5 2.625 V

1.7 VDDQ + 0.3 V

Note

–0.3

+0.7 V

Note –0.8 V (MIN.) (Pulse width : 2 ns)

Data Sheet M15561EJ3V0DS

13

µ

PD4481161, 4481181, 4481321, 4481361

DC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

LI

Input leakage current I

I/O leakage current I

Operating supply current I

Standby supply current I

Power down supply current I

I

I

SBZZ

IN

V

(except ZZ, MODE) = 0 V to V

LO

I/O

V

= 0 V to VDDQ, Outputs are disabled. –2 +2

DD

Device selected, -A65 250 mA

Cycle = MAX., -A65Y

IN

V

VIL or VIN ≥ VIH, -A75, -C75 225

≤

I/O

I

= 0 mA -A75Y, -C75Y

SB

Device deselected, Cycle = 0 MHz, 30 mA

IN

V

VIL or VIN ≥ VIH, All inputs are static.

≤

SB1

Device deselected, Cycle = 0 MHz, 15

IN

V

0.2 V or VIN ≥ V

≤

I/O

V

0.2 V, All inputs are static.

≤

SB2

Device deselected, Cycle = MAX., 110

IN

V

VIL or VIN ≥ V

≤

ZZ ≥ VDD – 0.2 V, V

DD

IH

I/O

≤ VDDQ + 0.2 V 15 mA

DD

–2 +2

-A85, -C85 200

-A85Y, -C85Y

– 0.2 V,

A

µ

A

µ

2.5 V LVTTL Interface

High level output voltage V

Low level output voltage V

OHIOH

I

OLIOL

I

= –2.0 mA 1.7 V

OH

= –1.0 mA 2.1

= +2.0 mA 0.7 V

OL

= +1.0 mA 0.4

3.3 V LVTTL Interface

High level output voltage V

Low level output voltage V

OHIOH

OLIOL

= –4.0 mA 2.4 V

= +8.0 mA 0.4 V

Capacitance (TA = 25 °°°°C, f = 1MHz)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

Input capacitance C

Input / Output capacitance C

Clock input capacitance C

IN

VIN = 0 V 6.0 pF

I/O

I/O

V

= 0 V 8.0 pF

clkVclk

= 0 V 6.0 pF

Remark These parameters are periodically sampled and not 100% tested.

14

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

AC Characteristics (VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)

AC Test Conditions

2.5 V LVTTL Interface

Input waveform (Rise / Fall time ≤≤≤≤ 2.4 ns)

2.4 V

1.2 V

V

SS

Output waveform

3.3 V LVTTL Interface

Test points

Test points1.2 V 1.2 V

1.2 V

Input waveform (Rise / Fall time

3.0 V

V

SS

Output waveform

Output load condition

CL : 30 pF

5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)

I/O (Output)

≤≤≤≤ 3.0 ns)

1.5 V

Test points

Test points1.5 V 1.5 V

Figure External load at test

O = 50 Ω

Z

1.5 V

Remark C

50 Ω

VT = +1.2 V / +1.5 V

includes capacitances of the probe and jig, and stray capacitances.

L

Data Sheet M15561EJ3V0DS

L

C

15

µ

PD4481161, 4481181, 4481321, 4481361

Read and Write Cycle (2.5 V LVTTL Interface)

Parameter Symbol -A65, -A75, -C75 -A85, -C85 Unit Note

-A65Y, -A75Y, -C75Y -A85Y, -C85Y

(117 MHz) (100 MHz)

Standard Alias MIN. MAX. MIN. MAX.

Cycle time TKHKH TCYC 8.6 – 10 – ns

Clock access time TKHQV TCD – 7.5 – 8.5 ns

Output enable access time TGLQV TOE – 3.5 – 3.5 ns

Clock high to output active TKHQX1 TDC1 2.5 – 2.5 – ns 1, 2

Clock high to output change TKHQX2 TDC2 2.5 – 2.5 – ns

Output enable to output active TGLQX TOLZ 0 – 0 – ns 1

Output disable to output High-Z TGHQZ TOHZ 0 3.5 0 3.5 ns 1

Clock high to output High-Z TKHQZ TCZ 2.5 5 2.5 5 ns 1, 2

Clock high pulse width TKHKL TCH 2.5 – 2.5 – ns

Clock low pulse width TKLKH TCL 2.5 – 2.5 – ns

Setup times Address TAVKH TAS 1.5 – 2 – ns

Address advance TADVVKH TADVS

Clock enable TEVKH TCES

Chip enable TCVKH TCSS

Data in TDVKH TDS

Write enable TWVKH TWS

Hold times Address TKHAX TAH 0.5 – 0.5 – ns

Address advance TKHADVX TADVH

Clock enable TKHEX TCEH

Chip enable TKHCX TCSH

Data in TKHDX TDH

Write enable TKHWX TWH

Power down entry time TZZE TZZE – 8.6 – 10 ns

Power down recovery time TZZR TZZR – 8.6 – 10 ns

Notes 1. Transition is measured ±200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus

contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA

max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).

VDD

16

Data Sheet M15561EJ3V0DS

min.,

µ

PD4481161, 4481181, 4481321, 4481361

Read and Write Cycle (3.3 V LVTTL Interface)

Parameter Symbol -A65 -A75 -A85 Unit Note

-A65Y -A75Y -A85Y

(133 MHz) (117 MHz) (100 MHz)

Standard Alias MIN. MAX. MIN. MAX. MIN. MAX.

Cycle time TKHKH TCYC 7.5 – 8.6 – 10 – ns

Clock access time TKHQV TCD – 6.5 – 7.5 – 8.5 ns

Output enable access time TGLQV TOE – 3.5 – 3.5 – 3.5 ns

Clock high to output active TKHQX1 TDC1 2.5 – 2.5 – 2.5 – ns 1, 2

Clock high to output change TKHQX2 TDC2 2.5 – 2.5 – 2.5 – ns

Output enable to output active TGLQX TOLZ 0 – 0 – 0 – ns 1

Output disable to output High-Z TGHQZ TOHZ 0 3.5 0 3.5 0 3.5 ns 1

Clock high to output High-Z TKHQZ TCZ 2.5 5 2.5 5 2.5 5 ns 1, 2

Clock high pulse width TKHKL TCH 2.5 – 2.5 – 2.5 – ns

Clock low pulse width TKLKH TCL 2.5 – 2.5 – 2.5 – ns

Setup times Address TAVKH TAS 1.5 – 1.5 – 2 – ns

Address advance TADVVKH TADVS

Clock enable TEVKH TCES

Chip enable TCVKH TCSS

Data in TDVKH TDS

Write enable TWVKH TWS

Hold times Address TKHAX TAH 0.5 – 0.5 – 0.5 – ns

Address advance TKHADVX TADVH

Clock enable TKHEX TCEH

Chip enable TKHCX TCSH

Data in TKHDX TDH

Write enable TKHWX TWH

Power down entry time TZZE TZZE – 7.5 – 8.6 – 10 ns

Power down recovery time TZZR TZZR – 7.5 – 8.6 – 10 ns

Notes 1. Transition is measured ±200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus

contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA

max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.).

VDD

Data Sheet M15561EJ3V0DS

min.,

17

READ / WRITE CYCLE

µ

PD4481161, 4481181, 4481321, 4481361

/CEs

/BWs

Address

CLK

TEVKH TKHEX

/CKE

TCVKH TKHCX

Note 1

TADVVKH TKHADVX

ADV

TWVKH TKHWX

/WE

TWVKH TKHWX

Note 2

12345678910

A1 A3 A4 A5 A6

TKHKH

TKLKHTKHKL

A2 A7

TAVKH TKHAX

Data In

Data Out

High-Z High-Z High-Z

High-Z High-Z

D (A1) D (A2)

TDVKH TKHDX TKHQX1

D (A2+1)

TKHQV

TKHQX2

Q (A3) Q (A4)

TGHQZ

TGLQV TKHQZ

Q (A4+1)

TGLQX

D (A5)

Q (A6) Q (A7)

TKHQX2

/G

Command

WRITE

D (A1)

WRITE

D (A2)

BURST
WRITE

D (A2+1)

READ
Q (A3)

READ

Q (A4)

BURST

READ

Q (A4+1)

WRITE

D (A5)

READ
Q (A6)

WRITE

Q (A7)

DESELECT

Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When

/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.

/BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables

2.

(/BW1, /BW2, /BW3 or /BW4) are LOW.

18

Data Sheet M15561EJ3V0DS

NOP, STALL AND DESELECT CYCLE

12345678910

CLK

/CKE

/CEs

ADV

/WE

/BWs

µ

PD4481161, 4481181, 4481321, 4481361

Address

Data In

Data Out

Command

High-Z

High-Z

WRITE

D (A1)

A2A1 A3 A4 A5

READ
Q (A3)

High-Z

Q (A3)

WRITE

D (A4)

D (A4)

High-Z

STALL NOP

D (A1)

READ
Q (A2)

Q (A2)

STALL

TKHQX2

READ
Q (A5)

TKHQZ

Q (A5)

DESELECT

High-Z

High-Z

CONTINUE
DESELECT

Data Sheet M15561EJ3V0DS

19

POWER DOWN (ZZ) CYCLE

µ

PD4481161, 4481181, 4481321, 4481361

CLK

/CKE

Note

/CEs

ADV

Note

/WE

/BWs

Address

Data Out

12345678910

A1

/G

High-Z High-Z

TKHKH

TKHKL TKLKH

Q (A1)

11 12

A2

Q1 (A2)

Q2 (A2)

ZZ

TZZE TZZR

Power Down (I

/WE or /CEs must be held HIGH at CLK rising edge (clock edge No.3 in this figure) prior to power down state

Note

SBZZ

) State

entry.

20

Data Sheet M15561EJ3V0DS

Package Drawing

100-PIN PLASTIC LQFP (14x20)

A
B

µ

PD4481161, 4481181, 4481321, 4481361

81

100

80

1

51

50

31

30

F

G

H

M

I

K

P

SN

NOTE

Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.

L

detail of lead end

S

C D

R

Q

J

S

M

ITEM MILLIMETERS

A

22.0±0.2

B

20.0±0.2
C 14.0±0.2
D

16.0±0.2
F 0.825
G

0.575
H 0.32

I 0.13
J
K
L

M 0.17

N
P
Q

R3°
S 1.7 MAX.

+0.08

−0.07

0.65 (T.P.)

1.0±0.2

0.5±0.2

+0.06

−0.05

0.10

1.4

0.125±0.075

+7°

−3°

S100GF-65-8ET-1

Data Sheet M15561EJ3V0DS

21

Recommended Soldering Condition

µ

PD4481161, 4481181, 4481321, 4481361

Please consult with our sales offices for soldering conditions of the

Types of Surface Mount Devices

PD4481161GF : 100-pin PLASTIC LQFP (14 x 20)

µ

PD4481181GF : 100-pin PLASTIC LQFP (14 x 20)

µ

PD4481321GF : 100-pin PLASTIC LQFP (14 x 20)

µ

PD4481361GF : 100-pin PLASTIC LQFP (14 x 20)

µ

PD4481161, 4481181, 4481321 and 4481361.

µ

22

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

Revision History

Edition/ Page Type of Location Description

Date This Previous revision (Previous edition → This edition)

edition edition

3rd edition/ Throughout Throughout Modification

Dec. 2002 Addition

−

−

Preliminary Data Sheet → Data Sheet

Extended operating temperature products

(TA = −40 to +85 °C)

Data Sheet M15561EJ3V0DS

23

[MEMO]

µ

PD4481161, 4481181, 4481321, 4481361

24

Data Sheet M15561EJ3V0DS

[MEMO]

µ

PD4481161, 4481181, 4481321, 4481361

Data Sheet M15561EJ3V0DS

25

[MEMO]

µ

PD4481161, 4481181, 4481321, 4481361

26

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Data Sheet M15561EJ3V0DS

27

µ

PD4481161, 4481181, 4481321, 4481361

ZEROSB is a trademark of NEC Electronics Corporation.

•

The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

•

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative

•

purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.

•

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redundancy, fire-containment and anti-failure features.

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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer­designated "quality assurance program" for a specific application. The recommended applications of an NEC
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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M8E 02. 11-1