NEC PD4481161, PD4481181, PD4481321, PD4481361 DATA SHEET

查询UPD4481161GF-A65供应商查询UPD4481161GF-A65供应商

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD4481161, 4481181, 4481321, 4481361

8M-BIT ZEROSBTM SRAM

FLOW THROUGH OPERATION

Description

The µPD4481161 is a 524,288-word by 16-bit, the µPD4481181 is a 524,288-word by 18-bit, the µPD4481321 is a

262,144-word by 32-bit and the µPD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cycles for read to

The

µ

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are suitable for applications which require

The

µ

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

PD4481161, µPD4481181, µPD4481321 and µPD4481361 are packaged in 100-pin PLASTIC LQFP with a

µ

The

1.4 mm package thickness for high density and low capacitive loading.

Features

• Low voltage core supply : V

• Synchronous operation

• Operating temperature : T

• 100 percent bus utilization

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for flow through operation

• All registers triggered off positive clock edge

• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4 (

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

= 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y)

DD

V

= 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y)

DD

= 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)

A

TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)

PD4481321 and µPD4481361)

µ

/BW1 and /BW2 (µPD4481161 and µPD4481181)

Document No. M15561EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan

The mark

shows major revised points.





2001

µ

PD4481161, 4481181, 4481321, 4481361

Ordering Information

Part number Access Clock Core Supply I/O Interface Operating Package

Time Frequency Voltage Temperature

ns MHz V °C

PD4481161GF-A65 6.5 133 3.3 ± 0.165 3.3 V LVTTL

µ

PD4481161GF-A75 7.5 117 3.3 V or 2.5 V LVTTL LQFP (14 x 20)

µ

PD4481161GF-A85 8.5 100

µ

PD4481181GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481181GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481181GF-A85 8.5 100

µ

PD4481321GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481321GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481321GF-A85 8.5 100

µ

PD4481361GF-A65 6.5 133 3.3 V LVTTL

µ

PD4481361GF-A75 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481361GF-A85 8.5 100

µ

PD4481161GF-C75 7.5 117 2.5 ± 0.125 2.5 V LVTTL

µ

PD4481161GF-C85 8.5 100

µ

PD4481181GF-C75 7.5 117

µ

PD4481181GF-C85 8.5 100

µ

PD4481321GF-C75 7.5 117

µ

PD4481321GF-C85 8.5 100

µ

PD4481361GF-C75 7.5 117

µ

PD4481361GF-C85 8.5 100

µ

Note

0 to 70 100-pin PLASTIC

(1/2)

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).

Note

2

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

Part number Access Clock Core Supply I/O Interface Operating Package

Time Frequency Voltage Temperature

ns MHz V °C

PD4481161GF-A65Y 6.5 133 3.3 ± 0.165 3.3 V LVTTL

µ

PD4481161GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL LQFP (14 x 20)

µ

PD4481161GF-A85Y 8.5 100

µ

PD4481181GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481181GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481181GF-A85Y 8.5 100

µ

PD4481321GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481321GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481321GF-A85Y 8.5 100

µ

PD4481361GF-A65Y 6.5 133 3.3 V LVTTL

µ

PD4481361GF-A75Y 7.5 117 3.3 V or 2.5 V LVTTL

µ

PD4481361GF-A85Y 8.5 100

µ

PD4481161GF-C75Y 7.5 117 2.5 ± 0.125 2.5 V LVTTL

µ

PD4481161GF-C85Y 8.5 100

µ

PD4481181GF-C75Y 7.5 117

µ

PD4481181GF-C85Y 8.5 100

µ

PD4481321GF-C75Y 7.5 117

µ

PD4481321GF-C85Y 8.5 100

µ

PD4481361GF-C75Y 7.5 117

µ

PD4481361GF-C85Y 8.5 100

µ

Note

−40 to +85 100-pin PLASTIC

(2/2)

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).

Note

Data Sheet M15561EJ3V0DS

3

Pin Configurations

/××× indicates active low signal.

µ

PD4481161, 4481181, 4481321, 4481361

100-pin PLASTIC LQFP (14 ×××× 20)

[

µµµµ

PD4481161GF,

µµµµ

PD4481181GF]

Marking Side

NC

V

DD

V

SS

NC

I/O9

I/O10

V

SS

V

DD

I/O11

I/O12

V

I/O13

I/O14

V

DD

V

SS

I/O15

I/O16

I/OP2, NC

NC

V

SS

V

DD

NC

A6A7/CE

CE2NCNC

/BW2

/BW1

/CE2

VDDVSSCLK

/WE

/CKE/GADVNCA17A8A9

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

2

3

Q

4

5

6

7

8

9

Q

10

11

12

13

SS

DD

SS

14

15

16

17

18

19

Q

20

21

22

23

24

25

Q

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A18

NC

DD

Q

V

SS

Q

NC

I/OP1, NC

I/O8

I/O7

V

SS

Q

V

DD

Q

I/O6

I/O5

V

SS

V

SS

V

DD

ZZ

I/O4

I/O3

V

DD

Q

V

SS

Q

I/O2

I/O1

NC

V

SS

Q

V

DD

Q

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A5A4A3A2A1

A0

NC

SS

V

MODE

Remark Refer to Package Drawing for the 1-pin index mark.

4

Data Sheet M15561EJ3V0DS

DD

NC

V

A10

A11

A12

A13

A14

A15

A16

Pin Identifications

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

PD4481161GF,

[

Symbol Pin No. Description

A0 to A18 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, Synchronous Address Input

I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,

I/OP1, NC

I/OP2, NC

ADV 85 Synchronous Address Load / Advance Input

/CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input

/WE 88 Synchronous Write Enable Input

/BW1, /BW2 93, 94 Synchronous Byte Write Enable Input

/G 86 Asynchronous Output Enable Input

CLK 89 Clock Input

/CKE 87 Synchronous Clock Enable Input

MODE 31 Asynchronous Burst Sequence Select Input

ZZ 64 Asynchronous Power Down State Input

DD

V

SS

V

VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply

VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground

NC 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection

Note

µµµµ

PD4481181GF]

44, 45, 46, 47, 48, 49, 50, 83, 80

18, 19, 22, 23 Synchronous / Asynchronous Data Out

74 Synchronous Data In (Parity),

24 Synchronous / Asynchronous Data Out (Parity)

Have to tied to VDD or VSS during normal operation

15, 16, 41, 65, 91 Power Supply

14, 17, 40, 66, 67, 90 Ground

51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96

NC (No Connection) is used in the µPD4481161GF.

Note

I/OP1 and I/OP2 are used in the µPD4481181GF.

Data Sheet M15561EJ3V0DS

5

µ

PD4481161, 4481181, 4481321, 4481361

100-pin PLASTIC LQFP (14 ×××× 20)

I/OP3, NC

I/O17

I/O18

V

DD

V

SS

I/O19

I/O20

I/O21

I/O22

V

SS

V

DD

I/O23

I/O24

V

I/O25

I/O26

V

DD

V

SS

I/O27

I/O28

I/O29

I/O30

V

SS

V

DD

I/O31

I/O32

I/OP4, NC

µµµµ

[

PD4481321GF,

µµµµ

PD4481361GF]

Marking Side

A6A7/CE

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

2

3

Q

4

5

6

7

8

9

Q

10

11

12

13

SS

DD

SS

14

15

16

17

18

19

Q

20

21

22

23

24

25

Q

26

27

28

29

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

CE2

/BW4

/BW3

/BW2

/BW1

/CE2

VDDVSSCLK

/WE

/CKE/GADVNCA17A8A9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/OP2, NC

I/O16

I/O15

DD

Q

V

SS

Q

I/O14

I/O13

I/O12

I/O11

V

SS

Q

V

DD

Q

I/O10

I/O9

V

SS

V

SS

V

DD

ZZ

I/O8

I/O7

V

DD

Q

V

SS

Q

I/O6

I/O5

I/O4

I/O3

V

SS

Q

DD

Q

V

I/O2

I/O1

I/OP1, NC

A5A4A3A2A1

A0

NC

MODE

Remark Refer to Package Drawing for the1-pin index mark.

6

Data Sheet M15561EJ3V0DS

SS

DD

NC

V

NC

V

A10

A11

A12

A13

A14

A15

A16

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

PD4481321GF,

[

Symbol Pin No. Description

A0 to A17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

I/O1 to I/O32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,

I/OP1, NC

I/OP2, NC

I/OP3, NC

I/OP4, NC

ADV 85 Synchronous Address Load / Advance Input

/CE, CE2, /CE2 98, 97, 92 Synchronous Chip Enable Input

/WE 88 Synchronous Write Enable Input

/BW1 to /BW4 93, 94, 95, 96 Synchronous Byte Write Enable Input

/G 86 Asynchronous Output Enable Input

CLK 89 Clock Input

/CKE 87 Synchronous Clock Enable Input

MODE 31 Asynchronous Burst Sequence Select Input

ZZ 64 Asynchronous Power Down State Input

DD

V

SS

V

VDDQ 4, 11, 20, 27, 54, 61, 70, 77 Output Buffer Power Supply

VSSQ 5, 10, 21, 26, 55, 60, 71, 76 Output Buffer Ground

NC 38, 39, 42, 43, 84 No Connection

Note

µµµµ

PD4481361GF]

45, 46, 47, 48, 49, 50, 83

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

51 Synchronous Data In (Parity),

80 Synchronous / Asynchronous Data Out (Parity)

1

30

Have to tied to VDD or VSS during normal operation

15, 16, 41, 65, 91 Power Supply

14, 17, 40, 66, 67, 90 Ground

Note NC (No Connection) is used in the

I/OP1 to I/OP4 are used in the µPD4481361GF.

PD4481321GF.

µ

Data Sheet M15561EJ3V0DS

7

Block Diagrams

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

[

PD4481161,

A0 to A18

MODE

CLK

/CKE

ADV /BW1 /BW2

/WE

/G

/CE

CE2

/CE2

ZZ Power down control

µ

PD4481181]

µ µ

K

Address register 0

Read

19 17

A1 A0

ADV

K

Write address register

Write registry and

data coherency

control logic

logic

Burst

logic

A1’ A0’

19

Write

drivers

19

Memory Cell Array

512 x 16 columns

(8,388,608 bits)

512 x 18 columns

(9,437,184 bits)

1,024 rows

Sense amplifiers

16/18

Data steering

Input register

16/18

E

Output buffers

I/O1 to I/O16 I/OP1, I/OP2

E

16/18

Burst Sequence

µµµµ

[

PD4481161,

Interleaved Burst Sequence Table (MODE = V

External Address A18 to A2, A1, A0

1st Burst Address A18 to A2, A1, /A0

2nd Burst Address A18 to A2, /A1, A0

3rd Burst Address A18 to A2, /A1, /A0

µ

PD4481181]

µ µ

DD

)

Linear Burst Sequence Table (MODE = VSS)

External Address A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1

1st Burst Address A18 to A2, 0, 1 A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0

2nd Burst Address A18 to A2, 1, 0 A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1

3rd Burst Address A18 to A2, 1, 1 A18 to A2, 0, 0 A18 to A2, 0, 1 A18 to A2, 1, 0

8

Data Sheet M15561EJ3V0DS

µ

PD4481161, 4481181, 4481321, 4481361

µµµµ

[

PD4481321,

A0 to A17

MODE

CLK

/CKE

ADV /BW1 /BW2 /BW3 /BW4

/WE

/G

/CE

CE2

/CE2

ZZ Power down control

µ

PD4481361]

µ µ

K

Address register 0

18 16

A1 A0

ADV

K

Write address register

Write registry and

data coherency

control logic

Read

logic

Burst logic

A1’ A0’

18

Write

drivers

18

Memory Cell Array

1,024 rows

256 x 32 columns

(8,388,608 bits)

256 x 36 columns

(9,437,184 bits)

Sense amplifiers

32/36

Data steering

Input register

32/36

E

Output buffers

I/O1 to I/O32 I/OP1 to I/OP4

E

32/36

µµµµ

[

PD4481321,

Interleaved Burst Sequence Table (MODE = V

µ

PD4481361]

µ µ

DD

)

External Address A17 to A2, A1, A0

1st Burst Address A17 to A2, A1, /A0

2nd Burst Address A17 to A2, /A1, A0

3rd Burst Address A17 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = VSS)

External Address A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1

1st Burst Address A17 to A2, 0, 1 A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0

2nd Burst Address A17 to A2, 1, 0 A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1

3rd Burst Address A17 to A2, 1, 1 A17 to A2, 0, 0 A17 to A2, 0, 1 A17 to A2, 1, 0

Data Sheet M15561EJ3V0DS

9