Motorola MC10198L, MC10198P Datasheet

LOGIC DIAGRAM

V

CC1

= PIN 1

V

CC2

= PIN 16

VEE= PIN 8

5

7
10
13

15

3

2

Q

Q

64

V

EE

V

CC

C

EXT

E pos
EXTERNAL PULSE

WIDTH CONTROL
E

NEG

TRIGGER
INPUT

HI–SPEED
INPUT

TRUTH TABLE

E

PosENeg

L
L
H
H

INPUT

OUTPUT

L
H
L
H

Triggers on both positive & negative input slopes
Triggers on positive input slope
Triggers on negative input slope
Trigger is disabled

R

EXT



SEMICONDUCTOR TECHNICAL DATA

3–172

REV 5

 Motorola, Inc. 1996

3/93

 

The MC10198 is a retriggerable monostable multivibrator. T wo enable inputs
permit triggering on any combination of positive or negative edges as shown in
the accompanying table. The trigger input is buffered by Schmitt triggers
making it insensitive to input rise and fall times.

The pulse width is controlled by an external capacitor and resistor. The
resistor sets a current which is the linear discharge rate of the capacitor. Also,
the pulse width can be controlled by an external current source or voltage (see
applications information).

For high–speed response with minimum delay, a hi–speed input is also
provided. This input bypasses the internal Schmitt triggers and the output
responds within 2 nanoseconds typically.

Output logic and threshold levels are standard MECL 10,000. Test
conditions are per Table 2. Each “Precondition” referred to in Table 2 is per the
sequence of Table 1.

PD = 415 mW typ/pkg (No Load)
tpd = 4.0 ns typ Trigger Inpt to Q

2.0 ns typ Hi–Speed Input to Q

Min Timing Pulse Width PW

Qmin

10 ns typ

1

Max Timing Pulse Width PW

Qmax

>10 ms typ

2

Min Trigger Pulse Width PW

T

2.0 ns typ

Min Hi–Speed PW

HS

3.0 ns typ
Trigger Pulse Width
Enable Setup Time t

set

1.0 ns typ
Enable Hold Time t

hold

1.0 ns typ
1

C

Ext

= 0 (Pin 4 open), R

Ext

= 0

(Pin 6 to VEE)

2

C

Ext

= 10 µF, R

Ext

= 2.7 kΩ



DIP

PIN ASSIGNMENT

V

CC1

Q
Q

C

EXT

E

POS

R

EXT

EXT.PULSE

WIDTH CONTROL

V

EE

V

CC2

HIGH–SPEED
INPUT

N/C
TRIGGER INPUT
N/C

N/C
E

NEG

N/C

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

T ables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

MC10198

3–173 MOTOROLAMECL Data

DL122 — Rev 6

1. At t = 0 a.) Apply V

IHmax

to Pin 5 and 10.

b.) Apply V

ILmin

to Pin 15.

c.) Ground Pin 4.

2. At t w 10 ns a.) Open Pin 1.
b.) Apply –3.0 Vdc to Pin 4.

Hold these conditions for

w

10 ns.

3. Return Pin 4 to Ground and perform test as

indicated in T able 2.

Pins 1, 16 = VCC = Ground
Pins 6, 8 = VEE = –5.2 Vdc
Outputs loaded 50 Ω to –2.0 Vdc

VIH

max

VIL

min

P1

–5.0

0

w

10 ns

t(ns)

–4.0

–3.0

–2.0

–1.0

0(Gnd)

10 20

Pin 1

open

30

TABLE 1 — PRECONDITION SEQUENCE

Pin 4 Voltage (Vdc)

w

10 ns

TABLE 2 — CONDITIONS FOR TESTING OUTPUT LEVELS

(See Table 1 for Precondition Sequence)

V

ILA max

VIL

min

P2

V

IHA max

VIL

min

P3

Pin Conditions Pin Conditions

Test P.U.T. 5 10 13 15 Test P.U.T. 5 10 13 15

Precondition Precondition

V

OH

2 VIL

min

V

OHA

2 V

IHA min

P1

V

OH

3 P1 V

OHA

3 V

ILA max

P1

Precondition Precondition

V

OL

3 VIL

min

V

OLA

3 V

ILA max

V

OL

2 P1 V

OLA

2 V

IHA min

Precondition Precondition

V

OHA

2 V

ILA max

V

OLA

2 VIL

min

V

OHA

3 V

IHA min

V

OLA

3 VIL

min

Precondition Precondition

V

OHA

2 VIL

min

V

OLA

3 P2

V

OHA

3 P3 V

OLA

2 P3

Precondition Precondition

V

OHA

2 P2 V

OLA

3 VIH

max

P2

V

OHA

3 P3 V

OLA

2 VIH

max

P3

Precondition Precondition

V

OHA

2 VIH

max

P2 V

OLA

3V

IHA minVIH max

P1

V

OHA

3 VIH

max

P3 V

OLA

2V

ILA maxVIH max

P1

Precondition Precondition

V

OHA

2 VIH

max

P1 V

OLA

3V

IH maxVIHA min

P1

V

OHA

3 VIH

max

P1 V

OLA

2V

IH maxVILA max

P1

MC10198

MOTOROLA MECL Data

DL122 — Rev 6

3–174

ELECTRICAL CHARACTERISTICS

Test Limits

Pin

Under

–30°C +25°C +85°C

Characteristic Symbol

Under

Test

Min Max Min Typ Max Min Max

Unit

Power Supply Drain Current I

E

8 110 80 100 110 mAdc

Input Current I

inH

5, 10

13
15

415
350
560

260
220
350

260
220
350

µAdc

I

inL

5 0.5 0.5 0.3 µAdc

Output Voltage Logic 1 V

OH

2
3

–1.060
–1.060

–0.890
–0.890

–0.960
–0.960

–0.810
–0.810

–0.890
–0.890

–0.700
–0.700

Vdc

Output Voltage Logic 0 V

OL

2
3

–1.890
–1.890

–1.675
–1.675

–1.850
–1.850

–1.650
–1.650

–1.825
–1.825

–1.615
–1.615

Vdc

Threshold Voltage Logic 1 V

OHA

2
3

–1.080
–1.080

–0.980
–0.980

–0.910
–0.910

Vdc

Threshold Voltage Logic 0 V

OLA

2
3

–1.655
–1.655

–1.630
–1.630

–1.595
–1.595

Vdc

Switching Times (50Ω Load)
Trigger Input t

T+Q+

t

T–Q+

3
3

2.5

2.5

6.5

6.5

2.5

2.5

4.0

4.0

5.5

5.5

2.5

2.5

6.5

6.5

ns

High Speed Trigger Input t

HS+Q+

3 1.5 3.2 1.5 2.0 2.8 1.5 3.2 ns

Minimum Timing Pulse Width PW

Qmin

3 10.0 ns

Maximum Timing Pulse Width PW

Qmax

3 >10 ms

Min Trigger Pulse Width PW

T

3 2.0 ns

Min Hi–Spd Trig Pulse Width PW

HS

3 3.0 ns
Rise Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns
Fall Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns
Enable Setup Time t

setup

(E) 3 1.0 ns

Enable Hold Time t

hold

(E) 3 1.0 ns

1. The monostable is in the timing mode at the time of this test.

2. C

EXT

= 0 (Pin 4 Open); R

EXT

= 0 (Pin 6 tied to VEE).

3. C

EXT

= 10µF (Pin); R

EXT

= 2.7k (Pin 6).

4.

V

IHmax

V

ILmin

P1