MOTOROLA MC100LVEP14DT, MC100LVEP14DTR2 Datasheet

MC100LVEP14
Low-Voltage 1:5 Differential

LVECL/LVPECL/LVEPECL/HSTL
Clock Driver

The MC100LVEP14 is a low skew 1–to–5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The LVECL/LVPECL input signals can be either differential
or single–ended (if the VBB output is used). HSTL inputs can be used
when the LVEP14 is operating under LVPECL conditions.

The LVEP14 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device and
from lot to lot.

To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50W even
if only one side is being used. When fewer than all five pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.

The common enable (EN
disabled in the LOW state. This avoids a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore all associated specification limits are referenced to the
negative edge of the clock input.

The MC100LVEP14, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP14 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.
Designers can take advantage of the LVEP14’s performance to
distribute low skew clocks across the backplane or the board. For more
information, refer to Application Note AN1406/D.

• 100ps Part–to–Part Skew

• 25ps Output–to–Output Skew

• Differential Design

• 400ps T ypical Propagation Delay

• High Bandwidth to 1.5 Ghz T ypical

• LVPECL and HSTL mode: +2.375V to +3.8V V

• LVECL mode: 0V V

• 75kΩ Internal Pulldown CLKs, Pull up & Pulldown CLKs

• ESD Protection: >2KV HBM; >100V MM

• Moisture Sensitivity Level 2

For Additional Information, See Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34

• Transistor Count = 357 devices

) is synchronous, outputs are enabled/

with VEE = 0V

CC

with VEE = –2.375V to –3.8V

CC

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1

TSSOP–20
DT SUFFIX

CASE 948E

MARKING DIAGRAM*

VP = LVEP

100

VP14

ALYW

*For additional information, see Application Note
AND8002/D

ORDERING INFORMATION

Device Package Shipping

MC100L VEP14DT TSSOP 75 Units/Tray

MC100L VEP14DTR2 TSSOP 2500 Tape & Reel

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week

 Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 1

1 Publication Order Number:

MC100L VEP14/D

VCC EN

1920

MC100LVEP14

VCC

CLK1 VBB CLK0 CLK0 CLK_SELVEE

CLK1

1718 16 15 14 13 12

10

D

Q

11

21

Q0

56789

43

Q2Q0 Q3 Q4Q4

Q2Q1

10

Q3Q1

Figure 1. 20–Lead TSSOP and Logic Diagram

(Top View)

Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.

PIN DESCRIPTION

Pins

CLK0, CLK0
CLK1, CLK1
Q0:4, Q0:4
CLK_SEL
EN
VBB
VCC
VEE

LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL Outputs
LVECL/LVPECL Active Clock Select Input
Sync Enable
Reference Voltage Output
Positive Supply
Negative, 0 Supply

Function

FUNCTION TABLE

CLK0

L
H
X
X
X

CLK1

X
X
L
H
X

CLK_SEL

L

L
H
H
X

EN

L
L
L
L

H

Q

L

H

L

H

L*

* On next negative transition of CLK0 or CLK1

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MC100LVEP14

MAXIMUM RATINGS*

Symbol Parameter Value Unit

V

EE

V

CC

V

I

V

I

I

out

I

BB

T

A

T

stg

θ

JA

θ

JC

T

sol

* Maximum Ratings are those values beyond which damage to the device may occur.

{

Use for inputs of same package only.

DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –3.3(+0.925, –0.5)V) (Note 5.)

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

V

BB

V

IHCMR

I

IH

I

IL

1. VCC = 0V, VEE = V

2. All loading with 50 ohms to VCC–2.0 volts.

3. Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.

4. V

5. Input and output parameters vary 1:1 with VCC.

Power Supply Current (Note 1.) 45 60 75 45 60 75 45 60 95 mA
Output HIGH Voltage (Note 2.) –1145 –1020 –0895 –1 145 –1020 –0895 –1145 –1020 –0895 mV
Output LOW Voltage (Note 2.) –1995 –1820 –1650 –1995 –1820 –1650 –1995 –1820 –1650 mV
Input HIGH Voltage –1165 –0880 –1165 –0880 –1165 –0880 mV
Input LOW Voltage –1810 –1625 –1810 –1625 –1810 –1625 mV
Output Reference Voltage (Note 3.) –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 mV
Input HIGH Voltage Common Mode

Range (Note 4.)
Input HIGH Current 150 150 150 µA
Input LOW Current 0.5

min varies 1:1 with VEE, max varies 1:1 with VCC.

IHCMR

DC CHARACTERISTICS, HSTL (VCC = 2.5(–0.125, +1.3)V, VEE = 0V)

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

V

IH

V

IL

V

X

I

CC

6. VCC = 2.375V to 3.8V , VEE = 0V, all other pins floating.

Input HIGH Voltage 1200 mV
Input LOW Voltage 400 mV
Input Crossover Voltage 680 900 mV
Power Supply Current (Note 6.) 100 100 100 mA

Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous

VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air

Thermal Resistance (Junction–to–Case) 30 to 35 °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C

to V

EEmin

EEmax

{

–40°C 25°C 85°C

VEE + 1.2 0.0 VEE + 1.2 0.0 VEE + 1.2 0.0 V

–150

, all other pins floating.

–40°C 25°C 85°C

Surge

500lfpm

0.5

–150

50

100

± 0.5 mA

90
60

0.5

–150

mA

°C/W

150 µA

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