MOTOROLA MC100LVEP111FA, MC100LVEP111FAR2 Datasheet
MC100LVEP111
Low-V oltage 1:10 Differential
L VECL/LVPECL/L VEPECL/HSTL
Clock Driver
The MC100LVEP111 is a low skew 1–to–10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The LVECL/LVPECL input signals can be either
differential or single–ended (if the VBB output is used). HSTL inputs can
be used when the L VEP1 1 1 is operating under L VPECL conditions.
The LVEP111 specifically guarantees low output–to–output skew.
Optimal design, layout, and processing minimize skew within a device and
from lot to lot.
To ensure that the tight skew specification is realized, both sides of
any differential output need to be terminated identically into 50W even
if only one side is being used. When fewer than all ten pairs are used,
identically terminate all the output pairs on the same package side
whether used or unused. If no outputs on a single side are used, then
leave these outputs open (unterminated). This will maintain minimum
output skew. Failure to do this will result in a 10–20ps loss of skew
margin (propagation delay) in the output(s) in use.
The MC100LVEP111, as with most other LVECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP111 to be used for high performance clock distribution in
+3.3V or +2.5V systems. Single ended input operation is limited to a
VCC ≥ 3.0V in LVPECL mode, or VEE ≤ –3.0V in LVECL mode.
Designers can take advantage of the LVEP111’s performance to
distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For more
information on using LVPECL, designers should refer to Application
Note AN1406/D.
• 100ps Part–to–Part Skew
• 25ps Output–to–Output Skew
• Dif ferential Design
• V
• 430ps Typical Propagation Delay
• High Bandwidth to 1.5 Ghz Typical
• LVPECL and HSTL mode: +2.375V to +3.8V V
• LVECL mode: 0V V
• 75kΩ Internal Input Pulldown Resistors on CLKs, Pull up &
• ESD Protection: >2KV HBM; >100V MM
• Moisture Sensitivity Level 2
• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
• Transistor Count = 602 devices
Output
BB
with VEE = 0V
CC
with VEE = –2.375V to –3.8V
CC
Pulldown resistors on CLK
For Additional Information, See Application Note AND8003/D
s
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32–LEAD TQFP
FA SUFFIX
CASE 873A
MARKING DIAGRAM*
MC100
LVEP111
AWLYYWW
32
1
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device Package Shipping
MC100L VEP111FA TQFP 250 Units/Tray
MC100L VEP111FAR2 TQFP 2000 Tape & Reel
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
Semiconductor Components Industries, LLC, 1999
March, 2000 – Rev . 2
1 Publication Order Number:
MC100L VEP111/D
MC100LVEP111
Q6Q6Q5Q5Q4Q4Q3 Q3
24 23 22 21 20 19 18 17
VCC
Q2
Q2
Q1
25
26
27
28
MC100LVEP111
Q1
Q0
Q0
VCC
29
30
31
32
12345678
VEECLK1CLK1VBBCLK0CLK0VCC
CLK_SEL
Figure 1. 32–Lead TQFP Pinout
(Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
PIN DESCRIPTION
16
15
14
13
12
11
10
9
VCC
Q7
Q7
Q8
Q8
Q9
Q9
VCC
Pins
CLK0, CLK0
CLK1, CLK1
Q0:9, Q0:9
CLK_SEL
VBB
VCC
VEE
CLK_SEL
0
1
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL/HSTL CLK Input
LVECL/LVPECL Outputs
LVECL/LVPECL Active Clock Select Input
Reference Voltage Output
Positive Supply
Negative, 0 Supply
FUNCTION TABLE
Function
Active Input
CLK0, CLK0
CLK1, CLK1
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
0
1
V
BB
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
Q
9
Q
9
Figure 2. Logic Symbol
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MC100LVEP111
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
EE
V
CC
V
I
V
I
I
out
I
BB
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –3.3(+0.925, –0.5)V) (Note 5.)
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC–2.0 volts.
3. Single ended input operation is limited VEE ≤ –3.0V in ECL/LVECL mode.
4. V
5. Input and output parameters vary 1:1 with VCC.
Power Supply Current (Note 1.) 70 100 120 70 100 120 70 100 120 mA
Output HIGH Voltage (Note 2.) –1145 –1020 –0895 –1145 –1020 –0895 –1 145 –1020 –0895 mV
Output LOW Voltage (Note 2.) –1995 –1820 –1650 –1995 –1820 –1650 –1995 –1820 –1650 mV
Input HIGH Voltage –1165 –0880 –1165 –0880 –1165 –0880 mV
Input LOW Voltage –1810 –1625 –1810 –1625 –1810 –1625 mV
Output Reference Voltage
(Note 3.)
Input HIGH Voltage Common
Mode Range (Note 4.)
Input HIGH Current 150 150 150 µA
Input LOW Current 0.5
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
DC CHARACTERISTICS, HSTL (VCC = 2.5(–0.125, +1.3)V, VEE = 0V)
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
V
IH
V
IL
V
X
I
CC
6. VCC = 2.375V to 3.8V , VEE = 0V, all other pins floating.
Input HIGH Voltage 1200 mV
Input LOW Voltage 400 mV
Input Crossover Voltage 680 900 mV
Power Supply Current (Note 6.) 70 100 120 70 100 120 70 100 120 mA
Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air
Thermal Resistance (Junction–to–Case) 12 to 17 °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
to V
EEmin
EEmax
{
–40°C 25°C 85°C
–1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 mV
VEE + 1.2 0.0 VEE + 1.2 0.0 VEE + 1.2 0.0 V
–150
, all other pins floating.
–40°C 25°C 85°C
Surge
500lfpm
0.5
–150
50
100
± 0.5 mA
80
55
0.5
–150
mA
°C/W
150 µA
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