Motorola MC100LVE222 Datasheet
SEMICONDUCTOR TECHNICAL DATA
÷÷
ECL fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system
skew. The LVE222 can be used as a simple fanout buffer or outputs can
be configured to provide half frequency outputs. The combination of 1x
and 1/2x frequencies is flexible providing for a myriad of combinations. All
timing differences between the 1x and 1/2x signals are compensated for
internal to the chip so that the output–to–output skew is identical
regardless of what output frequencies are selected.
The MC100LVE222 is a low voltage, low skew 1:15 differential ÷1/÷2
• Fifteen Differential Outputs
• 200ps Part–to–Part Skew
• 50ps Output–to–Output Skew
• Selectable 1x or 1/2x Frequency Outputs
• Extended Power Supply Range of –3.0V to –5.25V (+3.0V to +5.25V)
• 52–Lead TQFP Packaging
• ESD > 2000V
The fsel and CLK_Sel input pins are asynchronous control signals. As
a result, changing these inputs could cause indeterminent excursions on
the outputs immediately following the changes on the inputs.
For applications which require a single–ended input, the VBB reference
voltage is supplied. For single–ended input applications the V
reference should be connected to the CLK
via a 0.01µf capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50Ω, even if only one side is being used. In most applications all fifteen dif ferential pairs will be used and therefore terminated. In
the case where fewer than fifteen pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair
being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation
delay (on the order of 10–20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for
outputs on the same side of the package.
The MC100L VE222, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE222 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE222’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN1406/D.
The MC100LVE222 is packaged in the 52–lead TQFP package. For a 3.3V supply this package provides the optimum
performance and minimizes board space requirements. The LVE222 will operate from a standard 100E –4.5V supply or a 5.0V
PECL supply. The 52–lead TQFP utilizes a 10x10mm body with a lead pitch of 0.65mm.
input and bypassed to ground
BB
LOW VOLTAGE
1:15 DIFFERENTIAL ÷1/÷2
ECL/PECL CLOCK DRIVER
FA SUFFIX
TQFP PACKAGE
CASE 848D–03
10/96
Motorola, Inc. 1996
4–1
REV 1
MC100LVE222
VCCO
Pinout: 52–Lead TQFP (Top View)
VCCO
Qc0
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
VCCONCNC
39 38 37 36 35 34 33 32 31 30 29 28 27
40
VCCO
26
Qd0
Qb2
Qb2
Qb1
Qb1
Qb0
Qb0
VCCO
Qa1
Qa1
Qa0
Qa0
VCCO
41
42
43
44
45
46
47
48
49
50
51
52
12345678910111213
MR
VCC
fsela
MC100LVE222
fselb
CLK0
CLK0
CLK1
CLK_Sel
CLK1
VBB
fselc
fseld
25
24
23
22
21
20
19
18
17
16
15
14
VEE
Qd0
Qd1
Qd1
Qd2
Qd2
Qd3
Qd3
Qd4
Qd4
Qd5
Qd5
VCCO
LOGIC SYMBOL
MR
CLK0
CLK0
CLK1
CLK1
CLK_Sel
V
BB
fsela
fselb
fselc
fseld
MOTOROLA ECLinPS and ECLinPS Lite
÷
1
÷
2
2
Qa0:1
Qa0:1
FUNCTION TABLE
3
4
6
4–2
Qb0:2
Qb0:2
Qc0:3
Qc0:3
Qd0:5
Qd0:5
Input
MR
CLK_Sel
fseln
Function
01
Active
CLK0
÷1
Reset
CLK1
÷2
DL140 — Rev 3
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