MiTAC M722 Service Manual & Troubleshooting Manual

M722

TESTING TECHNOLOGY DEPARTMENT / TSSC

：：：：

Alex. Thomas

SEP. 2000

SERVICE MANUAL & TROUBLESHOOTING GUIDE FOR

M722 N/B MAINTENANCE

0. HARDWARE ENGINEERING SPECIFICATION

……………………..

1. DEFINITION & LOCATION CONNECTORS/ SWITCHES

…………..

2. DEFINITION & LOCATION MAJOR COMPONENTS

………………..

3. PIN DESCRIPTIONS OF MAJOR COMPONENTS

……………………

4. M722 BLOCK DIAGRAM &SWITCH SETTING

……………………...

5. ASSEMBLY & DISASSEMBLY

…………………….…………………….

5.A. MAINTENANCE DIAGNOSTIC

………………………………………

6. TROUBLE SHOOTING

…………………………………….……………..

7. SPARE PARTS LIST

……………………………….………………………

8. CIRCUIT DIAGRAM

………………………………………………………..

P.2

P.35

P.39

P.42

P.57

P.60

P.83-1

P.84

P.105

P.114

M722 N/B MAINTENANCE

M 722 Hardware Engineering Specification

0. HARDWARE ENGINEERING SPECIFICATION

M722 N/B MAINTENANCE

Table of Contents

0.1. INTRODUCTION…………............................................................................................................................................................................…..6

0.2. SYSTEM HARDWARE PARTS..........................................................................................................................................................................7

0.2.1 CPU – INTEL MOBILE C

ELERON/PENTIUM

III PROCESSOR IN UPGA2 PACKAGE................................................................................7

0.2.2 I

NTEL

82440MX-100 C

HIPSET HOST BRIDGE

..................................................................................................................................................8

0.2.3 S

YSTEM FREQUENCY SYNTHESIZER AND

SDRAM

BUFFER :

ICS9148-101.....................................................................................................11

0.2.4 VGA C

ONTROLLER

: ATI 3D R

AGE MOBILITY

-M I

NTEGRATED

4MB SDRAM ..........................................................................................13

0.2.5 PC C

ARD INTERFACE CONTROLLER

: TI1410..................................................................................................................................................16

0.2.6 S

INGLE-SLOT

PC C

ARD POWER INTERFACE SWITCH

: TPS2211.....................................................................................................................16

0.2.7 AC’97 AUDIO SYSTEM: CRYSTAL CS 4299............................................................................................................................................17

0.2.8 MDC: PCT

MODEM DAUGHTER CARD...............................................................................................................................................19

0.2.9 S

UPER

IO: NS PC 97338VJG.........................................................................................................................................................................19

0.2.10 IR MODULE: VISHAY

TFDU6101E..........................................................................................................................................................20

0.2.11 K

EYBOARD SYSTEM

: H8(3434) U

NIVERSAL KEYBOARD CONTROLLER

.........................................................................................................20

0.2.12 S

YSTEM FLASH MEMORY

(BIOS)...................................................................................................................................................................22

0.2.13 M

EMORY SYSTEM

...........................................................................................................................................................................................22

0.2.13.1 On Board Main Memory........................................................................................................................................................................22

0.2.13.2 JEDEC 144-pin SO DIMM sockets........................................................................................................................................................22

0.2.14 LAN :

REALTEK

RTL8139CL........................................................................................................................................................................23

0.2-15 IEEE 1394 : NEC UPD72870A

....................................................................................................................................................................25

0.3. I/O PORT..............................................................................................................................................................................................................27

0.4. PERIPHERAL COMPONENTS........................................................................................................................................................................27

0.4.1 LCD PANEL..................................................................................................................................................................................................27

0.4.2 F

LOPPY DISK DRIVE

(USB).............................................................................................................................................................................27

0.4.3 HDD...............................................................................................................................................................................................................27

0.4.4 24X CD-ROM D

RIVE

.....................................................................................................................................................................................28

0.4.5 8X DVD-ROM

DRIVE

....................................................................................................................................................................................28

0.4.6 K

EYBOARD

.....................................................................................................................................................................................................28

0.4.7 T

OUCH PAD

.....................................................................................................................................................................................................28

0.4.8 F

.................................................................................................................................................................................................................28

0.5. APPENDIX 1: BANISTER GPIO DEFINITIONS ...........................................................................................................................................29

M722 N/B MAINTENANCE

0.6. M722 EXTERNAL SPECIFICATIONS R0.4 .........................................................................................................................................................…..30

0.7. OUTPUT POWER ...........................................................................................................................................................................................................32

7.1 INVERTER OUTPUT CHARACTERISTICS ..........................................................................................................................................................32

7.2 AC LOAD CHARACTERISTICS.............................................................................................................................................................................32

0.8. ELECTRONIC SPECIFICATION .................. .... .... .... .... .... .... .... .... .... .... .... .. .. .... .... .... .... .... .... .... .... ..............................................................................33

8.1 INPUT SECTION ......................................................................................................................................................................................................33

8.2 OUTPUT SECTION ..................................................................................................................................................................................................34

M722 N/B MAINTENANCE

List of Figures

Figure 1: Intel 82440MX Simplified Block Diagram...................................................................................................................................................11

Figure 2 : System clock structure and ICS 9148-101 block diagram............................................................................................................................12

Figure 3: ATI Rage Mobility-M....................................................................................................................................................................................15

Figure 4: CS4299..........................................................................................................................................................................................................17

Figure 5: AC links..........................................................................................................................................................................................................17

Figure 6: NS PC97338VJG...........................................................................................................................................................................................19

Figure 7: SO-Dimm Module.........................................................................................................................................................................................22

Figure 8: RTL8139CL Block Diagram.........................................................................................................................................................................24

Figure 9: Block Diagrams……………………………………………………………………………………………………………………………….25 Figure 10: PHY Block Diagrams………………………………………………………………………………………………………………………..26 Figure 11: LINK Block Diagrams………………………………………………………………………………………………………………………26

M722 N/B MAINTENANCE

0.1. I

NTRODUCTION

The M722 model motherboard would support the Mobile Pentium III processor at 500/600*/650* /700*/750*/800*MHz uPGA2 package on board and Celeron 450/500/550/600/650/700MHz uPGA2 package .(*Enabled with IST,Intel Speedstep technology)

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which have standard hardware peripheral interface and support Intel Mobile Pentium III/Celeron (uPGA2) family. The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy configuration through CMOS setup, which is built in system BIOS sof tware and can be pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as Power indicator, LAN, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery charging status. It also equipped with Zoom Video capture port, FIR, 4 USB ports, and 3D stereo audio functions.

The memory subsystem supports 64MB SDRAM on board and one 144pin DIMM socket for upgrading up to 192MB or 256 MB of DRAM using PC-100 SDRAM DIMM module.

The 82440MX Chipset integrated the North Bridge chipset (without AGP) and the South Bridge chipset while adding a two channel, digital AC’97.2 links feature. 82440MX Chipset brings second important firsts to the mobile PC environment: (1) Concurrent PCI (PCI 2.1) reduces CPU latencies for smoother video and more realistic audio; (2) Universal Serial Bus (USB) technology makes Plug and Play peripheral connections a reality. The Intel 82440MX Chipset also contains an integrated PCI Bus Mastering IDE controller with one high performance IDE interfaces and supports “Ultra 33” synchronous DMA mode which transfers up to 33 Mbytes per second. In addition, the 440MX Chipse

supports Intel's new Dynamic Power Management Architecture (DPMA) for consuming less power consumption than earlier PCIset designs and supports Advanced Configuration and Power Interface (ACPI) 1.0 for longer battery life in mobile systems.

The ATI 3D RAGE Mobility-M VGA controller integrated with 4Mbyte SDRAM provides LCD, and CRT simultaneously and supports 2D and 3D acceleration, ZV port, DVD, ACPI power management, integrated LVDS…etc. The TI 1410 CARDBUS controller supports PCMCIA and CARDBUS. The National Semiconductor PC97338 Super I/O controller integrates an IrDA 1.1, 1.0 and sharp ASK compatible infrared interface To provide for the increasing number of multimedia applications, the AC97 CODEC CS4299 is integrate d onto the motherboard which contain 3D digital audio output.

A full set of software drivers and utilities a re avail able to allow ad van ced o peratin g systems su ch as Win dow s 98 to take f ull advantage of the hardware capabilities such as bus mastering IDE, Windows 95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI).

Following chapters will have more detail description for each individual sub-systems and functions.

M722 N/B MAINTENANCE

0.2. S

YSTEM HARDWARE PARTS

Central Processing Unit: Intel Mobile Pentium III microprocessor (uPGA2) operating at 500/600/650/700/750/800MHz and Celeron microprocessor (uPGA2) operating at 450/500/600/650/700MH Synthesizer and SDRAM buffer: ICS9248-101 CPU/PCI bridge with memory controller and PCI/ISA bridge with IDE/USB/PMU controller: Intel82440MX-100 -BANISTER PCI Video Controller: ATI 3D RAGE Mobility-M Super I/O Controller: NS PC97338VJG Cardbus Controller: TI 1410 Keyboard System: Hitachi H8 (3434) universal keyboard controller AC97 CODEC: Crystal CS4299 FIR port: VISHAY TFDU6101E FIR module FAX/MODEM: ASKEY 56Kbps MDC Software Modem LAN100M/10Mbits: RTL8139CL IEEE1394 :NEC UPD72870A

0.2.1 CPU – INTEL MOBILE Celeron/Pentium III PROCESSOR IN uPGA2 PACKAGE

Exceptional value and improved performance over existing mobile processors

Supports the Intel Architecture with Dynamic Execution Supports the Intel Architecture MMX technology Support for Streaming SIMD Extensions for enhanced video,sound and 3D performance Support Intel Speedstep Technology Integrated Intel Floating-Point Unit compatible with the IEEE Std 754

Integrated on die primary (L1) instruction and data caches

4-way set associative, 32-byte line size, 1 line per sector 16-Kbyte instruction cache and 16-Kbyte writeback data cache Cacheable range programmable by processor programmable registers

Integrated second level (L2) cache

4-way set associative, 32-byte line size,1 line per sector Operates at full core speed 128-Kbyte for Celeron 256-Kbyte for Pentium III, ECC protected cache data array 4 G Bytes cacheable range

Low Power GTL+ system bus interface

64-bit data bus, 100-MHz operation Uniprocessor, two loads only (processor and I/O bridge/memory controller) Integrated termination

M722 N/B MAINTENANCE

Voltage reduction technology Advanced Pentium III processor clock control

Quick Start for low power, low exit latency clock “throttling” Deep Sleep mode for extremely low power dissipation

Thermal diode for measuring processor temperature

0.2.2 Intel 82440MX-100 Chipset Host Bridge

64-bit GTL+ based Host Bus Interface 32-bit Host address Support 64-bit Main Memory Interface with optimized support for SDRAM at 100 MHz 32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter Extensive Data Buffering between all interfaces for high throughput and concurrent operations. Mobile and

“Deep Green”

Desktop power management support. Host bridge for translation from CPU bus cycle to PCI bus cycle Integrated IDE controller with Ultra DMA/33 support. Processor/Host bus support

Optimized for mobile Celeron processors or Pentium III processors at 100MHz host bus frequency Supports 32-bit mobile Celeron processor / Pentium III processor bus addressing. 4 or 1 deep in-order queue; 4 or 1 deep request queue Supports uni-processor systems only In-order transaction and dynamic deferred transaction support GTL+ bus driver technology (gated GTL+ receivers for reduced power)

Integrated DRAM controller

8 to 512 Mbytes . Supports up to 2 double-sided SO-DIMMs (4-row memory). 64-bit data interface without ECC support. Unbuffered SDRAM Support (x-1-1-1 access @ 100 MHz). Support only 3.3v DIMM DRAM configuration. Enhanced SDRAM Open Page Architecture Support for 16- and 64-Mbit DRAM devices with 2k, 4k and 8k page sizes Max address decode A0..A11, BA0, BA1

PCI bus interface

PCI Rev. 2.2, 3.3V, 33MHz interface compliant. 4 PCI bus masters support for combination of Graphic, LAN, Card Bus, and IEEE1394 PCI Parity Generation Support. Data streaming support from PCI to DRAM. Delayed Transaction supports for PCI-DRAM Reads. Supports concurrent CPU, and PCI transactions to main memory.

Power Management Functions

M722 N/B MAINTENANCE

Stop Clock Grant and Halt special c ycle translation (host to PCI Bus). Mobile and “deep Green” Desktop support for system suspend/resume (i.e., DRAM and power-on suspend). Dynamic power down idle DRAM rows. SDRAM self-refresh power down support in suspend mode. Independent, internal dynamic clock gating reduces average power dissipation. Static STOP CLOCK support. Power-on Suspend mode. Suspend to DRAM. ACPI compliant power management.

AC’97. 2 link controller (2 channels)

Interface to AC’97 x AUDIO CODEC

Interface to MDC mo dem GPIO pins (31) Supporting I/O Bridge.

System Management Bus (SMB) with support for DIMM Serial Presence Detect (SPD).

Power Management Support.

3.3V core and mixed 5V, 3.3V I/O and interface to the 2.5V CPU PCI-to-ISA/EIO bridge (south bridge) for passing th e cycles accessing ISA (w/EIO) Multifunction PCI to ISA Bridge

Supports PCI at 30 MHz and 33 MHz Supports PCI Rev 2.2 Specification Supports Full ISA or Extended I/O (EIO) Bus Supports Full Positive Decode or Subtractive Decode of PCI Supports ISA and EIO at 1/4 of PCI Frequency

Supports both Mobile and Desktop Deep Green Environments

3.3V Operation with 5V Tolerant Buffers

Ultra-low Power for Mobile Environments Support Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-OFF System States All Registers Readable and Restorable for Proper Resume from 0.V Suspend

Power Management Logic

Global and Local Device Management Suspend and Resume Logic Supports Thermal Alarm Support for External Micro controller Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power

Management 1 channel bus master IDE support ultra DMA33 Enhanced DMA Controller

Two 82C37 DMA Controllers

Supports PCI DMA with 1 PC/PCI Channels and Distributed DMA Protocols (Simultaneously)

M722 N/B MAINTENANCE

Interrupt Controller Based on Two 82C59

15 Interrupt Support Independently Programmable for Edge/Level Sensitivity Supports Optional I/O APIC Serial Interrupt Input

Timers Based on 82C54

System Timer, Refresh Request, Speaker Tone Output

USB

Two USB 1.1 Ports for Serial Transfers at 12 Mbor 1.5 MB/sec Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse. Supports UHCI Design Guide

SMBus

Host Interface Allows CPU to Communicate Via SMBus Slave Interface Allows External SMBus Master to Control Resume Events

Real-Time Clock

256-byte Battery-Back CMOS SRAM Includes Date Alarm Two 8-byte Lockout Ranges

Packaging/Voltage

492 Pin BGA

M722 N/B MAINTENANCE

3.3V core and mixed 3.3V and GTL I/O.

Figure 1: Intel 82440MX Simplified Block Diagram.

0.2.3 System frequency synthesizer and SDRAM buffer : ICS9148-101

Maximized EMI suppression using ICS spread spectrum technology. Two copies of CPU output, output to output skew between them within 175ps and six copies of PCI output, output to output skew within 500ps. One 48MHz output for USB and selectable 24/48MHz output (pin 27). Two buffer copies of 14.318MHz input reference signal. Supports 100MHz or 66MHz CPU operation.

M722 N/B MAINTENANCE

Power management control pins. Spread spectrum function can be disabled. Low voltage, 8 skew controlled CMOS output clock buffers (SDRAM 0:7) Supports two SDRAM DIMMS. Ideal for high performance systems designed around Intel’s latest mobile chip set. I2C serial configuration interface. Skew between any two SDRAM output is less than 250ps 1 to 5ns propagation delay. Dc to 133mhz operation. Singles 3.3V supply voltage. Low power CMOS design packaged in a 48-pin, SSOP(Shrink small package).

Figure 2 : System clock structure and ICS 9148-101 block diagram

M722 N/B MAINTENANCE

0.2.4 VGA Controller: ATI 3D Rage Mobility-M Integrated 4MB SDRAM

Supports PCI 33Mhz Support dual view controller. Dual independent displays (LCD/CRT) and the resolutions, refresh rates and display data can be

completely independent.

Primary display path supports:

- VGA and accelerated modes

- Video overlay

- Hardware cursor and hardware icon

- Palette gamma correctio n. Supports both independent displays at 1024 x 768, 24bpp. Secondary display path supports:

- Accelerated modes

- YUV422 video data

- 24-bit palette Integrated dual 65MHz LVDS interface

- Up to 10 LVDS channels for power and EMI reduction.

- Dual pixel SXGA resolution TFT panels

- XGA resolution DSTN panels.

- 24bpp TFT (SGA/XGA) using dual pixel LVDS (versus 18 bpp using direct digital interface).

- 455 Mbps/channel with 65 MHz pixel clock rate.

- 3 pairs (+1 clock ) and 4 pairs (+1 clock ) modes for both single and dual pixel LVDS.

- FPDI-2 compliant; compatible with receivers from National Semiconductor and Texas Instruments.

- LVDS eye pattern to improve testability of LVDS module. Flat panel power management:

- Automatic power down panel by programmable internal timer

- Standby/Suspend pins for hardware Power Management support.

- Standby/Suspend registers for software Power Management support. Flat panel support:

- Color STN/DSTN/CSTN LC D panels up to XGA (1024 x 768) resoluti on, up t o 160Hz-r efres h ra te, up t o 256k col ors on an

8-color panel.

- Color TFT panel up to 1600 x 1280 resolution, up to 24-bit per pixel, single/double pixel per clock.

- 2/4 levels of frame modulation can be done on 9-bit, 12-bit and 18-bit TFT panels.

- Hardware Z-buffer supports with both DSTN and TFT panels.

- Integrated LVDS interface support.

- Support for Panel Link Interface.

- Support external Panel Link transmitter.

M722 N/B MAINTENANCE

- Panel ID to allow multiple panels support without swapping BIOS.

- Five bits allocated for panel ID.

- DDC support for LCD monitors.

- General-purpose I/O pins available to support DDC on LCD monitor applications. Integrated a floating-point set-up engine

- Processing up to 1.2 million triangles per sen d. Supports 100 MHz SGRAM:

- 64-bit, 100MHz SGRAM interface

- 800 MB/s of low-latency frame buffer bandwidth ZV Port (PCMCIA compliant with CCIR601 timing )

- Allows transfer of video data directly into frame buffer without loading down PCI bus.

- Dedicated video port guarantees video frame rates (30 frames per second)

- Maximum 40 MHz, 16bpp YUV422 (PCMCIA specs 16 MHz maximum) DVD and Video Support

- Enhanced motion compensation acceleration

- 4-tap horizontal and 2-tap vertical high quality DVD v ide o scalar.

- De-interlacing filter, Video on graphics overlay, Multi-stream video

- Color-space conversion, Scatter-gather bus-master, Planar YUV mode

- ATI Multimedia Channel (AMC) video input po rt

- Zoom Video input port (ZV-port)

- Improves software DVD/MPEG-2 frame rate by 20 to 30%.

- Provides full motion MPEG-2 playback o n Pen tium III processors Supports 3D Acceleration

- integrated 1 million triangle/s set-u p e ngine

- 4K on-chip texture cache.

- Full screen or window double buffering for smooth animation

- Hidden surface removal using 16-bit Z-buffering

- Edge anti-aliasing

- Sub-pixel and sub-texe l accuracy

- Gouraud and specular shaded polygons

- Prospectively correct mip-mapped texturing with chroma-key support.

- Full support of Direct3D texture lighting. Extensive 3D mode support:

- Draw in RGBA32, RGBA16, and RGB16 .

- Texture map modes: RGBA32, RGBA16,RGB8,ARGB4444, YUV444.

- Compressed texture mode: YUV422, CLUT4 (CI4), CLUT8(CI8), VQ Mobile PCI 1.0 support. Pin, Register and Timer modes for hardware and software power management. Dynamic clock switching.

M722 N/B MAINTENANCE

Panel bias voltage and digital power control. Self-refresh SDRAM in Suspend mode Enhanced line buffer allows vertical filtering of native MPEG-2 size (720 x 480) images. DVD/MPEG-2 decode assist provides dramatically improved frame rate Hardware mirroring for flipping video images in video images in video conferencing systems. Smooth video scaling and enhanced YUV to RGB color space conversion Front and back end scalars support multi-strea m v id eo for video conferencing Filtered horizontal/vertical, up/d own, scaling enhances playback qu a lity.

. Figure 3: ATI Rage Mobility-M

M722 N/B MAINTENANCE

0.2.5 PC Card Interface Controller: TI1410

ACPI 1.0 Compliance PCI Power Management interface specification 1.0 Compliance Supports distributed DMA (DDMA) and PC/PCI DMA Advanced submicron, low-power CMOS technology. Supports two I/O windows and two memory windows available to cardbus socket. Supports five PCI memory windows and two I/O windows available to PC CARD16 socket. Supports Burst Transfers To Maximize Data Throughput On Both PCI Buses Provides Serial Interface To TI TPS2211 Single Slot PC CARD Power Interface Switch Supports up to 5 general purpose I/O Supports Distributed DMA(DDMA) Pipelined architecture allows greater than 130Mbps second throughput from cardbus to PCI and from PCI to cardbus. Support PCI Bus Lock (/LOCK)

3.3-V core logic with universal PCI interface PCI Local Bus Specification Revision 2.2 compliant 1998 PC Card Standard compliant Supports one 16-bit PC card or Cardbus card ;sockets powered at 3.3V or 5V with hot insertion and removal ExCA compatible Registers mapped in memory or I/O space. Supports ring indicate output, SUSPEND#, and programmable output select for CLKRUN#. Provides socket activity LED signals. Provides zoom video support signals. 144-Pin LQFP package

0.2.6 Single-Slot PC Card Power Interface Switch: TPS2211

Fully Integrated Vcc and Vpp Switching for Single-Slot PC Card Interface

3.3 V Low-Voltage Mode Meets PC Card Standards RESET for System Initialization of PC Cards 12-V Supply Can Be Disabled Except During 12-V Flash Programming Short Circuit and Thermal Protection 16-Pin SSOP (DB) Compatible With 3.3-V, 5-V and 12-V PC Cards Low Rds

(on) (140-mOHM 5-V Vcc Switch; 110-mOHM3.3-V Vcc Switch)

Break-Before-Make Switching

M722 N/B MAINTENANCE

0.2.7 AC’97 AUDIO SYSTEM: CRYSTAL CS 4299

82440MX is an AC’97 2.1 compliant controller that communicates with companion codecs via a digital serial link called the AC-link. The AC’97 CODEC provides a complete high quality audio solution, feature include: 20-bit Stereo Digital-to-Analog Converter and 18-bit Stereo Analog to Digital Converter with Sample Rate Conversion Four Analog Line-level Stereo Inputs for Connection from LINE IN, CD, VIDEO, and AUX Two Analog Line-level Mono Inputs for Modem Sub-system and Internal PC Beeper Mono Microphone Input Switch able from Two External Sources High Quality Pseudo Differential CD Input Dual Stereo Line-level Outputs CrystalClear 3D Stereo Enhancement

Figure 1: CS 42

Figure 4:CS4299

Figure5:AC links

M722 N/B MAINTENANCE

0.2.8 MDC: PCTel MODEM DAUGHTER CA RD

ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bis (4.8Kbps to 14.4Kbps), V.22 bis (1.2 bps to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol. Automode Virtual com port with a DTE throughout up to 460.8Kbps. G3 Fax compatible Auto dial and auto answer Ring detection Support AC-link primary and secondary operating modes Support ACPI power management Operating temperature range from 0 to 60 degree c Power consumption less than 100Mw Support PCTel, Modem driver on demand

0.2.9 Super IO: NS PC 97338VJG

High speed PC16550A compatible UART with receive/transmit 16 Bytes FIFO programmable serial baud rate generator Multi-mode parallel port support including standard port, EPP/ECP (IEEE1284 compliant, 2 interrupt pins) Plug and Play module FDC, 100% IBM compatible, S/W & register compatible to 82077 with 16Bytes data FIFO Support 3-Mode FDD FIR/MIR/SIR/SHARP ASK for Infrared application. COM2

M722 N/B MAINTENANCE

High speed PC16550A compatible UART w ith receive/transmit 16 Bytes FIFO programma ble serial baud rate generator Multi-mode p aralle l port su p p or t inc luding standard port, EPP/E CP (IEEE1284 comp lian t, 2 inte rr up t p ins) Plug and Play module FDC, 100% IBM c om p a tible, S/W & reg ister co m pa tib le to 8 20 7 7 w ith 16 By tes data FIF O Support 3-Mode FDD FIR/MIR/SIR/SHARP ASK for Infrared application. COM2

IrDA 1.0 / IrDA 1.1 / SHARP ASK

Baud rate: max. 4Mb Link distance: 0.01 to 1 m Half angle: ±15

Bit Error Rate (BER) : 10

-9

Peak wavelength: 0.85 - 0.90 µm TQFP 100 pins Standby mode: control by software

Figure 6: NS PC97338VJG

M722 N/B MAINTENANCE

IO address IRQx DRQx

COM1 3F8-3FF 4 FIR/MIR/SIR/ SHARP ASK ( COM2 )

278-27F 3 -

PIO 378-37F 7 FDD 3F0-3FF 6 2

Table 1: 97338 IO address.

0.2.10 IR MODULE: VISHAY TFDU6101E

Compliant to IrDA 1.1 ( Up to 4 Mbit/s) HP-SI R, Sharp ASK and TV Remote Wide Operating Voltage Range 2.6 V to 5.5 V Small Module Size 4.0 x 9.9 x 4.7 mm (HxWxD) Low Power Sonsumption (3mA Supply Current). Power Shutdown Mode (1uA Shutdown Current). Built-in EMI protection Edge Detection Input Prevents the LED from long turn-on time Directly Interface with various Super I/O and Controller Devices Few External Components Required

0.2.11 Keyboard System: H8(3434) Universa l Keyboard Controller

CPU: Two-way general register configuration

Eight 16-bit registers or Sixteen 8-bit registers High-speed operation Maximum clock rate : 16Mhz at 5V

Memory

include 32KB ROM and 1KB RAM

16-bit free-running timer

One 16-bit free-running counter Two output-compare lines Four input capture lines

M722 N/B MAINTENANCE

8-bit timer ( 2 channels )

Each channel has one 8-bit up-counter , two time constant registers

PWM timer (2 channels)

resolution :1/250 Duty cycle can be set from 0 to 100%

C bus interface ( on e channel )

include single master mode and slave mode

Host interface ( HIF)

8-bit host interface port Three host interrupt requests ( HIRQ1,11,12) Regular and fast A20 gate output

Keyboard controller

Controls a matrix-scan keyboard by providing a keyboard scan function with wake-up Interrupts and sense ports

A/D converter

10-bit resolution 8 channels : single or scan mode (selectable )

D/A converter

8-bit resolution 2 channels

Interrupts

nine external interrupt lines : NMI# , IRQ0 to 7# 26 on-chip interrupt sources

Power-down modes

Sleep mode

Software standby mode Hardware standby mode A single chip microcomputer On-chip flash memory Maximum 64-kbyte address space Support three PS/2 port for external ke yboard, mouse and internal track pad. Support SMI,SCI trigger input: Cover switch Battery charging control Smart Battery monitoring Control D/D system on/o ff Fan control and LED indicator serial interface 100pin TQFP

M722 N/B MAINTENANCE

0.2.12 System Flash Memory (BIOS)

2 M bit Flash memory Flashed by 5V only User can upgrade the system BIOS in the future just running flash program.

0.2.13 Memory System

0.2.13.1 On Board Main Memory

PC100 SDRAM on board

Config 1: memory size: 4Mx16bit SDRAM x8 pcs. Total 64Mbyte Config 2: memory size: 8Mx16bit SDRAM x4 pcs. Total 64Mbyte Config 3: memory size: 8Mx16bit SDRAM x8 pcs. Total 128Mbyte

Standard 54 pin TSOP package. Power supply: 3.3V±0.3V Memory bus bandwidth: 64 bits

0.2.13.2 JEDEC 144-pin SO DIMM sockets

Supports one JEDEC 144-pin SO DIMM sockets on Mother Board for expansion Supports 3.3V SDRAM 2 banks on one socket PC-100 DIMM Module uses only. Max Address line: A0.. A11, BA0 BA1

Figure 7: SO-Dimm Module.

M722 N/B MAINTENANCE

0.2.14 LAN : Realtek RT L8139CL

128 pins TQFP Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip 10 Mb/s and 100 Mb/s operation PCI local bus single-chip Fast Ethernet controller Compliant to PCI Revision 2.2 Supports PCI clock 16.75MHz-40MHz Supports PCI target fast back-to-back transaction Supports ACPI, PCI power management Supports LAN WAKE-UP function ( Magic packet only ) Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of RTL8139A's operational registers. Support 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation Support up to 128K bytes Boot ROM interface Allow remote wake-up(Magic packet and Microsoft wake-up frame) Include a programmable, PCI burst size and early tx/rx threshold Support a 32-bit general-purpose timer, referenced by the external PCI clock source, and timer-interrupt Contain two large (2Kbyte) independent receive and transmit FIFOs Use 9346 (64*16-bit EEPROM) to store resource configuration and ID parameter Support LED pins for various network activity indications Support digital and analog loopback capability on both ports Half/Full duplex capability Support Full Duplex Flow Control (IEEE 802.3x)

M722 N/B MAINTENANCE

Figure 8:RTL8139CL Block Diagram

M722 N/B MAINTENANCE

0.2-15 IEEE 1394 : NEC UPD72870A

-The µPD72870A is the LSIs which integrated OHCI-Link and PHY function into a single chip.

-The µPD72870A comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work up to 400 Mbps.

-Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0

-Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps)

-Compliant with protocol enhancement as defined in P1394a draft 2.0

-Modular 32-bit host interface compliant to PCI Specification release 2.1

-Support PCI-Bus Power Management Interface Specification release 1.0

-Modular 32-bit host interface compliant to Card Bus Specification

-Cycle Master and Isochronous Resource Manager capable

-Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048bytes)

-32-bit CRC generation and checking for receive/transmit packets

-4 isochronous transmit DMAs and 4 isochronous receive DMAs supported

-32-bit DMA channels for physical memory read/write

-Clock generation by 24.576 MHz X?al

-Internal control and operational registers direct-mapped to PCI configuration space

-2-wire Serial EEPROM

interface supported

-Separate power supply Link and PHY

Figure 9 :Block Diagrams

M722 N/B MAINTENANCE

Figure 10:PHY Block Daigrams

Figure 11:Link Block Daigram s

M722 N/B MAINTENANCE

0.3. I/O P

ORT

One Power Supply Jack. One External CRT Connector For CRT Display IRDA SIR /MIR/FIR Supports four USB port for all USB devices (Std x2+Min x2) One Mini IEEE 1394 port for all IEEE 1394 Device One MODEM RJ-11 phone jack for PSTN line One RJ-45 for LAN. S/PDIF Digital Audio output Microphone Input Jack. One Cardbus Socket for extension One IDE extended port for IDE CDROM/DVD

0.4.P

ERIPHERAL COMPONENTS

0.4.1LCD PANEL

Brand model mane

HITACHI TX31D70VC1CAA/XGA(P) HYUNDAI HT12X11-100(P) SANYO TM121XG-02L02A

0.4.2 Floppy Disk Drive(USB)

Mitsumi: D353GU (3.5” 1.44MB/1.2MB/720KB FDD)

0.4.3 HDD

IBM (2.5” 9.5mmH): 6.0GB – DARA-206000 1 2GB – DARA-212000

Hitachi (2.5” 9.5mmH): 6.0GB – DK23AA-60 (P) 1 2 GB – DK23AA-12 (P)

M722 N/B MAINTENANCE

0.4.4 24X CD-ROM Drive

Brand model mane

Quanta SCR-242E

Matsushita UJDA150

0.4.5 8X DVD-ROM drive

Brand model mane

QUANTA SDR-081E

0.4.6 Keyboard

OKI

0.4.7 Touch Pad

ALPS

0.4.8 Fan

M722 N/B MAINTENANCE

0.5.A

PPENDIX

1: BANISTER GPIO

DEFINITIONS

Signal Name

POWER

PLANE

Input

Output/OD

Device Activity

Monitor

Default

Function

Value

GPIO_DIR

Defaults

M722 GPIO Setting

GPIO0 Resume PME# PME#,1 Input

I SCI#

GPIO1 Resume GPI(1) GPIO1 Input

GCL_LO/HI#

GPI02 GPIO2 Input

SPK_OFF

GPIO3 GNTA# GPIO3 Output

IDE_RST#

GPIO4 Resume Generic0 Generic 0 Input

HDD_PWR#

GPIO5 Pide1 PIDE1 Input

CRTIN#

GPIO6 Resume IRQ8# GPIO6 Input

CD_PWR

GPIO7 SERIRQ SERIRQ GPIO7 Input

I/O

SERIRQ

GPIO8 Core THERM# THERM#,1 Input

THERM#

GPIO9 Resume Input

KBD_US/JP

GPIO10 Resume LID LID,0 Input

CDROM_PLUG#

GPIO11 Resume BATLOW# BATLOW#.1 Input

H8_12V

GPIO12 Resume RI# RI#,1 Input

WAKE_UP#

GPIO13 AUDIO AUDIO Input

IDEDASP_ON

GPIO14 SPKR FDD SPKR,0 Output

SPKR

GPIO15 SERIAL A SERIAL A Input

CCD1#

GPIO16 PCS1# SERIAL B PCS1#,1 Output

HUB_SUSPEND#

GPIO17 Resume LPT LPT Input

MD/ID0

GPIO18 Resume GENERIC 1 GENERIC 1 Input

MD/ID1#

GPIO19 PCS0# GFX PCS0#.1 Output

LAN_IN#

GPIO20 Resume

CARDBUS

CARDBUS 0 Input

IRMD0

GPIO21 ZEROWS# CARDBUS2 ZEROWS#,1 Input

ZER0WS#

GPIO22 PIRQC# PIRQC# PIRQC#,1 Input

PIRQC#

GPIO23 PIRQD# PIRQD# PIRQD#,1 Input

PIRQD#

GPIO24 Resume EXTSMI# EXTSMI# EXTSMI#,1 Input

EXTSMI#

GPIO25 MSSS# MSSS#,1 Output

MCCS#

GPIO26 KBCCS# KBCCS#,1 Output

KBCS#

GPIO27 DREQ3 DREQ3,0 Input

DREQ3

GPIO28 DACK3# DACK3#,1 Output

DACK3#

GPIO29 PREQ3 Input

PREQ3#

GPIO30 PGNT3# Output

PGNT3#

Table 2: GPIO definitions.

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Specifications and Main Features

Frequently Asked Questions

User Manual