Mitac 8050d Service Manual

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SERVICE MANUAL FOR

8050D

8050D8050D

8050D

8050D8050D

8050D

8050D8050D

BY:

Repair Technology Research Department /EDVD

Grass

Mar.2004

.Ren

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Contents

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1. Hardware Engineering Specification …………………………………………………………………..

1.1 Introduce

1.2 System Overview ……………………………………………………………………………………….

1.3 System Hardware Parts …………………………………………………………………………………

1.4 Other Functions …………………………………………………………………………………….….

1.5 Power Management …………………………………………………………………………………….

………………………………………………………………………………………………

2. System View & Disassembly …………………………………………………………………………..

2.1 System View …………………………………………………………………………………………..

2.2 System Disassembly …………………………………………………………………………………….

3. Definition & Location of Connectors / Switches Setting ………………………………………………

4. Definition & Location of Major Component …………………………………………………………..

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5. Pin Description of Major Component…………………………………………………………………..

5.1 Intel Pentium M (Banias) Processor ……………………………………………………………………..

5.2 Intel 855GM/GME North Bridge ………………………………………………………………….…….

5.3 Intel 82801 IDBM I/O Controller Hub 4 Mobile(ICH4-M) South Bridge …………………………………..

3 6

7 34 40

43 46

71 75 84

6. System Block Diagram ……………………………………………………….……………………….....

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7. Maintenance Diagnostics ………………………………………………………………………………..

7.1 Introduction ……………………………………………………………………………………………

7.2 Debug Card …………………………………… ………………………………………………………

7.3 Error code……………………………… ……………………………………………………………..

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8. Trouble Shooting ……………………………………………………………………………………..….

8.1 No Power ……………………………………………………………………………………………….

8.2 Battery Can not Be Charged ……………………………………………………………………………..

8.3 No Display ………………………………… …………………………………………………………...

8.4 External Monitor No Display …………………………………………………………………………….

8.5 Memory Test Error ……………………………………………………………………………………..

8.6 Keyboard/Touch-pad Test Error ………………………………………………………………………...

8.7 USB Port Test error……………………………………………………………………………………...

8.8 Hard Disk Drive Test Error………………………………………………………………………………

8.9 CD-ROM Test Error …………………………………………………………………………………….

8.10 Audio Test Failure………………………………………………………………………………..….…

8.11 LAN Test Error ………………………………………………………………………………………..

8.12 Modem Test Error…………… …………………………………………………………………..……

8.13 Mini-PCI Test Error……….. ……… ………………………………………………………………....

8.14 Card Bus&Reader Test Error…………………………………………………………………………...

8.15 IEEE1394 Test Failure …………………………………………………………………………………

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99 104 106 112 114 116 118 120 122 124 127 129 131 133 135

9. Spare Parts List ……………………………………………………………………………… ….…..…...

10. System Exploded View ……………………………………………………………………………...…..

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11. Circuit Diagram ………………………………………………………………………………………....

12. Reference Material …………………………………………………………………………………..….

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1. Engineer Hardware Specification

1.1 Introduce

The MiTAC 8050D model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator, HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function.

The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR- SDRAM.

The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port (DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.

The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Intel Hub interface technology.

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The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics performance for notebooks. It’s architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATIs support of support of DirectX® 9 features, highly optimized Open GL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.

The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It

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implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and 400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets: asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations.

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The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader interface may operate simultaneously.

The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and

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transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the input data.

The W83L950D is a high performance micro-controller on-chip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high performance systems can be implemented easily.

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A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Overview

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CPU

Core logic Intel 855GME + ICH4-M chipset VGA Control ATi M10 System BIOS ST39SF040 Memory

Video Memory Share memory 32Mb Clock Generator ICS 950812 TV ATi M10 IEEE1394 VT6307L LAN RTL8100C PCMCIA + 4 IN 1 CARD ENE CB710 Audio System

Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above Thermal spec 35W TDP

DDR RAM : Apacer : 77.11021.460 Samsung 16*16 256MB 1st Apacer : 77.11021.580 Winbond 16*16 256MB 2nd A-DATA : 256MB

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AC97 CODEC: Advance Logic, Inc, ALC655 Power Amplifier: TI TPA0212

Modem AC97 Link: MDC (Mobile Daughter Card) Askey: V1456VQL-P1(INT)

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1.3 System Hardware Parts

1.3.1 Intel Banias Processors in Micro-FCPGA Package

Intel Banias Processors with 478 pins Micro-FCPGA package.

The first Intel mobile processor with the Intel Net Burst micro-architecture which features include hyper-pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock.

Support Enhanced Intel Speed Step technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes.

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1.3.2 Clock Generator

System frequency synthesizer: ICS950812 Programmable output frequency, divider ratios, output rise/fall time, output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if

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system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write operations. Use external 14.318MHz crystal.

 Provides standard frequencies and additional 5% and 10% over-clocked frequencies

 Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%,or ±0.75%), or Down

Spread (- 0.5%, -1.0%, or -1.5%)

 Offers adjustable PCI early clock via latch inputs

 Selectable 1X or 2X strength for REF via I2C interface

 Efficient power management scheme through PD#,CPU_STOP# and PCI_STOP#.

 Uses external 14.318MHz crystal

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 Stop clocks and functional control available through

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1.3.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset

Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4Xinterface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M

Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In

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-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-M together. Intel®’ I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O

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Link layer to/from INTEL 82801DBM ICH4-M.

An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.

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Features

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

Processor/Host Bus Support

 Intel® Banias processor

 2X Address, 4X data

 Support host bus Dynamic Bus Inversion (DBI)

 Supports system bus at 400MT/s (100 MHz)

 Supports 64-bit host bus addressing

 8-deep In-Order-Queue

 AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V)

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 Supports Enhanced Intel® Speed Step TM Technology (EIST) and Geyserville III

 Support for DPWR# signal to Banias processor for PSB power management

 Memory System

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 Directly supports one DDR channel, 64-bits wide (72-b with ECC).

 Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated)

with unbuffered PC1600/PC2100 DDR(with ECC).

 Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x

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16 devices.

 All supported devices have 4 banks.

 Supports up to 16 simultaneous open pages.

 Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row.

 UMA support only.

 System Interrupt

 Supports 8259 and Processor System Bus interrupt delivery mechanism

 Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface

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 MSI sent to the CPU through the system Bus

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 From IOxAPIC in ICH4-M

 Provides redirection for upstream interrupts to the System Bus

 Video Stream Decoder

 Improved HW Motion Compensation for MPEG2All format decoder (18 ATSC formats) supported

 Dynamic Bob and Weave support for Video Streams

 Software DVD at 60 fields/second and 30 frames/second full screen

 Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization

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 Video Overlay

 Single high quality scalable overlay and second Sprite to support second overlay

 Multiple overay functionality provided via Arithmetic Stretch Blt

 Direct YUV from Overlay to TV-out

 Independent Gamma Correction

 Independent Brightness / Contrast / Saturation

 Independent Tint / Hue support

 Destination Color keying

 Source Chromakeying

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 Maximum source resolution of 1920x1080 pixels

 Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or

1280x1024@ 85 Hz

 Display

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 Analog Display Support 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan

analog monitor up to 1800x1350 @ 85 Hz accompanying I2C and DDC channels provided through multiplexed interface hot plug and display support

 Dual independent pipe with single display support Simultaneous: Same images and native display timings on

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each display device

 DVO (DVOB) support

 Digital video out port DVOB with 165-MHz dot clock on 12-bit interface

 Variety of DVO devices channel

 Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel

resolution, or digital CRT up to 1920x1080 pixel resolution

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1.3.4 I/O Controller Hub : INTEL 82801DBM

The INTEL 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller with AC 97 Interface, the IDE Master/Slave controllers, and Intel®’ I/O Hub architecture. The PCI to LPC Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are integrated as well.

The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as over current detection are also implemented.

The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting multiple audio codecs with one separate modem codec.

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The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment.

INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB interrupt delivery modes is supported.

The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and

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power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel Mobile processor.

A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM ICH4-M Hub interface together. Intel®’ I/O Hub architecture is developed

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1.3.5 VGA Control

 Introducing MOBILITY M10

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The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATI’s support of DirectX® 9 features, highly optimized OpenGL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.

 SMARTSHADER™ 2.0 — Advanced Shader Technology

 Provides complete hardware-accelerated support for the new DirectX® 9 programmable shader model,

enabling more complex and realistic texture and lighting effects than ever before.

 Significant improvement over first-generation shaders introduced in DirectX® 8, with a much more

powerful and intuitive instruction set.

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 Offers full support for this feature in OpenGL® applications.

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 MOOTHVISION™ 2.0 — Flexible Anti-Aliasing and Anisotropic Filtering

 2x/4x/6x full-scene anti-aliasing modes

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 Adaptive algorithm with programmable sample patterns

 2x/4x/8x/16x anisotropic filtering modes

 Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options

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 High Performance Memory Support

 Incorporates support for DDR SDRAM/SGRAM.

 Features key items from ATI’s third generation HYPER Z™ III technology that conserves memory

bandwidth for improved performance in demanding applications.

 Dual Display Support

 Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports multiple

combinations of notebook LCD, traditional CRT monitors, flat panel displays and TV.

 Features Dual Channel DVI support.

 230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution.

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 Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA (1600x1200) resolution.

 High performance DAC speeds of 400MHz.

Features in Deta il

 VIDEO Acceleration

 M10 allows the integration of industry leading digital video features, including advanced de-interlacing

algorithms for unprecedented video quality and integrated digital TV decode capability. Includes programmable,independent gamma control for the video overlay.

 New FULLSTREAM™ technology removes blocky artifacts from streaming and Internet video and

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provides sharper image quality.

 Integrated general purpose xDCT engine (capable of performing both forward and inverse discrete cosine

transform) and motion compensation (MC) support for the acceleration of MPEG encoding and decoding as well as DV (digital video) encoding and decoding.

1.3.6 CardBus: CB710

 Features

 3.3V operation with 5V tolerant

 208-pin LQFP / 209-ball LFBGA package for CB710

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 328-ball LFBGA package for CB720

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 PCI Interface compliant with

 PCI Local Bus Specification, Revision 2.2

 PCI Bus Power Management Interface Specification, Revision 1.1

 PCI Mobile Design Guide, Version 1.1

 Advanced Configuration and Power Interface Specification, Revision 1.0

 CardBus Interface

 Compliant with PC Card Standard 8.0Support Standardized Zoomed Video Register Model

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 Support CardBay PC card interface

 Smart Card Interface

 Compliant with PC/SC Specification 1.0

 Support ISO7816 T=0 and T=1 asynchronous communication protocols

 Two power enable pins to support 5V and 3V smart cards

 Support programmable card clock frequencies

 Programmable F and D parameters to support different data rates

 One traffic LED pin.

 Secure Digital Interface

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 Compliant with SD Memory Card Specification Version 1.0

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 Support 4 parallel data lines

 Has an optional reference clock source to control the operating clock frequency of SD card

 Up to 10MByte/sec Read/Write rate when the optional reference clock source is used

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 Contains 16 Bytes of data buffer to regulate the data flow between PCI interface and the SD card interface

 Support Write Protect Switch

 Support Card Detect either by DAT3 or by dedicated Card Detect Switch

 One Traffic LED pin

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 One power enable pin.

 Memory Stick Interface

 Compliant with Memory Stick Standard Format Specification Version 1.3

 Has an optional reference clock source to control the operating clock frequency of Memory Stick

 Up to 2.5MByte/sec Read/Write rate when the optional reference clock source is used

 Stick interface

 One Traffic LED pin

 One power enable pin

 Smart Media Interface

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 One traffic LED pin

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 Interrupt configuration

 Supports CLKRUN# protocol

 Supports SUSPEND#

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 Supports D3STATE#

 Supports Zoomed Video port.

 Power Switch Interface

 Misc Control Logic

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 Supports socket activity LED

 Supports 12 GPIOs and GPE#

 Supports PCI LOCK

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1.3.7 AC’97 AUDIO SYSTEM: Advance Logic, Inc, ALC655

The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems,including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (Win XP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs can be detected.

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 Meets performance requirements for audio on PC99/2001 systems

 Meets Microsoft WHQL/WLP 2.0 audio requirements

 16-bit Stereo full-duplex CODEC with 48KHz sampling rate

 Compliant with AC’97 2.3 specifications

 14.318MHz- 24.576MHz PLL to save crystal

 12.288MHz BITCLK input can be consumed

 Integrated PCBEEP generator to save buzzer

 Interrupt capability

 Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX

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 High quality differential CD input

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 Two analog line-level mono input: PCBEEP,PHONE-IN

 Two software selectable MIC inputs applications (software selectable)

 Boost preamplifier for MIC input

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 50mW/20 amplifier

 External Amplifier Power Down (EAPD) capability

 Power management and enhanced power saving features.

 Stereo MIC record for AEC/BF application

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 Supports Power Off CD function

 Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback

 Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification

 Power support: Digital: 3.3V; Analog: 3.3V/5V

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1.3.8 MDC:PCTEL MODEM DAUGHTER CARD PCT2303W (ASKEY V1456VQL-P1)

The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance.

PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future.

The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to

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4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface specification Rev. 2.1.

The chip set is fully programmable to meet world-wide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements.

 Features

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 Virtual com port with a DTE throughout up to 460.8Kbps.

 G3 Fax compatible

 Auto dial and auto answer

 Ring detection

 Codec/DAA Features

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 AC97 2.1 compliant

 86dB dynamic range TX/RX paths

 2-4-wire hybrid

 Integrated ring detector

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 High voltage isolation of 4000V

 Support for “Caller ID”

 Compliant with FCC Part68, CTR21, Net4 and JATE

 Low power standby

 Low profile SOIC package 16 pins 10x3x1.55mm

 Low power consumption

 10mA @ 3.3V operation

 1mA @ 3.3V power down

 Integrated modem codec

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 Standard Features

 Data

ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bits (4.8Kbps to 14.4Kbps), V.22 bits (1.2 bps to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol.

 Data Compression ITU-T V.42bis MNP Class 5

 Error Correction ITU-T V.42 LAPM MNP 2-4

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 Fax

ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I

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1.3.9 IEEE1394 VT6307L (Option)

1.3.9.1 Overview

The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements the Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCI host bus interface. The VT6307 supports 100, 200 and 400 M bit/sec transmission via an

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integrated 2-port PHY. The VT6307 services two types of data packets: asynchronous and isochronous (real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations. The VT6307 is ready to provide industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms. Support for the VT6307 is built into Microsoft Windows 98, Windows ME, Windows 2000, and Windows XP.

1.3.9.2 Features

 32 bit CRC generator and checker for receive and transmit data

 On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general receive plus

2K for isochronous transmit plus 2K for asynchronous transmit)

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 8 isochronous transmit contexts

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 4 isochronous receive context

 3-deep physical post-write queue

 2-deep physical response queue

 Dual buffer mode enhancements

 Skip Processing enhancements

 Block Read Request handling

 Ack_tardy processing

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1.3.10 System Flash Memory (BIOS)

 Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets  Flexible Erase Capability

 Uniform 4 K Byte Sectors

 Uniform 16 K Byte overlay blocks for SST49LF002A

 Uniform 64 K Byte overlay blocks for SST49LF004ATop boot block protection

 16 K Byte for SST49LF002A

 64 K Byte for SST49LF004A

 Chip-Erase for PP Mode

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 Single 3.0-3.6V Read and Write Operations

 Superior Reliability

 Firmware Hub Hardware Interface Mode

 5-signal communication interface supporting byte Read and Write

 33 MHz clock frequency operation

 WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

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 Block Locking Register for all blocks

 Standard SDP Command Set

 Data# Polling and Toggle Bit for End-of-Write detection

 5 GPI pins for system design flexibility

 4 ID pins for multi-chip selection

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1.3.11 Memory System

1.3.11.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMM

 JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

 Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components

 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64

Meg x 64 [HD])

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 VDD= VDDQ= +2.5V ±0.2V

 VDDSPD = +2.2V to +5.5V

 2.5V I/O (SSTL_2 compatible)

 Commands entered on each positive CK edge

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 DQS edge-aligned with data for READs; center-aligned with data for WRITEs

 Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle

 Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture

 Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

 Four internal device banks for concurrent operation

 Selectable burst lengths: 2, 4, or 8

 Auto precharge option

 Auto Refresh and Self Refresh Modes

 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,

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 Serial Presence Detect (SPD) with EEPROM

 Fast data transfer rates PC2100 or PC1600

 Selectable READ CAS latency for maximum compatibility

 Gold-plated edge contacts

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1.3.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Ceiver ,The ICS1893

is a low-power, physical-layer device (PHY)

General

The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most efficient power management possible. The RTL8100C(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up(including AMD Magic Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the RTL8100C(L) can be shut down temporarily according to user requirements or when the RTL8100C(L) is in a power down state with the wakeup function disabled. In addition, when the analog part is shut down and the Isolate B pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the power consumption of the RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration space.

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 128 pin QFP/LQFP

 Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip

 10 Mb/s and 100 Mb/s operation

 Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation

 PCI local bus single-chip Fast Ethernet controller

 Compliant to PCI Revision 2.2

 Supports PCI clock 16.75MHz-40MHz

 Supports PCI target fast back-to-back transaction

 Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of

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RTL8100C(L)'s operational registers

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 Supports PCI VPD (Vital Product Data)

 Supports ACPI, PCI power management

 Supports 25MHz crystal or 25MHz OSC as the internal clock source.

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 The frequency deviation of either crystal or OSC must be within 50 PPM.

 Compliant to PC99/PC2001 standard

 Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up

frame)

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 Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)

 Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains

off

 Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI

configuration space.

 Includes a programmable, PCI burst size and early Tx/Rx threshold.

 Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-

interrupt

 Contains two large (2Kbyte) independent receive and transmit FIFOs

 Advanced power saving mode when LAN function or wakeup function is not used

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 Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data.

 Supports LED pins for various network activity indications

 Supports loop back capability

 Half/Full duplex capability

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 Supports Full Duplex Flow Control (IEEE 802.3x)

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1.3.13 Keyboard System: Winbond W83L950D

The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP- ROM that is divided into four banks, two SMBus interface for master and slave, Support 4 PWM channels, 2 D-A and 8 A-D converters. 2

 8051 uC based

 Keyboard Controller Embedded Controller

 Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB.

 Support 4 Timer (8 bit) signal with 3 prescalers.

 Support 2 PWM channels, 2 D-A and 8 A-D converters.

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 Reduce Firmware burden by Hardware PS/2 decoding

 Support 72 useful GPIOs totally

 Support Flash utility for on board re-flash

 Support ACPI

 Hardware fast Gate A20 with software programmable

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1.4 Other Functions

1.4.1 Hot Key Function

Keys Combination Feature Meaning

Fn + F1 Power down Mini PCI power down Fn + F2 Reserve Fn + F3 Volume Down Fn + F4 Volume Up Fn + F5 LCD/external CRT switching Rotate display mode in LCD only, CRT only, and simultaneously display. Fn + F6 Brightness down Decreases the LCD brightness Fn + F7 Brightness up Increases the LCD brightness Fn + F10 Battery Low Beep On/Off Battery Low Beep Fn + F11 Panel Off/On Toggle Panel on/off Fn + F12 Suspend to DRAM / HDD Force the computer into either Suspend to HDD or Suspend to DRAM

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mode depending on BIOS Setup.

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1.4.2 Power on/off/suspend/resume button

 APM mode

At APM mode, Power button is on/off system power.

 ACPI mode

At ACPI mode. Windows power management control panel set power button behavior.You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power button function.

Continue pushing power button over 4 seconds will force system off at ACPI mode.

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1.4.3 Cover Switch

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover.

At ACPI mode there are four functions to be chosen at windows power management control panel.

 None

 Standby

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 Off

 Hibernate (must enable hibernate function in power management)

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1.4.4 LED Indicators

 Three LED indicators at front side:

From left to right that indicate BATTERY POWER, BATTERY STATUS and AC POWER

 AC POWER:

This LED lights green when the notebook was powered by AC power line, Flashes (on 1 second, off 1 second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or powered by battery.

 BATTERY POWER:

This LED lights green when the notebook is being powered by Battery, and flashes (on 1 second, off 1 second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or powered by AC adapter.

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 BATTERY STATUS:

During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged.

 AC POWER:

This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second) when Suspend to RAM no matter using AC power or Battery power. The LED is off when the notebook is off or powered by battery.

 BATTERY POWER:

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This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when Battery is low. The LED is off when the notebook is off or powered by AC adaptor.

 Seven LED indicators:

System has seven status LED indicators at front side which to display system activity. From left to right that indicate HARD DISK, CD-ROM, NUM LOCK, CAPS LOCK, SCROLL LOCK, Mini PCI and Card Reader.

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1.4.5 Battery status

 Battery Warning

 System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store

data before battery dead. This function also protects system from mal-function while battery capacity is low.

 Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2

seconds.

 System will Suspend to HDD after 2 Minutes to protect users data.

 Battery Low State

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 After Battery Warning State, and battery capacity is below 5%, system will generate beep sound for twice

per second.

 Battery Dead State

 When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend

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the battery packs' life.

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1.4.6 Fan power on/off management

FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.

1.4.7 CMOS Battery

CR2032 3V 220mAh lithium battery When AC in or system main battery inside, CMOS battery will consume no power AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.

1.4.8 I/O Port

 One Power Supply Jack.

 One External CRT Connector For CRT Display

 Supports three USB port for all USB devices.

 One MODEM RJ-11 phone jack for PSTN line

 One RJ-45 for LAN.

 One IEEE1394 port

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 Headphone Out Jack.

 Microphone Input Jack.

 Line in Jack

1.4.9 Battery current limit and learning.

Implanted H/W current limit and battery learning circuit to enhance protection of battery.

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1.5 Power management

The 8050D system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.

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1.5.1 System Management Mode

 Full on mode

In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.

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 Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability.

The CPU power consumption and temperature is lower in this mode.

 Standby mode

For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device:

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-- CPU: Stop grant

-- LCD: backlight off

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-- HDD: spin down

 Suspend to DRAM

The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device:

 Suspend to DRAM

 CPU: off

 Intel 855GME: Partial off

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 VGA: Suspend

 PCMCIA: Suspend

 Audio: off

 SDRAM: self refresh

 Suspend to HDD

 All devices are stopped clock and power-down

 System status is saved in HDD

 All system status will be restored when powered on again

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1.5.2 Other power management functions

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 HDD & Video access

System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.

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2. System View and Disassembly

2.1 System View

2.1.1 Front View

1394 Jack



Line Out Connector



Line In Connector



MIC In Connector



SD Card Slot















Top Cover Latch



2.1.2 Left-side View

VGA Port



S-Video Port



USB Ports *1



Ventilation Openings



RJ-11 Connector



RJ-45 Connector



PCMCIA Card Socket



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













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2.1.3 Right-side View

CD-ROM/DVD-ROM Drive

 

Kensington Lock

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2.1.4 Rear View



Kensington Lock



Power Connector



USB Port*2



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

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



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2.1.5 Bottom View

Hard Disk Drive



DDR SDRAM Card



Wireless Card



CPU



Battery Park



Stereo Speaker Set

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











2.1.6 Top-open View

LCD Screen



Power Button



Stereo Speaker Set



Keyboard



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Device LED Indicators



Touch Pad



Hard Disk Drive Indicator



Battery Power Charging Indicator



Power Indicator



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



















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2.2 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power.

2.2.1 Battery Pack

2.2.2 Keyboard

2.2.3 CPU

Modular Components

2.2.4 HDD Module

NOTEBOOK

2.2.5 DVD-ROM Drive

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2.2.6 Wireless Card

2.2.7 Modem Card

2.2.8 DDR-SDRAM

2.2.9 LCD Assem bly

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LCD Assembly Components

Base Unit Components

2.2.10 LCD Panel

2.2.11 Inverter Board

2.2.12 System Board

2.2.13 Touch Pad

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2.2.1 Battery Pack

Disassembly

1. Carefully put the notebook upside down.

2. Slide the two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of the compartment (). (Figure 2-1)





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Figure 2-1 Remove the battery pack

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Reassembly

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound.

2. Slide the release lever to the “lock” ( ) position.

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2.2.2 Keyboard

Disassembly

1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Open the top cover.

3. Loosen the four latches locking the keyboard. (Figure 2-2)

4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard. (Figure 2-3)

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Figure 2-2 Loosen the four latches Figure 2-3 Disconnect the cable

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Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place with four latches.

2. Replace the battery pack. (Refer to section 2.2.1 reassembly)

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2.2.3 CPU

Disassembly

1. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove three screws fastening the heatsink cover. (Figure 2-4)

3. Remove three spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from system board. (Figure 2-5)

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Figure 2-4 Remove three screws

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Figure 2-5 Free the heatsink

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4. To remove the existing CPU, Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-6)

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Figure 2-6 Remove the CPU

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Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU.

2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with three spring screws.

3. Replace the CPU cover and secure with three screws.

4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

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2.2.4 HDD Module

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove two screws fastening the HDD compartment cover. (Figure 2-7)

3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8)

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Figure 2-8 Remove HDD moduleFigure 2-7 Remove the HDD compartment cover

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4. Remove four screws to separate the hard disk drive from the bracket, remove four screws. (Figure 2-9)

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Figure 2-9 Remove hard disk drive

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Reassembly

1. Attach the bracket to hard disk drive and secure with four screws.

2. Slide the HDD module into the compartment and secure with one screw.

3. Place the HDD compartment cover and secure with two screws.

4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

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2.2.5 CD/DVD-ROM Drive

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-10)

3. Push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out. (Figure 2-11)

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Figure 2-10 Remove one screw

Figure 2-11 Remove the CD/DVD-

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Reassembly

1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.

2. Replace the battery pack. (Refer to section 2.2.1 reassembly)

ROM drive

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2.2.6 Wireless Card

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.2.1 Disassembly)

2. Remove the two screws fastening the Mini PCI compartment cover. (Figure 2-12)

3. Disconnect the wireless card’s antennae first (). Then pull the retaining clips outwards () and remove the wireless card (). (Figure 2-13)









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Figure 2-12 Remove two screws

Reassembly

1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then sure that the antennae fully populated.

2. Tighten the screws to secure the wireless card compartment cover to the housing.

3. Replace the battery pack. (Refer to section 2.2.1 reassembly)

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Figure 2-13 Remove the Wireless card

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2.2.7 Modem Card

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly)

2. Remove two screws fastening modem card’s compartment cover. (Refer to steps 1-2 of section 2.2.6 Disassembly)

3. Remove two screws fastening the modem card. (Figure 2-14)

4. Lift up the modem card and disconnect the cord. (Figure 2-15)

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Figure 2-14 Remove two screws Figure 2-15 Disconnect the cord

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Reassembly

1. Reconnect the cord and fit the modem card.

2. Fasten the modem card by two screws.

3. Replace the modem card’s compartment cover by two screws. (Refer to step 2 of section 2.2.6 reassembly).

4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

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2.2.8 DDR-SDRAM

Disassembly

1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly)

2. Remove two screws fastening the DDR compartment cover to access the SO-DIMM socket. (Figure 2-16)

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Figure 2-16 Remove the cover Figure 2-17 Remove the SO-DIMM

3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-17)

Reassembly

1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the

SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position.

2. Replace two screws to fasten the DDR compartment cover.

3. Replace the battery pack. (See section 2.2.1 reassembly)

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2.2.9 LCD ASSY

Disassembly

1. Remove the battery pack, keyboard,CPU, hard disk drive, CD/DVD-drive and wireless card. (See sections 2.2.1,2.2.2, 2.2.3, 2.2.4, 2.2.5 and 2.2.6 Disassembly)

2. Remove the nineteen screws on the bottom of notebook. (Figure 2-18)

3. Remove the four screws that secure the hinge cover. (Figure 2-19)

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Figure 2-18 Remove nineteen screws Figure 2-19 Remove four screws

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4. Remove the two screws and disconnect the touch pad’s cable, then free the top cover.(Figure 2-20)

5. Remove the two hinge covers. (Figure 2-21)

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Figure 2-20 Free the Top cover Figure 2-21 Remove the hinge covers

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6. Disconnect the two cables and remove the four screws. (Figure 2-22)

7. Remove the eight screws. (Figure 2-23)

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Figure 2-22 Remove the four screws and

Disconnect the two cables

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Figure 2-23 Remove the eight screws

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8. Carefully pull the antenna wires out. Now you can lift up the LCD ASSY from base unit. (Figure 2-24)

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Figure 2-24 Free the LCD ASSY

Reassembly

1. Attach the LCD assembly to the base unit and secure with four screws.

2. Rip the antenna wires back into Min-PCI compartment.

3. Reconnect the two cables to the system board. Screw the hinge covers by two screws.

4. Replace the shield and secure with eight screws.

5. Replace the top cover and secure with two screws. And reconnect the touch pad’s cable.

6. Upside down the notebook. secure the housing by nineteen screws and secure two screws in the rear.

7. Replace the Wireless card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery pack. (Refer to sections 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 reassembly)

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2.2.10 LCD Panel

Disassembly

1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)

2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-25)

3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the cover is completely separated from the housing.

4. Remove the twelve screws and disconnect the cable. (Figure 2-26)

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Figure 2-25 Remove LCD cover

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Figure 2-26 Remove twelve screws and

disconnect the cable

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5. Remove the six screws that secure the LCD bracket. (Figure 2-27)

6. Disconnect the cable to free the LCD panel. (Figure 2-28)

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Figure 2-27 Remove the six screws

Figure 2-28 Free the LCD panel

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Reassembly

1. Replace the cable to the LCD.

2. Attach the LCD panel’s bracket back to LCD panel and secure with six screws.

3. Replace the LCD panel into LCD housing.and reconnect two cables to inverter board and secure with two screws.

4. Fasten the LCD panel by ten screws.

5. Fit the LCD cover and secure with two screws and rubber pads.

6. Replace the LCD assembly, CD/DVD-ROM drive, hard disk drive, keyboard, battery pack. (See sections

2.2.9, 2.2.5, 2.2.4, 2.2.2, and 2.2.1 reassembly)

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2.2.11 Inverter Board

Disassembly

1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly)

2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.2.10 Disassembly )

3. Remove the one screw fastening the inverter board and disconnect the cable, Then free the inverter board. (Figure 2-29)

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Figure 2-29 Free the inverter board

Reassembly

1. Reconnect the cable. Fit the inverter board back into place and secure with one screw.

2. Replace the LCD Panel and LCD cover. (Refer to section 2.2.10 reassembly)

3. Replace the LCD assembly. (Refer to section 2.2.9 reassembly)

4. Replace the CD/DVD-ROM drive, hard disk drive, keyboard and battery pack. (Refer to sections 2.2.5,

2.2.4, 2.2.2 and 2.2.1 reassembly)

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2.2.12 System Board

Disassembly

1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive, Wireless card and LCD assembly. (Refer to sections 2.2.1, 2.2.2, 2.2.4, 2.2.5, 2.2.6 and 2.2.9 Disassembly)

2. Remove the four screws that secure the system board and disconnect the two speaker’s cables. Then lift it up from the housing. (Figure 2-30)

3. Disconnect the one speaker’s cables from the system board and remove the two screws, Then separate the bracket and free the system board. (Figure 2-31)

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Figure 2-30 Remove four screws and

disconnect the two cables Figure 2-31 Free the system board

Reassembly

1. Fit the bracket and secure with two screws .

2. Turn over the system board. Reconnect the speaker’s cords.

3. Replace the system board back into the housing and secure with four screws, then reconnect the cable.

4. Replace the LCD assembly, CD/DVD-ROM, HDD, keyboard and battery pack. (Refer to previous section reassembly)

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2.2.13 Touch Pad

Disassembly

1. Remove the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and

2.2.5 Disassembly)

2. Remove the top cover. (See steps 1-5 in section 2.2.9 Disassembly)

3. Remove the two screws and free the touch pad. (Figure 2-32).

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Figure 2-32 Remove the two screws

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Reassembly

1. Replace the touch pad and secure the two screws.

2. Replace the top cover. (Refer to the section in 2.2.9 reassembly)

3. Replace the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 ,

2.2.4 and 2.2.5 Disassembly).

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3. Definition & Location of Connectors / Switches

3.1 Mother Board - A

SW4

SW5

SW2

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 J1 : Inverter Board Connector  J2 : LCD panel connector  J3 : Internal Left Speaker Connector  J4 : Touch-pad Module Connector  J5 : Internal Key-board Connector  J6 : PCMCIA Card Connector  J7 : Internal Right Speaker Connector

 SW2 : Power Button  SW4 : Left Button Switch of Touch-pad  SW5 : Right Button Switch of Touch-pad

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3. Definition & Location of Connectors / Switches

3.2 Mother Board - B

J702 J704

J701

PJ701

J703

J706

J707

 PJ701 : AC Adaptor Connector

J709

 J701&J706 : USB Port Connector  J702 : CRT Connector

J713

 J703 : Battery Connector  J704 : External VGA Connector  J705 : Internal Subwoofer Speaker  J707: FAN Connector

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J711

J712

 J708 : CD-ROM IDE Connector  J709: RJ45 & RJ11 Connector  J710 : RTC Battery Connector  J711&J712 : DDR SO-DIMM Module Socket

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 J713 : Mini-PCI Connector

J710

 J714 : Hard Disk Driver Connector

J705

J708 J714

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3. Definition & Location of Connectors / Switches

3.2 Mother Board - B

-----Continue From Previous Page-----

J715

J717

J718

 J715&J717: Modem Daughter Board Connector  J716 : SD&MS Card Socket  J718 : IEEE 1394 Connector  J719 : External Micro Phone Jack  J720 : Line Out HP/OPT Jack  J721 : External Line-in Jack

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J720

J721

J719

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J716

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4. Definition & Location of Major Components

4.1 Mother Board - A

 PU2 : +3VS/+5VS Voltage Generator  PU3 : CPU Core Voltage Generator  PU14: +1.8V/+1.35V Voltage Generator

PU2

 PU15 : +2.5VS/+1.25V Voltage Generator

U524

U16

U15

PU15

PU3

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 U2 : TV Encoder Controller  U15: SYS BIOS Controller  U16: WINBOND KBC Controller  U524: TPA02012 Audio Amplifier

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PU14

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4. Definition & Location of Major Components

4.2 Mother Board - B

 U706 : Thermal Sensor/Fan Controller  U710 : ATI-M10-P

U719

 U713 : Intel BANIAS CPU  U714 : Intel 855GM/GME North Bridge

U706

U710

 U715 : Intel ICH4-M South Bridge  U719 : LAN-RTL8100CL Controller  U724 : IEEE1394 Controller

U713

U727

U724

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 U725 : SUBWOOFER AMP Controller

U714

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U715

U725

U726

 U726 : Audio CODEC(ALC655)  U727 : CB710 Card Bus Reader Controller

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5. Pin Descriptions of Major Components

5.1 Intel Pentium M(Banias) Processor(1)

Signal Name Type Description

A[31:3]#

A20M#

ADS#

ADSTB[1:0]#

BCLK[1:0]

BNR#

BPM[2:0]# BPM[3]

I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space.

In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted.

I If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

I/O ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising

and falling edges. Strobes are associated with signals as shown below.

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]#

I The differential pair BCLK (Bus Clock) determines the system bus

frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs.

I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent

that is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

I/O

monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents. This includes debug or performance monitoring tools.

rocessor system bus. A[31:3]# are source

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Signal Name Type Description

BPRI#

BR0#

COMPP3:0]

D[63:0]#

DBR#

I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the

processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

I/O BR0# is used by the processor to request the bus. The arbitration is done

between the Intel Pentium M processor (Symmetric Agent) and the MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM chipset.

Analog COMP[3:0] must be terminated on the system board using precision

(1% tolerance) resistors. Refer to the platform design guides for more implementation details.

I/O D[63:0]# (Data) are the data signals. These signals provide a 64-

path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.

Quad-Pumped Signal Groups

Data Group DSTBN#/DSTBP# DINV#

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2

D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

O DBR# (Data Bus Reset) is used only in processor systems where no

debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal.

it data

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5.1 Intel Pentium M(Banias) Processor(2)

Signal Name Type Description

DBSY#

DEFER#

DINV[3:0]#

DPSLP#

DRDY#

DSTBN[3:0]#

DSTBP[3:0]#

I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving

data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both processor system bus agents.

I DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both processor system bus agents.

I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate

the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.

DINV[3:0]# Assignment To Data Bus

Bus Signal Data Bus Signals

DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]#

I DPSLP# when asserted on the platform causes the processor to

transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset.

I/O DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both processor system bus agents.

I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]#

I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]#

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Signal Name Type Description

DPWR#

FERR#/PBE#

GTLREF

HIT# HITM#

IERR#

IGNNE#

REQ[4:0]#

I DPWR# is a control signal from the Intel 855PM and Intel 855GM

chipsets used to reduce power on the Intel Pentium M data bus input buffers.

O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a

multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 80387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event.

I GTLREF determines the signal reference level for AGTL+ input pins.

GTLREF should be set at 2/3 receivers to determine if a signal is a logical 0 or logical 1.

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop

I/O

operation results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

O IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

I IGNNE# (Ignore Numeric Error) is asserted to force the processor to

ignore a numeric error and continue to execute noncontrol floating- instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

I/O REQ[4:0]# (Request Command) must connect the appropriate pins of

both processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

VCCP . GTLREF is used by the AGTL+

oint

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5.1 Intel Pentium M(Banias) Processor(3)

Signal Name Type Description

INIT#

LINT[1:0]

LOCK#

PRDY#

PREQ#

PROCHOT#

PSI#

I INIT# (Initialization), when asserted, resets integer registers inside the

processor without affecting its internal caches or floating- The processor then begins execution at the power on Reset vector configured during power on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST)

I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of

all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

I/O LOCK# indicates to the system that a transaction must occur atomically.

This signal must connect the appropriate pins of both processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock.

O Probe Ready signal used by debug tools to determine processor debug

readiness.

I Probe Request signal used by debug tools to request debug operation of

the processor.

O PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal may require voltage translation on the motherboard.

O Processor Power Status Indicator signal. This signal is asserted when the

processor is in a lower state (Deep Sleep and Deeper Sleep).

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Signal Name Type Description

oint registers.

PWRGOOD

ITP_CLK[1:0]

RESET#

I PWRGOOD (Power Good) is a processor input. The processor requires

I ITP_CLK[1:0] are copies of BCLK that are used only in processor

I Asserting the RESET# signal resets the processor to a known state and

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RS[2:0]#

RSVD

SLP#

I RS[2:0]# (Response Status) are driven by the response agent (the agent

- These pins are RESERVED and must be left unconnected on the board.

I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to

this signal as a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation.

systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects. These are not processor signals.

invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both system bus agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted.

responsible for completion of the current transaction), and must connect the appropriate pins of both processor system bus agents.

However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the platform design guides for more details.

enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

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5.1 Intel Pentium M(Banias) Processor(4)

Signal Name Type Description

SMI#

STPCLK#

TCK

TDI

TDO

TEST1, TEST2, TEST3 THERMDA THERMDC THERMTRIP#

TMS

TRDY#

TRST#

I SMI# (System Management Interrupt) is asserted asynchronously by

system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

I STPCLK# (Stop Clock), when asserted, causes the processor to enter a

low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

I TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

I TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

O TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

I TEST1, TEST2, and TEST3 must be left unconnected but should have a

stuffing option connection to V SS separately using 1-k, pull-down resisitors.

Other Thermal Diode Anode. Other Thermal Diode Cathode.

O The processor protects itself from catastrophic overheating by use of an

internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.

I TMS (Test Mode Select) is a JTAG specification support signal used by

debug tools.

I TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents.

I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

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Signal Name Type Description

VCC VCCA[3:0] VCCP VCCQ[1:0]

VCCSENSE

VID[5:0]

VSSSENSE

I Processor core power supply. I VCCA provides isolated power for the internal processor core PLL’s. I Processor I/O Power Supply. I Quiet power supply for on die COMP circuitry. These pins should be

O VCCSENSE is an isolated low impedance connection to processor core

O VID[5:0] (Voltage ID) pins are used to support automatic selection of

O VSSSENSE is an isolated low impedance connection to processor core

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connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary.

power (VCC ). It can be used to sense or measure power near the silicon with little noise.

power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Pentium M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations.

VSS. It can be used to sense or measure ground near the silicon with little noise.

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5.2 Intel 855GM/GME North Bridge(1)

Host Interface Signal Descriptions

Signal Name Type Description

ADS#

BNR#

BPRI#

BREQ0#

CPURST#

DBSY#

DEFER#

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

Addres s St r obe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth.

Bus Priority Request: The GMCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted.

Bus Request 0#:

low during CPURST#. The signal is sampled by the processor on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs. BREQ0# should be tristated after the hold time requirement has been satisfied. During regular operation, the GMCH will use BREQ0# as an early indication for FSB Address and Ctl input buffer and sense amp activation.

CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is asserted and for approximately 1 ms after RESET# is deasserted. The CPURST# allows the processor to begin execution in a known state. Note that the ICH4-M must provide CPU strap set-up and hold-times around CPURST#. This requires strict synchronization between GMCH, CPURST# deassertion and ICH4-M driving the straps. Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle.

Defer:

GMCH will generate a deferred response as defined by the

rules of the GMCH’s Dynamic Defer policy. The GMCH will also use the DEFER# signal to indicate a CPU retry response.

The GMCH pulls the processor bus BREQ

Confidential Document

Host Interface Signal Descriptions(Continued)

Signal Name Type Description

DINV[3:0]#

DPSLP#

signal

DRDY#

HA[31:3]#

MiTac Secret

HADSTB[1:0]#

HD[63:0]#

I/O

AGTL+

CMOS

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.

Indicates if the associated signals are inverted or not. DINV[3:0]# are

asserted such that the number of data bits driven electrically low (low

voltage) within the corresponding 16-bit group never exceeds 8.

DINV# Data Bits

DINV[3]# HD[63:48]#

DINV[2]# HD[47:32]#

DINV[1]# HD[31:16]#

DINV[0]# HD[16:0]#

Deep Sleep #: This signal comes from the ICH4-M device, providing

an indication of C3 and C4 state control to the CPU. Deassertion of

this signal is used as an early indication for C3 and C4 wake up (to

active HPLL). Note that this is a low-voltage

CMOS buffer operating on the FSB VTT power plane.

Data Ready: Asserted for each cycle that data is transferred.

Host Address Bus: HA[31:3]# connects to the CPU address bus.

During processor cycles the HA[31:3]# are inputs. The GMCH drives

HA[31:3]# during snoop cycles on behalf of Hub interface.

HA[31:3]# are transferred at 2x rate. Note that the

address is inverted on the CPU bus.

Host Address Strobe: HA[31:3]# connects to the CPU address bus.

During CPU cycles, the source synchronous strobes are used to

transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.

Strobe Address Bits

HADSTB[0]# HA[16:3]#, HREQ[4:0]#

HADSTB[1]# HA[31:17]#

Host Data: These signals are connected to the CPU data bus.

HD[63:0]# are transferred at 4x rate. Note that the data signals are

inverted on the CPU bus.

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Host Interface Signal Descriptions (Continued)

Signal Name Type Description

HDSTBP[3:0]# HDSTBN[3:0]#

HIT#

HITM#

HLOCK#

HREQ[4:0]#

HTRDY#

RS[2:0]#

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

I/O

AGTL+

Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x transfer rate.

Strobe Data Bits

HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]# HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]# HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]# HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]# Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no Hub interface snoopable access to system memory is allowed when HLOCK# is asserted by the CPU. Host Request Command: Defines the attributes of the request. HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent during both halves of the Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the GMCH Host Bridge are defined in the Host Interface section of this document.

Host Target Ready: Indicates that the target of the processor transaction is able to enter the data transfer phase.

Response Status: Indicates the type of response according to the following the table:

RS[2:0]# Response type

000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by GMCH) 100 Hard Failure (not driven by GMCH) 101 No data response 110 Implicit Write back 111 Normal data response

Confidential Document

DDR SDRAM Interface Descriptions

Signal Name Type Description

SCS[3:0]#

SMA[12:0]

SBA[1:0]

SRAS#

SCAS#

SWE#

MiTac Secret

SDQ[71:0]

SSTL_2

I/O

SSTL_2

Chip Select: These pins select the particular DDR SDRAM

components during the active state.

NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM

device row.

These signals can be toggled on every rising System Memory Clock

edge (SCMDCLK).

Multiplexed Memory Address: These signals are used to provide

the multiplexed row and column address to the DDR SDRAM.

Bank Select (Memory Bank Address): These signals define which

banks are selected within each DDR SDRAM row. The SMA and

SBA signals combine to address every possible location within a

DDR SDRAM device.

DDR Row Address Strobe: SRAS# may be heavily loaded and

requires tw0 DDR SDRAM clock cycles for setup time to the DDR

SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define

the system memory commands.

DDR Column Address Strobe: SCAS# may be heavily loaded and

requires two clock cycles for setup time to the DDR SDRAMs. Used

with SRAS# and SWE# (along with SCS#) to define the system

memory commands.

Write E n a b l e : Used with SCAS# and SRAS# (along with SCS#) to

define the DDR SDRAM commands. SWE# is asserted during writes

to DDR SDRAM.

SWE# may be heavily loaded and requires two clock cycles for setup

time to the DDR SDRAMs.

Data Lines: These signals are used to interface to the DDR SDRAM

data bus.

NOTE: ECC error detection is supported: by the SDQ[71:64] signals.

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DDR SDRAM Interface Descriptions (Continued)

Signal Name Type Description

I/O

SDQS[8:0]

SSTL_2

SCKE[3:0]

SSTL_2

SMAB[5,4,2,1]

SSTL_2

SDM[8:0]

SSTL_2

RCVENOUT#

SSTL_2

RCVENIN#

SSTL_2

Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group. SDQS[7] -> SDQ[63:56] SDQS[6] -> SDQ[55:48] SDQS[5] -> SDQ[47:40] SDQS[4] -> SDQ[39:32] SDQS[3] -> SDQ[31:24] SDQS[2] -> SDQ[23:16] SDQS[1] -> SDQ[15:8] SDQS[0] -> SDQ[7:0] NOTE: ECC error detection is supported by the SDQS[8] signal.

Clock Enable: These pins are used to signal a self-refresh or power down command to the DDR SDRAM array when entering system suspend. SCKE is also used to dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR SDRAM row. These signals can be toggled on every rising SCK edge.

Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not inverted.

Data Mask: When activated during writes, the corresponding data groups in the DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be sampled on both edges of the data strobes. NOTE: ECC error detection is supported by the SDM[8] signal.

Clock Output: Reserved, NC.

Clock Input: Reserved, NC.

Confidential Document

AGP Addressing Signal Descriptions

Signal Name Type Description

GPIPE#

GSBA[7:0]

AGP

MiTac Secret

5 contains two mechanism s to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master isnot allowed to queue addresses using the SBA bus . For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when the device is first being configured after reset

Pipelined Read: This signal is asserted by the AGP master to

indicate a full width address is to be enqueued on by the target using

the AD bus. One address is placed

in the AGP request queue on each rising clock edge while PIPE# is

asserted. When PIPE# is deasserted no new requests are queued

across the AD bus.

During SBA Operation: This signal is not used if SBA (Side Band

Addressing) is selected.

During F R AM E# Oper atio n: This signal is not used during AGP

FRAME# operation.

PIPE# is a sustained tri-state signal from masters (graphics

controller), and is an input to the GMCH.

Side-band Address: These signals are used by the AGP master

(graphics controller) to pass address and command to the GMCH. The

SBA bus and AD bus operate independently. That is, transactions can

proceed on the

AD bus simultaneously.

During PIPE# Operation:

operation.

During F R AM E# Oper atio n:

AGP FRAME# operation.

NOTE: When sideband addressing is disabled, these signals are

isolated (no external/internal pull-ups are required).

SBA

bus and the

These signals are

not used

These signals are

during PIPE#

not used

during

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AGP Status Signal Descriptions

Signal Name Type Description

GST[2:0]

AGP

Status: Provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be gnored.

ST[2:0 Meaning

000 Previously requested low priority

read data is being returned to the master arbiter to an AGP

001 Previously requested high priority

read data is being returned to the master

010 The master is to provide low priority

write data for a previously queued write command

011 The master is to provide high

priority write data for a previously queued write command.

100 Reserved

101 Reserved

110 Reserved

111 The master has been given

permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#

Confidential Document

AGP Flow Control Signals

Signal Name Type Description

GRBF#

GWBF#

AGP

MiTac Secret

Read Buffer Full: Read buffer full indicates if the master is ready to

accept previously requested low priority read data. When RBF# is

asserted the GMCH is not allowed to initiate the return low priority

read data. That is, the GMCH can finish

returning the data for the request currently being serviced. RBF# is

only sampled at the beginning of a cycle.

If the AGP master is always ready to accept return read data then it is

not required to implement this signal.

During FRAME# Operation: This signal is not used during AGP

FRAME# operation.

Write-Buffer Full: indicates if the master is ready to accept Fast

Write data from the GMCH. When WBF# is asserted the GMCH is

not allowed to drive Fast Write data to the AGP master. WBF# is

only sampled at the beginning of a cycle.

If the AGP master is always ready to accept fast write data then it is

not required to implement this signal.

During FRAME# Operation: This signal is not used during AGP

FRAME# operation.

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AGP/PCI Signals-Semantics Descriptions

Signal Name Type Description

I/O

GFRAME#

AGP

GIRDY#

AGP

G_FRAME: Frame. During PIPE# and SBA Operation: Not used by AGP SBA and

PIPE# operations. During Fast Write Operation: Used to frame transactions as an output during Fast Writes.

During FRAME# Operation:

GMCH acts as an initiator on the AGP Interface. G_FRAME# is asserted by the GMCH to indicate the beginning and duration of an access. G_FRAME# is an input when the GMCH acts as a FRAME#-based AGP target. As a FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which GMCH samples FRAME# active.

I/O

G_IRDY#: Initiator Ready. During PIPE# and SBA Operation: Not used while enqueueing

requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#- acts as a FRAME#-based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus initiator's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred.

ased AGP initiator and an input when the GMCH

G_FRAME# is an output when the

AGP Strobe Descriptions

Signal Name Type Description

GADSTB[0]

GADSTB#[0]

GADSTB[1]

GADSTB#[1]

GSBSTB

GSBSTB#

I/O

AGP

I/O

AGP

I/O

AGP

I/O

AGP

MiTac Secret

Address/Data Bus Strobe-0: provides timing for 2x and 4x data on

AD[15:0] and C/BE[1:0]# signals. The agent that is providing the

data will drive this signal.

Address/Data Bus Strobe-0 Complement: With AD STB0, forms a

differential strobe pair that provides timing information for the

AD[15:0] and C/BE[1:0]# signals. The agent that is providing the

data will drive this signal.

Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on

AD[31:16] and C/BE[3:2]# signals. The agent that is providing the

data will drive this signal.

Address/Data Bus Strobe-1 Complement: With AD STB1, forms a

differential strobe pair that provides timing information for the

AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is

providing the data will drive this signal.

Sideband Strobe: Provides timing for 2x and 4x data on the

SBA[7:0] bus. It is driven by the AGP master after the system has

been configured for 2x or 4x sideband address mode.

Sideband Strobe Complement: The differential complement to the

SB_STB signal. It is used to provide timing 4x mode.

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AGP/PCI Signals-Semantics Descriptions (Continued)

Signal Name Type Description

I/O

GTRDY#

AGP

GSTOP#

AGP

GDEVSEL#

AGP

GREQ#

AGP

G_TRDY#: Target Ready. During PIPE# and SBA Operation: Not used while enqueueing

requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The assertion of G_TRDY# indicates the target’s ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions.

I/O

G_STOP#: Stop. During PIPE# and SBA Operation: This signal is not used during

PIPE# or SBA operation. During FRAME# Operation: G_STOP# is an input when the GMCH acts as a FRAME#- the GMCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface.

I/O

G_ DEVSEL#: Device Select. During PIPE# and SBA Operation: This signal is not used during

PIPE# or SBA operation. During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The GMCH asserts G_DEVSEL# based on the DDR SDRAM address range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP master has recognized a PCI cycle to it.

G_REQ#: Request. During SBA Operation: This signal is not used during SBA

operation. During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based operation.

ased AGP initiator and is an output when

Confidential Document

ATP/PCI Signals-Semantics Descriptions(Continued)

Signal Name Type Description

GGNT#

GAD[31:0]

GCBE#[3:0]

MiTac Secret

GPAR

PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as an input to reset its internal logic.

AGP

I/O

AGP

I/O

AGP

I/O

AGP

G_GNT#: Grant.

During SBA, PIPE# and FRAME# Operation: G_GNT#, along

with the information on the ST[2:0] signals (status bus), indicates

how the AGP interface will be used next. Refer to the

Specificati on , Rev isi on 2.0

of the ST[2:0] values and their meanings.

G_AD[31:0]: Address/Data Bus.

During PIPE# and FRAME# Operation: The G_AD[31:0] signals

are used to transfer both address and data information on the AGP

interface.

During SBA Operation: The G_AD[31:0] signals are used to

transfer data on the AGP interface.

Command/Byte Enable.

During FRAME# Operation: During the address phase of a

transaction, the G_CBE[3:0]# signals define the bus command.

During the data phase, the G_CBE[3:0]# signals are used as byte

enables. The byte enables determine which byte lanes carry

meaningful data. The commands issued on the G_CBE# signals

during FRAME#-based AGP transactions are the same G_CBE#

command described in the PCI 2.2 specification.

During PIPE# Operation: When an address is enqueued using

PIPE#, the C/BE# signals carry command information. The command

encoding used during PIPE#-based AGP is

command encoding used during FRAME#-based AGP cycles (or

standard PCI cycles on a PCI bus).

During SBA Operation: These signals are not used during SBA

operation.

Parity.

During FRAME# Operation: G_PAR is driven by the GMCH when

it acts as a FRAME#-based AGP initiator during address and data

phases for a write cycle, and during the address phase for a read

cycle. G_PAR is driven by the GMCH when it acts as a

FRAME#-based AGP target during each data phase of a

FRAME#-based AGP memory read cycle. Even parity is generated

across G_AD[31:0] and G_CBE[3:0]#.

During SBA and PIPE# Operation: This signal is not used during

SBA and PIPE# operation.

for further explanation

different than the

AGP Interface

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Hub Interface Signals

Signal Name Type Description

HL[10:0]

HLSTB

HLSTB#

I/O

Hub

I/O

Hub

I/O

Hub

Packet Da ta: Data signals used for HI read and write operations.

Packet Strobe: One of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: One of two differential strobe signals used to transmit or receive packet data over HI.

Dedicated LVDS LCD Flat Panel Interface Signal Descriptions

Name Type Voltage Description

ICLKAP

LVDS

ICLKAM

LVDS

IYAP[3:0]

LVDS

IYAM[3:0]

LVDS

ICLKBP

LVDS

ICLKBM

LVDS

IYBP[3:0]

LVDS

IYBM[3:0]

LVDS

1.25 V± 225 mV

1.25 V±225 mV

1.25 V± 225 mV

Channel A differential clock pair output (true):

245-800 MHz

Channel A differential clock pair output (compliment): 245-800 MHz. Channel A differential data pair 3:0 output (true): 245-800MHz. Channel A differential data pair 3:0 output (compliment): 245-800 MHz. Channel B differential clock pair output (true): 245-800 MHz. Channel B differential clock pair output (compliment): 245-800 MHz. Channel B differential data pair 3:0 output (true): 245-800MHz. Channel B differential data pair 3:0 output (compliment): 245-800 MHz.

MiTac Secret

Confidential Document

Digital Video Output B (DVOB) Port Signal Descriptions

Name Type Description

DVOBD[11:0]

DVOBHSYNC

DVOBVSYNC

DVOBBLANK#

DVOBFLDSTL

DVO

O DVO

I DVO

DVOB Data: This data bus is used to drive 12-bit RGB data on each

edge of the differential clock signals, DVOBCLK and DVOBCLK#.

This provides 24-bits of data per clock period. In dual channel mode,

this provides the lower 12-bits of pixel data.

DVOBD[11:0] should be left as left as NC (“Not Connected”) if not

used.

Horizontal Sync: HSYNC signal for the DVOB interface.

DVOBHSYNC should be left as left as NC (“Not Connected”) if not

used.

Vertical Sync: VSYNC signal for the DVOB interface.

DVOBVSYNC should be left as left as NC (“Not Connected”) if the

signal is NOT used when using internal graphics device.

Flicker Blank or Border Period Indication: DVOBBLANK# is a

programmable output pin driven by the GMCH.

When programmed as a blank period indication, this pin indicates

active pixels excluding the border. When programmed as a border

period indication, this pin indicates active pixel including the border

pixels.

DVOBBLANK# should be left as left as NC (“Not Connected”) if not

used.

TV Field and Flat Panel Stall Signal. This input can be

programmed to be either a TV Field input from the TV encoder or

Stall input from the flat panel.

DVOB TV Field Signal: When used as a Field input, it synchronizes

the overlay field with the TV encoder field when the overlay is

displaying an interleaved source.

DVOB Flat Panel Stall Signal: When used as the Stall input, it

indicates that the pixel pipeline should stall one horizontal line. The

signal changes during horizontal blanking. The panel fitting logic,

when expanding the image vertically, uses this.

DVOBFLDSTL needs to be pulled down if not used.

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DVOB and DVOC Port Common Signal Descriptions

Name Type Description

DVOBCINTR#

DVO

ADDID[7:0]

DVO

DVODETECT

DVO

DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display.

ADDID[7:0]: These pins are used to communicate to the Video BIOS when an external device is interfaced to the DVO port. Note: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC.

DVODETECT: This strapping signal indicates to the GMCH whether a DVO device is present or not. When a DVO device is connected, then DVODETECT = 0.

Analog CRT Display Signal Descriptions

Pin Name Type Description

VSYNC

HSYNC

RED

RED#

GREEN

GREEN#

BLUE

BLUE#

CMOS

Analog

CRT Vertical Synchronization: This signal is used as the vertical sync signal.

CRT Horizontal Synchronization: This signal is used as the horizontal sync signal.

Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75-§Ù resistor on the board, in parallel with the 75-§Ù CRT load).

Red# (Analog Output): Tied to ground.

Green (Analog Video Output): This signal is a CRT analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g.,75-§Ù resistor on the board, in parallel with the 75- §Ù CRT load).

Green# (Analog Output): Tied to ground.

Blue (Analog Video Output) : This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75- ohm resistor on the board, in parallel with the 75-§Ù CRT load).

Blue# (Analog Output): Tied to ground.

Confidential Document

Digital Video Output C (DVOC) Port Signal Descriptions

Name Type Description

DVOCD[11:0]

DVOCHSYNC

DVOCVSYNC

DVOCBLANK#

DVOCFLDSTL

MiTac Secret

DVO

DVOC Data: This data bus is used to drive 12-bit RGB data on each

edge of the differential clock signals, DVOCCLK and DVOCCLK#.

This provides 24-bits of data per clock period. In dual channel mode,

this provides the upper 12-bits of pixel data.

DVOCD[11:0] should be left as left as NC (“Not Connected”) if not

used.

Horizontal Sync: HSYNC signal for the DVOC interface.

DVOCHSYNC should be left as left as NC (“Not Connected”) if not

used.

Vertical Sync: VSYNC signal for the DVOC interface.

DVOCVSYNC should be left as left as NC (“Not Connected”) if the

signal is NOT used when using internal graphics device.

Flicker Blank or Border Period Indication: DVOCBLANK# is a

programmable output pin driven by the GMCH.

When programmed as a blank period indication, this pin indicates

active pixels excluding the border. When programmed as a border

period indication, this pin indicates active pixel including the border

pixels.

DVOCBLANK# should be left as left as NC (“Not Connected”) if not

used.

TV Field and Flat Panel Stall Signal. This input can be

programmed to be either a TV Field input from the TV encoder or

Stall input from the flat panel.

DVOC TV Field Signal: When used as a Field input, it synchronizes

the overlay field with the TV encoder field when the overlay is

displaying an interleaved source.

DVOC Flat Panel Stall Signal: When used as the Stall input, it

indicates that the pixel pipeline should stall one horizontal line. The

signal changes during horizontal blanking. The panel fitting logic,

when expanding the image vertically, uses this.

DVOCFLDSTL needs to be pulled down if not used.

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GPIO Signal Descriptions

GPIO I/F Total Type Comments

RSTIN#

PWROK

AGPBUSY#

EXTTS_0

LCLKCTLA

LCLKCTLB

PANELVDDEN

PANELBKLTE N PANELBKLTC TL

DDCACLK

DDCADATA

DDCPCLK

DDCPDATA

CMOS

Reset: Primary Reset, Connected to PCIRST# of ICH4-M.

Power OK: Indicates that power to GMCH is stable.

AGPBUSY:

indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went active. Not active when the IGD is in any ACPI state other than D0.

External Thermal Sensor Input: This signal is an active low input to the GMCH and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle. The GMCH can be optionally programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the triggering of this signal.

SSC Chip Clock Control: Can be used to control an external clock chip with SSC control.

SSC Chip Data Control: Can be used to control an external clock chip for SSC control.

LVDS LCD Flat Panel Power Control: This signal is used enable power to the panel interface.

LVDS LCD Flat Panel Backlight Enable: This signal is used to enable the backlight inverter (BLI)

LVDS LCD Flat Panel Backlight Brightness Control: This signal is used as the Pulse Width Modulated (PWM) control signal to control the backlight inverter.

I/O

CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and the GMCH.

I/O

CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the GMCH.

I/O

Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the GMCH.

I/O

Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH.

Output of the GMCH IGD to the ICH4-M, which

Confidential Document

GPIO Signal Descriptions(Continued)

GPIO I/F Total Type Comments

MI2CCLK

MI2CDATA

MDVICLK

MDVIDATA

MDDCDATA

MDDCCLK

MiTac Secret

I/O

DVO

I/O

DVO

I/O

DVO

I/O

DVO

I/O

DVO

I/O

DVO

DVO I2C Clock: This signal is used as the I2C_CLK for a digital

display (i.e. TV-Out Encoder, TMDS transmitter). This signal is