MiTAC m230 Service Manual

BY: Sanny Gao

Technical Maintenance

Department /

GTK MTC

Nov.2006 / R01

SERVICE MANUAL FOR

M230

SERVICE MANUAL FOR

M230

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M230 N/B Maintenance

Contents

1. Hardware Engineering Specification ……………………………………………………………………

1.1 Introduction …………………………………………………………………………………………………………….

1.2 System Architecture ………………………………………………………………..………………………………….

1.3 Electrical Characteristic ……...………………………………………………………………………………………..

2. System View and Disassembly ……………………………………………… … ………… ………… …..

2.1 System View …………………………………………………………………………………………………………….

2.2 Tools Introduction …………………………………………………………………………………………………..….

2.3 System Disassembly …………………………………………………………………………………………………….

3. Definition & Location of Connectors/Switches …………………………………………………………

3.1 Mother Board ……….……………………………………………………………..……………………………………

3.2 I/O Board ……………………………………………...…………………………………………………………………

3.3 LED Board ………………………………………………………………………………………………………………

3.4 Touch Screen Board ……………………………………………………………………………………………………

3.5 Switch Board ……………………………………………………………………………………………………………

4. Definition & Location of Major Components …………………………………………………………..

4.1 Mother Board …………………………………………………………………………………………………..………

5. Pin Description of Major Component …….………………………………………………………… ….

5.1 Intel Yonah Processor CPU ……..…………………………………………………………………………………….

5.2 Intel 945GM North Bridge …………………………………………………………………………………………….

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5.3 Intel ICH7-M South Bridge ……………………………………………………………………………………………

6. System Block Diagram ……………………………………………………………………………………

7. Maintenance Diagnostics ……………………………… …………………………………………………

7.1 Introduction …………………………………………………………………………………………………………….

7.2 Maintenance Diagnostics ………………………………………………………………………………………………

7.3 Error Codes …………………………………………………………………………………………………………….

8. Trouble Shooting …………………………………………………………………………………… ……

8.1 No Power ……………………………………………………………………………………………………………….

8.2 No Display ………………………………………………………………………………………………………………

8.3 Graphic Controller Test Error LCD No Display …………………………………………………………………….

8.4 External Monitor No Display or Color Abnormal ….. ………………………………………………………………

8.5 Memory Test Error ………………………………………….…………………………………………………………

8.6 Keyboard (K/B) or Touch Pad (T/P) Test Error ……………..…………………………………………………...…

8.7 Hard Disk Drive Test Error ………………………..………………………………………………………………….

8.8 CD-ROM Test Error …………………………………………………………………..……………………………..…

8.9 USB Port Test Error ……………………………………………………………………………………………………

8.10 Audio Test Error ………………………………………………………………………………………..……………..

8.11 LAN Test Error ……………………………………………………………………………………………………….

8.12 1394B Test Error ……………………………………………………………………………………………………...

8.13 Mini Express (Wireless) Socket Test Error ………………………………………………………………………….

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8.14 PCMCIA Socket Test Error ……..……………………………………..………………………………………….…

9. Spare Parts List …………………………………………………………………………………………..

10. System Exploded Views ……………………………… ………………………………………………...

11. Reference Material ………………………………………………………………………………….…..

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The new M230 is ruggedized notebook, high-portability industrial computer. It can be used in the vehicle field and office. The notebook computer also can connect with a docking to extend the capability of I/O devices.

The M230 will support the Intel Mobile Pentium M based on 65 nm technology – Yonah 1.66 GHz processor or

1.5 GHz (option) processor via the 479-ball Micro-FCBGA packages and an operating Front Side Bus speed of 667 MHz.

The Intel 945GM north bridge chipset supports host system bus at 667 MHz, 2 slots of DDR2 SODIMM (400/533 MHz) 256 MB to 2 GB total, internal video controller support RGB, TV-out, SDVO and LVDS video interfaces and hub interface to south bridge ICH7-M.

The Intel 82801GBM (ICH7-M) south bridge supports PCI 2.3 interface, integrated IDE (PATA) controller, integrated Serial ATA (SATA) controller, integrated USB hub 2.0 up to 8 ports, integrated LAN 10/100 Mbit/s, integrated Intel high definition controller (Azalia), LPC interface, SMBus 2.0 interface, FWH interface, Real Time

1.1 Introduction

1. Hardware Engineering Specification

This document describes the system hardware engineering specification for M230 portable notebook computer system. The M230 notebook computer is a new mainstream high performance thin and light notebook in the MiTAC notebook family.

1.1.1 General Description

1.1.2 System Overview

– Marketing Requirement

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Clock (RTC), IRQ controller and advance programmable interrupt controller (APIC) support.

On PCI Bus interface exist PCI1520 card-bus controller and TSB82AA2 1394B controller that supports PC cards and 1394B device separately, Wireless LAN on mini PCIE interface and X-BAY radio interface.

On LPC interface exist super I/O that is SIO10N268. It provides four serial ports and one parallel port. The LPC will connect the Keyboard embedded controller H8S/2140 and flash memory for BIOS.

There are two SMBus interfaces, one is connected from ICH7-M and operating under master mode, the second is multi-master Bus and connected from H8S/2140. The Master provides interface to synthesizer and to memory identification. The multi-master channel used for thermal sensor controller (SMBus from LCD interface and SMBus from Docking).

A CODEC (ALC260) with TI audio amplifier stereo analog audio to internal speakers, audio jack and docking. Digital audio-PDIF standard also provided to audio jack and to docking.

System also provides LEDs to display system status, such as power on, battery state, HDD, Num Lock, Caps Lock and Scroll Lock.

The system also provides a port to expand docking capability. Input/Output (I/O) ports can include parallel port, serial port, VGA port, USB, line out, video input.

The system also provides DVD-ROM, Bluetooth, GPS, X-BAY radios.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows 2000 and Windows XP to take full advantage of the hardware capabilities.

Detailed specs as follow.

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Stan da rd: Intel Yonah processor LV dual core 1.66 GHz in µ-FCBGA package Intel Yonah processor LV dual core 1.5 GHz in µ-FCBGA package

CPU the rmal ceilin g: 15 W

FSB 667 M Hz

Core Logic

Intel 945GM chip s et (Calist oga) + ICH7-M (PCI Expres s x 6 chan nels )

L2 Cache

on-die 2 MB

1 MB flas h EPROM Includes system BIOS (Phoenix solution, Kernel core version), VGA BIOS, plug & play, ACPI2.0 c ap abilit y Boot from IDE & SATA devices, USB CD-ROM, USB FDD

Suspend to DRAM/HDD PC2001 compliance

Sta nda rd: 256 MB

Options : 512 MB/1 GB/2 GB (Max sys tem memory of 2 GB in 2 s lots )

Supports 400/533 MHz DDR2 devices

2 DDR2 SO-DIMM (200-p in)

- Integrated in 945GM chipset, Intel GMA950 graphic controller

- Optional A TI M54-CSP VGA con troller with 128 MB memory

- Dual view function/LCD/CRT simultaneous display capability

- 14.1" T FT XGA (1024 x 768) SPWG ty pe 14.1" LCD

- 15.0" TFT SXGA+ (1400 x 1050) SPW G ty pe 15.0" LCD (Opt iona l)

Factory optional touch screen

Factory option Hi-Contrast solution for 14" panel only

Structure

3-sp indle

Video Memory

Shared system memory 64 MB

- Stan dard: Serial ATA 60 GB; up t o 120 GB (5400 or 7200 rpm)

- Factory optional HDD heater for low temperature (-20 C~55 C) support

- Optional low temperature 20 GB HDD without HDD heater

Features

CPU

Memory

VGA Co ntroller

Display

Sy ste m BIOS

HDD

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- Built-in design to support operating mode free drop from 0 to 3 feet heigh

1~3 feet: Protected by G-sensor

0~1 foot: Protected by special construction resistance design

CD-ROM Bay

Easy swappable bay for CD-ROM/COMBO Drive/DVD dual recorder/2nd battery

- Wa te r-pro of membra ne key bo ard

- Factory optional water-proof rubber keyboard

- Factory optional back-light rubber keyboard

Pointing Device

A sensitive control touch pad: capacitance type (Optional water-proof: resistance type)

- Typ e II x 2 - Card Bus sup port

- Typ e II x 1 and bu ilt-in s mart c ard rea de r x 1 (option al)

Audio

Azalia 32 bits 192 KHz/AC97' 2.3 Audio digital controllerBuild-in Stereo 2 W speakers

- Serial port x 1

- USB 2.0 x 2 (USB power support maximum 1 A per port)

- IrDA FIR x 1

- DC inpu t x 1

- Docking Port (POGO pin, hot docking) compatible with M220

- CRT port x 1

- 1394B port x 1 (Optional: PS2 port x 1 )

- Parallel p ort x 1

- RJ-45 x 1

- RJ-11 x 1

- Microphone-in x 1

- Line-out x 1

- Integrated 10/100/1000 base-T Ethernet with TPM security function

- Integ rat ed 56 kbps Mo dem

- Integ rat ed Wireles s LAN (802.11 a/b /g ) with an tenna

- Factory optional GPS module with antenna

- Factory optional wireless module for GSM GPRS/CDMA with antenna

I/O Ports

Keyboard

PCMCIA

HDD

Communication

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- Factory optional Bluetooth with antenna

- No any interface between 4 antennas in the same time

Cooling

No fan

- Main battery supports over 5 hours

- Second battery supports over 2 hours (Based on system without M54 VGA controller)

- 90 Watts universal or above, auto sensing/switching, fully support all the functions

- Inp ut: 100-240 V, 50/60 Hz AC

- 328 x 272.1 x 46 mm fo r M230-4 (14.1")

- 338 x 286 x 46 mm fo r M230-5 (15") -Sa me dimensio n as M220

Weight

x1 (Fron t s ide)

Software

USB2.0, right side x 2, rear side x 2

IEC 68-2-1,2,14 / MIL-STD-810F, Method 501.4, 502.4

Operating: 0

C to 55 o C (standard)-W/O battery pack > 50 o C

-20

C to 60 o C (opt ion al)-W /O b attery p ac k > 50 o C

Storage: -40

C to 70oC

Humi dity

According to IEC 68-2-30/MIL-STD-810F, Method 507.45% to 95% RH, non-condensing Ac cordin g to IEC 68-2-13/MIL-STD-810F, Met hod 500.4 Operating: 15,000 ft, non-operating: 40,000 ft Altitude change rate: 2,000 ft/min

Ac cordin g to IEC 68-2-27/MIL-STD-810F, Met hod 516.5

Operating: 15 g, 11 ms, half sine wave

Non-operating: 50 g, 11 ms, half sine wave

Ac cordin g to IEC 68-2-6 / MIL-STD-810F, Me th od 514.5

Operat in g: 10~57.5 Hz/ 0.075 mm, 57.5~500 Hz/1.0 g

MIL-STD-810F, 514.5C1-high way truck vibration exposure

Non-operating: 10~57.5 Hz/0.15 mm, 57.5~500 Hz/2.0 g

MIL-STD-810F-514.5C-17 general minimum integrity exposure

Shock

Altitude

Battery

AC Adaptor

Temperature

Vibration

Dimensions

Enviro nmenta l Stan dard (Ma in System )

Communication

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According to IEC 68-2-32 / MIL-STD-810F, Method 516.5

- 3-foot-high free drop on steel plate, 4-foot-high free drop on plywood plate

- 26 times/one machine (Panel close/Power off)

Ac cordin g to IEC1000-4-2

Air Dis charg e:

0 KV~8 KV (includ ed), no any erro r

8 KV~15 KV, allow s oft error

Contact data pin discharge:

0 KV~6 KV (includ ed), no any erro r

6 KV~ 8 KV, allow so ft error

Sa lt Fog *

5% Sodium Chloride (NaCl) during the entire exposure period measure the salt fog fallout rate and PH of the fallout solution at least at 48-hour intervals. Ens ure the fallout is

between 1 and 3 ml/80 cm

/hr

Regulation

FCC p art 15, Su bp art B, C, Cla ss B, UL, CUL, TUV, CE! , CB, CCC, W HQL, BSM I, E-M ark

Removable Options:

Easy ch angea ble wireles s modem in X-BAY: EDGE, EVDO, GPS

ODD dev ices (Co mbo drive, DVD dual)

Veh icle do cking bo ard (Backward co mpatible with M220)

Factory Options:

HDD heater

Full travel membrane keyb oard with backlight

Rubber keyboard with backlight

Blu e too th (clas s 1) - TECOM Class I module BT3014 with Broad co m firmware v1.2

Options

Drop

ESD

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1.2.1 Function Description

1.2 System Architecture

1.2.1.1 CPU

 Intel Mobile Yonah processor

• First dual core processor for mobile (Yonah and Yonah low voltage skus)

• 667 MT/s (667 MHz) FSB support

• On-die, primary 32-KB instruction cache and 32-KB write back data cache

• On-die, 2 MB L2 cache with advanced transfer cache architecture

• Streaming SIMD Extension 2 (SSE2) and Streaming SIMD Extension 3 (SSE3)

• Support Intel architecture with dynamic execution

• Advanced gunning transceiver logic (AGTL+) bus driver technology

• Enhanced Intel SpeedStep technology to anable real-time dynamic switching between multiple

voltage and frequency points

• Data prefetch logic

• 479-ball Micro-FCBGA package

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1.2.1.2 North Bridge & 3D Graphics DDR2 Chipset – Intel 945GM

 FSB Support

• AGTL+bus driver technology with integrated GTL termination resister (gated AGTL+receivers for reduced

power)

• Supports 32-bit AGTL+host bus addressing

• 667 MT/s (667 MHz) and 533 MT/s (533 MHz) FSB support

• 2X address, 4X data

• Host bus dynamic bus inversion HDINV support

• 12 deep, in-order queue

 Integrated System Memory DRAM Controller

• Supports up to two DDR2 SDRAM channels (64 bit wide per channel)

• One SO-DIMM connecter per channel

• Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)

• Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 row=128 MB), using 256

MB technology Serial ATA controller

• 256 MB, 512 MB and 1 GB technology using X8 and X16 devices

• Three memory channel organization are supported for DDR2

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- Single channel

- Dual channel symmetric

- Dual channel asymmetric

• Support DDR2 400/533/667 devices

• Supports On-Die Termination (ODT) for DDR2

• Supports fast chip select mode

• Supports partial writes to memory using Data Mask signals (DM)

• Supports high-density memory package for DDR2 type devices

• Supports Reduced Power DDR2 (RPDDR2)

• Supports Intel Rapid Memory Power Management

 External Graphics Using PCI Express Architecture Interface

• One X16 (16 lanes) PCI Express port intended for graphics attach; fully compliant to the PCI Express base

specification revision 1.0a

• Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an

aggregate of 8 GB/s when X16

• Automatic discovery, negotiation and training of link out of set

• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)

• Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X ordering)

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• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e. normal PCI 2.3

configuration space as a PCI-to-PCI bridge)

• Supports lane reversal and bit swapping

 Internal Graphics Controller

• Graphics core frequency

- 2D Display core frequency at 133, 200 or 250 MHz @ Vcc=1.05 V depending on the host/ memory configurations

- 3D Render core frequency at 133, 166, 250 MHz @Vcc=1.05 V depending on the host/ memory configurations

-Intel

Smart 2D Display Technology

-Intel

dual-frequency graphics technology support

- Dynamic Video Memory Technology (DVMT) 3.0 support

• 3D graphics engine

- DirectX* 9.0 support

- OpenGL* 1.5 and 2.0 support

- Zone rendering 2.0 support

• Analog CRT DAC interface support

- Supports max DAC frequency up to 400 MHz

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- 24-bit RAMDAC support

- DDC2B compliant

- Up to 2048x1536 resolution support

• Analog TV-out interface support

- Integrated TV-out device supported on display pipes A and B

- NTSC/PAL encoder standard formats supports

- 480i/480p/576i/576p/720p/1080i/1080p modes supported

- Tri-level Sync signal

- Multiplexed output interface

- Composite video with S-Video

-S-Video

- Component video

- Up to 1024x768 resolution supported for NTSC/PAL

- Macrovision, overscan scaling and flicker filtering support

• Serial Digital Video out Port (SDVO) interface support

- Two SDVO ports are muxed with a subset of the external graphics interface using PCI Express architecture signals

- Each SDVO port support display pixel rates up to 200 MP/s (600 MB/s)

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- Supports a variety display devices such as DVI, TV-out, LVDS .etc

- Supports hot plug and display

- Support for HDCP SDVO devices

- Support for Macrovision on SDVO TV-out devices

- Support for lane reversal

• Digital LVDS interface support

- Integrated dual channel LVDS interface supported on display pipe B only

- Compliant with ANSI/TIA/EIA-644-2001 spec

- Supports 25 MHz to 112 MHz single/dual channel LVDS LCD interface with support for format of 1x18

bpp for TFT panels with single channel LVDS, 2x18 bpp for TFT panels with dual channels LVDS

- Panel fitting, panning and center mode supported

- Spread Spectrum Clocking (SSC) supported

- Panel power sequencing compliant with SPWG timing specification

- Integrated PWM or dedicated GMBus interface for LCD backlight inverter control

-Intel

Display Power Savings Technology 2.0 support

- Maximum UXGA panel size supported

- Maximum WUXGA wide panel size supported

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• PCI Express x1 port support

- One general purpose PCI Express port support

- External graphics using PCI Express architecture and SDVO are functional in this mode

• Direct Media Interface (DMI)

- Chip-to-chip interconnect between the GMCH and Intel 82801GBM

- DMI X2 and DMI X4 configurations support

- Bit swapping is supported

- Lane reversal is supported

• Packing/power

- 1466-ball micro-FCBGA (37.5 mm x 37.5 mm) with a 42-mil x 34-mil ball pitch

- VCC (1.05 core supply)

- VCCSM (DDR2=1.8 V I/O supply)

- VCCHV (3.3 V high voltage supply) VCCA_CRTDAC (2.5 V CRT analog supply) VCC_SYNC (2.5 V HSYNC/VSYNC supply)

- VCCD LVDS (1.5 V digital supply)

VCCTX_LVDS (2.5 V Data/CLK Tx power supply) VCCA_LVDS (2.5 V LVDS analog supply)

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- VCCA_TVBG (3.3 V TV DAC bnad gap supply)

VCCD_TVDAC (1.5 V TV DAC supply) VCCDQ_TVDAC (1.5 V TV DAC quiet supply) VCCA_TVDACA (3.3 V TV-out Channel A supply) VCCA_TVDACB (3.3 V TV-out Channel B supply) VCCA_TVDACC (3.3 V TV-out Channel C supply)

- VCC3G (1.5 V PIC-E/DMI analog supply)

VCC3A_GBG (2.5V PCI-E/DMI band gap supply)

- VCCA_HPLL (1.5 V host VCO supply) VCCA_MPLL (1.5 V system memory VCO) VCCD_HMPLL (1.5 V digital dividers supply) VCCA_3GPLL (1.5 V PCI-E PLL supply) VCCA_DPLLA/B (1.5 V Display A/B PLL supply)

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1.2.1.3 System Frequency Synthesizer – ICS9LPR310

 TI PCI 1520 – Card Bus Controller

• ICS9LPR310 is a low power CK410M-compliant clock specification. This clock synthesizer provides a

single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR310 is driven with a

14.318 MHz crystal 667 MT/s (667 MHz) FSB support

• Supports tight ppm accuracy clocks for Serial-ATA and PCIEX

• Supports programmable spread percentage and frequency

• Uses external 14.318 MHz crystal, external crystal load caps are required for frequency tuning

• PEREQ# pins to support PCIEX power management

• Programmable watchdog safe frequency

• Low power differential clock outputs (No 50 ohm resistor to GND needed)

1.2.1.4 PCMCIA Controller – TI PCI 1520+TPS2224A

•

The PCI1520, a dual-slot Card Bus controller designed to meet the PCI Bus power management interface specification for PCI to Card Bus bridges, is an ultra-low power high-performance PCI-to-Card Bus controller that supports two independent card sockets compliant with the PC card standard

• The PCI1520 provides features that make it the best choice for bridging between PCI and PC cards in both

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notebook and desktop computers. The 1997 PC card standard retains the 16-bit PC card specification defined in PCI local bus specification and defines the new 32-bit PC card, Card Bus, capable of full 32-bit data transfers at 33 MHz. The PCI1520 supports any combination of 16-bit and Card Bus PC cards in the two sockets, powered at 5 V or 3.3 V, as required

• The PCI1520 is compliant with the PCI local bus specification and its PCI interface can act as either a PCI master

device or a PCI slave device. The PCI bus mastering is initiated during Card Bus PC card bridging transactions. The PCI1520 is also compliant with PCI bus power management interface specification

• Key Features

- 209-terminal MicroStar BGA ball-grid array (GHK/ZHK) package

- 2.5 V core logic and 3.3 V I/O with universal PCI interfaces compatible with 3.3 V 5 V PCI signaling environments

- Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5 V power supply

- Mix-and-match 5 V/3.3 V 16-bit PC cards and 3.3 V Card Bus cards

- Two PC card or Card Bus slots with hot insertion and removal

- Serial interface to TI TPS222X dual-slot PC card power switch

- Burst transfers to maximize data throughput with Card Bus cards

- Interrupt configurations: parallel PCI, serialized PCI, parallel ISA and serialized ISA

- Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

- Pipelined architecture greater than 130 Mbps throughout from Card Bus-to-PCI and from PCI-to-Card Bus

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 TPS2224A – PCMCIA and Card Bus Power Switch

• The TPS2224A Card Bus power-interface switch provide an integrated power management solution for two

PC card sockets. These devices allow the controlled distribution of 3.3 V, 5 V, 12 V to each card slot. The current-limiting and thermal protection features eliminate the need for fuses. Current-limiting reporting helps the user isolate a system fault. The switch Rds (on) and current-limiting values have been set for the peak and average current requirements stated in the PC card specification

• key features

- Fast current limit response time

- Fully integrated VCC and VPP switching for 3.3 V, 5 V and 12 V

- Meets current PC card standards

- VPP output selection independent of VCC

- 12 V and 5 V supplies can be disabled

- TTL-Logic compatible inputs

- Short-circuit and thermal protection

- 140 µA (Typical) quiescent current from 3.3 V input

- Break-before-make switching

- Power-on reset

- 40 °C to 85 °C operating ambient temperature range

- 32-pin SSOP package

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1.2.1.5 Read Only Memory (Flash ROM)

•

FWH bus interface

• Single 3.3 V operations

• 3.3 V – volt Read

• 3.3 V – volt Erase

• 3.3 V – program

• Fast program operation

• VPP=12 V

• Byte-by-Byte programming: 9 µs (typ.)

• Fast erase operation

• Fast read access time: Tkg 11 ns

• Endurance: 30 K cycles (typ.)

• Twenty-year data retention

• 16 even sectors with 64 K bytes

• Any individual sector can be erased

• Hardware protection

• #TBL supports 64-Kbyte Boot Block hardware protection

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• #WP supports the whole chip except boot block hardware protection

• Hardware features

• Latched address and data

• TTL compatible I/O

• Automatic program and erase timing with internal VPP generation

• End of program or erase detection

• Toggle bit

• Data polling

• Low power consumption

• Read active current:15 mA (typ. for FWH mode)

• VPP input pin

• Acceleration (ACC) function accelerates program timing

• Hardware reset pin (#RESET)

• Reset the internal state machine to the read mode

• Ready/#Busy output (RY/#BY)

• Detect program or erase cycle completion

• Dual BIOS function

• Full-chip partition with 8 M-bit or dual-block partition with 4 M-bit

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• Available packages: 32L PLCC, 32L STSOP, 40L TSOP (10x20 mm), 32 PLCC lead free, 32L STSOP

lead free and 40L TSOP (10x20 mm) lead free

The H8S/2140 is a high-speed central processing unit with an internal 32-bit architecture that is upward- compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space and is ideal for real-time control.

Detail specification as below:

1.2.1.6 Keyboard Controller

•

Basic bus interface

• Burst ROM interface

• Idle cycle insertion

• Bus arbitration function

 Bus Controller

 Data Transfer Controller

• Transfer is possible over any number of channels

• Three transfer modes

• One activation source can trigger a number of data transfers (chain transfer)

• Direct specification of 16-Mbyte address space is possible

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• Operable at a maximum carrier frequency of 625 KHz using pulse division (at 10 MHz operation)

• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)

• Direct or inverted PWM output and PWM output enable/disable control

• Activation by software is possible

• Transfer can be set in byte or word units

• A CPU interrupt can be requested for the interrupt that activated the DTC

• Module stop mode can be set

• Selection of four clock sources

• Two independent comparators

• Four independent input capture channels

• Counter clearing

• Seven independent interrupts

• Special functions provided by automatic addition function

 16-Bit Free-Running Timer (FRT)

 8-Bit PWM Timer (PWM)

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 14-Bit PWM Timer (PWMX)

• Division of pulse into multiple base cycles to reduce ripple

• Two resolution settings

• Two base cycle settings

• Four operating speeds

• Four operation clocks (by combination of two resolution settings and two base cycle settings)

 8-Bit Timer (TMR)

• Selection of clock sources

• Selection of three ways to clear the counters

• Timer output controlled by two compare-match signals

• Cascading of TMR_0 and TMR_1

• Multiple interrupt sources for each channel

 Timer Connection

• Five input pins and four output pins, all of which can be designated for phase inversion

• An edge-detection circuit is connected to the input pins, simplifying signal input detection

• TMR_X can be used for PWM input signal decoding

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• TMR_X can be used for clamp waveform generation

• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks

• Switchable between watchdog timer mode and interval timer mode

 Serial Communication Interface (SCI & IrDA)

• Choice of asynchronous or clocked synchronous serial communication mode

• Full-duplex communication capability

• The on-chip baud rate generator allows any bit rate to be selected

• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)

• Four interrupt sources

 Watchdog Timer (WDT)

 Bus Interface (IIC)

• Selection of addressing format or non-addressing format

• Conforms to Philips I2Cbus interface (I2Cbus format)

• Two ways of setting slave address (I2Cbus format)

• Start and stop conditions generated automatically in master mode (I2C bus format)

• Selection of the acknowledge output level in reception (I2C bus format)

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• Automatic loading of an acknowledge bit in transmission (I2C bus format)

• Wait function in master mode (I2C bus format)

• Wait function (I2C bus format)

• Interrupt sources

• Selection of 16 internal clocks (in master mode)

• Direct bus drive (SCL/SDA pin)

• Automatic switching from formatless mode to I2C bus format (IIC_0 only)

 Host Interface X-Bus Interface

• Control of the fast GATE A20 function

• Shutdown of the XBS module by the HIFSD pin

• Five host interrupt requests

 Keyboard Buffer Controller

• Conforms to PS/2 interface specifications

• Direct bus drive (via the KCLK and KD pins)

• Interrupt sources: on completion of data reception and on detection of clock edge

• Error detection: parity error and stop bit monitoring

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 Host Interface LPC Interface (LPC)

• Supports LPC interface I/O read cycles and I/O write cycles

• Has three register sets comprising data and status registers

• Supports SERIRQ

• Eleven interrupt sources

 A/D Converter

• 10-bit resolution

• Input channels: eight analog input channels and 16 digital input channels

• Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as

an analog reference voltage

• Conversion time: 13.4 µs per channel (at 10-MHz operation)

• Two kinds of operating modes

• Four data registers

• Sample and hold function

• Three kinds of conversion start

• Interrupt request

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 D/A Converter

• 8-bit resolution

• Two output channels

• Conversion time: Max. 10 µs (when load capacitance is 20 pF)

• Output voltage: 0 V to AVref

• D/A output retaining function in software standby mode

 I/O ports

• Ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7)

 Interrupt Controller

• Two interrupt control modes

• Priorities settable with ICR

• Independent vector addresses

• Thirty-one external interrupts

• DTC control

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MiTAC m230 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual