MiTAC 8500 Service Manual

SERVICE MANUAL FOR
SERVICE MANUAL FOR
SERVICE MANUAL FOR
8500
8500
85008500
8500
8500
85008500
8500
8500
85008500
BY:
TESTING TECHNOLOGY DEPARTMENT / TSSC
TESTING TECHNOLOGY DEPARTMENT / TSSC
Sissel Diao
Sissel Diao
Aug . 2002
Contents
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1. Hardware Engineering Spec ification ……………………………… …………………………………
Introduction ………………………………………………………………………………………………………….
1.1
1.2 System Hardware Parts …………………………………………………………………………………………….
1.3 Other Functions ……………………………………………………………………………………………………..
1.4 Peripheral Components ……………………………………………………………………………………………..
1.5 Power Management …………………………………………………………………………………………………
1.6 Appendix 1: SiS961 GPIO Definitions ……………………………………………………………………………..
1.7 Appendix 2: H8 Pins Definitions ……………………………………………………………………………………
2. System View and Disassembly ………………………………………………………………………...
2.1 System View ………………………………………………………………………………………………………….
2.2 System Disassembly …………………………………………………………………………………………………
3. Definition & Location of Connectors / Switches ……………………………………………………..
3.1
Mother Board ………………………………………………………………………………………………………..
4. Definition & Location of Major Comp onent …………………………………………………………
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4.1
Mother Board ………………………………………………………………………………………………………..
5. Pin Description of Major Component ………………………………………………………………...
Intel Pentium 4 Processor mPGA478 Socket ……………………………………………………………………...
5.1
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5.2 SiS650 IGUI Host / Memory Controller …………………………………………………………………………...
5.3 SiS691 MuTIOL Media I/O Controller ……………………………………………………………………………
5.4 SiS301LV / Chrontel CH7017 TV/LVDS Encoder ………………………………………………………………..
5.5 MB86613L IEEE1394 Controller ………………………………………………………………………………….
6. System Block Diagram ……………………………………………… …………………………………
7. Maintenance Diagnostics …………… ………………………………………… ………………………
7.1 Introduction ………………………………………………………………………………………………………….
7.2 Error Codes ………………………………………………………………………………………………………….
7.3 Maintenance Diagnostics ……………………………………………………………………………………………
8. Trouble Shooting ……………………………………………………………………………………….
No Power ……………………………………………………………………………………………………………..
8.1
8.2 No Display ……………………………………………………………………………………………………………
8.3 VGA Controller Failure LCD No Display …………………………………………………………………………
8.4 External Monitor No Display ………………………………………………………………………………………
8.5 Memory Test Error …………………………………………………………………………………………………
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………….
8.7 Hard Disk Drive Test Error ………………………………………………………………………………………..
8.8 CD-ROM Drive Test Error …………………………………………………………………………………………
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8.9 Floppy drive Test Error……………………………………………………………………………………………..
8.10 USB Test Error …………………………………………………………………………………………………….
8.11 PIO Port Test Error ……………………………………………………………………………………………….
8.12 Audio Failure ………………………………………………………………………………………………………
8.13 LAN Test Error ……………………………………………………………………………………………………
8.14 IEEE 1394 Failure …………………………………………………………………………………………………
9. Spare Parts List ………………………………………………………………………………………..
10. System Exploded Views …………… ………………………………………… ………………………
11. Circuit Diagram …………………………………………………………… …………………………
12. Reference Material ……………………………………………………………………………………
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1. Hardware Engineering Specification
1.1 Introduction
The 8500 motherboard would support the Intel® Pentium® 4 processor with FCPGA packaged, mPGA478 Socket,
which will supports the different levels up to Willamette P4 1.7GHz (Throttling)/Northwood above 2.0GHz
(Throttling).
This system is based on PCI architecture, which have standard hardware peripheral interface. The power
management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy
configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at
system start up or warm reset. System also provides icon LEDs to display system status, such as power indicator,
HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery charging status. It
also equipped 4 USB ports.
The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual in-line
memory module (SODIMM), support PC2100 & PC2700.
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor,
a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.
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The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the
Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect to PCI
bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O
Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated.
The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86
compatible microprocessors like PIII, K7 and P4.
The SiS301LV/Chrontel CH7017 is a Display Controller device which accepts two digital graphics input data
streams. One data stream outputs through an LVDS transmitter to an LCD panel, while the other data stream is
encoded for NTSC or PALTV and outputs through a 10-bit high speed DAC. The TV encoder device encodes a
graphics signal up to 1024 x 768 resolution and outputs the video signals according to NTSC or PAL standards.
The LVDS transmitter operates at pixel speeds up to 165MHz per link, supporting 1600 x 1200 panels at 60Hz
refresh rate.
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To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto
the motherboard.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Me
and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows 95-
ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI).
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Hardware Parts
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CPU
Core logic
VGA Control System BIOS
Memory
Video Memory Clock Generator DDR Clock Buffer IEEE1394 Audio System
Super I/O Modem PHY of LAN
Intel Desktop Pentium 4 processor with OLGA Package, uFC-PGA 478 Socket Support up to P4 2.4GHz (Target Thermal ceiling 65W) SiS650+SiS961: Host & Memory & AGP Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance memory controller, a AGP interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO. SiS301LV/Chrontel CH7017 256KB Flash EPROM Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI 0MB on board memory
-Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
-Support PC2100 & PC2700 8/16/32/64 UMA ICS 952001 ICS 93722 MB86613L AC97 CODEC: Advance Logic, Inc, ALC201 Power Amplifier: TI TPA0202 W83697HG 56Kbps(V.90, worldwide) MDC Modem ICS1893Y-10 10/100 base T PHY
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1.2.1 CPU_Intel Pentium 4 Processor
The Intel® Pentium® 4 processor, Intel’s most advanced, most powerful processor, is based on the new Intel®
NetBurst™ micro-architecture. The Pentium 4 processor is designed to deliver performance across applications and
usages where end users can truly appreciate and experience the performance. These applications include Internet
audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multi-media, and
multi-tasking user environments. The Intel Pentium 4 processor delivers this world-class performance for consumer
enthusiast and business professional desktop users as well as for entry-level workstation users.
Highlights of the Pentium 4 Processor :
Available at speeds ranging from 1.50 to 2 GHz
Featuring the new Intel NetBurst micro-architecture
Supported by the SiS650 chipset
Fully compatible with existing Intel Architecture-based software
Internet Streaming SIMD Extensions 2
Intel® MMX™ media enhancement technology
Memory cache ability up to 4 GB of addressable memory space and system memory scalability up to 64GB of
physical memory
Support for uni-processor designs
Based upon Intel’s 0.18 micron manufacturing process
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Intel Pentium 4 Processor Product Feature Highlights
The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper Pipelined
Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as a number of
enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floating-point and Multi-
media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances were made possible
with improvements in processor technology, process technology, and circuit design that could not previously be
implemented in high-volume, manufacturable solutions. The features and resulting benefits of the new micro-
architecture are defined below.
Hyper Pipelined Technology:
The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared to the P6
micro-architecture used on today’s Pentium III processors. One of the key pipelines, the branch prediction/
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recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to 10 stages in the P6
micro-architecture. This technology significantly increases the performance, frequency, and scalability of the
processor.
400 MHZ System Bus:
The Pentium4 processor supports Intel’s highest performance desktop system bus by delivering 3.2 GB of data
per second into and out of the processor. This is accomplished through a physical signaling scheme of quad
pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowing for sustained
400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium III processor’s 133-MHz system
bus.
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Level 1 Execution Trace Cache:
In addition to the 8KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processor’s execution units and a reduction in the overall time required to recover from branches that have been mis-predicted.
Rapid Execution Engine:
Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in half a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processor runs at 3 GHz.
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256KB, Level 2 Advanced Transfer Cache:
The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughput
channel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256­bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium III processor at 1 GHz. Features of the ATC include:
Non-Blocking, full speed, on-die Level 2 cache
8-way set associativity 256-bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle
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Advanced Dynamic Execution:
The Advanced Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about 33% over the P6 generation processor’s branch prediction capability. It does this by implementing a 4KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction
algorithm.
Enhanced Floating-Point and Multimedia Unit:
The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register for
data movement which improves performance on both floating-point and multimedia applications.
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Internet Streaming SIMD Extensions 2 (SSE2):
With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities that MMX
technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications.
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Features Used for Test and Performance / Thermal Monitoring:
Built-in Self Test (BIST) provides single stuck-at fault coverage of the micro-code and large logic arrays, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs), and ROMs.
IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Pentium 4 processor and system connections through a standard interface.
Internal performance counters can be used for performance monitoring and event counting.
Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to expected application power usages rather than theoretical maximums.
1.2.2 System Frequenc y
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1.2.2.1 System frequency synthesizer_ICS952001
Programmable Timing Control Hub™ for P4™ processor General Description :
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with
a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the
necessary clocks signals for such a system.
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The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control
Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a
single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output
clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the
output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's
Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N
control can configure output frequency with resolution up to 0.1MHz increment.
Recommended Application:
SiS645/650 style chipsets
Output features:
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2 - Pairs of differential CPUCLKs @ 3.3V
1 - SDRAM @ 3.3V
8 - PCI @3.3V
2 - AGP @ 3.3V
2 - ZCLKs @ 3.3V
1 - 48MHz, @3.3V fixed
1 - 24/48MHz, @3.3V selectable by I2C
3 - REF @3.3V, 14.318MHz
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Features/Benefits:
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write operations
For PC133 SDRAM system use the ICS9179-06 as the memory buffer.
For DDR SDRAM system use the ICS93705 as the memory buffer.
Uses external 14.318MHz crystal.
Key Specifications:
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PCI - PCI output skew: < 500ps
CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
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1.2.2.2 DDR buffer frequency synthesizer_ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
SiS645/650 style chipsets
Product description/features:
Low skew, low jitter PLL clock driver
I2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
Switching Characteristics
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
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1.2.3 Core Logic_SiS650 + SiS961
1.2.3.1 SiS650 IGUI Host/Memory Controller
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a
high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS
MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media IO.
SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die
termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support
maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video
Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series
based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the
bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O
masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability
and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is incorporated to connect
SiS650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is developed into three layers, the
Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and
external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder
in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer to/from SiS650, and the
Multi-threaded I/O Link Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link
layer to/from SiS961.
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An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high
performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or
external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function
by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts
the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing
the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D
accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware
acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to
SiS301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to support
the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge integrates an
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NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-
linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The
primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View
Capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.
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Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128 bit
are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266
memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate,
respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and
the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP
controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of
dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous
downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb
the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-
data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue.
The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an
effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background
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when the data requests streamlines in the foreground.
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1.2.3.2 SiS961 MuTIOL® Media I/O overview
The SiS961 MuTIOL® Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC,
the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL® Connect to
PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O
Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated.
The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86
compatible microprocessors like PIII, K7 and P4.
The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1-channel
Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation. Besides, 4
separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codec maximally,
effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both traditional consumer
digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are supported. VRA mode is
also associated with both the AC 97 audio link and the traditional consumer digital audio channel.
The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supporting full
duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames, Magic Packet
and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated MAC provides a
scheme to store the MAC address without the need of an external EEPROM. The 25 MHz oscillating circuit is
integrated so as only an external low cost 25 MHz crystal is needed for the clocking system.
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The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host
controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be
optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also
implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting
PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that
sustain the high data transfer rate in the multitasking environment. The MuTIOL® Connect to PCI bridge
supporting 6 PCI master is compliant to PCI 2.2 specification. The SiS961 also incorporates the legacy system I/O
like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired
keyboard controller and PS2 mouse interface, Real Time clock with 256B CMOS SRAM and two 8259A
compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB
interrupt delivery modes is supported.
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The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep power state for
Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during
C3 and S1 state.
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1.2.4 SiS301LV/Chrontel CH7017 TV Encoder / LVDS Transmitter
General Description
SiS301LV, which is an accompany chip of SiS VGA chip, integrates :
A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display.
A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display.
All the above functions can support dual-display features. It means that the second display device driven by
SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT
monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the
primary VGA chip then transforms them into composite, S-Video or component video output for TV display,
LVDS signals for LCD display. The output display combination can be one of the three :
(1) Primary CRT+SiS301LV TV
(2) Primary CRT+SiS301LV LCD
(3) SiS301LV TV + SiS301LV LCD.
The package type of SiS301LV is 128-pin LQFP.
Frame Buffe r
Primary
VGA
(SiS650/ SiS330
1st channel
2
)
nd
channel
Video
Decoder
Feature Connector
SiS301LV
CRT
Monitor
NTSC/PAL
TV
LCD
Monitor
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1.2.4.1 TV Display :
Supports PAL and NTSC Systems.
Supports Composite, S-Video, and Component RGB( SCART) Output Signals
Supports Macrovision Copy Protection Process Rev. 7.1.L1
Support Progressive TV 525P YPbPr Output Signals.
Support Macrovision Conpy Protection Waveforms for 525p Progressive Scan Output
Supports TV/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode
Provides Adaptive 6-Line Anti-Flicker Filtering.
Provides Hardware Interpolation for Programmable Under-Scan/Over-Scan Adjustment.
Provides Programmable Display Position Adjustment.
Provides Programmable Notch Filter for Cross Color Elimination.
Provides Chrominance Filter for Cross Luminance Elimination.
Provides Color Saturation Adjustment for Vivid TV Output.
Provides Gamma Correction Independent of That of Primary VGA.
Auto-Sense of TV Connection
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1.2.4.2 LVDS Interfaced LCD Panel Display :
Supports LVDS Transmitter Function.
Single LVDS supports pixel rate up to 110M pixel/sec.
Compatible with TIA/EIA-644 LVDS standard.
Provides Bi-linear Scaling to Scale VGA Low Resolution Mode up for LCD Display – up to 1280x1024
Supports LCD/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode.
Support 2D dither for 18-bit panels.
Provides Programmable Display Centering.
Compliant with VESA DDC2B
Compliant with VESA Plug & Display, Hot Plugging Function.
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1.2.5 AC’97 Audio System: Advance Logic, Inc, ALC201
SiS961 is an AC’97 2.1 compliant controller that communicates with companion Codecs SiS a digital serial link
called the AC-link.
The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The ALC201
provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where high-quality audio
is required. The ALC201 AC’97 CODEC provides a complete high quality audio solution.
Features
Single chip audio CODEC with high S/N ratio (>90 dB)
18-bit ADC and DAC resolution
Compliant with AC’97 2.2 specification
Meet performance requirements for audio on PC2001 systems
18-bit stereo full-duplex CODEC with independent and variable sampling rate
4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX
2 analog line-level mono input: PC_BEEP, PHONE_IN
Mono output with 5-bit volume control
Stereo output with 5-bit volume control
2 MIC inputs: Software selectable
Power management
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3D Stereo Enhancement
Headphone output with 50mW/20ohm driving capability (ALC201)
Line output with 50mW/20ohm driving capability (ALC201A)
Headphone jack-detect function to mute LINE output
Multiple CODEC extension
MC’97 chained in allowed for multi-channel application
External Amplifier power down capability
Support S/PDIF out is fully compliant with AC’97 specification rev2.2
DC offset cancellation
Power support: Digital: 3.3V Analog: 5V
Standard 48-Pin LQFP Package
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1.2.6 MDC: PCTel Modem Daughter Card PCT2303W
The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The
combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows
systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining
higher system performance.
PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the
Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to
operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-
effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a
programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available
in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The
chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The
PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve
compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface
specification Rev. 2.1.
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The chip set is fully programmable to meet worldwide telephone line interface requirements including those
described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable
parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer
threshold. The PCT2303W chip set has been designed to meet stringent worldwide requirements for out-of-
band energy, billing-tone immunity, lightning surges, and safety requirements.
Operating System Compatibility
Windows 98 /NT4.0 /Win 2K /Win XP
Compatibility
ITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000,
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46667, 45333, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000bps
K56Flex 56000, 54000, 52000, 50000, 48000, 46000, 44000,
42000, 40000, 38000, 36000, 32000bps
ITU-T V.34Annex 33600,31200 bps
ITU-T V.34 28800 bps
ITU-T V.32bis 14400 bps
ITU-T V.32 9600,4800 bps
ITU-T V.22bis 2400 bps
ITU-T V.22 1200 bps
ITU-T V.21 300 bps
ITU-T V.23 1200/75 bps
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ITU-T V.17 14400,12000,9600,7200 bps
ITU-T V.29 9600,7200 bps
ITU-T V.27ter 4800,2400 bps
Bell 212A 1200 bps
Bell 103 300 bps
Modulation
56000bps (V90&K56Flex) PCM
33600 bps (V.34Annex) TCM
28800 bps (V.34) TCM
14400 bps (V.32bis) TCM
12000 bps (V.32bis) TCM
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9600 bps (V.32bis) TCM
7200 bps (V.32bis) QAM
9600 bps (V.32) TCM, QAM
4800 bps (V.32) QAM
14400 bps (V.17) TCM
12000 bps (V.17) TCM
9600 bps (V.29) QAM
7200 bps (V.29) QAM
4800 bps (V.27ter) DPSK
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2400 bps (V.27ter) DPS
2400 bps (V.22bis) QAM
1200/75bps (V.23) FSK
1200bps (V.22/Bell 212A) DPSK
300bps (V.21/Bell 103) FSK
Data Compression
V.42bis, MNP5
Error Correction
V.42 LAPM, MNP 2-4
DTE interface
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DTMF Tone Frequency
Low Group Frequency (Hz)
697 770 852 941 High Group 1209 1 4 7 * Frequency 1336 2 5 8 0 (Hz) 1477 3 6 9 # 1633 A B C D
DTMF signal level
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1.2.6.1 High Group -10+/-2dBm
1.2.6.2 Low Group -12+/-2dBm
Dialing Type Tone or pulse dialing
Telephone Line interface RJ-11
Return Loss 300HZ - 3400HZ >= 10db
Flow Control XOFF/XON or RTS/CTS
Receive Level -35 +/- 2dBm
Transmit Level >-15 dBm
Specification and features subject to change without notice!
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