Audio cable
USB cable
AC adapter
User guide
CD-ROM (U, N only)
Handy strap
Customer Registration Document (US only)
Tripod/Belt clip adapter
SD card
• Specifi cations are subject to change without notice.
Outputs
LINE
Type ..........................................................1/8" stereo jack
Standard level ...........................................1.0 V/10 kohms
Headphone
Type ..........................................................1/8" stereo jack
Standard level ..........................................16 mW/16 ohms
Speaker
Standard level ..........................................150 mW/8 ohms
1
2. SERVICE MENU
2. SERVICE メニュー
<Service Menu Details>
<サービスメニューの内容>
DisplayMenu
表示メニュー
1 OLED Check
2 LED Check
3 Door Sense
4 Heat Run
5 Factory Default
ServiceDetails
サービス内容
Check the display section by lighting all OLED.
OLEDの全点灯により、表示部を確認します。
Check the LED by lighting all LED.
LEDの全点灯により、LEDを確認します。
Set the door sensor ON/OFF.
ドアセンサの ON/OFFを設定します。
Perform a heat run test by using continuous play.
連続再生によりヒートラン試験を行います。
Return to the factory default settings.
工場出荷状態に戻します。
2.1 OLED Check
1) Press the REC PAUSE button and REC LEVEL – button
at the same time, and turn the POWER slide switch ON.
At this time, the service menu list is displayed in the
display section.
2)
Press the VOL + and VOL – buttons to select “OLED Check”.
At this time, the selected menu item is highlighted.
3) If the 3/8/ENTER button is pressed, all of the OLED
light.
• If the 4 button is pressed while all OLEDs are lit,
the display returns to the service menu list.
• If the 3/8/
are lit, the display returns to the service menu list.
ENTER
button is pressed while all OLEDs
2.1 OLED チェック
REC PAUSE
1)
押しながら、
とき、表示部にサービスメニュー一覧が表示されます。
VOL +
2)
Check” を選 択します。このとき、選択したメニュ ーが
ハイライト表示されます。
3) 3/8/
•
OLEDが全点灯中に 4ボタンを押すと、サービス
メニュー一覧に戻ります。
•
OLEDが全点灯中に 3/8/
ビスメニュー一覧に戻ります。
ボタンと
POWER slide
ボタンおよび
ENTER
ボタンを押すと、OLEDが全点灯します。
REC LEVEL −
スイッチを Onします。この
VOL –
ボタンを押して、“OLED
ENTER
ボタンを同 時に
ボタンを押すと、サー
2
2.2 LED Check
1) Press the REC PAUSE button and REC LEVEL – button
at the same time, and turn the POWER slide switch ON.
At this time, the service menu list is displayed in the
display section.
2) Press the VOL + and VOL – buttons to select “LED Check”.
At this time, the selected menu item is highlighted.
2.2 LED チェック
REC PAUSE
1)
押しながら、
とき、表示部にサービスメニュー一覧が表示されます。
VOL +
2)
Check” を選 択します。このとき、選択したメニュ ーが
ハイライト表示されます。
ボタンと
POWER slide
ボタンおよび
REC LEVEL −
スイッチを Onします。この
VOL –
ボタンを押して、“LED
ボタンを同 時に
3) If the 3/8/ENTER button is pressed, “∗” is displayed on
the back of “LED Check”, and all LEDs light (REC, OVER,
LEVEL, REMOTE RED, REMOTE GREEN).
• If the 4 button is pressed while all LEDs are lit, all
LEDs go off, and the display returns to the service
menu list.
• If the 3/8/
are lit, all LEDs go off, the “∗” display switches off, and
the display returns to the service menu list.
ENTER
button is pressed while all LEDs
2.3 Door Sence
1) Press the REC PAUSE button and REC LEVEL – button
at the same time, and turn the POWER slide switch ON.
At this time, the service menu list is displayed in the
display section.
2) Press the VOL + and VOL – buttons to select “Door Sence”.
At this time, the selected menu item is highlighted.
3) If the 3/8/ENTER button is pressed, the PMD620 sensor
is set to OFF.
• At this time, “Executing…” is displayed in the display
section.
• If the settings are completed, “Completed” is
displayed in the display section for 1 second, the
display returns to the service menu and “Door Sense
OFF” is displayed.
If the 3/8/ENTER button is pressed while “Door Sense
OFF” is displayed, the PMD620 sensor is set to ON.
ENTER
3) 3/8/
状態に設定します。
•
このとき、表示部に“Executing...”が表示されます。
•
設定が完了すると、表示部に “Completed”が1 秒間
表示され、サービスメニューに戻り “Door Sense OFF”
が表示されます。
“Door Sense OFF” 表 示しているときに 3/8/
ボタンを押すと、PMD620をセンサON状態に設定します。
ボタンを押すと、PMD620 をセンサOFF
ENTER
3
2.4 Heat Run
1) Press the REC PAUSE button and REC LEVEL – button
at the same time, and turn the POWER slide switch ON.
At this time, the service menu list is displayed in the
display section.
2) Press the VOL + and VOL – buttons to select “Heat Run”.
At this time, the selected menu item is highlighted.
2.4 ヒートラン実行
REC PAUSE
1)
押しながら、
とき、表示部にサービスメニュー一覧が表示されます。
VOL +
2)
Run” を選択します。 このとき、選 択したメニューが
ハイライト表示されます。
ボタンと
POWER slide
ボタンおよび
REC LEVEL −
スイッチを Onします。この
VOL –
ボタンを押して、“Heat
ボタンを同 時に
3) If the 3/8/ENTER button is pressed, continuous play
starts.
• During continuous play, all switches other than the
POWER slide
• During playback, if playback continues to the fi nal fi le,
all fi les are repeated and playback continues from the
fi rst fi le.
• If an error occurs during continuous playback, the
display remains in the error display status.
switch are inactive.
2.5 Factory Default
1) Press the REC PAUSE button and REC LEVEL – button
at the same time, and turn the POWER slide switch ON.
At this time, the service menu list is displayed in the
display section.
2) Press the VOL + and VOL – buttons to select “Factory
Default?”. At this time, the selected menu item is
highlighted.
3) If the 3 /8 /ENTER button is pressed “Default?” is
displayed in the display section.
4) While “Default?” is being displayed, press the 4 button
and select “YES”.
5) If the 3/8/ENTER button is pressed “Executing…” fl ashes
in the display section.
• When the settings have returned to the factory default
settings, “Completed” is displayed for 1 second, after
which the display section returns to the service menu.
• When the settings have been returned to the factory
default settings, the “Date Form” default setting is the
setting for the US. This needs to be set correctly for
the destination.
1) Open the battery cover on the back of the main unit, and
remove the 4 “A” screws.
A
1) 本体背面のバッテリーカバーを開き、ネジA 4本を外し
ます。
Battery cover
A
2) Lift the rear block slowly in the direction of the arrows,
disconnect the speaker cable q connector from J609 as
shown in the diagram below to remove the rear block.
Rear block
1
1 Speaker cable
00MYB00067520 (W003)
P2
P1
63mm
Red
Black
2) リアブロックをゆっくり矢印の方向へ持ち上げ、下図の
ようにスピーカケーブルqのコネクタ 1ヶ所をJ609か
ら外すと、リアブロックが取り外せます。
1
5
3) As shown in the diagram below, disconnect the Mic
RchLch
J608
J607
J611
J609
Rch cable 2 connector from J608, the Mic Lch cable
3 connector from J607, and the Mic shield cable r
connector from J611, and the top block can now be
removed. Also remove the button side block in the
direction of the arrow.
Top block
4
2
3
3) 下図のように Mic Rchケーブルwのコネクタを J608から外し、Mic Lch ケーブルeのコネクタをJ607から外し、
Mic シールドケーブルrのコネクタを J611から外すと、
トップブロックが取り外せます。またボタンサイドブ
ロックも矢印方向に取り外します。
2
4
3
Button side block
2 Mic Rch cable
P2
P1
3 Mic Lch cable
P2
P1
4 Mic shield cable
P2
P1
00MYB00051800 (W002)
Black
45mm
50mm
Black
00MYB00067540 (W001)
63mm
68mm
00MYB00051790 (W004)
Black
53mm
Black
Black
6
k
4) Lift the P102 jack section, and remove the P102 board
from the battery block in the direction of the arrow. Also,
the jack side block can be removed. The battery block
is held in place by the foot of the USB cap. Remove the
USB cap foot, and remove the battery block from the front
block in the direction of the arrow.
W001100MYB0006754000MYB00067540CONNECTIVE CORDWIRE FOR MIC L
W002100MYB0005180000MYB00051800CONNECTIVE CORDWIRE FOR MIC R
W003100MYB0006752000MYB00067520CONNECTIVE CORD8000-BARA WIRE AWG32 L=6.5
W004100MYB0005179000MYB00051790CONNECTIVE CORDWIRE FOR MIC NET
005B
012B
001B
020B
018B
034B
010B
x2
032B
016B
014B
008B
006B
052B
049B
050B
N001
044BV001
026B
028B
030B
007G
012G
006G
x2
044B
N002
050B
038B
040B
048B
007B
000B
007G
010B
001G
N003
005G
x2
5125
2x12(U)x2
5125
2x12(U)x2
2728
9. IC DATA
Q001 : TMS320VC5509AZHH
179-TERMINAL GHH AND ZHH BALL GRID ARRAY (BOTTOM VIEW)
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12
5634
BLOCK DIAGRAM
USB PLL
7
1412 1310 118 9
†
†
7/8
†
†
Number of pins determined by package type.
5
29
Q001 : TMS320VC5509AZHH
PIN ASSIGNMENTS FOR THE GHH AND ZHH PACKAGES
BALL #SIGNAL NAMEBALL #
A2V
A3GPIO4D6DR0H3A19L14CV
A4DV
A5FSR0D8S11H5C5M2C13
A6CV
A7S12D10S25H11A’[0]M4CV
A8DV
A9S20D12AIN2H13SDAM6A5
A10S21D13AIN1H14SCLM7A1
A11S23D14AIN0J1C6M8A15
A12RTCINX1E1GPIO1J2DV
A13RDV
A14RDV
B1V
B2CV
B3GPIO3E6DV
B4TIN/TOUT0E7DX0J12TRSTN1V
B5CLKR0E8S15J13TCKN2V
B6FSX0E9S13J14TMSN3A13
B7CV
B8CV
B9V
B10S24E13V
B11V
B12RTCINX2F1X1K6A3N9V
B13RDV
B14AV
C1PUF4V
C2V
C3NCF10ADV
C4GPIO6F11V
C5V
C6CLKX0F13DV
C7V
C8S14G1CV
C9S22G2C1L3C12P6A4
C10CV
C11V
C12RCV
C13AV
C14AV
D1GPIO7G12USBPLLV
D2USBV
D3DNG14INT0L11D13P14DV
D4DPH1C3L12D14
SS
DD
DD
DD
DD
DD
SS
DD
DD
DD
SS
SS
DD
SS
SS
SS
SS
DD
SS
DD
SS
DD
DD
D5GPIO5H2DV
D7S10H4C4M1C10
D9DV
D11V
E2GPIO2J3C7M10D6
E3DV
E4V
E5V
E10NCK1A18N4A10
E11AIN3K2C9N5A7
E12ADV
E14XFK5V
F2X2/CLKINK7A2N10V
F3GPIO0K8D1N11D8
F5CLKOUTK10DV
F12INT4K13TDOP2V
F14INT3L1CV
G3A20L4A11P7A16
G4C2L5A8P8DV
G5C0L6A6P9D2
G10INT2L7A0P10D5
G11USBPLLV
G13INT1L10D9P13DV
SIGNAL
NAME
DD
SS
DD
SS
SS
DD
SS
SS
SS
DD
SS
DD
DD
DD
SS
BALL #
H10DV
H12RESETM5V
J4C8M11CV
J5CV
J10CV
J11CV
K3C11N6DV
K4V
K9A14N12D11
K11EMU0N14V
K12EMU1/OFFP1V
K14TDIP3A12
L2C14P5A17
L8D0P11D7
L9D4P12D10
SIGNAL
NAME
DD
DD
DD
DD
DD
DD
SS
SS
DD
DD
BALL #
L13D15
M3V
M9D3
M12DV
M13V
M14D12
N7CV
N8CV
N13DV
P4A9
SIGNAL
NAME
DD
SS
DD
SS
DD
DD
SS
SS
SS
DD
DD
DD
SS
SS
DD
SS
SS
SS
DD
DD
DD
30
Q004 : PST3629NR
13
5
2
4
1OUT
2V
DD
3GND
4NC
5Cd
SOT-25A
(TOP VIEW)
31
Q005 : MT48LC4M16A2B4-7E
CKE
CLK
WE#
CAS#
RAS#
CS#
CONTROL
LOGIC
DECODE
COMMAND
MODE REGISTER
12
REFRESH
COUNTER
12
BLOCK DIAGRAM
BANK3
BANK2
BANK1
12
ROW-
ADDRESS
MUX
BANK0
12
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 4)
SENSE AMPLIFIERS
4096
11
DATA
OUTPUT
4
REGISTER
DQM
A0–A11,
BA0, BA1
2
ADDRESS
14
REGISTER
2
10
BANK
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
10
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
1024
(x4)
COLUMN
DECODER
4
DATA
INPUT
4
REGISTER
DQ0–DQ3
X16 VFBGA BALL ASSIGNMENT (TOP VIEW, BALL DOWN)
12345678
VSS
DQ15
SSQ
DQ13
DQ11
V
V
DDQ
SSQ
V
A
DQ14
B
DQ12
C
DDQ
V
V
SSQ
DDQ
V
DQ0
DQ2
DQ4
V
DQ1
DQ3
9
DD
VDDQ
DQ9
DQ10
D
V
SS
NC
DQ8
E
CKE
CLK
DQMH
F
A9
A11
NC/A12
G
A6
A7
A8
H
SS
V
J
A4
A5
VSSQ
V
CAS#
BA0
A0
A3
DQ6
DQ5
DD
DQML
DQ7
RAS#
WE#
BA1
CS#
A1
A10
DD
A2
V
Notes: The balls at A4, A5, and A6 are absent from the physical package. They are
included to illustrate that rows 4, 5, and 6 exist but contain no solder balls.
32
Q005 : MT48LC4M16A2B4-7E
PIN/BALL DESCRIPTIONS
VFBGA
Ball
NumbersSymbolTy peDescription
F2CLKInput
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
F3CKEInput
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE power-down and
SELF REFRESH operation (all banks idle), ACTIVE power-down (row
active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
G9CS#Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH, but READ/WRITE bursts already in progress will
continue and DQM will retain its DQ mask capability while CS#
remains HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
F9, F7, F8WE#, CAS#,
RAS#
–x4, x8:
DQM
E8, F1x16:
DQML,
DQMH
Input
Input
Command inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
Input/Output mask: DQM is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked
when DQM is sampled HIGH during a WRITE cycle. The output buffers
are placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC
and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7 and
DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered
same state when referenced as DQM.
G7, G8BA0, BA1Input
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
H7, H8, J8,
J7, J3, J2,
H3, H2, H1,
G3, H9, G2
A0–A11Input
Address inputs: A0–A11 are sampled during the ACTIVE command
(row-address A0–A11) and READ/WRITE command (column-address
A0–A9 [x4]; A0–A8 [x8]; A0–A7 [x16]; with A10 defining auto
precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a precharge command to
determine if all banks are to be precharged (A10[HIGH]) or bank
selected by BA0, BA1 (A1[LOW]). The address inputs also provide the
op-code during a LOAD MODE REGISTER command.
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
DQ0–DQ15x16: I/O
Data input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for
x4).
D2, D1, C2,
C1, B2, B1,
A2
–DQ0–DQ7x8: I/O
Data input/output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
–DQ0–DQ3x4: I/O
E2NC–
G1NC–
A7, B3, C7, D3V
A3, B7, C3,
DDQSupply
SSQSupply
V
D7
A9, E7, J9V
A1, E3, J1V
DDSupply
SSSupply
Data input/output: Data bus for x4.
No connect: These pins should be left unconnected.
Address input (A12) for the 256Mb and 512Mb devices
DQ power: Isolated DQ power on the die for improved noise
immunity.
DQ ground: Isolated DQ ground on the die for improved noise
immunity.
Power supply: +3.3V ±0.3V.
Ground.
33
Q006 : S29AL016D70BFI020
RY/BY#
V
CC
V
SS
RESET#
BLOCK DIAGRAM
Sector Switches
Erase Voltage
Generator
DQ0–DQ15 (A-1)
Input/Output
Buffers
WE#
BYTE#
CE#
OE#
A0–A19
State
Control
Command
Register
Detector
V
CC
PGM Voltage
Generator
Timer
STB
Chip Enable
Output Enable
Logic
Y-Decoder
X-Decoder
Address Latch
STB
Data
Latch
Y-Gating
Cell Matrix
CONNECTION DIAGRAMS
FBGA
Top View, Balls Facing Down
A6B6C6D6E6F6G6H6
BYTE#A16A15A14A12A13
DQ15/A-1V
A5B5C5D5E5F5G5H5
DQ13DQ6DQ14DQ7A11A10A8A9
A4B4C4D4E4F4G4H4
V
CC
DQ4DQ12DQ5A19NCRESET#WE#
A3B3C3D3E3F3G3H3
DQ11DQ3DQ10DQ2NCA18NCRY/BY#
A2B2C2D2E2F2G2H2
DQ9DQ1DQ8DQ0A5A6A17A7
A1B1C1D1E1F1G1H1
CE#A0A1A2A4A3
OE#V
SS
SS
34
Q006 : S29AL016D70BFI020
PIN CONFIGURATION
A0–A19=20 addresses
DQ0–DQ14=15 data inputs/outputs
DQ15/A-1=DQ15 (data input/output, word mode),
BYTE#=Selects 8-bit or 16-bit mode
CE#=Chip enable
OE#= Output enable
WE#=Write enable
RESET#=Hardware reset pin
RY/BY#= Ready/Busy output
V
CC
V
SS
NC=Pin not connected internally
bol
A-1 (LSB address input, byte mode)
=3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
=Device ground
LOGIC SYMBOL
20
A0–A19
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#RY/BY#
16 or 8
35
Q083 : NJU7700-F4/F15
3
412
F
1. V
OUT
2. V
DD
3. NC
4. V
SS
V
DD
V
OUT
VRE
V
SS
36
Q201 : NJU3713A
A
K
Package Outline
SSOP20
DAT
CL
BLOCK DIAGRAM
Shift Register
PIN CONFIGURATION
P5
P6
P7
P8
V
NC
P9
P10
P11
P12
1
2
3
4
5
6
7
8
9
10
Latch Circuit
20
19
18
17
16
15
14
13
12
11
V
DD
P4
P3
P2
P1
NC
CLR
STB
CLK
DATA
P1
P2
P3
P11
P12
STB
CLR
TERMINAL DESCRIPTION
No. SYMBOL I/O FUNCTION
1 P5 O
2 P6 O
3 P7 O
Parallel Conversion Data Output Terminals
4 P8 O
5 V
- GND
SS
6 NC - Non Connection
7 P9 O
8 P10 O
9 P11 O
Parallel Conversion Data Output Terminals
10 P12 O
11 DATA I Serial Data Input Terminal
12 CLK I Clock Signal Input Terminal
13
14
STB
CLR
I Strobe Signal Input Terminal
I Clear Signal Input Terminal
15 NC - Non Connection
16 P1 O
17 P2 O
18 P3 O
Parallel Conversion Data Output Terminals
19 P4 O
20 V
- Power Supply Terminal (2.4 to 5.5V)
DD
37
Q202 : NJU3754
Package Outline
SSOP16
P0
P1
P2
BLOCK DIAGRAM
V
SS
Latch Circuit
V
V
P0
P1
P2
P3
P4
P5
P6
SS
DD
PIN CONFIGURATION
1
2
3
4
5
6
7
8
Shift Register
16
15
14
13
12
11
10
V
DD
CE
CLK
SO
P10
P9
P8
9
P7
SO
P9
P10
Control Circuit
CE
CLK
TERMINAL DESCRIPTION
No.SYMBOL I/O FUNCTION
1 P0 I
2 P1 I
3 P2 I
4 P3 I
Parallel Data Input Terminals (with pull-up resistors)
5 P4 I
6 P5 I
7 P6 I
8 V
- Ground
SS
9 P7 I
10 P8 I
11 P9 I
Parallel Data Input Terminals (with pull-up resistors)
12 P10 I
13 SO O Serial Data Output Terminal
14
15
16 V
CLK
CE
- Power Supply Terminal (2.7 to 5.5V)
DD
I Serial Clock Input Terminal
I Chip Enable Input Terminal
38
Q207 : M66592FP
V
V
T
V
V
T
A
A5A4A3A2A
PIN LAYOUT DIAGRAM
SD5
SD4
SD3
SD2
SD1
48
47
46
45
44
SD0
VIF
DGND
VDD
D15
D14
D13
D12
D11
D10
D9
43
42
41
40
39
38
37
36
35
34
33
SD6
SD7
INT_N
SOF_N
RD_N
WR0_N
WR1_N
CS_N
DREQ0_N
DACK0_N
DEND0_N
DREQ1_N
DACK1_N/DSTB0_N
DEND1_N
RST_N
VIF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
M66592FP
(TOP VIEW)
1
2
3
4
5
6
7
8
9
11
10
DP
DM
AFED33
AFED33G
VBUS
REFRIN
AFEA15
AFEA15G
XIN
AFEA33G
12
13
14
XOU
AFEA33
AFED15
AFED15G
15
VIF
26
25
24
23
22
21
20
19
18
17
16
TES
D8
D7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
D1/AD1
D0
6/ ALE
1
MPBUS
*The “_N” in the signal name
indicates that the signal is in
the “L” active state.
Package
M66592FP : 64pinLQFP (0.5mm pitch)
39
Q207 : M66592FP
CPU bus
D15-0 Data Bus I/O This is a 16-bit data bus. 24-39*4) *4)
interface
AD6-1 Multiplex
A6-1 Address Bus IN This is a 6-bit address bus.
ALE Address Latch
CS_N Chip Select IN Setting this to the “L” level selects this
RD_N Read Strobe IN Setting this to the “L” level reads data
WR0_N D7-0 Byte Write
WR1_N D15-8 Byte Write
MPBUS*3 Bus Mode
Split bus
SD7-0 Split Data Bus I/O If a split bus is selected, this functions as
interface
DMA bus
interface
DREQ0_N*1
DREQ1_N*1
DACK0_N*1
DACK1_N*1
DSTB0_N*2 Data Strobe 0 IN This functions as the data strobe signal
DEND0_N*1
DEND1_N*1
INT_N Interrupt OUT In the “L” active state, this notifies the
SOF
output
SOF_N SOF pulse output OUT When an SOF is detected in the “L” active
XOUT Oscillation output OUT
PIN DESCRIPTIONS
I/O When a multiplex bus is specified, this
Address Bus
group of pins is used on a time-shared
basis for some of the data buses (D6-D1),
or for 6 bits of the address bus (A6-A1).
Because the data bus consists of 16 bits,
there is no A0.
IN When a multiplex bus is specified, the A6
Enable
pin is used as the ALE signal.
controller.
from the controller registers.
IN At the rising edge, D7-D0 are written to
Strobe
the registers of the controller.
IN At the rising edge, D15-D8 are written to
Strobe
the registers of the controller.
IN Setting this to the “L” level selects a
Selection
separate bus.
Setting this to the “H” level selects a
multiplex bus.
This should be fixed at either the “H” or “L”
level.
the data bus for the split bus.
DMA Request OUT This notifies the system of a D0FIFO port
or D1FIFO port DMA transfer request.
DMA
Acknowledge
IN Input the DMA Acknowledge signal for the
D0FIFO or D1FIFO port.
for the D0FIFO port.
Because it is also used for the DMA
Acknowledge signal of the D1FIFO port,
the DSTB0_N function cannot be used if
the DACK1_N function is being used.
DMA Transfer
End
I/O <In the FIFO port access writing
direction>
This receives the Transfer End signal
from another peripheral chip or the CPU
as an input signal.
<In the FIFO port access reading
direction>
This indicates the transfer end data as an
output signal.
system of various types of interrupts
relating to USB communication.
state, an SOF pulse is output.
A crystal oscillator should be connected
between XIN and XOUT. When using
external clock input, the external clock
signal should be connected to XIN, and
XOUT should be open.
State of pin *7) Category Pin name NameI/OFunction Pin
count
(Pin nos.)
RST_N=”L”RST_N
goes “H”
PCUT=1
Input
(Hi-z)
18-23Input
*5)
Input
*5)
Input
(Hi-z)
Input
Input Input
56Input
*6)
Input
*6)
Input
53Input Input Input
54Input
*6)
55Input
*6)
17Input
*3)
43-50Input
(Hi-z)
Input
*6)
Input
*6)
Input
*3)
Input
(Hi-z)
Input
Input
Input
*3)
Input
(Hi-z)
57, 60H H H/L
*8)
58, 61Input Input
59, 62Input
(Hi-z)
Input
(Hi-z)
Input
Input
(Hi-z)
51H H H Interrupt/
52H H H
10 NI tupni noitallicsO NIXClock
11
40
System
*1)
.
*2)
*3)
t
*4)
*5)
*6)
r
*7)
*8)
control
count
(Pin nos.)
RST_N=”L”RST_N
RST_N Reset signal IN At “L” level, the controller is initialized. 63 Input
(L)
TEST Test signal IN This should be fixed at “L” or open. 16
State of pin *7) Category Pin name NameI/OFunction Pin
goes “H”
Input
(H)
PCUT=1
Input
(H)
USB bus
interface
VBUS
monitor
input
Reference
resistance
Power
supply /
GND
DP USB D+ data I/O This should be connected to the D+ pin of
the USB bus.
DM USB D- data I/O This should be connected to the D- pin of
the USB bus.
VBUS VBUS input IN This should be connected directly to the
Vbus of the USB bus. The connected or
disconnected state of the Vbus can be
detected. If This pin is not connectted with
Vbus of a USB bus, connect it with 5V.
REFRIN Reference input IN This should be connected to AFEA33G
through a 5.6 kΩ±1% resistance.
AFEA33V Transceiver unit
- This should be connected to 3.3 V. 12
analog power
supply
AFEA33G Transceiver unit
analog GND
AFED33V Transceiver unit
- This should be connected to 3.3 V. 2
digital power
supply
AFED33G Transceiver unit
digital GND
AFEA15V Transceiver unit
- This should be connected to 1.5 V. 6
analog 1.5 V
power supply
AFEA15G Transceiver unit
analog GND
AFED15V Transceiver unit
- This should be connected to 1.5 V. 13
digital 1.5 V
power supply
AFED15G Transceiver unit
digital GND
VDD Core power
- This should be connected to 1.5 V. 40
supply
VIF IO power supply - This should be connected to 3.3 V or 1.8
V.
4Input
(Hi-z)
3Input
(Hi-z)
5Input
(Hi-z)
8
9 -
1 -
7 -
14 -
15, 42,
64
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
Input
(Hi-z)
41 - DNG latigiD DNGD
The “L” active and “H” active states of these pins can be specified using the control program for the user system
”_N” indicates that the “L” active state is the default state.
DSTB0_N and DACK1_N are assigned to the same pin, so the functions of one or the other are valid.
The input level of the MPBUS pin needs to be established just before the end of H/W reset. Also, this should no
be switched during operation.
When CS_N and RD_N are “L”, these pins output “H” or “L”.
If MPBUS is “H”, these pins can be made to open.
CS_N, WR0_N, and WR1_N should be kept as (a) or (b) during RST_N=”L” (from RST_N goes "L" to right afte
RST_N goes "H").
(a) CS_N=”H”
(b) WR0_N=”H” and WR1_N=”H”
Discription of “State of pin”
(a) Input : Pins are Hi-z state. Please do not make it “open” on a board.
(b) Input(Hi-z) : Pins are Hi-z state. Pins can be “open” on a board.
(c) H, L, H/L : Output states is shown.